[urcu.git] / urcu / uatomic_arch_ppc.h

#ifndef _URCU_ARCH_UATOMIC_PPC_H
#define _URCU_ARCH_UATOMIC_PPC_H

/* 
 * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
 * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
 * Copyright (c) 2009      Mathieu Desnoyers
 *
 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
 * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
 *
 * Permission is hereby granted to use or copy this program
 * for any purpose,  provided the above notices are retained on all copies.
 * Permission to modify the code and to distribute modified code is granted,
 * provided the above notices are retained, and a notice that the code was
 * modified is included with the above copyright notice.
 *
 * Code inspired from libuatomic_ops-1.2, inherited in part from the
 * Boehm-Demers-Weiser conservative garbage collector.
 */

#include <urcu/compiler.h>
#include <urcu/system.h>

#ifndef __SIZEOF_LONG__
#ifdef __powerpc64__
#define __SIZEOF_LONG__ 8
#else
#define __SIZEOF_LONG__ 4
#endif
#endif

#ifndef BITS_PER_LONG
#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
#endif

#define ILLEGAL_INSTR	".long	0xd00d00"

#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
#define uatomic_read(addr)	LOAD_SHARED(*(addr))

/*
 * Using a isync as second barrier for exchange to provide acquire semantic.
 * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
 * explicit that this also has acquire semantics."
 * Derived from AO_compare_and_swap(), but removed the comparison.
 */

/* xchg */

static inline __attribute__((always_inline))
unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
{
	switch (len) {
	case 4:
	{
		unsigned int result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"stwcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"stdcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}

#define uatomic_xchg(addr, v)						    \
	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
						sizeof(*(addr))))
/* cmpxchg */

static inline __attribute__((always_inline))
unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
			      unsigned long _new, int len)
{
	switch (len) {
	case 4:
	{
		unsigned int old_val;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"cmpd %0,%3\n"		/* if load is not equal to */
			"bne 2f\n"		/* old, fail */
			"stwcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
		"2:\n"
				: "=&r"(old_val)
				: "r"(addr), "r"((unsigned int)_new),
				  "r"((unsigned int)old)
				: "memory", "cc");

		return old_val;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long old_val;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"cmpd %0,%3\n"		/* if load is not equal to */
			"bne 2f\n"		/* old, fail */
			"stdcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
		"2:\n"
				: "=&r"(old_val),
				: "r"(addr), "r"((unsigned long)_new),
				  "r"((unsigned long)old)
				: "memory", "cc");

		return old_val;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}


#define uatomic_cmpxchg(addr, old, _new)				    \
	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
						(unsigned long)(_new), 	    \
						sizeof(*(addr))))

/* uatomic_add_return */

static inline __attribute__((always_inline))
unsigned long _uatomic_add_return(void *addr, unsigned long val,
				 int len)
{
	switch (len) {
	case 4:
	{
		unsigned int result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"add %0,%2,%0\n"	/* add val to value loaded */
			"stwcx. %0,0,%1\n"	/* store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"add %0,%2,%0\n"	/* add val to value loaded */
			"stdcx. %0,0,%1\n"	/* store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}


#define uatomic_add_return(addr, v)					\
	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
						  (unsigned long)(v),	\
						  sizeof(*(addr))))

/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */

#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))

#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))

#define uatomic_inc(addr)		uatomic_add((addr), 1)
#define uatomic_dec(addr)		uatomic_add((addr), -1)

#define URCU_CAS_AVAIL()	1
#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)

#endif /* _URCU_ARCH_UATOMIC_PPC_H */
Commit	Line	Data
ec4e58a3 MD	1	#ifndef _URCU_ARCH_UATOMIC_PPC_H
ec4e58a3 MD	2	#define _URCU_ARCH_UATOMIC_PPC_H
0114ba7f MD	3
	4	/*
	5	* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
	6	* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
	7	* Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
	8	* Copyright (c) 2009 Mathieu Desnoyers
	9	*
	10	* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
	11	* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
	12	*
	13	* Permission is hereby granted to use or copy this program
	14	* for any purpose, provided the above notices are retained on all copies.
	15	* Permission to modify the code and to distribute modified code is granted,
	16	* provided the above notices are retained, and a notice that the code was
	17	* modified is included with the above copyright notice.
	18	*
ec4e58a3	19	* Code inspired from libuatomic_ops-1.2, inherited in part from the
0114ba7f MD	20	* Boehm-Demers-Weiser conservative garbage collector.
	21	*/
	22
ec4e58a3	23	#include <urcu/compiler.h>
b46b23cb	24	#include <urcu/system.h>
1315d277	25
bcf80111 SM	26	#ifndef __SIZEOF_LONG__
	27	#ifdef __powerpc64__
	28	#define __SIZEOF_LONG__ 8
	29	#else
	30	#define __SIZEOF_LONG__ 4
	31	#endif
	32	#endif
	33
0114ba7f MD	34	#ifndef BITS_PER_LONG
	35	#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
	36	#endif
	37
e7061ad2	38	#define ILLEGAL_INSTR ".long 0xd00d00"
0114ba7f	39
b46b23cb MD	40	#define uatomic_set(addr, v) STORE_SHARED(*(addr), (v))
b46b23cb MD	41	#define uatomic_read(addr) LOAD_SHARED(*(addr))
5f8052b4	42
0114ba7f MD	43	/*
0114ba7f MD	44	* Using a isync as second barrier for exchange to provide acquire semantic.
ec4e58a3	45	* According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
0114ba7f MD	46	* explicit that this also has acquire semantics."
	47	* Derived from AO_compare_and_swap(), but removed the comparison.
	48	*/
	49
f689dcbc MD	50	/* xchg */
f689dcbc MD	51
da1c1635	52	static inline __attribute__((always_inline))
ec4e58a3	53	unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
0114ba7f	54	{
f689dcbc MD	55	switch (len) {
	56	case 4:
	57	{
	58	unsigned int result;
	59
	60	__asm__ __volatile__(
	61	"lwsync\n"
	62	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	63	"stwcx. %2,0,%1\n" /* else store conditional */
	64	"bne- 1b\n" /* retry if lost reservation */
	65	"isync\n"
	66	: "=&r"(result)
	67	: "r"(addr), "r"(val)
	68	: "memory", "cc");
	69
	70	return result;
	71	}
	72	#if (BITS_PER_LONG == 64)
	73	case 8:
	74	{
	75	unsigned long result;
	76
	77	__asm__ __volatile__(
	78	"lwsync\n"
	79	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	80	"stdcx. %2,0,%1\n" /* else store conditional */
	81	"bne- 1b\n" /* retry if lost reservation */
	82	"isync\n"
	83	: "=&r"(result)
	84	: "r"(addr), "r"(val)
	85	: "memory", "cc");
	86
	87	return result;
	88	}
	89	#endif
	90	}
	91	/* generate an illegal instruction. Cannot catch this with linker tricks
	92	* when optimizations are disabled. */
	93	__asm__ __volatile__(ILLEGAL_INSTR);
	94	return 0;
0114ba7f MD	95	}
0114ba7f MD	96
ec4e58a3 MD	97	#define uatomic_xchg(addr, v) \
ec4e58a3 MD	98	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
da1c1635	99	sizeof(*(addr))))
f689dcbc	100	/* cmpxchg */
0114ba7f	101
da1c1635	102	static inline __attribute__((always_inline))
ec4e58a3	103	unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
f689dcbc	104	unsigned long _new, int len)
0114ba7f	105	{
f689dcbc MD	106	switch (len) {
	107	case 4:
	108	{
	109	unsigned int old_val;
	110
	111	__asm__ __volatile__(
	112	"lwsync\n"
	113	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	114	"cmpd %0,%3\n" /* if load is not equal to */
	115	"bne 2f\n" /* old, fail */
	116	"stwcx. %2,0,%1\n" /* else store conditional */
	117	"bne- 1b\n" /* retry if lost reservation */
	118	"isync\n"
	119	"2:\n"
e72f4937	120	: "=&r"(old_val)
f689dcbc MD	121	: "r"(addr), "r"((unsigned int)_new),
	122	"r"((unsigned int)old)
	123	: "memory", "cc");
	124
	125	return old_val;
	126	}
	127	#if (BITS_PER_LONG == 64)
	128	case 8:
	129	{
	130	unsigned long old_val;
	131
	132	__asm__ __volatile__(
	133	"lwsync\n"
	134	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	135	"cmpd %0,%3\n" /* if load is not equal to */
	136	"bne 2f\n" /* old, fail */
	137	"stdcx. %2,0,%1\n" /* else store conditional */
	138	"bne- 1b\n" /* retry if lost reservation */
	139	"isync\n"
	140	"2:\n"
	141	: "=&r"(old_val),
	142	: "r"(addr), "r"((unsigned long)_new),
	143	"r"((unsigned long)old)
	144	: "memory", "cc");
	145
	146	return old_val;
	147	}
	148	#endif
	149	}
	150	/* generate an illegal instruction. Cannot catch this with linker tricks
	151	* when optimizations are disabled. */
	152	__asm__ __volatile__(ILLEGAL_INSTR);
	153	return 0;
0114ba7f MD	154	}
0114ba7f MD	155
da1c1635	156
ec4e58a3 MD	157	#define uatomic_cmpxchg(addr, old, _new) \
ec4e58a3 MD	158	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
da1c1635 MD	159	(unsigned long)(_new), \
da1c1635 MD	160	sizeof(*(addr))))
f689dcbc	161
ec4e58a3	162	/* uatomic_add_return */
0114ba7f	163
da1c1635	164	static inline __attribute__((always_inline))
ec4e58a3	165	unsigned long _uatomic_add_return(void *addr, unsigned long val,
f689dcbc	166	int len)
0114ba7f MD	167	{
0114ba7f MD	168	switch (len) {
f689dcbc MD	169	case 4:
	170	{
	171	unsigned int result;
	172
	173	__asm__ __volatile__(
	174	"lwsync\n"
	175	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	176	"add %0,%2,%0\n" /* add val to value loaded */
	177	"stwcx. %0,0,%1\n" /* store conditional */
	178	"bne- 1b\n" /* retry if lost reservation */
	179	"isync\n"
	180	: "=&r"(result)
	181	: "r"(addr), "r"(val)
	182	: "memory", "cc");
	183
	184	return result;
	185	}
0114ba7f	186	#if (BITS_PER_LONG == 64)
f689dcbc MD	187	case 8:
	188	{
	189	unsigned long result;
	190
	191	__asm__ __volatile__(
	192	"lwsync\n"
	193	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	194	"add %0,%2,%0\n" /* add val to value loaded */
	195	"stdcx. %0,0,%1\n" /* store conditional */
	196	"bne- 1b\n" /* retry if lost reservation */
	197	"isync\n"
	198	: "=&r"(result)
	199	: "r"(addr), "r"(val)
	200	: "memory", "cc");
	201
	202	return result;
	203	}
0114ba7f MD	204	#endif
	205	}
	206	/* generate an illegal instruction. Cannot catch this with linker tricks
	207	* when optimizations are disabled. */
	208	__asm__ __volatile__(ILLEGAL_INSTR);
	209	return 0;
	210	}
	211
da1c1635	212
ec4e58a3 MD	213	#define uatomic_add_return(addr, v) \
ec4e58a3 MD	214	((__typeof__(*(addr))) _uatomic_add_return((addr), \
da1c1635 MD	215	(unsigned long)(v), \
da1c1635 MD	216	sizeof(*(addr))))
f689dcbc	217
ec4e58a3	218	/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
f689dcbc	219
ec4e58a3	220	#define uatomic_sub_return(addr, v) uatomic_add_return((addr), -(v))
f689dcbc	221
ec4e58a3 MD	222	#define uatomic_add(addr, v) (void)uatomic_add_return((addr), (v))
ec4e58a3 MD	223	#define uatomic_sub(addr, v) (void)uatomic_sub_return((addr), (v))
f689dcbc	224
ec4e58a3 MD	225	#define uatomic_inc(addr) uatomic_add((addr), 1)
ec4e58a3 MD	226	#define uatomic_dec(addr) uatomic_add((addr), -1)
0114ba7f	227
7d413817 MD	228	#define URCU_CAS_AVAIL() 1
	229	#define compat_uatomic_cmpxchg(ptr, old, _new) uatomic_cmpxchg(ptr, old, _new)
	230
ec4e58a3	231	#endif /* _URCU_ARCH_UATOMIC_PPC_H */