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ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_UATOMIC_PPC_H |
2 | #define _URCU_ARCH_UATOMIC_PPC_H | |
0114ba7f MD |
3 | |
4 | /* | |
5 | * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved. | |
6 | * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved. | |
7 | * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P. | |
8 | * Copyright (c) 2009 Mathieu Desnoyers | |
9 | * | |
10 | * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED | |
11 | * OR IMPLIED. ANY USE IS AT YOUR OWN RISK. | |
12 | * | |
13 | * Permission is hereby granted to use or copy this program | |
14 | * for any purpose, provided the above notices are retained on all copies. | |
15 | * Permission to modify the code and to distribute modified code is granted, | |
16 | * provided the above notices are retained, and a notice that the code was | |
17 | * modified is included with the above copyright notice. | |
18 | * | |
ec4e58a3 | 19 | * Code inspired from libuatomic_ops-1.2, inherited in part from the |
0114ba7f MD |
20 | * Boehm-Demers-Weiser conservative garbage collector. |
21 | */ | |
22 | ||
ec4e58a3 | 23 | #include <urcu/compiler.h> |
b46b23cb | 24 | #include <urcu/system.h> |
1315d277 | 25 | |
36bc70a8 MD |
26 | #ifdef __cplusplus |
27 | extern "C" { | |
28 | #endif | |
29 | ||
e7061ad2 | 30 | #define ILLEGAL_INSTR ".long 0xd00d00" |
0114ba7f | 31 | |
0114ba7f | 32 | /* |
dabbe4f8 MD |
33 | * Providing sequential consistency semantic with respect to other |
34 | * instructions for cmpxchg and add_return family of atomic primitives. | |
35 | * | |
36 | * This is achieved with: | |
37 | * lwsync (prior loads can be reordered after following load) | |
38 | * lwarx | |
39 | * stwcx. | |
40 | * test if success (retry) | |
41 | * sync | |
42 | * | |
43 | * Explanation of the sequential consistency provided by this scheme | |
44 | * from Paul E. McKenney: | |
45 | * | |
46 | * The reason we can get away with the lwsync before is that if a prior | |
47 | * store reorders with the lwarx, then you have to store to the atomic | |
48 | * variable from some other CPU to detect it. | |
49 | * | |
50 | * And if you do that, the lwarx will lose its reservation, so the stwcx | |
51 | * will fail. The atomic operation will retry, so that the caller won't be | |
52 | * able to see the misordering. | |
0114ba7f MD |
53 | */ |
54 | ||
f689dcbc MD |
55 | /* xchg */ |
56 | ||
da1c1635 | 57 | static inline __attribute__((always_inline)) |
ec4e58a3 | 58 | unsigned long _uatomic_exchange(void *addr, unsigned long val, int len) |
0114ba7f | 59 | { |
f689dcbc MD |
60 | switch (len) { |
61 | case 4: | |
62 | { | |
63 | unsigned int result; | |
64 | ||
65 | __asm__ __volatile__( | |
701dd8de | 66 | LWSYNC_OPCODE |
f689dcbc MD |
67 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
68 | "stwcx. %2,0,%1\n" /* else store conditional */ | |
69 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 70 | "sync\n" |
f689dcbc MD |
71 | : "=&r"(result) |
72 | : "r"(addr), "r"(val) | |
73 | : "memory", "cc"); | |
74 | ||
75 | return result; | |
76 | } | |
b39e1761 | 77 | #if (CAA_BITS_PER_LONG == 64) |
f689dcbc MD |
78 | case 8: |
79 | { | |
80 | unsigned long result; | |
81 | ||
82 | __asm__ __volatile__( | |
701dd8de | 83 | LWSYNC_OPCODE |
f689dcbc MD |
84 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
85 | "stdcx. %2,0,%1\n" /* else store conditional */ | |
86 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 87 | "sync\n" |
f689dcbc MD |
88 | : "=&r"(result) |
89 | : "r"(addr), "r"(val) | |
90 | : "memory", "cc"); | |
91 | ||
92 | return result; | |
93 | } | |
94 | #endif | |
95 | } | |
96 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
97 | * when optimizations are disabled. */ | |
98 | __asm__ __volatile__(ILLEGAL_INSTR); | |
99 | return 0; | |
0114ba7f MD |
100 | } |
101 | ||
ec4e58a3 MD |
102 | #define uatomic_xchg(addr, v) \ |
103 | ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \ | |
da1c1635 | 104 | sizeof(*(addr)))) |
f689dcbc | 105 | /* cmpxchg */ |
0114ba7f | 106 | |
da1c1635 | 107 | static inline __attribute__((always_inline)) |
ec4e58a3 | 108 | unsigned long _uatomic_cmpxchg(void *addr, unsigned long old, |
f689dcbc | 109 | unsigned long _new, int len) |
0114ba7f | 110 | { |
f689dcbc MD |
111 | switch (len) { |
112 | case 4: | |
113 | { | |
114 | unsigned int old_val; | |
115 | ||
116 | __asm__ __volatile__( | |
701dd8de | 117 | LWSYNC_OPCODE |
f689dcbc | 118 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
0ecb3fde | 119 | "cmpw %0,%3\n" /* if load is not equal to */ |
f689dcbc MD |
120 | "bne 2f\n" /* old, fail */ |
121 | "stwcx. %2,0,%1\n" /* else store conditional */ | |
122 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 123 | "sync\n" |
f689dcbc | 124 | "2:\n" |
e72f4937 | 125 | : "=&r"(old_val) |
f689dcbc MD |
126 | : "r"(addr), "r"((unsigned int)_new), |
127 | "r"((unsigned int)old) | |
128 | : "memory", "cc"); | |
129 | ||
130 | return old_val; | |
131 | } | |
b39e1761 | 132 | #if (CAA_BITS_PER_LONG == 64) |
f689dcbc MD |
133 | case 8: |
134 | { | |
135 | unsigned long old_val; | |
136 | ||
137 | __asm__ __volatile__( | |
701dd8de | 138 | LWSYNC_OPCODE |
f689dcbc MD |
139 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
140 | "cmpd %0,%3\n" /* if load is not equal to */ | |
141 | "bne 2f\n" /* old, fail */ | |
142 | "stdcx. %2,0,%1\n" /* else store conditional */ | |
143 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 144 | "sync\n" |
f689dcbc | 145 | "2:\n" |
b96b22e1 | 146 | : "=&r"(old_val) |
f689dcbc MD |
147 | : "r"(addr), "r"((unsigned long)_new), |
148 | "r"((unsigned long)old) | |
149 | : "memory", "cc"); | |
150 | ||
151 | return old_val; | |
152 | } | |
153 | #endif | |
154 | } | |
155 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
156 | * when optimizations are disabled. */ | |
157 | __asm__ __volatile__(ILLEGAL_INSTR); | |
158 | return 0; | |
0114ba7f MD |
159 | } |
160 | ||
da1c1635 | 161 | |
ec4e58a3 MD |
162 | #define uatomic_cmpxchg(addr, old, _new) \ |
163 | ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\ | |
da1c1635 MD |
164 | (unsigned long)(_new), \ |
165 | sizeof(*(addr)))) | |
f689dcbc | 166 | |
ec4e58a3 | 167 | /* uatomic_add_return */ |
0114ba7f | 168 | |
da1c1635 | 169 | static inline __attribute__((always_inline)) |
ec4e58a3 | 170 | unsigned long _uatomic_add_return(void *addr, unsigned long val, |
f689dcbc | 171 | int len) |
0114ba7f MD |
172 | { |
173 | switch (len) { | |
f689dcbc MD |
174 | case 4: |
175 | { | |
176 | unsigned int result; | |
177 | ||
178 | __asm__ __volatile__( | |
701dd8de | 179 | LWSYNC_OPCODE |
f689dcbc MD |
180 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
181 | "add %0,%2,%0\n" /* add val to value loaded */ | |
182 | "stwcx. %0,0,%1\n" /* store conditional */ | |
183 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 184 | "sync\n" |
f689dcbc MD |
185 | : "=&r"(result) |
186 | : "r"(addr), "r"(val) | |
187 | : "memory", "cc"); | |
188 | ||
189 | return result; | |
190 | } | |
b39e1761 | 191 | #if (CAA_BITS_PER_LONG == 64) |
f689dcbc MD |
192 | case 8: |
193 | { | |
194 | unsigned long result; | |
195 | ||
196 | __asm__ __volatile__( | |
701dd8de | 197 | LWSYNC_OPCODE |
f689dcbc MD |
198 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
199 | "add %0,%2,%0\n" /* add val to value loaded */ | |
200 | "stdcx. %0,0,%1\n" /* store conditional */ | |
201 | "bne- 1b\n" /* retry if lost reservation */ | |
dabbe4f8 | 202 | "sync\n" |
f689dcbc MD |
203 | : "=&r"(result) |
204 | : "r"(addr), "r"(val) | |
205 | : "memory", "cc"); | |
206 | ||
207 | return result; | |
208 | } | |
0114ba7f MD |
209 | #endif |
210 | } | |
211 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
212 | * when optimizations are disabled. */ | |
213 | __asm__ __volatile__(ILLEGAL_INSTR); | |
214 | return 0; | |
215 | } | |
216 | ||
da1c1635 | 217 | |
ec4e58a3 MD |
218 | #define uatomic_add_return(addr, v) \ |
219 | ((__typeof__(*(addr))) _uatomic_add_return((addr), \ | |
da1c1635 MD |
220 | (unsigned long)(v), \ |
221 | sizeof(*(addr)))) | |
f689dcbc | 222 | |
36bc70a8 MD |
223 | #ifdef __cplusplus |
224 | } | |
225 | #endif | |
226 | ||
a2e7bf9c | 227 | #include <urcu/uatomic/generic.h> |
8760d94e | 228 | |
ec4e58a3 | 229 | #endif /* _URCU_ARCH_UATOMIC_PPC_H */ |