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ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_X86_H |
2 | #define _URCU_ARCH_X86_H | |
121a5d44 | 3 | |
6d0ce021 | 4 | /* |
af02d47e | 5 | * arch_x86.h: trivial definitions for the x86 architecture. |
6d0ce021 | 6 | * |
af02d47e | 7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
6982d6d7 | 8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
6d0ce021 | 9 | * |
af02d47e MD |
10 | * This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2.1 of the License, or (at your option) any later version. | |
05dd4b94 | 14 | * |
af02d47e | 15 | * This library is distributed in the hope that it will be useful, |
6d0ce021 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
af02d47e MD |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
18 | * Lesser General Public License for more details. | |
6d0ce021 | 19 | * |
af02d47e MD |
20 | * You should have received a copy of the GNU Lesser General Public |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | |
6d0ce021 PM |
23 | */ |
24 | ||
ec4e58a3 | 25 | #include <urcu/compiler.h> |
c96a3726 | 26 | #include <urcu/config.h> |
121a5d44 | 27 | |
36bc70a8 MD |
28 | #ifdef __cplusplus |
29 | extern "C" { | |
30 | #endif | |
31 | ||
06f22bdb | 32 | #define CAA_CACHE_LINE_SIZE 128 |
b4e52e3e | 33 | |
02be5561 | 34 | #ifdef CONFIG_RCU_HAVE_FENCE |
5481ddb3 | 35 | #define cmm_mb() asm volatile("mfence":::"memory") |
4e029f65 PB |
36 | |
37 | /* | |
38 | * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when | |
39 | * using SSE or working with I/O areas. cmm_smp_rmb/cmm_smp_wmb are | |
40 | * only compiler barriers, which is enough for general use. | |
41 | */ | |
42 | #define cmm_rmb() asm volatile("lfence":::"memory") | |
43 | #define cmm_wmb() asm volatile("sfence"::: "memory") | |
44 | #define cmm_smp_rmb() cmm_barrier() | |
45 | #define cmm_smp_wmb() cmm_barrier() | |
6d0ce021 PM |
46 | #else |
47 | /* | |
4e029f65 PB |
48 | * We leave smp_rmb/smp_wmb as full barriers for processors that do not have |
49 | * fence instructions. | |
50 | * | |
51 | * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor | |
52 | * systems, due to an erratum. The Linux kernel says that "Even distro | |
53 | * kernels should think twice before enabling this", but for now let's | |
54 | * be conservative and leave the full barrier on 32-bit processors. Also, | |
55 | * IDT WinChip supports weak store ordering, and the kernel may enable it | |
56 | * under our feet; cmm_smp_wmb() ceases to be a nop for these processors. | |
6d0ce021 | 57 | */ |
5481ddb3 DG |
58 | #define cmm_mb() asm volatile("lock; addl $0,0(%%esp)":::"memory") |
59 | #define cmm_rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory") | |
60 | #define cmm_wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory") | |
6d0ce021 PM |
61 | #endif |
62 | ||
06f22bdb | 63 | #define caa_cpu_relax() asm volatile("rep; nop" : : : "memory"); |
6d0ce021 | 64 | |
af02d47e MD |
65 | #define rdtscll(val) \ |
66 | do { \ | |
67 | unsigned int __a, __d; \ | |
68 | asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \ | |
69 | (val) = ((unsigned long long)__a) \ | |
70 | | (((unsigned long long)__d) << 32); \ | |
71 | } while(0) | |
6d0ce021 PM |
72 | |
73 | typedef unsigned long long cycles_t; | |
74 | ||
06f22bdb | 75 | static inline cycles_t caa_get_cycles(void) |
6d0ce021 | 76 | { |
af02d47e | 77 | cycles_t ret = 0; |
6d0ce021 PM |
78 | |
79 | rdtscll(ret); | |
80 | return ret; | |
81 | } | |
121a5d44 | 82 | |
36bc70a8 MD |
83 | #ifdef __cplusplus |
84 | } | |
85 | #endif | |
86 | ||
1b9119f8 | 87 | #include <urcu/arch/generic.h> |
e4d1eb09 | 88 | |
ec4e58a3 | 89 | #endif /* _URCU_ARCH_X86_H */ |