Commit | Line | Data |
---|---|---|
60a1db9d MD |
1 | /* |
2 | * mem.spin: Promela code to validate memory barriers with OOO memory. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * Copyright (c) 2009 Mathieu Desnoyers | |
19 | */ | |
20 | ||
21 | /* Promela validation variables. */ | |
22 | ||
23 | #define NR_READERS 1 | |
24 | #define NR_WRITERS 1 | |
25 | ||
26 | #define NR_PROCS 2 | |
27 | ||
28 | #define get_pid() (_pid) | |
29 | ||
30 | /* | |
31 | * Each process have its own data in cache. Caches are randomly updated. | |
32 | * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces | |
33 | * both. | |
34 | */ | |
35 | ||
36 | #define DECLARE_CACHED_VAR(type, x, v) \ | |
37 | type mem_##x = v; \ | |
38 | type cached_##x[NR_PROCS] = v; \ | |
39 | bit cache_dirty_##x[NR_PROCS] = 0 | |
40 | ||
41 | #define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) | |
42 | ||
43 | #define READ_CACHED_VAR(x) (cached_##x[get_pid()]) | |
44 | ||
45 | #define WRITE_CACHED_VAR(x, v) \ | |
46 | atomic { \ | |
47 | cached_##x[get_pid()] = v; \ | |
48 | cache_dirty_##x[get_pid()] = 1; \ | |
49 | } | |
50 | ||
51 | #define CACHE_WRITE_TO_MEM(x, id) \ | |
52 | if \ | |
53 | :: IS_CACHE_DIRTY(x, id) -> \ | |
54 | mem_##x = cached_##x[id]; \ | |
55 | cache_dirty_##x[id] = 0; \ | |
56 | :: else -> \ | |
57 | skip \ | |
58 | fi; | |
59 | ||
60 | #define CACHE_READ_FROM_MEM(x, id) \ | |
61 | if \ | |
62 | :: !IS_CACHE_DIRTY(x, id) -> \ | |
63 | cached_##x[id] = mem_##x;\ | |
64 | :: else -> \ | |
65 | skip \ | |
66 | fi; | |
67 | ||
68 | /* | |
69 | * May update other caches if cache is dirty, or not. | |
70 | */ | |
71 | #define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ | |
72 | if \ | |
73 | :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ | |
74 | :: 1 -> skip \ | |
75 | fi; | |
76 | ||
77 | #define RANDOM_CACHE_READ_FROM_MEM(x, id)\ | |
78 | if \ | |
79 | :: 1 -> CACHE_READ_FROM_MEM(x, id); \ | |
80 | :: 1 -> skip \ | |
81 | fi; | |
82 | ||
83 | inline smp_rmb(i) | |
84 | { | |
85 | atomic { | |
86 | CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); | |
87 | CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); | |
88 | CACHE_READ_FROM_MEM(generation_ptr, get_pid()); | |
89 | } | |
90 | } | |
91 | ||
92 | inline smp_wmb(i) | |
93 | { | |
94 | atomic { | |
95 | CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); | |
96 | CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); | |
97 | CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); | |
98 | } | |
99 | } | |
100 | ||
101 | inline smp_mb(i) | |
102 | { | |
103 | atomic { | |
104 | #ifndef NO_WMB | |
105 | smp_wmb(i); | |
106 | #endif | |
107 | #ifndef NO_RMB | |
108 | smp_rmb(i); | |
109 | #endif | |
110 | skip; | |
111 | } | |
112 | } | |
113 | ||
114 | /* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ | |
115 | DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); | |
116 | /* Note ! currently only one reader */ | |
117 | DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); | |
118 | /* pointer generation */ | |
119 | DECLARE_CACHED_VAR(byte, generation_ptr, 0); | |
120 | ||
121 | byte last_free_gen = 0; | |
122 | bit free_done = 0; | |
123 | byte read_generation = 1; | |
124 | bit data_access = 0; | |
125 | ||
126 | inline ooo_mem(i) | |
127 | { | |
128 | atomic { | |
129 | RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); | |
130 | RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, | |
131 | get_pid()); | |
132 | RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); | |
133 | RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); | |
134 | RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, | |
135 | get_pid()); | |
136 | RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); | |
137 | } | |
138 | } | |
139 | ||
140 | #define get_readerid() (get_pid()) | |
141 | #define get_writerid() (get_readerid() + NR_READERS) | |
142 | ||
143 | inline wait_for_reader(tmp, id, i) | |
144 | { | |
145 | tmp = READ_CACHED_VAR(urcu_active_readers_one); | |
146 | ooo_mem(i); | |
147 | do | |
148 | :: (tmp & RCU_GP_CTR_NEST_MASK) && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) | |
149 | & RCU_GP_CTR_BIT) | |
150 | -> | |
151 | ooo_mem(i); | |
152 | skip; | |
153 | :: else -> | |
154 | break; | |
155 | od; | |
156 | } | |
157 | ||
158 | inline wait_for_quiescent_state(tmp, i, j) | |
159 | { | |
160 | i = 0; | |
161 | do | |
162 | :: i < NR_READERS -> | |
163 | wait_for_reader(tmp, i, j); | |
164 | i++ | |
165 | :: i >= NR_READERS -> break | |
166 | od; | |
167 | } | |
168 | ||
169 | /* Model the RCU read-side critical section. */ | |
170 | ||
171 | active [NR_READERS] proctype urcu_reader() | |
172 | { | |
173 | byte i; | |
174 | byte tmp, tmp2; | |
175 | ||
176 | assert(get_pid() < NR_PROCS); | |
177 | ||
178 | ooo_mem(i); | |
179 | tmp = READ_CACHED_VAR(urcu_active_readers_one); | |
180 | ooo_mem(i); | |
181 | if | |
182 | :: (!(tmp & RCU_GP_CTR_NEST_MASK)) | |
183 | -> | |
184 | tmp2 = READ_CACHED_VAR(urcu_gp_ctr); | |
185 | ooo_mem(i); | |
186 | WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); | |
187 | :: else -> | |
188 | WRITE_CACHED_VAR(urcu_active_readers_one, tmp + 1); | |
189 | fi; | |
190 | ooo_mem(i); | |
191 | smp_mb(i); | |
192 | read_generation = READ_CACHED_VAR(generation_ptr); | |
193 | ooo_mem(i); | |
194 | data_access = 1; | |
195 | ooo_mem(i); | |
196 | data_access = 0; | |
197 | ooo_mem(i); | |
198 | smp_mb(i); | |
199 | ooo_mem(i); | |
200 | tmp2 = READ_CACHED_VAR(urcu_active_readers_one); | |
201 | ooo_mem(i); | |
202 | WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); | |
203 | ooo_mem(i); | |
204 | //smp_mc(i); /* added */ | |
205 | } | |
206 | ||
207 | ||
208 | /* Model the RCU update process. */ | |
209 | ||
210 | active [NR_WRITERS] proctype urcu_writer() | |
211 | { | |
212 | byte i, j; | |
213 | byte tmp; | |
214 | byte old_gen; | |
215 | ||
216 | assert(get_pid() < NR_PROCS); | |
217 | ||
218 | ooo_mem(i); | |
219 | atomic { | |
220 | old_gen = READ_CACHED_VAR(generation_ptr); | |
221 | WRITE_CACHED_VAR(generation_ptr, old_gen + 1); | |
222 | } | |
223 | ooo_mem(i); | |
224 | ||
225 | smp_mb(i); | |
226 | ooo_mem(i); | |
227 | tmp = READ_CACHED_VAR(urcu_gp_ctr); | |
228 | ooo_mem(i); | |
229 | WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); | |
230 | ooo_mem(i); | |
231 | //smp_mc(i); | |
232 | wait_for_quiescent_state(tmp, i, j); | |
233 | //smp_mc(i); | |
234 | ooo_mem(i); | |
235 | tmp = READ_CACHED_VAR(urcu_gp_ctr); | |
236 | ooo_mem(i); | |
237 | WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); | |
238 | //smp_mc(i); | |
239 | ooo_mem(i); | |
240 | wait_for_quiescent_state(tmp, i, j); | |
241 | ooo_mem(i); | |
242 | smp_mb(i); | |
243 | /* free-up step, e.g., kfree(). */ | |
244 | ooo_mem(i); | |
245 | atomic { | |
246 | last_free_gen = old_gen; | |
247 | free_done = 1; | |
248 | } | |
249 | } |