Fix c99 compatibility: use __asm__ and __volatile__ in public headers

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

diff --git a/urcu/arch/alpha.h b/urcu/arch/alpha.h
index 300213e2ba616d9e35b8e3a6c33a110d1a08c474..9c81f0dfb989646b2551ba866c9d9267582338f0 100644 (file)
--- a/urcu/arch/alpha.h
+++ b/urcu/arch/alpha.h
@@ -28,9 +28,9 @@
 extern "C" {
 #endif
 
-#define cmm_mb()                       asm volatile("mb":::"memory")
-#define cmm_wmb()                      asm volatile("wmb":::"memory")
-#define cmm_read_barrier_depends()     asm volatile("mb":::"memory")
+#define cmm_mb()                       __asm__ __volatile__ ("mb":::"memory")
+#define cmm_wmb()                      __asm__ __volatile__ ("wmb":::"memory")
+#define cmm_read_barrier_depends()     __asm__ __volatile__ ("mb":::"memory")
 
 typedef unsigned long long cycles_t;
 

diff --git a/urcu/arch/arm.h b/urcu/arch/arm.h
index b49f7821052b5e00d0fd30d09145d72c95bc970a..e20695ecf3cf6acb142a1830fe5d527c0f4d0cf6 100644 (file)
--- a/urcu/arch/arm.h
+++ b/urcu/arch/arm.h
@@ -30,9 +30,9 @@ extern "C" {
 #endif 
 
 #ifdef CONFIG_RCU_ARM_HAVE_DMB
-#define cmm_mb()       asm volatile("dmb":::"memory")
-#define cmm_rmb()      asm volatile("dmb":::"memory")
-#define cmm_wmb()      asm volatile("dmb":::"memory")
+#define cmm_mb()       __asm__ __volatile__ ("dmb":::"memory")
+#define cmm_rmb()      __asm__ __volatile__ ("dmb":::"memory")
+#define cmm_wmb()      __asm__ __volatile__ ("dmb":::"memory")
 #endif /* CONFIG_RCU_ARM_HAVE_DMB */
 
 #include <stdlib.h>

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index 2fcbf5660958a12d2ad6dd957838ed73da4f2bec..95393ea0be0ee89b888c64ad53322e41e30631c8 100644 (file)
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -46,7 +46,7 @@ extern "C" {
  * order cacheable and non-cacheable memory operations separately---i.e.
  * not the latter against the former.
  */
-#define cmm_mb()         asm volatile("sync":::"memory")
+#define cmm_mb()         __asm__ __volatile__ ("sync":::"memory")
 
 /*
  * lwsync orders loads in cacheable memory with respect to other loads,
@@ -54,27 +54,27 @@ extern "C" {
  * Therefore, use it for barriers ordering accesses to cacheable memory
  * only.
  */
-#define cmm_smp_rmb()    asm volatile(LWSYNC_OPCODE:::"memory")
-#define cmm_smp_wmb()    asm volatile(LWSYNC_OPCODE:::"memory")
+#define cmm_smp_rmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
+#define cmm_smp_wmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
 
 #define mftbl()                                                \
        ({                                              \
                unsigned long rval;                     \
-               asm volatile("mftbl %0" : "=r" (rval)); \
+               __asm__ __volatile__ ("mftbl %0" : "=r" (rval));        \
                rval;                                   \
        })
 
 #define mftbu()                                                \
        ({                                              \
                unsigned long rval;                     \
-               asm volatile("mftbu %0" : "=r" (rval)); \
+               __asm__ __volatile__ ("mftbu %0" : "=r" (rval));        \
                rval;                                   \
        })
 
 #define mftb()                                         \
        ({                                              \
                unsigned long long rval;                \
-               asm volatile("mftb %0" : "=r" (rval));  \
+               __asm__ __volatile__ ("mftb %0" : "=r" (rval));         \
                rval;                                   \
        })
 

diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
index c1e2e072ff752582a93e90cb7189e45b14283870..5853604932793fb5fe40b5244fc5b33042393437 100644 (file)
--- a/urcu/arch/x86.h
+++ b/urcu/arch/x86.h
@@ -32,15 +32,15 @@ extern "C" {
 #define CAA_CACHE_LINE_SIZE    128
 
 #ifdef CONFIG_RCU_HAVE_FENCE
-#define cmm_mb()    asm volatile("mfence":::"memory")
+#define cmm_mb()    __asm__ __volatile__ ("mfence":::"memory")
 
 /*
  * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when
  * using SSE or working with I/O areas.  cmm_smp_rmb/cmm_smp_wmb are
  * only compiler barriers, which is enough for general use.
  */
-#define cmm_rmb()     asm volatile("lfence":::"memory")
-#define cmm_wmb()     asm volatile("sfence"::: "memory")
+#define cmm_rmb()     __asm__ __volatile__ ("lfence":::"memory")
+#define cmm_wmb()     __asm__ __volatile__ ("sfence"::: "memory")
 #define cmm_smp_rmb() cmm_barrier()
 #define cmm_smp_wmb() cmm_barrier()
 #else
@@ -55,17 +55,17 @@ extern "C" {
  * IDT WinChip supports weak store ordering, and the kernel may enable it
  * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
  */
-#define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_rmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-#define caa_cpu_relax()        asm volatile("rep; nop" : : : "memory");
+#define caa_cpu_relax()        __asm__ __volatile__ ("rep; nop" : : : "memory");
 
 #define rdtscll(val)                                                     \
        do {                                                              \
             unsigned int __a, __d;                                       \
-            asm volatile("rdtsc" : "=a" (__a), "=d" (__d));              \
+            __asm__ __volatile__ ("rdtsc" : "=a" (__a), "=d" (__d));     \
             (val) = ((unsigned long long)__a)                            \
                        | (((unsigned long long)__d) << 32);              \
        } while(0)

diff --git a/urcu/compiler.h b/urcu/compiler.h
index 974885a73f36c08e322bb6606bb3cd0e8e964ddd..0c6ece252ca0e8bee2a480ab45588bb8ccd15bcd 100644 (file)
--- a/urcu/compiler.h
+++ b/urcu/compiler.h
@@ -24,7 +24,7 @@
 #define caa_likely(x)  __builtin_expect(!!(x), 1)
 #define caa_unlikely(x)        __builtin_expect(!!(x), 0)
 
-#define        cmm_barrier()   asm volatile("" : : : "memory")
+#define        cmm_barrier()   __asm__ __volatile__ ("" : : : "memory")
 
 /*
  * Instruct the compiler to perform only a single access to a variable
@@ -38,7 +38,7 @@
  * use is to mediate communication between process-level code and irq/NMI
  * handlers, all running on the same CPU.
  */
-#define CMM_ACCESS_ONCE(x)     (*(volatile __typeof__(x) *)&(x))
+#define CMM_ACCESS_ONCE(x)     (*(__volatile__  __typeof__(x) *)&(x))
 
 #ifndef caa_max
 #define caa_max(a,b) ((a)>(b)?(a):(b))