From b4e52e3e9e563d38607a8e0ab0aa72e7ab2b47b4 Mon Sep 17 00:00:00 2001 From: Mathieu Desnoyers Date: Mon, 28 Sep 2009 23:32:27 -0400 Subject: [PATCH] define CACHE_LINE_SIZE in arch_*.h Signed-off-by: Mathieu Desnoyers --- tests/api_ppc.h | 4 ++-- tests/api_x86.h | 2 +- tests/test_mutex.c | 3 --- tests/test_perthreadlock.c | 3 --- tests/test_perthreadlock_timing.c | 3 --- tests/test_qsbr.c | 3 --- tests/test_qsbr_gc.c | 3 --- tests/test_qsbr_timing.c | 3 --- tests/test_rwlock.c | 3 --- tests/test_rwlock_timing.c | 3 --- tests/test_urcu.c | 3 --- tests/test_urcu_defer.c | 3 --- tests/test_urcu_gc.c | 3 --- tests/test_urcu_timing.c | 3 --- urcu/arch_ppc.h | 3 +++ urcu/arch_x86.h | 2 ++ 16 files changed, 8 insertions(+), 39 deletions(-) diff --git a/tests/api_ppc.h b/tests/api_ppc.h index da12019..c351d4d 100644 --- a/tests/api_ppc.h +++ b/tests/api_ppc.h @@ -73,7 +73,7 @@ #define CONFIG_PPC64 -#define CACHE_LINE_SIZE 128 +/*#define CACHE_LINE_SIZE 128 */ #define ____cacheline_internodealigned_in_smp \ __attribute__((__aligned__(1 << 7))) @@ -665,7 +665,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) */ #ifndef CACHE_LINE_SIZE -#define CACHE_LINE_SIZE 128 +/* #define CACHE_LINE_SIZE 128 */ #endif /* #ifndef CACHE_LINE_SIZE */ /* diff --git a/tests/api_x86.h b/tests/api_x86.h index 77d86a1..95f4c93 100644 --- a/tests/api_x86.h +++ b/tests/api_x86.h @@ -71,7 +71,7 @@ * Machine parameters. */ -#define CACHE_LINE_SIZE 64 +/* #define CACHE_LINE_SIZE 64 */ #define ____cacheline_internodealigned_in_smp \ __attribute__((__aligned__(1 << 6))) diff --git a/tests/test_mutex.c b/tests/test_mutex.c index e3b1b64..f2ef706 100644 --- a/tests/test_mutex.c +++ b/tests/test_mutex.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_perthreadlock.c b/tests/test_perthreadlock.c index ea47e46..8e0800f 100644 --- a/tests/test_perthreadlock.c +++ b/tests/test_perthreadlock.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_perthreadlock_timing.c b/tests/test_perthreadlock_timing.c index 10720cb..9761f5d 100644 --- a/tests/test_perthreadlock_timing.c +++ b/tests/test_perthreadlock_timing.c @@ -34,9 +34,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c index cf2fec2..6230510 100644 --- a/tests/test_qsbr.c +++ b/tests/test_qsbr.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_qsbr_gc.c b/tests/test_qsbr_gc.c index d32d1a0..9766067 100644 --- a/tests/test_qsbr_gc.c +++ b/tests/test_qsbr_gc.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_qsbr_timing.c b/tests/test_qsbr_timing.c index 3585f83..bbe983e 100644 --- a/tests/test_qsbr_timing.c +++ b/tests/test_qsbr_timing.c @@ -32,9 +32,6 @@ #include #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) diff --git a/tests/test_rwlock.c b/tests/test_rwlock.c index d3f072c..923ecad 100644 --- a/tests/test_rwlock.c +++ b/tests/test_rwlock.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_rwlock_timing.c b/tests/test_rwlock_timing.c index b26f83d..c5c9478 100644 --- a/tests/test_rwlock_timing.c +++ b/tests/test_rwlock_timing.c @@ -33,9 +33,6 @@ #include #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) diff --git a/tests/test_urcu.c b/tests/test_urcu.c index 8d090eb..3b838c1 100644 --- a/tests/test_urcu.c +++ b/tests/test_urcu.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c index 1c6f742..08e3e60 100644 --- a/tests/test_urcu_defer.c +++ b/tests/test_urcu_defer.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_urcu_gc.c b/tests/test_urcu_gc.c index 60f7816..162fae0 100644 --- a/tests/test_urcu_gc.c +++ b/tests/test_urcu_gc.c @@ -35,9 +35,6 @@ #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - /* hardcoded number of CPUs */ #define NR_CPUS 16384 diff --git a/tests/test_urcu_timing.c b/tests/test_urcu_timing.c index 27d9730..13c0993 100644 --- a/tests/test_urcu_timing.c +++ b/tests/test_urcu_timing.c @@ -32,9 +32,6 @@ #include #include -/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ -#define CACHE_LINE_SIZE 4096 - #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h index 8dfd6d1..aaf61d3 100644 --- a/urcu/arch_ppc.h +++ b/urcu/arch_ppc.h @@ -28,6 +28,9 @@ #define CONFIG_HAVE_FENCE 1 #define CONFIG_HAVE_MEM_COHERENCY +/* Include size of POWER5+ L3 cache lines: 256 bytes */ +#define CACHE_LINE_SIZE 256 + #ifndef BITS_PER_LONG #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #endif diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h index 29612e0..d455b89 100644 --- a/urcu/arch_x86.h +++ b/urcu/arch_x86.h @@ -29,6 +29,8 @@ #define CONFIG_HAVE_FENCE 1 #define CONFIG_HAVE_MEM_COHERENCY +#define CACHE_LINE_SIZE 128 + #ifndef BITS_PER_LONG #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #endif -- 2.34.1