From 06e8b2a87f862183a26e0005bf04221633f49d0c Mon Sep 17 00:00:00 2001 From: Mathieu Desnoyers Date: Thu, 18 Jun 2009 16:26:17 -0400 Subject: [PATCH] Add nosched model results (for signal readers) Signed-off-by: Mathieu Desnoyers --- .../result-signal-over-reader/DEFINES | 17 + .../result-signal-over-reader/Makefile | 172 + .../result-signal-over-reader/asserts.log | 312 + .../asserts.spin.input | 722 + .../asserts.spin.input.trail | 6 + .../result-signal-over-reader/references.txt | 13 + .../result-signal-over-reader/urcu.sh | 29 + .../result-signal-over-reader/urcu.spin | 705 + .../result-signal-over-reader/urcu_free.log | 326 + .../result-signal-over-reader/urcu_free.ltl | 1 + .../urcu_free.spin.input | 722 + .../urcu_free.spin.input.trail | 15043 ++++++++++ .../urcu_free_nested.define | 1 + .../urcu_free_nested.log | 20 + .../urcu_free_nested.spin.input | 696 + .../urcu_free_nested.spin.input.trail | 11161 ++++++++ .../urcu_free_no_mb.define | 2 + .../urcu_free_no_mb.log | 303 + .../urcu_free_no_mb.spin.input | 724 + .../urcu_free_no_mb.spin.input.trail | 2144 ++ .../urcu_free_no_rmb.define | 1 + .../urcu_free_no_rmb.log | 300 + .../urcu_free_no_rmb.spin.input | 723 + .../urcu_free_no_rmb.spin.input.trail | 1777 ++ .../urcu_free_no_wmb.define | 1 + .../urcu_free_no_wmb.log | 320 + .../urcu_free_no_wmb.spin.input | 723 + .../urcu_free_no_wmb.spin.input.trail | 1653 ++ .../urcu_free_single_flip.define | 1 + .../urcu_free_single_flip.log | 217 + .../urcu_free_single_flip.spin.input | 723 + .../urcu_free_single_flip.spin.input.trail | 1355 + .../urcu_progress.ltl | 1 + .../urcu_progress_reader.define | 1 + .../urcu_progress_reader.log | 506 + .../urcu_progress_reader.spin.input | 723 + .../urcu_progress_reader.spin.input.trail | 1270 + .../urcu_progress_writer.define | 1 + .../urcu_progress_writer.log | 524 + .../urcu_progress_writer.spin.input | 723 + .../urcu_progress_writer.spin.input.trail | 9 + .../urcu_progress_writer_error.define | 2 + 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.../testmerge/urcu.spin | 500 + .../testmerge/urcu.spin.bkp2 | 395 + .../testmerge/urcu.spin.bkp5 | 398 + .../testmerge/urcu_free.log | 414 + .../testmerge/urcu_free.ltl | 1 + .../testmerge/urcu_free.spin.input | 531 + .../testmerge/urcu_free.spin.input.trail | 1902 ++ .../testmerge/urcu_free_nested.define | 0 .../testmerge/urcu_free_nested.log | 415 + .../testmerge/urcu_free_nested.spin.input | 531 + .../urcu_free_nested.spin.input.trail | 7 + .../testmerge/urcu_free_no_mb.define | 2 + .../testmerge/urcu_free_no_mb.log | 16 + .../testmerge/urcu_free_no_mb.spin.input | 533 + .../urcu_free_no_mb.spin.input.trail | 2082 ++ .../testmerge/urcu_free_no_rmb.define | 1 + .../testmerge/urcu_free_no_rmb.log | 369 + .../testmerge/urcu_free_no_rmb.spin.input | 532 + .../urcu_free_no_rmb.spin.input.trail | 1739 ++ .../testmerge/urcu_free_no_wmb.define | 1 + .../testmerge/urcu_free_no_wmb.log | 381 + .../testmerge/urcu_free_no_wmb.spin.input | 532 + .../urcu_free_no_wmb.spin.input.trail | 1892 ++ .../testmerge/urcu_free_single_flip.define | 1 + .../testmerge/urcu_free_single_flip.log | 349 + .../urcu_free_single_flip.spin.input | 532 + .../urcu_free_single_flip.spin.input.trail | 1356 + .../testmerge/urcu_progress.ltl | 1 + .../testmerge/urcu_progress_reader.define | 1 + .../testmerge/urcu_progress_reader.log | 16 + .../testmerge/urcu_progress_reader.spin.input | 410 + .../urcu_progress_reader.spin.input.trail | 9 + .../testmerge/urcu_progress_writer.define | 1 + .../testmerge/urcu_progress_writer.log | 14 + .../testmerge/urcu_progress_writer.spin.input | 410 + .../urcu_progress_writer.spin.input.trail | 9 + .../urcu_progress_writer_error.define | 2 + .../testmerge/urcu_progress_writer_error.log | 16 + .../urcu_progress_writer_error.spin.input | 411 + ...rcu_progress_writer_error.spin.input.trail | 4590 +++ .../result-signal-over-writer/urcu.sh | 29 + .../result-signal-over-writer/urcu.spin | 705 + .../result-signal-over-writer/urcu_free.log | 345 + .../result-signal-over-writer/urcu_free.ltl | 1 + .../urcu_free.spin.input | 721 + .../urcu_free.spin.input.trail | 15043 ++++++++++ .../urcu_free_nested.define | 1 + .../urcu_free_nested.log | 232 + .../urcu_free_nested.spin.input | 696 + .../urcu_free_nested.spin.input.trail | 11161 ++++++++ .../urcu_free_no_mb.define | 2 + .../urcu_free_no_mb.log | 382 + .../urcu_free_no_mb.spin.input | 723 + .../urcu_free_no_mb.spin.input.trail | 2172 ++ .../urcu_free_no_rmb.define | 1 + .../urcu_free_no_rmb.log | 280 + .../urcu_free_no_rmb.spin.input | 722 + .../urcu_free_no_rmb.spin.input.trail | 1805 ++ .../urcu_free_no_wmb.define | 1 + .../urcu_free_no_wmb.log | 224 + .../urcu_free_no_wmb.spin.input | 722 + .../urcu_free_no_wmb.spin.input.trail | 1677 ++ .../urcu_free_single_flip.define | 1 + .../urcu_free_single_flip.log | 224 + .../urcu_free_single_flip.spin.input | 722 + .../urcu_free_single_flip.spin.input.trail | 1379 + .../urcu_progress.ltl | 1 + .../urcu_progress_reader.define | 1 + .../urcu_progress_reader.log | 348 + .../urcu_progress_reader.spin.input | 722 + .../urcu_progress_reader.spin.input.trail | 1270 + .../urcu_progress_writer.define | 1 + .../urcu_progress_writer.log | 348 + .../urcu_progress_writer.spin.input | 722 + .../urcu_progress_writer.spin.input.trail | 9 + .../urcu_progress_writer_error.define | 2 + .../urcu_progress_writer_error.log | 286 + .../urcu_progress_writer_error.spin.input | 723 + ...rcu_progress_writer_error.spin.input.trail | 4231 +++ .../result-standard-execution-nest/DEFINES | 17 + .../result-standard-execution-nest/Makefile | 172 + .../asserts.log | 250 + .../asserts.spin.input | 722 + .../asserts.spin.input.trail | 6 + .../references.txt | 13 + .../result-standard-execution-nest/urcu.sh | 29 + .../result-standard-execution-nest/urcu.spin | 705 + .../urcu_free.log | 262 + .../urcu_free.ltl | 1 + .../urcu_free.spin.input | 722 + .../urcu_free.spin.input.trail | 15043 ++++++++++ .../urcu_free_nested.define | 1 + .../urcu_free_nested.log | 20 + .../urcu_free_nested.spin.input | 696 + .../urcu_free_nested.spin.input.trail | 11161 ++++++++ .../urcu_free_no_mb.define | 2 + .../urcu_free_no_mb.log | 267 + .../urcu_free_no_mb.spin.input | 724 + .../urcu_free_no_mb.spin.input.trail | 2149 ++ .../urcu_free_no_rmb.define | 1 + .../urcu_free_no_rmb.log | 266 + .../urcu_free_no_rmb.spin.input | 723 + .../urcu_free_no_rmb.spin.input.trail | 1804 ++ .../urcu_free_no_wmb.define | 1 + .../urcu_free_no_wmb.log | 294 + .../urcu_free_no_wmb.spin.input | 723 + .../urcu_free_no_wmb.spin.input.trail | 1885 ++ .../urcu_free_single_flip.define | 1 + .../urcu_free_single_flip.log | 197 + .../urcu_free_single_flip.spin.input | 723 + .../urcu_free_single_flip.spin.input.trail | 1374 + .../urcu_progress.ltl | 1 + .../urcu_progress_reader.define | 1 + .../urcu_progress_reader.log | 275 + .../urcu_progress_reader.spin.input | 723 + .../urcu_progress_reader.spin.input.trail | 1270 + .../urcu_progress_writer.define | 1 + .../urcu_progress_writer.log | 275 + .../urcu_progress_writer.spin.input | 723 + .../urcu_progress_writer.spin.input.trail | 9 + .../urcu_progress_writer_error.define | 2 + .../urcu_progress_writer_error.log | 514 + .../urcu_progress_writer_error.spin.input | 724 + ...rcu_progress_writer_error.spin.input.trail | 4823 ++++ 190 files changed, 193454 insertions(+) create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/DEFINES create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/Makefile create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/asserts.log create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/references.txt create mode 100644 formal-model/urcu-nosched-model/result-signal-over-reader/urcu.sh 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formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.log create mode 100644 formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.spin.input create mode 100644 formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/DEFINES create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/Makefile create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/references.txt create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.sh create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.spin create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.ltl create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress.ltl create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.spin.input.trail create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.define create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.log create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.spin.input create mode 100644 formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/DEFINES b/formal-model/urcu-nosched-model/result-signal-over-reader/DEFINES new file mode 100644 index 0000000..2fcb038 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/DEFINES @@ -0,0 +1,17 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/Makefile b/formal-model/urcu-nosched-model/result-signal-over-reader/Makefile new file mode 100644 index 0000000..8af320d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/Makefile @@ -0,0 +1,172 @@ +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) Mathieu Desnoyers, 2009 +# +# Authors: Mathieu Desnoyers + +#CFLAGS=-DSAFETY +#for multi-core verif, 15.5GB shared mem, use files if full +#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2 +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8 + +#liveness +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 +CFLAGS=-DHASH64 + +SPINFILE=urcu.spin + +default: + make urcu_free | tee urcu_free.log + #nested useless with signal test. + #make urcu_free_nested | tee urcu_free_nested.log + make urcu_free_no_rmb | tee urcu_free_no_rmb.log + make urcu_free_no_wmb | tee urcu_free_no_wmb.log + make urcu_free_no_mb | tee urcu_free_no_mb.log + make urcu_free_single_flip | tee urcu_free_single_flip.log + make urcu_progress_writer | tee urcu_progress_writer.log + make urcu_progress_reader | tee urcu_progress_reader.log + make urcu_progress_writer_error | tee urcu_progress_writer_error.log + make asserts | tee asserts.log + make summary + +#show trail : spin -v -t -N pan.ltl input.spin +# after each individual make. + +summary: + @echo + @echo "Verification summary" + @grep errors: *.log + +asserts: clean + cat DEFINES > .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X .input.spin + gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c + ./pan -v -c1 -X -m10000000 -w20 + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free: clean urcu_free_ltl run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested_define: + cp urcu_free_nested.define .input.define + +urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_rmb_define: + cp urcu_free_no_rmb.define .input.define + +urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_wmb_define: + cp urcu_free_no_wmb.define .input.define + +urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_mb_define: + cp urcu_free_no_mb.define .input.define + +urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_single_flip_define: + cp urcu_free_single_flip.define .input.define + +urcu_free_ltl: + touch .input.define + cat .input.define >> pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl + +# Progress checks + +urcu_progress_writer: clean urcu_progress_writer_ltl \ + urcu_progress_writer_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_define: + cp urcu_progress_writer.define .input.define + +urcu_progress_writer_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_reader: clean urcu_progress_reader_ltl \ + urcu_progress_reader_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_reader_define: + cp urcu_progress_reader.define .input.define + +urcu_progress_reader_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \ + urcu_progress_writer_error_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_error_define: + cp urcu_progress_writer_error.define .input.define + +urcu_progress_writer_error_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + + +run_weak_fair: pan + ./pan -a -f -v -c1 -X -m10000000 -w20 + +run: pan + ./pan -a -v -c1 -X -m10000000 -w20 + +pan: pan.c + gcc -O2 -w ${CFLAGS} -o pan pan.c + +pan.c: pan.ltl ${SPINFILE} + cat .input.define > .input.spin + cat DEFINES >> .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X -N pan.ltl .input.spin + +.PHONY: clean default distclean summary +clean: + rm -f pan* trail.out .input.spin* *.spin.trail .input.define +distclean: + rm -f *.trail *.input *.log diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.log b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.log new file mode 100644 index 0000000..d317f57 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.log @@ -0,0 +1,312 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +cat DEFINES > .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w20 +Depth= 4926 States= 1e+06 Transitions= 9.03e+06 Memory= 527.287 t= 5.98 R= 2e+05 +Depth= 7228 States= 2e+06 Transitions= 1.88e+07 Memory= 588.322 t= 12.9 R= 2e+05 +Depth= 7228 States= 3e+06 Transitions= 3.14e+07 Memory= 649.358 t= 21.9 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 7228 States= 4e+06 Transitions= 4.3e+07 Memory= 741.416 t= 30.3 R= 1e+05 +Depth= 7228 States= 5e+06 Transitions= 5.65e+07 Memory= 802.451 t= 39.6 R= 1e+05 +Depth= 7228 States= 6e+06 Transitions= 6.78e+07 Memory= 863.486 t= 47.5 R= 1e+05 +Depth= 7228 States= 7e+06 Transitions= 8.05e+07 Memory= 924.522 t= 56.5 R= 1e+05 +Depth= 7228 States= 8e+06 Transitions= 9.49e+07 Memory= 985.557 t= 66.8 R= 1e+05 +Depth= 7228 States= 9e+06 Transitions= 1.06e+08 Memory= 1046.592 t= 74.7 R= 1e+05 +pan: resizing hashtable to -w24.. done +Depth= 7228 States= 1e+07 Transitions= 1.18e+08 Memory= 1231.721 t= 84.9 R= 1e+05 +Depth= 7228 States= 1.1e+07 Transitions= 1.29e+08 Memory= 1292.756 t= 92.8 R= 1e+05 +Depth= 7228 States= 1.2e+07 Transitions= 1.4e+08 Memory= 1353.791 t= 100 R= 1e+05 +Depth= 7228 States= 1.3e+07 Transitions= 1.53e+08 Memory= 1414.826 t= 109 R= 1e+05 +Depth= 7228 States= 1.4e+07 Transitions= 1.65e+08 Memory= 1475.861 t= 117 R= 1e+05 +Depth= 7228 States= 1.5e+07 Transitions= 1.77e+08 Memory= 1536.897 t= 126 R= 1e+05 +Depth= 7228 States= 1.6e+07 Transitions= 1.89e+08 Memory= 1597.932 t= 134 R= 1e+05 +Depth= 7228 States= 1.7e+07 Transitions= 2.02e+08 Memory= 1658.967 t= 143 R= 1e+05 +Depth= 7228 States= 1.8e+07 Transitions= 2.16e+08 Memory= 1720.002 t= 153 R= 1e+05 +Depth= 7228 States= 1.9e+07 Transitions= 2.27e+08 Memory= 1781.037 t= 160 R= 1e+05 +Depth= 7228 States= 2e+07 Transitions= 2.39e+08 Memory= 1842.072 t= 169 R= 1e+05 +Depth= 7228 States= 2.1e+07 Transitions= 2.51e+08 Memory= 1903.108 t= 177 R= 1e+05 +Depth= 7228 States= 2.2e+07 Transitions= 2.62e+08 Memory= 1964.143 t= 185 R= 1e+05 +Depth= 7228 States= 2.3e+07 Transitions= 2.74e+08 Memory= 2025.178 t= 194 R= 1e+05 +Depth= 7228 States= 2.4e+07 Transitions= 2.86e+08 Memory= 2086.213 t= 203 R= 1e+05 +Depth= 7228 States= 2.5e+07 Transitions= 2.99e+08 Memory= 2147.248 t= 212 R= 1e+05 +Depth= 7228 States= 2.6e+07 Transitions= 3.1e+08 Memory= 2208.283 t= 220 R= 1e+05 +Depth= 7228 States= 2.7e+07 Transitions= 3.24e+08 Memory= 2269.318 t= 230 R= 1e+05 +Depth= 7228 States= 2.8e+07 Transitions= 3.37e+08 Memory= 2330.354 t= 239 R= 1e+05 +Depth= 7228 States= 2.9e+07 Transitions= 3.49e+08 Memory= 2391.389 t= 248 R= 1e+05 +Depth= 7228 States= 3e+07 Transitions= 3.6e+08 Memory= 2452.424 t= 256 R= 1e+05 +Depth= 7228 States= 3.1e+07 Transitions= 3.72e+08 Memory= 2513.459 t= 265 R= 1e+05 +Depth= 7228 States= 3.2e+07 Transitions= 3.83e+08 Memory= 2574.494 t= 273 R= 1e+05 +Depth= 7228 States= 3.3e+07 Transitions= 3.95e+08 Memory= 2635.529 t= 282 R= 1e+05 +Depth= 7228 States= 3.4e+07 Transitions= 4.07e+08 Memory= 2696.565 t= 291 R= 1e+05 +pan: resizing hashtable to -w26.. done +Depth= 7228 States= 3.5e+07 Transitions= 4.2e+08 Memory= 3253.682 t= 308 R= 1e+05 +Depth= 7228 States= 3.6e+07 Transitions= 4.32e+08 Memory= 3314.717 t= 316 R= 1e+05 +Depth= 7228 States= 3.7e+07 Transitions= 4.45e+08 Memory= 3375.752 t= 325 R= 1e+05 +Depth= 7228 States= 3.8e+07 Transitions= 4.58e+08 Memory= 3436.787 t= 334 R= 1e+05 +Depth= 7228 States= 3.9e+07 Transitions= 4.71e+08 Memory= 3497.822 t= 343 R= 1e+05 +Depth= 7228 States= 4e+07 Transitions= 4.82e+08 Memory= 3558.858 t= 350 R= 1e+05 +Depth= 7228 States= 4.1e+07 Transitions= 4.94e+08 Memory= 3619.893 t= 359 R= 1e+05 +Depth= 7228 States= 4.2e+07 Transitions= 5.04e+08 Memory= 3680.928 t= 366 R= 1e+05 +Depth= 7228 States= 4.3e+07 Transitions= 5.16e+08 Memory= 3741.963 t= 374 R= 1e+05 +Depth= 7228 States= 4.4e+07 Transitions= 5.29e+08 Memory= 3802.998 t= 383 R= 1e+05 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim - (none specified) + assertion violations + + cycle checks - (disabled by -DSAFETY) + invalid end states + + +State-vector 56 byte, depth reached 7228, errors: 0 + 44157204 states, stored +4.8641845e+08 states, matched +5.3057565e+08 transitions (= stored+matched) +1.8453582e+09 atomic steps +hash conflicts: 2.8837553e+08 (resolved) + +Stats on memory usage (in Megabytes): + 3537.374 equivalent memory usage for states (stored*(State-vector + overhead)) + 2843.050 actual memory usage for states (compression: 80.37%) + state-vector as stored = 40 byte + 28 byte overhead + 512.000 memory used for hash table (-w26) + 457.764 memory used for DFS stack (-m10000000) + 3812.568 total actual memory usage + +unreached in proctype urcu_reader + line 398, ".input.spin", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 61, "(1)" + line 417, ".input.spin", state 91, "(1)" + line 398, ".input.spin", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 158, "(1)" + line 417, ".input.spin", state 188, "(1)" + line 398, ".input.spin", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 256, "(1)" + line 417, ".input.spin", state 286, "(1)" + line 398, ".input.spin", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 395, "(1)" + line 417, ".input.spin", state 425, "(1)" + line 539, ".input.spin", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 398, ".input.spin", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 70, "(1)" + line 417, ".input.spin", state 100, "(1)" + line 398, ".input.spin", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 158, "(1)" + line 417, ".input.spin", state 188, "(1)" + line 398, ".input.spin", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 247, "(1)" + line 417, ".input.spin", state 277, "(1)" + line 398, ".input.spin", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 359, "(1)" + line 417, ".input.spin", state 389, "(1)" + line 613, ".input.spin", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 398, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 59, "(1)" + line 412, ".input.spin", state 72, "(1)" + line 417, ".input.spin", state 89, "(1)" + line 398, ".input.spin", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 153, "(1)" + line 412, ".input.spin", state 166, "(1)" + line 651, ".input.spin", state 199, "(1)" + line 174, ".input.spin", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 178, ".input.spin", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 240, "(1)" + line 163, ".input.spin", state 248, "(1)" + line 167, ".input.spin", state 260, "(1)" + line 174, ".input.spin", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, ".input.spin", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 370, "(1)" + line 163, ".input.spin", state 378, "(1)" + line 167, ".input.spin", state 390, "(1)" + line 398, ".input.spin", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 449, "(1)" + line 412, ".input.spin", state 462, "(1)" + line 417, ".input.spin", state 479, "(1)" + line 398, ".input.spin", state 498, "(1)" + line 402, ".input.spin", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 554, "(1)" + line 417, ".input.spin", state 571, "(1)" + line 402, ".input.spin", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 647, "(1)" + line 417, ".input.spin", state 664, "(1)" + line 178, ".input.spin", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 710, "(1)" + line 163, ".input.spin", state 718, "(1)" + line 167, ".input.spin", state 730, "(1)" + line 174, ".input.spin", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, ".input.spin", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 840, "(1)" + line 163, ".input.spin", state 848, "(1)" + line 167, ".input.spin", state 860, "(1)" + line 398, ".input.spin", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, ".input.spin", state 884, "(1)" + line 398, ".input.spin", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, ".input.spin", state 885, "else" + line 398, ".input.spin", state 888, "(1)" + line 402, ".input.spin", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 898, "(1)" + line 402, ".input.spin", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 899, "else" + line 402, ".input.spin", state 902, "(1)" + line 402, ".input.spin", state 903, "(1)" + line 402, ".input.spin", state 903, "(1)" + line 400, ".input.spin", state 908, "((i<1))" + line 400, ".input.spin", state 908, "((i>=1))" + line 407, ".input.spin", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 927, "(1)" + line 408, ".input.spin", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 408, ".input.spin", state 928, "else" + line 408, ".input.spin", state 931, "(1)" + line 408, ".input.spin", state 932, "(1)" + line 408, ".input.spin", state 932, "(1)" + line 412, ".input.spin", state 940, "(1)" + line 412, ".input.spin", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 412, ".input.spin", state 941, "else" + line 412, ".input.spin", state 944, "(1)" + line 412, ".input.spin", state 945, "(1)" + line 412, ".input.spin", state 945, "(1)" + line 410, ".input.spin", state 950, "((i<1))" + line 410, ".input.spin", state 950, "((i>=1))" + line 417, ".input.spin", state 957, "(1)" + line 417, ".input.spin", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 417, ".input.spin", state 958, "else" + line 417, ".input.spin", state 961, "(1)" + line 417, ".input.spin", state 962, "(1)" + line 417, ".input.spin", state 962, "(1)" + line 419, ".input.spin", state 965, "(1)" + line 419, ".input.spin", state 965, "(1)" + line 402, ".input.spin", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 1040, "(1)" + line 417, ".input.spin", state 1057, "(1)" + line 402, ".input.spin", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 1130, "(1)" + line 417, ".input.spin", state 1147, "(1)" + line 398, ".input.spin", state 1166, "(1)" + line 402, ".input.spin", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 1222, "(1)" + line 417, ".input.spin", state 1239, "(1)" + line 402, ".input.spin", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, ".input.spin", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, ".input.spin", state 1315, "(1)" + line 417, ".input.spin", state 1332, "(1)" + line 178, ".input.spin", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 1378, "(1)" + line 163, ".input.spin", state 1386, "(1)" + line 167, ".input.spin", state 1398, "(1)" + line 174, ".input.spin", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, ".input.spin", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 1508, "(1)" + line 163, ".input.spin", state 1516, "(1)" + line 167, ".input.spin", state 1528, "(1)" + line 398, ".input.spin", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, ".input.spin", state 1552, "(1)" + line 398, ".input.spin", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, ".input.spin", state 1553, "else" + line 398, ".input.spin", state 1556, "(1)" + line 402, ".input.spin", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 1566, "(1)" + line 402, ".input.spin", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, ".input.spin", state 1567, "else" + line 402, ".input.spin", state 1570, "(1)" + line 402, ".input.spin", state 1571, "(1)" + line 402, ".input.spin", state 1571, "(1)" + line 400, ".input.spin", state 1576, "((i<1))" + line 400, ".input.spin", state 1576, "((i>=1))" + line 407, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, ".input.spin", state 1595, "(1)" + line 408, ".input.spin", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 408, ".input.spin", state 1596, "else" + line 408, ".input.spin", state 1599, "(1)" + line 408, ".input.spin", state 1600, "(1)" + line 408, ".input.spin", state 1600, "(1)" + line 412, ".input.spin", state 1608, "(1)" + line 412, ".input.spin", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 412, ".input.spin", state 1609, "else" + line 412, ".input.spin", state 1612, "(1)" + line 412, ".input.spin", state 1613, "(1)" + line 412, ".input.spin", state 1613, "(1)" + line 410, ".input.spin", state 1618, "((i<1))" + line 410, ".input.spin", state 1618, "((i>=1))" + line 417, ".input.spin", state 1625, "(1)" + line 417, ".input.spin", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 417, ".input.spin", state 1626, "else" + line 417, ".input.spin", state 1629, "(1)" + line 417, ".input.spin", state 1630, "(1)" + line 417, ".input.spin", state 1630, "(1)" + line 419, ".input.spin", state 1633, "(1)" + line 419, ".input.spin", state 1633, "(1)" + line 178, ".input.spin", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 1681, "(1)" + line 163, ".input.spin", state 1689, "(1)" + line 167, ".input.spin", state 1701, "(1)" + line 174, ".input.spin", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, ".input.spin", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, ".input.spin", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, ".input.spin", state 1811, "(1)" + line 163, ".input.spin", state 1819, "(1)" + line 167, ".input.spin", state 1831, "(1)" + line 701, ".input.spin", state 1856, "-end-" + (158 of 1856 states) +unreached in proctype :init: + (0 of 46 states) + +pan: elapsed time 384 seconds +pan: rate 114968.77 states/second +pan: avg transition delay 7.2389e-07 usec +cp .input.spin asserts.spin.input +cp .input.spin.trail asserts.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input new file mode 100644 index 0000000..2d7f62d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input @@ -0,0 +1,722 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input.trail new file mode 100644 index 0000000..287e52a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/asserts.spin.input.trail @@ -0,0 +1,6 @@ +-4:-4:-4 +1:0:2673 +2:0:2674 +3:0:2675 +4:0:2676 +5:4:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/references.txt b/formal-model/urcu-nosched-model/result-signal-over-reader/references.txt new file mode 100644 index 0000000..72c67a2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/references.txt @@ -0,0 +1,13 @@ +http://spinroot.com/spin/Man/ltl.html +http://en.wikipedia.org/wiki/Linear_temporal_logic +http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt + +http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php +http://spinroot.com/spin/Man/index.html +http://spinroot.com/spin/Man/promela.html + +LTL vs CTL : + +http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18 +http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf + (downloaded) diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.sh b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.sh new file mode 100644 index 0000000..65ff517 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.sh @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Compiles and runs the urcu.spin Promela model. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) IBM Corporation, 2009 +# Mathieu Desnoyers, 2009 +# +# Authors: Paul E. McKenney +# Mathieu Desnoyers + +# Basic execution, without LTL clauses. See Makefile. + +spin -a urcu.spin +cc -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w21 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.spin b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.spin new file mode 100644 index 0000000..2cfcb70 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu.spin @@ -0,0 +1,705 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.log new file mode 100644 index 0000000..a6ab537 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.log @@ -0,0 +1,326 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 743) +Depth= 6837 States= 1e+06 Transitions= 9.03e+06 Memory= 534.904 t= 7.74 R= 1e+05 +Depth= 8887 States= 2e+06 Transitions= 1.88e+07 Memory= 603.557 t= 16.6 R= 1e+05 +Depth= 8887 States= 3e+06 Transitions= 3.14e+07 Memory= 672.209 t= 28 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 8887 States= 4e+06 Transitions= 4.33e+07 Memory= 771.885 t= 39.1 R= 1e+05 +Depth= 8887 States= 5e+06 Transitions= 5.65e+07 Memory= 840.635 t= 50.7 R= 1e+05 +Depth= 8887 States= 6e+06 Transitions= 6.79e+07 Memory= 909.287 t= 61 R= 1e+05 +Depth= 8887 States= 7e+06 Transitions= 8.08e+07 Memory= 977.940 t= 72.6 R= 1e+05 +Depth= 8887 States= 8e+06 Transitions= 9.5e+07 Memory= 1046.592 t= 85.5 R= 9e+04 +Depth= 8887 States= 9e+06 Transitions= 1.07e+08 Memory= 1115.342 t= 96.7 R= 9e+04 +pan: resizing hashtable to -w24.. done +Depth= 8887 States= 1e+07 Transitions= 1.18e+08 Memory= 1308.088 t= 108 R= 9e+04 +Depth= 8887 States= 1.1e+07 Transitions= 1.3e+08 Memory= 1376.740 t= 119 R= 9e+04 +Depth= 8887 States= 1.2e+07 Transitions= 1.41e+08 Memory= 1445.393 t= 128 R= 9e+04 +Depth= 8887 States= 1.3e+07 Transitions= 1.51e+08 Memory= 1514.045 t= 138 R= 9e+04 +Depth= 8887 States= 1.4e+07 Transitions= 1.64e+08 Memory= 1582.795 t= 149 R= 9e+04 +Depth= 8887 States= 1.5e+07 Transitions= 1.77e+08 Memory= 1651.447 t= 160 R= 9e+04 +Depth= 8887 States= 1.6e+07 Transitions= 1.9e+08 Memory= 1720.100 t= 172 R= 9e+04 +Depth= 8887 States= 1.7e+07 Transitions= 2.02e+08 Memory= 1788.752 t= 183 R= 9e+04 +Depth= 8887 States= 1.8e+07 Transitions= 2.15e+08 Memory= 1857.502 t= 194 R= 9e+04 +Depth= 8887 States= 1.9e+07 Transitions= 2.29e+08 Memory= 1926.154 t= 207 R= 9e+04 +Depth= 8887 States= 2e+07 Transitions= 2.4e+08 Memory= 1994.807 t= 217 R= 9e+04 +Depth= 8887 States= 2.1e+07 Transitions= 2.51e+08 Memory= 2063.459 t= 227 R= 9e+04 +Depth= 8887 States= 2.2e+07 Transitions= 2.63e+08 Memory= 2132.209 t= 238 R= 9e+04 +Depth= 8887 States= 2.3e+07 Transitions= 2.74e+08 Memory= 2200.861 t= 248 R= 9e+04 +Depth= 8887 States= 2.4e+07 Transitions= 2.86e+08 Memory= 2269.514 t= 259 R= 9e+04 +Depth= 8887 States= 2.5e+07 Transitions= 2.98e+08 Memory= 2338.166 t= 270 R= 9e+04 +Depth= 8887 States= 2.6e+07 Transitions= 3.1e+08 Memory= 2406.916 t= 281 R= 9e+04 +Depth= 8887 States= 2.7e+07 Transitions= 3.24e+08 Memory= 2475.568 t= 294 R= 9e+04 +Depth= 8887 States= 2.8e+07 Transitions= 3.36e+08 Memory= 2544.221 t= 305 R= 9e+04 +Depth= 8887 States= 2.9e+07 Transitions= 3.49e+08 Memory= 2612.873 t= 317 R= 9e+04 +Depth= 8887 States= 3e+07 Transitions= 3.63e+08 Memory= 2681.526 t= 329 R= 9e+04 +Depth= 8887 States= 3.1e+07 Transitions= 3.73e+08 Memory= 2750.276 t= 339 R= 9e+04 +Depth= 8887 States= 3.2e+07 Transitions= 3.85e+08 Memory= 2818.928 t= 351 R= 9e+04 +Depth= 8887 States= 3.3e+07 Transitions= 3.97e+08 Memory= 2887.580 t= 362 R= 9e+04 +Depth= 8887 States= 3.4e+07 Transitions= 4.08e+08 Memory= 2956.233 t= 373 R= 9e+04 +pan: resizing hashtable to -w26.. done +Depth= 8887 States= 3.5e+07 Transitions= 4.2e+08 Memory= 3520.967 t= 391 R= 9e+04 +Depth= 8887 States= 3.6e+07 Transitions= 4.32e+08 Memory= 3589.619 t= 402 R= 9e+04 +Depth= 8887 States= 3.7e+07 Transitions= 4.44e+08 Memory= 3658.272 t= 413 R= 9e+04 +Depth= 8887 States= 3.8e+07 Transitions= 4.58e+08 Memory= 3727.022 t= 425 R= 9e+04 +Depth= 8887 States= 3.9e+07 Transitions= 4.7e+08 Memory= 3795.674 t= 435 R= 9e+04 +Depth= 8887 States= 4e+07 Transitions= 4.83e+08 Memory= 3864.326 t= 447 R= 9e+04 +Depth= 8887 States= 4.1e+07 Transitions= 4.97e+08 Memory= 3932.979 t= 459 R= 9e+04 +Depth= 8887 States= 4.2e+07 Transitions= 5.07e+08 Memory= 4001.729 t= 468 R= 9e+04 +Depth= 8887 States= 4.3e+07 Transitions= 5.19e+08 Memory= 4070.381 t= 479 R= 9e+04 +Depth= 8887 States= 4.4e+07 Transitions= 5.31e+08 Memory= 4139.033 t= 489 R= 9e+04 +Depth= 8887 States= 4.5e+07 Transitions= 5.42e+08 Memory= 4207.686 t= 499 R= 9e+04 +Depth= 8887 States= 4.6e+07 Transitions= 5.54e+08 Memory= 4276.338 t= 510 R= 9e+04 +Depth= 8887 States= 4.7e+07 Transitions= 5.67e+08 Memory= 4345.088 t= 521 R= 9e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 8887, errors: 0 + 47143033 states, stored +5.2129161e+08 states, matched +5.6843464e+08 transitions (= stored+matched) +1.9783052e+09 atomic steps +hash conflicts: 3.1395137e+08 (resolved) + +Stats on memory usage (in Megabytes): + 4136.237 equivalent memory usage for states (stored*(State-vector + overhead)) + 3385.741 actual memory usage for states (compression: 81.86%) + state-vector as stored = 47 byte + 28 byte overhead + 512.000 memory used for hash table (-w26) + 457.764 memory used for DFS stack (-m10000000) + 4354.854 total actual memory usage + +unreached in proctype urcu_reader + line 398, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 61, "(1)" + line 417, "pan.___", state 91, "(1)" + line 398, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 158, "(1)" + line 417, "pan.___", state 188, "(1)" + line 398, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 256, "(1)" + line 417, "pan.___", state 286, "(1)" + line 398, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 395, "(1)" + line 417, "pan.___", state 425, "(1)" + line 539, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 398, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 70, "(1)" + line 417, "pan.___", state 100, "(1)" + line 398, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 158, "(1)" + line 417, "pan.___", state 188, "(1)" + line 398, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 247, "(1)" + line 417, "pan.___", state 277, "(1)" + line 398, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 359, "(1)" + line 417, "pan.___", state 389, "(1)" + line 613, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 59, "(1)" + line 412, "pan.___", state 72, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 153, "(1)" + line 412, "pan.___", state 166, "(1)" + line 651, "pan.___", state 199, "(1)" + line 174, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 178, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 240, "(1)" + line 163, "pan.___", state 248, "(1)" + line 167, "pan.___", state 260, "(1)" + line 174, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 370, "(1)" + line 163, "pan.___", state 378, "(1)" + line 167, "pan.___", state 390, "(1)" + line 398, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 449, "(1)" + line 412, "pan.___", state 462, "(1)" + line 417, "pan.___", state 479, "(1)" + line 398, "pan.___", state 498, "(1)" + line 402, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 554, "(1)" + line 417, "pan.___", state 571, "(1)" + line 402, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 647, "(1)" + line 417, "pan.___", state 664, "(1)" + line 178, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 710, "(1)" + line 163, "pan.___", state 718, "(1)" + line 167, "pan.___", state 730, "(1)" + line 174, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 840, "(1)" + line 163, "pan.___", state 848, "(1)" + line 167, "pan.___", state 860, "(1)" + line 398, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, "pan.___", state 884, "(1)" + line 398, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, "pan.___", state 885, "else" + line 398, "pan.___", state 888, "(1)" + line 402, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 898, "(1)" + line 402, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 899, "else" + line 402, "pan.___", state 902, "(1)" + line 402, "pan.___", state 903, "(1)" + line 402, "pan.___", state 903, "(1)" + line 400, "pan.___", state 908, "((i<1))" + line 400, "pan.___", state 908, "((i>=1))" + line 407, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 927, "(1)" + line 408, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 408, "pan.___", state 928, "else" + line 408, "pan.___", state 931, "(1)" + line 408, "pan.___", state 932, "(1)" + line 408, "pan.___", state 932, "(1)" + line 412, "pan.___", state 940, "(1)" + line 412, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 412, "pan.___", state 941, "else" + line 412, "pan.___", state 944, "(1)" + line 412, "pan.___", state 945, "(1)" + line 412, "pan.___", state 945, "(1)" + line 410, "pan.___", state 950, "((i<1))" + line 410, "pan.___", state 950, "((i>=1))" + line 417, "pan.___", state 957, "(1)" + line 417, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 417, "pan.___", state 958, "else" + line 417, "pan.___", state 961, "(1)" + line 417, "pan.___", state 962, "(1)" + line 417, "pan.___", state 962, "(1)" + line 419, "pan.___", state 965, "(1)" + line 419, "pan.___", state 965, "(1)" + line 402, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 1040, "(1)" + line 417, "pan.___", state 1057, "(1)" + line 402, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 1130, "(1)" + line 417, "pan.___", state 1147, "(1)" + line 398, "pan.___", state 1166, "(1)" + line 402, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 1222, "(1)" + line 417, "pan.___", state 1239, "(1)" + line 402, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 407, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 412, "pan.___", state 1315, "(1)" + line 417, "pan.___", state 1332, "(1)" + line 178, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 1378, "(1)" + line 163, "pan.___", state 1386, "(1)" + line 167, "pan.___", state 1398, "(1)" + line 174, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 1508, "(1)" + line 163, "pan.___", state 1516, "(1)" + line 167, "pan.___", state 1528, "(1)" + line 398, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, "pan.___", state 1552, "(1)" + line 398, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 398, "pan.___", state 1553, "else" + line 398, "pan.___", state 1556, "(1)" + line 402, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 1566, "(1)" + line 402, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 402, "pan.___", state 1567, "else" + line 402, "pan.___", state 1570, "(1)" + line 402, "pan.___", state 1571, "(1)" + line 402, "pan.___", state 1571, "(1)" + line 400, "pan.___", state 1576, "((i<1))" + line 400, "pan.___", state 1576, "((i>=1))" + line 407, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1595, "(1)" + line 408, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 408, "pan.___", state 1596, "else" + line 408, "pan.___", state 1599, "(1)" + line 408, "pan.___", state 1600, "(1)" + line 408, "pan.___", state 1600, "(1)" + line 412, "pan.___", state 1608, "(1)" + line 412, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 412, "pan.___", state 1609, "else" + line 412, "pan.___", state 1612, "(1)" + line 412, "pan.___", state 1613, "(1)" + line 412, "pan.___", state 1613, "(1)" + line 410, "pan.___", state 1618, "((i<1))" + line 410, "pan.___", state 1618, "((i>=1))" + line 417, "pan.___", state 1625, "(1)" + line 417, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 417, "pan.___", state 1626, "else" + line 417, "pan.___", state 1629, "(1)" + line 417, "pan.___", state 1630, "(1)" + line 417, "pan.___", state 1630, "(1)" + line 419, "pan.___", state 1633, "(1)" + line 419, "pan.___", state 1633, "(1)" + line 178, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 1681, "(1)" + line 163, "pan.___", state 1689, "(1)" + line 167, "pan.___", state 1701, "(1)" + line 174, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 178, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 182, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 159, "pan.___", state 1811, "(1)" + line 163, "pan.___", state 1819, "(1)" + line 167, "pan.___", state 1831, "(1)" + line 701, "pan.___", state 1856, "-end-" + (158 of 1856 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 748, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 523 seconds +pan: rate 90149.985 states/second +pan: avg transition delay 9.1997e-07 usec +cp .input.spin urcu_free.spin.input +cp .input.spin.trail urcu_free.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.ltl b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.ltl new file mode 100644 index 0000000..1954414 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.ltl @@ -0,0 +1 @@ +[] (read_free -> !read_free_race) diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input new file mode 100644 index 0000000..2d7f62d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input @@ -0,0 +1,722 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input.trail new file mode 100644 index 0000000..837f3d9 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free.spin.input.trail @@ -0,0 +1,15043 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 +18:4:4344 +19:4:4344 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diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.log new file mode 100644 index 0000000..d503334 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.log @@ -0,0 +1,20 @@ +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_nested.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) +Depth= 3880 States= 1e+06 Transitions= 1.18e+07 Memory= 527.190 t= 9.48 R= 1e+05 +Depth= 3880 States= 2e+06 Transitions= 2.39e+07 Memory= 588.225 t= 19.6 R= 1e+05 +Depth= 3880 States= 3e+06 Transitions= 3.61e+07 Memory= 649.260 t= 30.3 R= 1e+05 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input new file mode 100644 index 0000000..c94928c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input @@ -0,0 +1,696 @@ +#define READER_NEST_LEVEL 1 + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE +#define get_pid() ((_pid < 1) -> 0 : 1) +#elif defined(TEST_SIGNAL_ON_READ) +#define get_pid() ((_pid < 2) -> 0 : 1) +#else +#define get_pid() (_pid) +#endif + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + dispatch_sighand_read_exec(); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 1; + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input.trail new file mode 100644 index 0000000..6f29ad2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_nested.spin.input.trail @@ -0,0 +1,11161 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 +18:4:4344 +19:4:4344 +20:4:4347 +21:4:4355 +22:4:4359 +23:4:4360 +24:0:4365 +25:4:4362 +26:0:4365 +27:3:2331 +28:0:4365 +29:3:2337 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b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.define new file mode 100644 index 0000000..136ef67 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.define @@ -0,0 +1,2 @@ +#define NO_RMB +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.log new file mode 100644 index 0000000..3afaead --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.log @@ -0,0 +1,303 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_mb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 745) +Depth= 6009 States= 1e+06 Transitions= 1.08e+07 Memory= 534.904 t= 9.22 R= 1e+05 +Depth= 6009 States= 2e+06 Transitions= 3.4e+07 Memory= 603.557 t= 31.1 R= 6e+04 +Depth= 7527 States= 3e+06 Transitions= 4.91e+07 Memory= 672.209 t= 45.6 R= 7e+04 +pan: resizing hashtable to -w22.. done +Depth= 68651 States= 4e+06 Transitions= 6.74e+07 Memory= 772.080 t= 62.9 R= 6e+04 +Depth= 68651 States= 5e+06 Transitions= 8.62e+07 Memory= 840.733 t= 80.2 R= 6e+04 +Depth= 68651 States= 6e+06 Transitions= 1.03e+08 Memory= 909.385 t= 95.7 R= 6e+04 +Depth= 68651 States= 7e+06 Transitions= 1.21e+08 Memory= 978.037 t= 112 R= 6e+04 +Depth= 68651 States= 8e+06 Transitions= 1.37e+08 Memory= 1046.690 t= 128 R= 6e+04 +Depth= 68651 States= 9e+06 Transitions= 1.52e+08 Memory= 1115.440 t= 143 R= 6e+04 +pan: resizing hashtable to -w24.. done +Depth= 68651 States= 1e+07 Transitions= 1.72e+08 Memory= 1308.186 t= 163 R= 6e+04 +Depth= 68651 States= 1.1e+07 Transitions= 1.89e+08 Memory= 1376.838 t= 178 R= 6e+04 +Depth= 68651 States= 1.2e+07 Transitions= 2.05e+08 Memory= 1445.490 t= 193 R= 6e+04 +Depth= 68651 States= 1.3e+07 Transitions= 2.22e+08 Memory= 1514.143 t= 208 R= 6e+04 +Depth= 68651 States= 1.4e+07 Transitions= 2.39e+08 Memory= 1582.893 t= 224 R= 6e+04 +pan: claim violated! (at depth 2141) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 88 byte, depth reached 68651, errors: 1 + 14155711 states, stored +2.2815817e+08 states, matched +2.4231388e+08 transitions (= stored+matched) +8.5461256e+08 atomic steps +hash conflicts: 1.1483359e+08 (resolved) + +Stats on memory usage (in Megabytes): + 1565.993 equivalent memory usage for states (stored*(State-vector + overhead)) + 1008.042 actual memory usage for states (compression: 64.37%) + state-vector as stored = 47 byte + 28 byte overhead + 128.000 memory used for hash table (-w24) + 457.764 memory used for DFS stack (-m10000000) + 1593.537 total actual memory usage + +unreached in proctype urcu_reader + line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 61, "(1)" + line 419, "pan.___", state 91, "(1)" + line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 158, "(1)" + line 419, "pan.___", state 188, "(1)" + line 400, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 227, "(1)" + line 409, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 256, "(1)" + line 419, "pan.___", state 286, "(1)" + line 400, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 366, "(1)" + line 409, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 395, "(1)" + line 419, "pan.___", state 425, "(1)" + line 541, "pan.___", state 456, "-end-" + (19 of 456 states) +unreached in proctype urcu_reader_sig + line 400, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 70, "(1)" + line 419, "pan.___", state 100, "(1)" + line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 158, "(1)" + line 419, "pan.___", state 188, "(1)" + line 400, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 247, "(1)" + line 419, "pan.___", state 277, "(1)" + line 400, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 330, "(1)" + line 409, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 359, "(1)" + line 419, "pan.___", state 389, "(1)" + line 615, "pan.___", state 411, "-end-" + (18 of 411 states) +unreached in proctype urcu_writer + line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 20, "(1)" + line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 34, "(1)" + line 404, "pan.___", state 35, "(1)" + line 404, "pan.___", state 35, "(1)" + line 402, "pan.___", state 40, "((i<1))" + line 402, "pan.___", state 40, "((i>=1))" + line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 59, "(1)" + line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 60, "else" + line 410, "pan.___", state 63, "(1)" + line 410, "pan.___", state 64, "(1)" + line 410, "pan.___", state 64, "(1)" + line 414, "pan.___", state 72, "(1)" + line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 73, "else" + line 414, "pan.___", state 76, "(1)" + line 414, "pan.___", state 77, "(1)" + line 414, "pan.___", state 77, "(1)" + line 412, "pan.___", state 82, "((i<1))" + line 412, "pan.___", state 82, "((i>=1))" + line 419, "pan.___", state 89, "(1)" + line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 90, "else" + line 419, "pan.___", state 93, "(1)" + line 419, "pan.___", state 94, "(1)" + line 419, "pan.___", state 94, "(1)" + line 421, "pan.___", state 97, "(1)" + line 421, "pan.___", state 97, "(1)" + line 370, "pan.___", state 99, "(1)" + line 640, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)" + line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]" + line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 114, "(1)" + line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 128, "(1)" + line 404, "pan.___", state 129, "(1)" + line 404, "pan.___", state 129, "(1)" + line 410, "pan.___", state 153, "(1)" + line 414, "pan.___", state 166, "(1)" + line 421, "pan.___", state 191, "(1)" + line 421, "pan.___", state 191, "(1)" + line 653, "pan.___", state 199, "(1)" + line 400, "pan.___", state 209, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 223, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 254, "(1)" + line 414, "pan.___", state 267, "(1)" + line 400, "pan.___", state 300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 314, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 345, "(1)" + line 414, "pan.___", state 358, "(1)" + line 400, "pan.___", state 395, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 409, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 440, "(1)" + line 414, "pan.___", state 453, "(1)" + line 400, "pan.___", state 488, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 533, "(1)" + line 414, "pan.___", state 546, "(1)" + line 400, "pan.___", state 582, "(1)" + line 404, "pan.___", state 594, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 638, "(1)" + line 404, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 731, "(1)" + line 404, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 821, "(1)" + line 419, "pan.___", state 838, "(1)" + line 404, "pan.___", state 868, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 886, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 912, "(1)" + line 419, "pan.___", state 929, "(1)" + line 404, "pan.___", state 963, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 981, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1007, "(1)" + line 419, "pan.___", state 1024, "(1)" + line 400, "pan.___", state 1050, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1052, "(1)" + line 400, "pan.___", state 1053, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1053, "else" + line 400, "pan.___", state 1056, "(1)" + line 404, "pan.___", state 1064, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1066, "(1)" + line 404, "pan.___", state 1067, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1067, "else" + line 404, "pan.___", state 1070, "(1)" + line 404, "pan.___", state 1071, "(1)" + line 404, "pan.___", state 1071, "(1)" + line 402, "pan.___", state 1076, "((i<1))" + line 402, "pan.___", state 1076, "((i>=1))" + line 409, "pan.___", state 1082, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 1095, "(1)" + line 410, "pan.___", state 1096, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 1096, "else" + line 410, "pan.___", state 1099, "(1)" + line 410, "pan.___", state 1100, "(1)" + line 410, "pan.___", state 1100, "(1)" + line 414, "pan.___", state 1108, "(1)" + line 414, "pan.___", state 1109, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 1109, "else" + line 414, "pan.___", state 1112, "(1)" + line 414, "pan.___", state 1113, "(1)" + line 414, "pan.___", state 1113, "(1)" + line 412, "pan.___", state 1118, "((i<1))" + line 412, "pan.___", state 1118, "((i>=1))" + line 419, "pan.___", state 1125, "(1)" + line 419, "pan.___", state 1126, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 1126, "else" + line 419, "pan.___", state 1129, "(1)" + line 419, "pan.___", state 1130, "(1)" + line 419, "pan.___", state 1130, "(1)" + line 421, "pan.___", state 1133, "(1)" + line 421, "pan.___", state 1133, "(1)" + line 404, "pan.___", state 1164, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1208, "(1)" + line 404, "pan.___", state 1254, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1298, "(1)" + line 400, "pan.___", state 1334, "(1)" + line 404, "pan.___", state 1346, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1390, "(1)" + line 404, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1483, "(1)" + line 404, "pan.___", state 1529, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1547, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1573, "(1)" + line 419, "pan.___", state 1590, "(1)" + line 404, "pan.___", state 1620, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1638, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1664, "(1)" + line 419, "pan.___", state 1681, "(1)" + line 404, "pan.___", state 1715, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1733, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1759, "(1)" + line 419, "pan.___", state 1776, "(1)" + line 400, "pan.___", state 1802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1804, "(1)" + line 400, "pan.___", state 1805, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1805, "else" + line 400, "pan.___", state 1808, "(1)" + line 404, "pan.___", state 1816, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1818, "(1)" + line 404, "pan.___", state 1819, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1819, "else" + line 404, "pan.___", state 1822, "(1)" + line 404, "pan.___", state 1823, "(1)" + line 404, "pan.___", state 1823, "(1)" + line 402, "pan.___", state 1828, "((i<1))" + line 402, "pan.___", state 1828, "((i>=1))" + line 409, "pan.___", state 1834, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 1847, "(1)" + line 410, "pan.___", state 1848, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 1848, "else" + line 410, "pan.___", state 1851, "(1)" + line 410, "pan.___", state 1852, "(1)" + line 410, "pan.___", state 1852, "(1)" + line 414, "pan.___", state 1860, "(1)" + line 414, "pan.___", state 1861, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 1861, "else" + line 414, "pan.___", state 1864, "(1)" + line 414, "pan.___", state 1865, "(1)" + line 414, "pan.___", state 1865, "(1)" + line 412, "pan.___", state 1870, "((i<1))" + line 412, "pan.___", state 1870, "((i>=1))" + line 419, "pan.___", state 1877, "(1)" + line 419, "pan.___", state 1878, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 1878, "else" + line 419, "pan.___", state 1881, "(1)" + line 419, "pan.___", state 1882, "(1)" + line 419, "pan.___", state 1882, "(1)" + line 421, "pan.___", state 1885, "(1)" + line 421, "pan.___", state 1885, "(1)" + line 404, "pan.___", state 1916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1960, "(1)" + line 404, "pan.___", state 2007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 2051, "(1)" + line 404, "pan.___", state 2102, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 2146, "(1)" + line 703, "pan.___", state 2192, "-end-" + (144 of 2192 states) +unreached in proctype :init: + line 710, "pan.___", state 9, "((j<2))" + line 710, "pan.___", state 9, "((j>=2))" + line 711, "pan.___", state 20, "((j<2))" + line 711, "pan.___", state 20, "((j>=2))" + line 716, "pan.___", state 33, "((j<2))" + line 716, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 750, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 227 seconds +pan: rate 62472.797 states/second +pan: avg transition delay 9.3511e-07 usec +cp .input.spin urcu_free_no_mb.spin.input +cp .input.spin.trail urcu_free_no_mb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input new file mode 100644 index 0000000..5de16b8 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input @@ -0,0 +1,724 @@ +#define NO_RMB +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input.trail new file mode 100644 index 0000000..d437aad --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_mb.spin.input.trail @@ -0,0 +1,2144 @@ +-2:4:-2 +-4:-4:-4 +1:0:3107 +2:4:3059 +3:4:3062 +4:4:3062 +5:4:3065 +6:4:3073 +7:4:3073 +8:4:3076 +9:4:3082 +10:4:3086 +11:4:3086 +12:4:3089 +13:4:3097 +14:4:3101 +15:4:3102 +16:0:3107 +17:4:3104 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+2118:2:729 +2119:0:3107 +2120:3:3052 +2121:0:3107 +2122:2:741 +2123:0:3107 +2124:3:3053 +2125:0:3107 +2126:2:750 +2127:0:3107 +2128:3:3052 +2129:0:3107 +2130:2:753 +2131:0:3107 +2132:3:3053 +2133:0:3107 +2134:2:758 +2135:0:3107 +2136:3:3052 +2137:0:3107 +2138:2:759 +2139:0:3105 +2140:3:3053 +2141:0:3111 +2142:2:647 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.define new file mode 100644 index 0000000..73e61a4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.define @@ -0,0 +1 @@ +#define NO_RMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.log new file mode 100644 index 0000000..5bcef22 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.log @@ -0,0 +1,300 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_rmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +Depth= 5678 States= 1e+06 Transitions= 8.21e+06 Memory= 534.904 t= 6.72 R= 1e+05 +Depth= 5678 States= 2e+06 Transitions= 1.6e+07 Memory= 603.557 t= 13.4 R= 1e+05 +Depth= 16003 States= 3e+06 Transitions= 2.49e+07 Memory= 672.209 t= 21.5 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 31043 States= 4e+06 Transitions= 3.44e+07 Memory= 771.983 t= 30.1 R= 1e+05 +Depth= 31043 States= 5e+06 Transitions= 4.41e+07 Memory= 840.635 t= 38.4 R= 1e+05 +Depth= 31043 States= 6e+06 Transitions= 5.25e+07 Memory= 909.287 t= 45.7 R= 1e+05 +Depth= 31043 States= 7e+06 Transitions= 6.12e+07 Memory= 977.940 t= 53.4 R= 1e+05 +Depth= 31043 States= 8e+06 Transitions= 6.95e+07 Memory= 1046.690 t= 60.8 R= 1e+05 +Depth= 31043 States= 9e+06 Transitions= 7.78e+07 Memory= 1115.342 t= 68.5 R= 1e+05 +pan: resizing hashtable to -w24.. done +Depth= 31043 States= 1e+07 Transitions= 8.68e+07 Memory= 1308.088 t= 77.9 R= 1e+05 +Depth= 31043 States= 1.1e+07 Transitions= 1.01e+08 Memory= 1376.740 t= 90.1 R= 1e+05 +Depth= 31043 States= 1.2e+07 Transitions= 1.13e+08 Memory= 1445.393 t= 101 R= 1e+05 +Depth= 31043 States= 1.3e+07 Transitions= 1.25e+08 Memory= 1514.045 t= 111 R= 1e+05 +Depth= 31043 States= 1.4e+07 Transitions= 1.38e+08 Memory= 1582.795 t= 122 R= 1e+05 +pan: claim violated! (at depth 1774) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 31043, errors: 1 + 14288659 states, stored +1.2755714e+08 states, matched +1.418458e+08 transitions (= stored+matched) +4.6616273e+08 atomic steps +hash conflicts: 65726574 (resolved) + +Stats on memory usage (in Megabytes): + 1253.659 equivalent memory usage for states (stored*(State-vector + overhead)) + 1017.191 actual memory usage for states (compression: 81.14%) + state-vector as stored = 47 byte + 28 byte overhead + 128.000 memory used for hash table (-w24) + 457.764 memory used for DFS stack (-m10000000) + 1602.619 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 256, "(1)" + line 418, "pan.___", state 286, "(1)" + line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 395, "(1)" + line 418, "pan.___", state 425, "(1)" + line 540, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 70, "(1)" + line 418, "pan.___", state 100, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 247, "(1)" + line 418, "pan.___", state 277, "(1)" + line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 359, "(1)" + line 418, "pan.___", state 389, "(1)" + line 614, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 20, "(1)" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 34, "(1)" + line 403, "pan.___", state 35, "(1)" + line 403, "pan.___", state 35, "(1)" + line 401, "pan.___", state 40, "((i<1))" + line 401, "pan.___", state 40, "((i>=1))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 59, "(1)" + line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 60, "else" + line 409, "pan.___", state 63, "(1)" + line 409, "pan.___", state 64, "(1)" + line 409, "pan.___", state 64, "(1)" + line 413, "pan.___", state 72, "(1)" + line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 73, "else" + line 413, "pan.___", state 76, "(1)" + line 413, "pan.___", state 77, "(1)" + line 413, "pan.___", state 77, "(1)" + line 411, "pan.___", state 82, "((i<1))" + line 411, "pan.___", state 82, "((i>=1))" + line 418, "pan.___", state 89, "(1)" + line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 90, "else" + line 418, "pan.___", state 93, "(1)" + line 418, "pan.___", state 94, "(1)" + line 418, "pan.___", state 94, "(1)" + line 420, "pan.___", state 97, "(1)" + line 420, "pan.___", state 97, "(1)" + line 369, "pan.___", state 99, "(1)" + line 639, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)" + line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 114, "(1)" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 128, "(1)" + line 403, "pan.___", state 129, "(1)" + line 403, "pan.___", state 129, "(1)" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 420, "pan.___", state 191, "(1)" + line 420, "pan.___", state 191, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 175, "pan.___", state 243, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 291, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 304, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 320, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 334, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 352, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 365, "(1)" + line 413, "pan.___", state 378, "(1)" + line 418, "pan.___", state 395, "(1)" + line 399, "pan.___", state 414, "(1)" + line 403, "pan.___", state 426, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 444, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 470, "(1)" + line 418, "pan.___", state 487, "(1)" + line 403, "pan.___", state 519, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 537, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 563, "(1)" + line 418, "pan.___", state 580, "(1)" + line 179, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 175, "pan.___", state 629, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 677, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 690, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 714, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 716, "(1)" + line 399, "pan.___", state 717, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 717, "else" + line 399, "pan.___", state 720, "(1)" + line 403, "pan.___", state 728, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 730, "(1)" + line 403, "pan.___", state 731, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 731, "else" + line 403, "pan.___", state 734, "(1)" + line 403, "pan.___", state 735, "(1)" + line 403, "pan.___", state 735, "(1)" + line 401, "pan.___", state 740, "((i<1))" + line 401, "pan.___", state 740, "((i>=1))" + line 408, "pan.___", state 746, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 759, "(1)" + line 409, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 760, "else" + line 409, "pan.___", state 763, "(1)" + line 409, "pan.___", state 764, "(1)" + line 409, "pan.___", state 764, "(1)" + line 413, "pan.___", state 772, "(1)" + line 413, "pan.___", state 773, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 773, "else" + line 413, "pan.___", state 776, "(1)" + line 413, "pan.___", state 777, "(1)" + line 413, "pan.___", state 777, "(1)" + line 411, "pan.___", state 782, "((i<1))" + line 411, "pan.___", state 782, "((i>=1))" + line 418, "pan.___", state 789, "(1)" + line 418, "pan.___", state 790, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 790, "else" + line 418, "pan.___", state 793, "(1)" + line 418, "pan.___", state 794, "(1)" + line 418, "pan.___", state 794, "(1)" + line 420, "pan.___", state 797, "(1)" + line 420, "pan.___", state 797, "(1)" + line 403, "pan.___", state 828, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 846, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 872, "(1)" + line 418, "pan.___", state 889, "(1)" + line 403, "pan.___", state 918, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 936, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 962, "(1)" + line 418, "pan.___", state 979, "(1)" + line 399, "pan.___", state 998, "(1)" + line 403, "pan.___", state 1010, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1028, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1054, "(1)" + line 418, "pan.___", state 1071, "(1)" + line 403, "pan.___", state 1103, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1121, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1147, "(1)" + line 418, "pan.___", state 1164, "(1)" + line 179, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1200, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 175, "pan.___", state 1213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1261, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1300, "(1)" + line 399, "pan.___", state 1301, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1301, "else" + line 399, "pan.___", state 1304, "(1)" + line 403, "pan.___", state 1312, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1314, "(1)" + line 403, "pan.___", state 1315, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1315, "else" + line 403, "pan.___", state 1318, "(1)" + line 403, "pan.___", state 1319, "(1)" + line 403, "pan.___", state 1319, "(1)" + line 401, "pan.___", state 1324, "((i<1))" + line 401, "pan.___", state 1324, "((i>=1))" + line 408, "pan.___", state 1330, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1343, "(1)" + line 409, "pan.___", state 1344, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 1344, "else" + line 409, "pan.___", state 1347, "(1)" + line 409, "pan.___", state 1348, "(1)" + line 409, "pan.___", state 1348, "(1)" + line 413, "pan.___", state 1356, "(1)" + line 413, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 1357, "else" + line 413, "pan.___", state 1360, "(1)" + line 413, "pan.___", state 1361, "(1)" + line 413, "pan.___", state 1361, "(1)" + line 411, "pan.___", state 1366, "((i<1))" + line 411, "pan.___", state 1366, "((i>=1))" + line 418, "pan.___", state 1373, "(1)" + line 418, "pan.___", state 1374, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 1374, "else" + line 418, "pan.___", state 1377, "(1)" + line 418, "pan.___", state 1378, "(1)" + line 418, "pan.___", state 1378, "(1)" + line 420, "pan.___", state 1381, "(1)" + line 420, "pan.___", state 1381, "(1)" + line 179, "pan.___", state 1406, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1419, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 175, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1480, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1493, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 702, "pan.___", state 1520, "-end-" + (144 of 1520 states) +unreached in proctype :init: + line 709, "pan.___", state 9, "((j<2))" + line 709, "pan.___", state 9, "((j>=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 125 seconds +pan: rate 114108.44 states/second +pan: avg transition delay 8.8279e-07 usec +cp .input.spin urcu_free_no_rmb.spin.input +cp .input.spin.trail urcu_free_no_rmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input new file mode 100644 index 0000000..ccf5f5c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input @@ -0,0 +1,723 @@ +#define NO_RMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail new file mode 100644 index 0000000..1e5e132 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail @@ -0,0 +1,1777 @@ +-2:4:-2 +-4:-4:-4 +1:0:2435 +2:4:2387 +3:4:2390 +4:4:2390 +5:4:2393 +6:4:2401 +7:4:2401 +8:4:2404 +9:4:2410 +10:4:2414 +11:4:2414 +12:4:2417 +13:4:2425 +14:4:2429 +15:4:2430 +16:0:2435 +17:4:2432 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+1732:0:2435 +1733:2:654 +1734:2:658 +1735:2:659 +1736:2:667 +1737:2:668 +1738:2:672 +1739:2:673 +1740:2:681 +1741:2:686 +1742:2:690 +1743:2:691 +1744:2:698 +1745:2:699 +1746:2:710 +1747:2:711 +1748:2:712 +1749:2:723 +1750:2:735 +1751:2:736 +1752:0:2435 +1753:3:2380 +1754:0:2435 +1755:2:741 +1756:0:2435 +1757:3:2381 +1758:0:2435 +1759:2:750 +1760:0:2435 +1761:3:2380 +1762:0:2435 +1763:2:753 +1764:0:2435 +1765:3:2381 +1766:0:2435 +1767:2:758 +1768:0:2435 +1769:3:2380 +1770:0:2435 +1771:2:759 +1772:0:2433 +1773:3:2381 +1774:0:2439 +1775:0:2435 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.define new file mode 100644 index 0000000..710f29d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.define @@ -0,0 +1 @@ +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.log new file mode 100644 index 0000000..0423ec5 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.log @@ -0,0 +1,320 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_wmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +Depth= 10656 States= 1e+06 Transitions= 8.86e+06 Memory= 534.807 t= 7.38 R= 1e+05 +Depth= 35214 States= 2e+06 Transitions= 1.82e+07 Memory= 603.557 t= 15.5 R= 1e+05 +Depth= 35214 States= 3e+06 Transitions= 2.73e+07 Memory= 672.209 t= 23.8 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 35214 States= 4e+06 Transitions= 4.08e+07 Memory= 771.885 t= 35.9 R= 1e+05 +pan: claim violated! (at depth 1650) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 35214, errors: 1 + 4154272 states, stored + 38595853 states, matched + 42750125 transitions (= stored+matched) +1.4058824e+08 atomic steps +hash conflicts: 21492325 (resolved) + +Stats on memory usage (in Megabytes): + 364.488 equivalent memory usage for states (stored*(State-vector + overhead)) + 292.863 actual memory usage for states (compression: 80.35%) + state-vector as stored = 46 byte + 28 byte overhead + 32.000 memory used for hash table (-w22) + 457.764 memory used for DFS stack (-m10000000) + 782.529 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 227, "(1)" + line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 256, "(1)" + line 418, "pan.___", state 286, "(1)" + line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 366, "(1)" + line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 395, "(1)" + line 418, "pan.___", state 425, "(1)" + line 540, "pan.___", state 456, "-end-" + (19 of 456 states) +unreached in proctype urcu_reader_sig + line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 70, "(1)" + line 418, "pan.___", state 100, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 247, "(1)" + line 418, "pan.___", state 277, "(1)" + line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 330, "(1)" + line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 359, "(1)" + line 418, "pan.___", state 389, "(1)" + line 614, "pan.___", state 411, "-end-" + (18 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 20, "(1)" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 34, "(1)" + line 403, "pan.___", state 35, "(1)" + line 403, "pan.___", state 35, "(1)" + line 401, "pan.___", state 40, "((i<1))" + line 401, "pan.___", state 40, "((i>=1))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 59, "(1)" + line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 60, "else" + line 409, "pan.___", state 63, "(1)" + line 409, "pan.___", state 64, "(1)" + line 409, "pan.___", state 64, "(1)" + line 413, "pan.___", state 72, "(1)" + line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 73, "else" + line 413, "pan.___", state 76, "(1)" + line 413, "pan.___", state 77, "(1)" + line 413, "pan.___", state 77, "(1)" + line 411, "pan.___", state 82, "((i<1))" + line 411, "pan.___", state 82, "((i>=1))" + line 418, "pan.___", state 89, "(1)" + line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 90, "else" + line 418, "pan.___", state 93, "(1)" + line 418, "pan.___", state 94, "(1)" + line 418, "pan.___", state 94, "(1)" + line 420, "pan.___", state 97, "(1)" + line 420, "pan.___", state 97, "(1)" + line 369, "pan.___", state 99, "(1)" + line 639, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)" + line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 114, "(1)" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 128, "(1)" + line 403, "pan.___", state 129, "(1)" + line 403, "pan.___", state 129, "(1)" + line 401, "pan.___", state 134, "((i<1))" + line 401, "pan.___", state 134, "((i>=1))" + line 409, "pan.___", state 153, "(1)" + line 409, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 154, "else" + line 409, "pan.___", state 157, "(1)" + line 409, "pan.___", state 158, "(1)" + line 409, "pan.___", state 158, "(1)" + line 413, "pan.___", state 166, "(1)" + line 413, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 167, "else" + line 413, "pan.___", state 170, "(1)" + line 413, "pan.___", state 171, "(1)" + line 413, "pan.___", state 171, "(1)" + line 411, "pan.___", state 176, "((i<1))" + line 411, "pan.___", state 176, "((i>=1))" + line 418, "pan.___", state 183, "(1)" + line 418, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 184, "else" + line 418, "pan.___", state 187, "(1)" + line 418, "pan.___", state 188, "(1)" + line 418, "pan.___", state 188, "(1)" + line 420, "pan.___", state 191, "(1)" + line 420, "pan.___", state 191, "(1)" + line 369, "pan.___", state 193, "(1)" + line 652, "pan.___", state 199, "(1)" + line 646, "pan.___", state 202, "((write_lock==0))" + line 646, "pan.___", state 202, "else" + line 644, "pan.___", state 203, "(1)" + line 160, "pan.___", state 209, "(1)" + line 164, "pan.___", state 217, "(1)" + line 164, "pan.___", state 218, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 164, "pan.___", state 218, "else" + line 162, "pan.___", state 223, "((j<1))" + line 162, "pan.___", state 223, "((j>=1))" + line 168, "pan.___", state 229, "(1)" + line 168, "pan.___", state 230, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 168, "pan.___", state 230, "else" + line 160, "pan.___", state 241, "(1)" + line 168, "pan.___", state 261, "(1)" + line 160, "pan.___", state 277, "(1)" + line 164, "pan.___", state 285, "(1)" + line 168, "pan.___", state 297, "(1)" + line 399, "pan.___", state 311, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 325, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 343, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 356, "(1)" + line 413, "pan.___", state 369, "(1)" + line 418, "pan.___", state 386, "(1)" + line 399, "pan.___", state 405, "(1)" + line 403, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 461, "(1)" + line 418, "pan.___", state 478, "(1)" + line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 554, "(1)" + line 418, "pan.___", state 571, "(1)" + line 164, "pan.___", state 594, "(1)" + line 168, "pan.___", state 606, "(1)" + line 160, "pan.___", state 618, "(1)" + line 168, "pan.___", state 638, "(1)" + line 164, "pan.___", state 662, "(1)" + line 168, "pan.___", state 674, "(1)" + line 399, "pan.___", state 696, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 698, "(1)" + line 399, "pan.___", state 699, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 699, "else" + line 399, "pan.___", state 702, "(1)" + line 403, "pan.___", state 710, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 712, "(1)" + line 403, "pan.___", state 713, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 713, "else" + line 403, "pan.___", state 716, "(1)" + line 403, "pan.___", state 717, "(1)" + line 403, "pan.___", state 717, "(1)" + line 401, "pan.___", state 722, "((i<1))" + line 401, "pan.___", state 722, "((i>=1))" + line 408, "pan.___", state 728, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 741, "(1)" + line 409, "pan.___", state 742, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 742, "else" + line 409, "pan.___", state 745, "(1)" + line 409, "pan.___", state 746, "(1)" + line 409, "pan.___", state 746, "(1)" + line 413, "pan.___", state 754, "(1)" + line 413, "pan.___", state 755, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 755, "else" + line 413, "pan.___", state 758, "(1)" + line 413, "pan.___", state 759, "(1)" + line 413, "pan.___", state 759, "(1)" + line 411, "pan.___", state 764, "((i<1))" + line 411, "pan.___", state 764, "((i>=1))" + line 418, "pan.___", state 771, "(1)" + line 418, "pan.___", state 772, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 772, "else" + line 418, "pan.___", state 775, "(1)" + line 418, "pan.___", state 776, "(1)" + line 418, "pan.___", state 776, "(1)" + line 420, "pan.___", state 779, "(1)" + line 420, "pan.___", state 779, "(1)" + line 403, "pan.___", state 810, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 828, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 854, "(1)" + line 418, "pan.___", state 871, "(1)" + line 403, "pan.___", state 900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 918, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 944, "(1)" + line 418, "pan.___", state 961, "(1)" + line 399, "pan.___", state 980, "(1)" + line 403, "pan.___", state 992, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1010, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1036, "(1)" + line 418, "pan.___", state 1053, "(1)" + line 403, "pan.___", state 1085, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1103, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1129, "(1)" + line 418, "pan.___", state 1146, "(1)" + line 164, "pan.___", state 1169, "(1)" + line 168, "pan.___", state 1181, "(1)" + line 160, "pan.___", state 1193, "(1)" + line 168, "pan.___", state 1213, "(1)" + line 164, "pan.___", state 1237, "(1)" + line 168, "pan.___", state 1249, "(1)" + line 399, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1273, "(1)" + line 399, "pan.___", state 1274, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1274, "else" + line 399, "pan.___", state 1277, "(1)" + line 403, "pan.___", state 1285, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1287, "(1)" + line 403, "pan.___", state 1288, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1288, "else" + line 403, "pan.___", state 1291, "(1)" + line 403, "pan.___", state 1292, "(1)" + line 403, "pan.___", state 1292, "(1)" + line 401, "pan.___", state 1297, "((i<1))" + line 401, "pan.___", state 1297, "((i>=1))" + line 408, "pan.___", state 1303, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1316, "(1)" + line 409, "pan.___", state 1317, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 1317, "else" + line 409, "pan.___", state 1320, "(1)" + line 409, "pan.___", state 1321, "(1)" + line 409, "pan.___", state 1321, "(1)" + line 413, "pan.___", state 1329, "(1)" + line 413, "pan.___", state 1330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 1330, "else" + line 413, "pan.___", state 1333, "(1)" + line 413, "pan.___", state 1334, "(1)" + line 413, "pan.___", state 1334, "(1)" + line 411, "pan.___", state 1339, "((i<1))" + line 411, "pan.___", state 1339, "((i>=1))" + line 418, "pan.___", state 1346, "(1)" + line 418, "pan.___", state 1347, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 1347, "else" + line 418, "pan.___", state 1350, "(1)" + line 418, "pan.___", state 1351, "(1)" + line 418, "pan.___", state 1351, "(1)" + line 420, "pan.___", state 1354, "(1)" + line 420, "pan.___", state 1354, "(1)" + line 164, "pan.___", state 1379, "(1)" + line 168, "pan.___", state 1391, "(1)" + line 160, "pan.___", state 1403, "(1)" + line 168, "pan.___", state 1423, "(1)" + line 164, "pan.___", state 1447, "(1)" + line 168, "pan.___", state 1459, "(1)" + line 702, "pan.___", state 1484, "-end-" + (160 of 1484 states) +unreached in proctype :init: + line 709, "pan.___", state 9, "((j<2))" + line 709, "pan.___", state 9, "((j>=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 37.6 seconds +pan: rate 110515.35 states/second +pan: avg transition delay 8.793e-07 usec +cp .input.spin urcu_free_no_wmb.spin.input +cp .input.spin.trail urcu_free_no_wmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input new file mode 100644 index 0000000..d5d174d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input @@ -0,0 +1,723 @@ +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail new file mode 100644 index 0000000..f2ce974 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail @@ -0,0 +1,1653 @@ +-2:4:-2 +-4:-4:-4 +1:0:2399 +2:4:2351 +3:4:2354 +4:4:2354 +5:4:2357 +6:4:2365 +7:4:2365 +8:4:2368 +9:4:2374 +10:4:2378 +11:4:2378 +12:4:2381 +13:4:2389 +14:4:2393 +15:4:2394 +16:0:2399 +17:4:2396 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a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.define new file mode 100644 index 0000000..5e642ef --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.define @@ -0,0 +1 @@ +#define SINGLE_FLIP diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.log new file mode 100644 index 0000000..5d7d35c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.log @@ -0,0 +1,217 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_single_flip.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +Depth= 8352 States= 1e+06 Transitions= 1.05e+07 Memory= 534.807 t= 8.93 R= 1e+05 +pan: claim violated! (at depth 1352) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 8352, errors: 1 + 1456373 states, stored + 13442538 states, matched + 14898911 transitions (= stored+matched) + 50580660 atomic steps +hash conflicts: 5166006 (resolved) + +Stats on memory usage (in Megabytes): + 127.779 equivalent memory usage for states (stored*(State-vector + overhead)) + 100.443 actual memory usage for states (compression: 78.61%) + state-vector as stored = 44 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 566.154 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 256, "(1)" + line 418, "pan.___", state 286, "(1)" + line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 395, "(1)" + line 418, "pan.___", state 425, "(1)" + line 540, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 70, "(1)" + line 418, "pan.___", state 100, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 247, "(1)" + line 418, "pan.___", state 277, "(1)" + line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 359, "(1)" + line 418, "pan.___", state 389, "(1)" + line 614, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 370, "(1)" + line 164, "pan.___", state 378, "(1)" + line 168, "pan.___", state 390, "(1)" + line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 449, "(1)" + line 413, "pan.___", state 462, "(1)" + line 418, "pan.___", state 479, "(1)" + line 399, "pan.___", state 498, "(1)" + line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 554, "(1)" + line 418, "pan.___", state 571, "(1)" + line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 647, "(1)" + line 418, "pan.___", state 664, "(1)" + line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 710, "(1)" + line 164, "pan.___", state 718, "(1)" + line 168, "pan.___", state 730, "(1)" + line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 840, "(1)" + line 164, "pan.___", state 848, "(1)" + line 168, "pan.___", state 860, "(1)" + line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 884, "(1)" + line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 885, "else" + line 399, "pan.___", state 888, "(1)" + line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 898, "(1)" + line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 899, "else" + line 403, "pan.___", state 902, "(1)" + line 403, "pan.___", state 903, "(1)" + line 403, "pan.___", state 903, "(1)" + line 401, "pan.___", state 908, "((i<1))" + line 401, "pan.___", state 908, "((i>=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 179, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1003, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1013, "(1)" + line 164, "pan.___", state 1021, "(1)" + line 168, "pan.___", state 1033, "(1)" + line 175, "pan.___", state 1044, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1133, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1143, "(1)" + line 164, "pan.___", state 1151, "(1)" + line 168, "pan.___", state 1163, "(1)" + line 702, "pan.___", state 1188, "-end-" + (100 of 1188 states) +unreached in proctype :init: + line 709, "pan.___", state 9, "((j<2))" + line 709, "pan.___", state 9, "((j>=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 12.8 seconds +pan: rate 113424.69 states/second +pan: avg transition delay 8.6181e-07 usec +cp .input.spin urcu_free_single_flip.spin.input +cp .input.spin.trail urcu_free_single_flip.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input new file mode 100644 index 0000000..103464e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input @@ -0,0 +1,723 @@ +#define SINGLE_FLIP + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input.trail new file mode 100644 index 0000000..e81c46c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_free_single_flip.spin.input.trail @@ -0,0 +1,1355 @@ +-2:4:-2 +-4:-4:-4 +1:0:2103 +2:4:2055 +3:4:2058 +4:4:2058 +5:4:2061 +6:4:2069 +7:4:2069 +8:4:2072 +9:4:2078 +10:4:2082 +11:4:2082 +12:4:2085 +13:4:2093 +14:4:2097 +15:4:2098 +16:0:2103 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+1347:3:2048 +1348:0:2103 +1349:2:759 +1350:0:2101 +1351:3:2049 +1352:0:2107 +1353:3:1181 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress.ltl b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress.ltl new file mode 100644 index 0000000..8718641 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress.ltl @@ -0,0 +1 @@ +([] <> !np_) diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.define new file mode 100644 index 0000000..ff3f783 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.define @@ -0,0 +1 @@ +#define READER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.log new file mode 100644 index 0000000..e3ec127 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.log @@ -0,0 +1,506 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_reader.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +depth 15: Claim reached state 9 (line 749) +depth 1803: Claim reached state 9 (line 748) +Depth= 5838 States= 1e+06 Transitions= 1.06e+07 Memory= 494.865 t= 9.24 R= 1e+05 +Depth= 5838 States= 2e+06 Transitions= 1.97e+07 Memory= 532.658 t= 17.7 R= 1e+05 +Depth= 5838 States= 3e+06 Transitions= 3.15e+07 Memory= 555.315 t= 28.4 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 6855 States= 4e+06 Transitions= 4.32e+07 Memory= 613.096 t= 39.1 R= 1e+05 +Depth= 9059 States= 5e+06 Transitions= 5.48e+07 Memory= 642.295 t= 49.5 R= 1e+05 +Depth= 9059 States= 6e+06 Transitions= 6.91e+07 Memory= 672.178 t= 62.5 R= 1e+05 +Depth= 9059 States= 7e+06 Transitions= 7.99e+07 Memory= 706.455 t= 72.5 R= 1e+05 +Depth= 9059 States= 8e+06 Transitions= 9.23e+07 Memory= 735.752 t= 84 R= 1e+05 +Depth= 9059 States= 9e+06 Transitions= 1.04e+08 Memory= 766.318 t= 94.5 R= 1e+05 +pan: resizing hashtable to -w24.. done +Depth= 9059 States= 1e+07 Transitions= 1.16e+08 Memory= 920.002 t= 106 R= 9e+04 +Depth= 9059 States= 1.1e+07 Transitions= 1.3e+08 Memory= 945.002 t= 119 R= 9e+04 +Depth= 9059 States= 1.2e+07 Transitions= 1.54e+08 Memory= 967.756 t= 140 R= 9e+04 +Depth= 9059 States= 1.3e+07 Transitions= 1.72e+08 Memory= 995.002 t= 157 R= 8e+04 +Depth= 9059 States= 1.4e+07 Transitions= 1.92e+08 Memory= 1022.736 t= 175 R= 8e+04 +Depth= 9059 States= 1.5e+07 Transitions= 2.1e+08 Memory= 1050.080 t= 191 R= 8e+04 +Depth= 9059 States= 1.6e+07 Transitions= 2.22e+08 Memory= 1082.502 t= 203 R= 8e+04 +Depth= 9059 States= 1.7e+07 Transitions= 2.41e+08 Memory= 1108.479 t= 219 R= 8e+04 +Depth= 9059 States= 1.8e+07 Transitions= 2.58e+08 Memory= 1134.455 t= 235 R= 8e+04 +Depth= 9059 States= 1.9e+07 Transitions= 2.7e+08 Memory= 1164.533 t= 246 R= 8e+04 +Depth= 9059 States= 2e+07 Transitions= 2.83e+08 Memory= 1193.830 t= 258 R= 8e+04 +Depth= 9059 States= 2.1e+07 Transitions= 3.03e+08 Memory= 1219.026 t= 276 R= 8e+04 +Depth= 9059 States= 2.2e+07 Transitions= 3.19e+08 Memory= 1248.420 t= 291 R= 8e+04 +Depth= 9059 States= 2.3e+07 Transitions= 3.42e+08 Memory= 1271.858 t= 312 R= 7e+04 +Depth= 9059 States= 2.4e+07 Transitions= 3.6e+08 Memory= 1298.908 t= 328 R= 7e+04 +Depth= 9059 States= 2.5e+07 Transitions= 3.84e+08 Memory= 1323.127 t= 350 R= 7e+04 +Depth= 9059 States= 2.6e+07 Transitions= 4e+08 Memory= 1348.518 t= 365 R= 7e+04 +Depth= 9059 States= 2.7e+07 Transitions= 4.16e+08 Memory= 1379.865 t= 380 R= 7e+04 +Depth= 9059 States= 2.8e+07 Transitions= 4.26e+08 Memory= 1411.115 t= 389 R= 7e+04 +Depth= 9059 States= 2.9e+07 Transitions= 4.42e+08 Memory= 1439.631 t= 404 R= 7e+04 +Depth= 9059 States= 3e+07 Transitions= 4.64e+08 Memory= 1462.385 t= 423 R= 7e+04 +Depth= 9059 States= 3.1e+07 Transitions= 4.82e+08 Memory= 1490.998 t= 439 R= 7e+04 +Depth= 9059 States= 3.2e+07 Transitions= 4.99e+08 Memory= 1519.514 t= 456 R= 7e+04 +Depth= 9059 States= 3.3e+07 Transitions= 5.18e+08 Memory= 1545.393 t= 473 R= 7e+04 +Depth= 9059 States= 3.4e+07 Transitions= 5.33e+08 Memory= 1578.108 t= 486 R= 7e+04 +pan: resizing hashtable to -w26.. done +Depth= 9059 States= 3.5e+07 Transitions= 5.49e+08 Memory= 2098.994 t= 504 R= 7e+04 +Depth= 9059 States= 3.6e+07 Transitions= 5.74e+08 Memory= 2121.651 t= 528 R= 7e+04 +Depth= 9059 States= 3.7e+07 Transitions= 5.96e+08 Memory= 2147.334 t= 547 R= 7e+04 +Depth= 9059 States= 3.8e+07 Transitions= 6.17e+08 Memory= 2170.186 t= 567 R= 7e+04 +Depth= 9059 States= 3.9e+07 Transitions= 6.3e+08 Memory= 2199.776 t= 578 R= 7e+04 +Depth= 9059 States= 4e+07 Transitions= 6.53e+08 Memory= 2225.459 t= 599 R= 7e+04 +Depth= 9059 States= 4.1e+07 Transitions= 6.69e+08 Memory= 2250.361 t= 614 R= 7e+04 +Depth= 9059 States= 4.2e+07 Transitions= 6.85e+08 Memory= 2279.268 t= 628 R= 7e+04 +Depth= 9059 States= 4.3e+07 Transitions= 7.03e+08 Memory= 2304.463 t= 644 R= 7e+04 +Depth= 9059 States= 4.4e+07 Transitions= 7.13e+08 Memory= 2338.252 t= 654 R= 7e+04 +Depth= 9059 States= 4.5e+07 Transitions= 7.25e+08 Memory= 2366.768 t= 665 R= 7e+04 +Depth= 9059 States= 4.6e+07 Transitions= 7.41e+08 Memory= 2393.330 t= 679 R= 7e+04 +Depth= 9059 States= 4.7e+07 Transitions= 7.57e+08 Memory= 2420.381 t= 694 R= 7e+04 +Depth= 9059 States= 4.8e+07 Transitions= 7.72e+08 Memory= 2447.041 t= 708 R= 7e+04 +Depth= 9059 States= 4.9e+07 Transitions= 7.88e+08 Memory= 2476.143 t= 722 R= 7e+04 +Depth= 9059 States= 5e+07 Transitions= 8.04e+08 Memory= 2501.045 t= 737 R= 7e+04 +Depth= 9059 States= 5.1e+07 Transitions= 8.2e+08 Memory= 2530.440 t= 752 R= 7e+04 +Depth= 9059 States= 5.2e+07 Transitions= 8.37e+08 Memory= 2554.854 t= 766 R= 7e+04 +Depth= 9059 States= 5.3e+07 Transitions= 8.5e+08 Memory= 2583.467 t= 779 R= 7e+04 +Depth= 9059 States= 5.4e+07 Transitions= 8.66e+08 Memory= 2611.299 t= 794 R= 7e+04 +Depth= 9059 States= 5.5e+07 Transitions= 8.79e+08 Memory= 2640.791 t= 805 R= 7e+04 +Depth= 9059 States= 5.6e+07 Transitions= 8.9e+08 Memory= 2672.139 t= 815 R= 7e+04 +Depth= 9059 States= 5.7e+07 Transitions= 9.05e+08 Memory= 2702.705 t= 829 R= 7e+04 +Depth= 9059 States= 5.8e+07 Transitions= 9.22e+08 Memory= 2727.998 t= 845 R= 7e+04 +Depth= 9059 States= 5.9e+07 Transitions= 9.38e+08 Memory= 2754.463 t= 859 R= 7e+04 +Depth= 9059 States= 6e+07 Transitions= 9.49e+08 Memory= 2789.717 t= 870 R= 7e+04 +Depth= 9059 States= 6.1e+07 Transitions= 9.62e+08 Memory= 2817.744 t= 881 R= 7e+04 +Depth= 9059 States= 6.2e+07 Transitions= 9.79e+08 Memory= 2838.447 t= 896 R= 7e+04 +Depth= 9059 States= 6.3e+07 Transitions= 1e+09 Memory= 2863.154 t= 919 R= 7e+04 +Depth= 9059 States= 6.4e+07 Transitions= 1.02e+09 Memory= 2889.131 t= 936 R= 7e+04 +Depth= 9059 States= 6.5e+07 Transitions= 1.04e+09 Memory= 2919.502 t= 952 R= 7e+04 +Depth= 9059 States= 6.6e+07 Transitions= 1.06e+09 Memory= 2943.916 t= 968 R= 7e+04 +Depth= 9059 States= 6.7e+07 Transitions= 1.07e+09 Memory= 2978.975 t= 979 R= 7e+04 +Depth= 9059 States= 6.8e+07 Transitions= 1.09e+09 Memory= 3003.877 t= 996 R= 7e+04 +Depth= 9059 States= 6.9e+07 Transitions= 1.11e+09 Memory= 3028.584 t= 1.01e+03 R= 7e+04 +Depth= 9059 States= 7e+07 Transitions= 1.12e+09 Memory= 3058.174 t= 1.02e+03 R= 7e+04 +Depth= 9059 States= 7.1e+07 Transitions= 1.13e+09 Memory= 3088.350 t= 1.04e+03 R= 7e+04 +Depth= 9059 States= 7.2e+07 Transitions= 1.15e+09 Memory= 3113.350 t= 1.05e+03 R= 7e+04 +Depth= 9059 States= 7.3e+07 Transitions= 1.17e+09 Memory= 3142.158 t= 1.07e+03 R= 7e+04 +Depth= 9059 States= 7.4e+07 Transitions= 1.19e+09 Memory= 3166.279 t= 1.09e+03 R= 7e+04 +Depth= 9059 States= 7.5e+07 Transitions= 1.21e+09 Memory= 3192.744 t= 1.11e+03 R= 7e+04 +Depth= 9059 States= 7.6e+07 Transitions= 1.23e+09 Memory= 3217.256 t= 1.13e+03 R= 7e+04 +Depth= 9059 States= 7.7e+07 Transitions= 1.25e+09 Memory= 3242.549 t= 1.14e+03 R= 7e+04 +Depth= 9059 States= 7.8e+07 Transitions= 1.26e+09 Memory= 3273.115 t= 1.16e+03 R= 7e+04 +Depth= 9059 States= 7.9e+07 Transitions= 1.27e+09 Memory= 3303.975 t= 1.17e+03 R= 7e+04 +Depth= 9059 States= 8e+07 Transitions= 1.29e+09 Memory= 3334.541 t= 1.18e+03 R= 7e+04 +Depth= 9059 States= 8.1e+07 Transitions= 1.31e+09 Memory= 3356.221 t= 1.2e+03 R= 7e+04 +Depth= 9059 States= 8.2e+07 Transitions= 1.33e+09 Memory= 3385.127 t= 1.22e+03 R= 7e+04 +Depth= 9059 States= 8.3e+07 Transitions= 1.35e+09 Memory= 3412.959 t= 1.23e+03 R= 7e+04 +Depth= 9059 States= 8.4e+07 Transitions= 1.37e+09 Memory= 3438.936 t= 1.25e+03 R= 7e+04 +Depth= 9059 States= 8.5e+07 Transitions= 1.38e+09 Memory= 3471.455 t= 1.26e+03 R= 7e+04 +Depth= 9059 States= 8.6e+07 Transitions= 1.4e+09 Memory= 3498.115 t= 1.28e+03 R= 7e+04 +Depth= 9059 States= 8.7e+07 Transitions= 1.42e+09 Memory= 3519.014 t= 1.3e+03 R= 7e+04 +Depth= 9059 States= 8.8e+07 Transitions= 1.44e+09 Memory= 3546.162 t= 1.32e+03 R= 7e+04 +Depth= 9059 States= 8.9e+07 Transitions= 1.46e+09 Memory= 3567.842 t= 1.34e+03 R= 7e+04 +Depth= 9059 States= 9e+07 Transitions= 1.48e+09 Memory= 3598.799 t= 1.35e+03 R= 7e+04 +Depth= 9059 States= 9.1e+07 Transitions= 1.5e+09 Memory= 3622.920 t= 1.37e+03 R= 7e+04 +Depth= 9059 States= 9.2e+07 Transitions= 1.52e+09 Memory= 3648.701 t= 1.39e+03 R= 7e+04 +Depth= 9059 States= 9.3e+07 Transitions= 1.53e+09 Memory= 3676.045 t= 1.4e+03 R= 7e+04 +Depth= 9059 States= 9.4e+07 Transitions= 1.55e+09 Memory= 3702.412 t= 1.42e+03 R= 7e+04 +Depth= 9059 States= 9.5e+07 Transitions= 1.56e+09 Memory= 3735.713 t= 1.43e+03 R= 7e+04 +Depth= 9059 States= 9.6e+07 Transitions= 1.57e+09 Memory= 3764.522 t= 1.44e+03 R= 7e+04 +Depth= 9059 States= 9.7e+07 Transitions= 1.59e+09 Memory= 3790.693 t= 1.45e+03 R= 7e+04 +Depth= 9059 States= 9.8e+07 Transitions= 1.61e+09 Memory= 3817.940 t= 1.47e+03 R= 7e+04 +Depth= 9059 States= 9.9e+07 Transitions= 1.62e+09 Memory= 3845.283 t= 1.48e+03 R= 7e+04 +Depth= 9059 States= 1e+08 Transitions= 1.64e+09 Memory= 3873.213 t= 1.5e+03 R= 7e+04 +Depth= 9059 States= 1.01e+08 Transitions= 1.65e+09 Memory= 3897.920 t= 1.51e+03 R= 7e+04 +Depth= 9059 States= 1.02e+08 Transitions= 1.67e+09 Memory= 3926.631 t= 1.53e+03 R= 7e+04 +Depth= 9059 States= 1.03e+08 Transitions= 1.68e+09 Memory= 3952.315 t= 1.54e+03 R= 7e+04 +Depth= 9059 States= 1.04e+08 Transitions= 1.7e+09 Memory= 3981.026 t= 1.56e+03 R= 7e+04 +Depth= 9059 States= 1.05e+08 Transitions= 1.71e+09 Memory= 4010.029 t= 1.57e+03 R= 7e+04 +Depth= 9059 States= 1.06e+08 Transitions= 1.73e+09 Memory= 4038.838 t= 1.58e+03 R= 7e+04 +Depth= 9059 States= 1.07e+08 Transitions= 1.74e+09 Memory= 4070.381 t= 1.59e+03 R= 7e+04 +Depth= 9059 States= 1.08e+08 Transitions= 1.75e+09 Memory= 4099.385 t= 1.61e+03 R= 7e+04 +Depth= 9059 States= 1.09e+08 Transitions= 1.77e+09 Memory= 4126.338 t= 1.62e+03 R= 7e+04 +Depth= 9059 States= 1.1e+08 Transitions= 1.79e+09 Memory= 4151.924 t= 1.64e+03 R= 7e+04 +Depth= 9059 States= 1.11e+08 Transitions= 1.8e+09 Memory= 4187.276 t= 1.65e+03 R= 7e+04 +Depth= 9059 States= 1.12e+08 Transitions= 1.81e+09 Memory= 4214.326 t= 1.66e+03 R= 7e+04 +Depth= 9059 States= 1.13e+08 Transitions= 1.83e+09 Memory= 4237.471 t= 1.67e+03 R= 7e+04 +Depth= 9059 States= 1.14e+08 Transitions= 1.85e+09 Memory= 4261.104 t= 1.7e+03 R= 7e+04 +Depth= 9059 States= 1.15e+08 Transitions= 1.87e+09 Memory= 4286.690 t= 1.71e+03 R= 7e+04 +Depth= 9059 States= 1.16e+08 Transitions= 1.89e+09 Memory= 4314.619 t= 1.73e+03 R= 7e+04 +Depth= 9059 States= 1.17e+08 Transitions= 1.91e+09 Memory= 4341.768 t= 1.75e+03 R= 7e+04 +Depth= 9059 States= 1.18e+08 Transitions= 1.92e+09 Memory= 4375.166 t= 1.76e+03 R= 7e+04 +Depth= 9059 States= 1.19e+08 Transitions= 1.94e+09 Memory= 4401.338 t= 1.78e+03 R= 7e+04 +Depth= 9059 States= 1.2e+08 Transitions= 1.95e+09 Memory= 4426.436 t= 1.79e+03 R= 7e+04 +Depth= 9059 States= 1.21e+08 Transitions= 1.97e+09 Memory= 4456.807 t= 1.8e+03 R= 7e+04 +Depth= 9059 States= 1.22e+08 Transitions= 1.98e+09 Memory= 4486.592 t= 1.82e+03 R= 7e+04 +Depth= 9059 States= 1.23e+08 Transitions= 2e+09 Memory= 4511.787 t= 1.83e+03 R= 7e+04 +Depth= 9059 States= 1.24e+08 Transitions= 2.02e+09 Memory= 4540.108 t= 1.85e+03 R= 7e+04 +Depth= 9059 States= 1.25e+08 Transitions= 2.04e+09 Memory= 4564.033 t= 1.87e+03 R= 7e+04 +Depth= 9059 States= 1.26e+08 Transitions= 2.06e+09 Memory= 4591.865 t= 1.89e+03 R= 7e+04 +Depth= 9059 States= 1.27e+08 Transitions= 2.08e+09 Memory= 4615.889 t= 1.91e+03 R= 7e+04 +Depth= 9059 States= 1.28e+08 Transitions= 2.1e+09 Memory= 4640.303 t= 1.92e+03 R= 7e+04 +Depth= 9059 States= 1.29e+08 Transitions= 2.11e+09 Memory= 4670.479 t= 1.94e+03 R= 7e+04 +Depth= 9059 States= 1.3e+08 Transitions= 2.12e+09 Memory= 4702.998 t= 1.95e+03 R= 7e+04 +Depth= 9059 States= 1.31e+08 Transitions= 2.14e+09 Memory= 4732.393 t= 1.96e+03 R= 7e+04 +Depth= 9059 States= 1.32e+08 Transitions= 2.16e+09 Memory= 4754.756 t= 1.98e+03 R= 7e+04 +Depth= 9059 States= 1.33e+08 Transitions= 2.18e+09 Memory= 4783.174 t= 2e+03 R= 7e+04 +Depth= 9059 States= 1.34e+08 Transitions= 2.19e+09 Memory= 4810.518 t= 2.01e+03 R= 7e+04 +Depth= 9059 States= 1.35e+08 Transitions= 2.21e+09 Memory= 4837.568 t= 2.03e+03 R= 7e+04 +pan: resizing hashtable to -w28.. done +Depth= 9059 States= 1.36e+08 Transitions= 2.23e+09 Memory= 6885.568 t= 2.06e+03 R= 7e+04 +Depth= 9059 States= 1.37e+08 Transitions= 2.24e+09 Memory= 6885.568 t= 2.08e+03 R= 7e+04 +Depth= 9059 States= 1.38e+08 Transitions= 2.27e+09 Memory= 6900.412 t= 2.1e+03 R= 7e+04 +Depth= 9059 States= 1.39e+08 Transitions= 2.29e+09 Memory= 6927.658 t= 2.12e+03 R= 7e+04 +Depth= 9059 States= 1.4e+08 Transitions= 2.31e+09 Memory= 6950.315 t= 2.14e+03 R= 7e+04 +Depth= 9059 States= 1.41e+08 Transitions= 2.33e+09 Memory= 6981.858 t= 2.15e+03 R= 7e+04 +Depth= 9059 States= 1.42e+08 Transitions= 2.35e+09 Memory= 7005.295 t= 2.17e+03 R= 7e+04 +Depth= 9059 States= 1.43e+08 Transitions= 2.36e+09 Memory= 7031.076 t= 2.18e+03 R= 7e+04 +Depth= 9059 States= 1.44e+08 Transitions= 2.38e+09 Memory= 7056.955 t= 2.2e+03 R= 7e+04 +Depth= 9059 States= 1.45e+08 Transitions= 2.4e+09 Memory= 7084.494 t= 2.22e+03 R= 7e+04 +Depth= 9059 States= 1.46e+08 Transitions= 2.41e+09 Memory= 7115.744 t= 2.23e+03 R= 7e+04 +Depth= 9059 States= 1.47e+08 Transitions= 2.42e+09 Memory= 7146.604 t= 2.24e+03 R= 7e+04 +Depth= 9059 States= 1.48e+08 Transitions= 2.44e+09 Memory= 7172.287 t= 2.25e+03 R= 7e+04 +Depth= 9059 States= 1.49e+08 Transitions= 2.45e+09 Memory= 7200.315 t= 2.26e+03 R= 7e+04 +Depth= 9059 States= 1.5e+08 Transitions= 2.47e+09 Memory= 7226.389 t= 2.28e+03 R= 7e+04 +Depth= 9059 States= 1.51e+08 Transitions= 2.48e+09 Memory= 7253.733 t= 2.29e+03 R= 7e+04 +Depth= 9059 States= 1.52e+08 Transitions= 2.5e+09 Memory= 7279.709 t= 2.31e+03 R= 7e+04 +Depth= 9059 States= 1.53e+08 Transitions= 2.52e+09 Memory= 7309.104 t= 2.32e+03 R= 7e+04 +Depth= 9059 States= 1.54e+08 Transitions= 2.53e+09 Memory= 7334.592 t= 2.34e+03 R= 7e+04 +Depth= 9059 States= 1.55e+08 Transitions= 2.55e+09 Memory= 7362.229 t= 2.35e+03 R= 7e+04 +Depth= 9059 States= 1.56e+08 Transitions= 2.56e+09 Memory= 7391.135 t= 2.36e+03 R= 7e+04 +Depth= 9059 States= 1.57e+08 Transitions= 2.57e+09 Memory= 7420.822 t= 2.38e+03 R= 7e+04 +Depth= 9059 States= 1.58e+08 Transitions= 2.59e+09 Memory= 7452.854 t= 2.39e+03 R= 7e+04 +Depth= 9059 States= 1.59e+08 Transitions= 2.6e+09 Memory= 7481.760 t= 2.4e+03 R= 7e+04 +Depth= 9059 States= 1.6e+08 Transitions= 2.62e+09 Memory= 7509.299 t= 2.41e+03 R= 7e+04 +Depth= 9059 States= 1.61e+08 Transitions= 2.63e+09 Memory= 7534.201 t= 2.43e+03 R= 7e+04 +Depth= 9059 States= 1.62e+08 Transitions= 2.65e+09 Memory= 7567.600 t= 2.44e+03 R= 7e+04 +Depth= 9059 States= 1.63e+08 Transitions= 2.66e+09 Memory= 7594.846 t= 2.45e+03 R= 7e+04 +Depth= 9059 States= 1.64e+08 Transitions= 2.67e+09 Memory= 7619.455 t= 2.47e+03 R= 7e+04 +Depth= 9059 States= 1.65e+08 Transitions= 2.7e+09 Memory= 7642.502 t= 2.49e+03 R= 7e+04 +Depth= 9059 States= 1.66e+08 Transitions= 2.72e+09 Memory= 7669.260 t= 2.51e+03 R= 7e+04 +Depth= 9059 States= 1.67e+08 Transitions= 2.73e+09 Memory= 7696.799 t= 2.52e+03 R= 7e+04 +Depth= 9059 States= 1.68e+08 Transitions= 2.75e+09 Memory= 7723.850 t= 2.54e+03 R= 7e+04 +Depth= 9059 States= 1.69e+08 Transitions= 2.77e+09 Memory= 7757.053 t= 2.55e+03 R= 7e+04 +Depth= 9059 States= 1.7e+08 Transitions= 2.78e+09 Memory= 7782.346 t= 2.57e+03 R= 7e+04 +Depth= 9059 States= 1.71e+08 Transitions= 2.8e+09 Memory= 7808.908 t= 2.58e+03 R= 7e+04 +Depth= 9059 States= 1.72e+08 Transitions= 2.81e+09 Memory= 7838.791 t= 2.59e+03 R= 7e+04 +Depth= 9059 States= 1.73e+08 Transitions= 2.83e+09 Memory= 7867.893 t= 2.61e+03 R= 7e+04 +Depth= 9059 States= 1.74e+08 Transitions= 2.85e+09 Memory= 7892.990 t= 2.62e+03 R= 7e+04 +Depth= 9059 States= 1.75e+08 Transitions= 2.86e+09 Memory= 7922.190 t= 2.64e+03 R= 7e+04 +Depth= 9059 States= 1.76e+08 Transitions= 2.89e+09 Memory= 7945.627 t= 2.66e+03 R= 7e+04 +Depth= 9059 States= 1.77e+08 Transitions= 2.9e+09 Memory= 7973.947 t= 2.68e+03 R= 7e+04 +Depth= 9059 States= 1.78e+08 Transitions= 2.93e+09 Memory= 7997.483 t= 2.7e+03 R= 7e+04 +Depth= 9059 States= 1.79e+08 Transitions= 2.94e+09 Memory= 8020.920 t= 2.71e+03 R= 7e+04 +Depth= 9059 States= 1.8e+08 Transitions= 2.96e+09 Memory= 8050.412 t= 2.73e+03 R= 7e+04 +Depth= 9059 States= 1.81e+08 Transitions= 2.97e+09 Memory= 8085.666 t= 2.74e+03 R= 7e+04 +Depth= 9059 States= 1.82e+08 Transitions= 2.98e+09 Memory= 8114.279 t= 2.75e+03 R= 7e+04 +Depth= 9059 States= 1.83e+08 Transitions= 3e+09 Memory= 8137.131 t= 2.77e+03 R= 7e+04 +Depth= 9059 States= 1.84e+08 Transitions= 3.02e+09 Memory= 8165.451 t= 2.79e+03 R= 7e+04 +Depth= 9059 States= 1.85e+08 Transitions= 3.04e+09 Memory= 8193.186 t= 2.8e+03 R= 7e+04 +Depth= 9059 States= 1.86e+08 Transitions= 3.06e+09 Memory= 8218.674 t= 2.82e+03 R= 7e+04 +Depth= 9059 States= 1.87e+08 Transitions= 3.08e+09 Memory= 8255.100 t= 2.83e+03 R= 7e+04 +Depth= 9059 States= 1.88e+08 Transitions= 3.09e+09 Memory= 8279.221 t= 2.85e+03 R= 7e+04 +Depth= 9059 States= 1.89e+08 Transitions= 3.12e+09 Memory= 8298.264 t= 2.87e+03 R= 7e+04 +Depth= 9059 States= 1.9e+08 Transitions= 3.14e+09 Memory= 8325.998 t= 2.89e+03 R= 7e+04 +Depth= 9059 States= 1.91e+08 Transitions= 3.16e+09 Memory= 8349.338 t= 2.91e+03 R= 7e+04 +Depth= 9059 States= 1.92e+08 Transitions= 3.17e+09 Memory= 8379.221 t= 2.92e+03 R= 7e+04 +Depth= 9059 States= 1.93e+08 Transitions= 3.19e+09 Memory= 8403.440 t= 2.94e+03 R= 7e+04 +Depth= 9059 States= 1.94e+08 Transitions= 3.21e+09 Memory= 8430.100 t= 2.96e+03 R= 7e+04 +Depth= 9059 States= 1.95e+08 Transitions= 3.23e+09 Memory= 8455.295 t= 2.97e+03 R= 7e+04 +Depth= 9059 States= 1.96e+08 Transitions= 3.25e+09 Memory= 8482.932 t= 2.99e+03 R= 7e+04 +Depth= 9059 States= 1.97e+08 Transitions= 3.26e+09 Memory= 8515.256 t= 3e+03 R= 7e+04 +Depth= 9059 States= 1.98e+08 Transitions= 3.27e+09 Memory= 8542.502 t= 3.01e+03 R= 7e+04 +Depth= 9059 States= 1.99e+08 Transitions= 3.29e+09 Memory= 8569.260 t= 3.02e+03 R= 7e+04 +Depth= 9059 States= 2e+08 Transitions= 3.3e+09 Memory= 8598.459 t= 3.04e+03 R= 7e+04 +Depth= 9059 States= 2.01e+08 Transitions= 3.32e+09 Memory= 8624.631 t= 3.05e+03 R= 7e+04 +Depth= 9059 States= 2.02e+08 Transitions= 3.33e+09 Memory= 8652.365 t= 3.07e+03 R= 7e+04 +Depth= 9059 States= 2.03e+08 Transitions= 3.35e+09 Memory= 8678.440 t= 3.08e+03 R= 7e+04 +Depth= 9059 States= 2.04e+08 Transitions= 3.36e+09 Memory= 8706.369 t= 3.1e+03 R= 7e+04 +Depth= 9059 States= 2.05e+08 Transitions= 3.38e+09 Memory= 8732.932 t= 3.11e+03 R= 7e+04 +Depth= 9059 States= 2.06e+08 Transitions= 3.39e+09 Memory= 8760.276 t= 3.12e+03 R= 7e+04 +Depth= 9059 States= 2.07e+08 Transitions= 3.41e+09 Memory= 8789.475 t= 3.14e+03 R= 7e+04 +Depth= 9059 States= 2.08e+08 Transitions= 3.42e+09 Memory= 8819.455 t= 3.15e+03 R= 7e+04 +Depth= 9059 States= 2.09e+08 Transitions= 3.43e+09 Memory= 8851.779 t= 3.16e+03 R= 7e+04 +Depth= 9059 States= 2.1e+08 Transitions= 3.45e+09 Memory= 8880.100 t= 3.17e+03 R= 7e+04 +Depth= 9059 States= 2.11e+08 Transitions= 3.46e+09 Memory= 8907.053 t= 3.19e+03 R= 7e+04 +Depth= 9059 States= 2.12e+08 Transitions= 3.48e+09 Memory= 8932.639 t= 3.2e+03 R= 7e+04 +Depth= 9059 States= 2.13e+08 Transitions= 3.49e+09 Memory= 8964.572 t= 3.22e+03 R= 7e+04 +Depth= 9059 States= 2.14e+08 Transitions= 3.51e+09 Memory= 8991.526 t= 3.23e+03 R= 7e+04 +Depth= 9059 States= 2.15e+08 Transitions= 3.52e+09 Memory= 9018.088 t= 3.24e+03 R= 7e+04 +Depth= 9059 States= 2.16e+08 Transitions= 3.54e+09 Memory= 9039.865 t= 3.26e+03 R= 7e+04 +Depth= 9059 States= 2.17e+08 Transitions= 3.56e+09 Memory= 9067.600 t= 3.28e+03 R= 7e+04 +Depth= 9059 States= 2.18e+08 Transitions= 3.58e+09 Memory= 9094.260 t= 3.3e+03 R= 7e+04 +Depth= 9059 States= 2.19e+08 Transitions= 3.6e+09 Memory= 9122.483 t= 3.31e+03 R= 7e+04 +Depth= 9059 States= 2.2e+08 Transitions= 3.61e+09 Memory= 9153.635 t= 3.32e+03 R= 7e+04 +Depth= 9059 States= 2.21e+08 Transitions= 3.63e+09 Memory= 9181.272 t= 3.34e+03 R= 7e+04 +Depth= 9059 States= 2.22e+08 Transitions= 3.65e+09 Memory= 9207.639 t= 3.36e+03 R= 7e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 9059, errors: 0 + 88961904 states, stored (2.22145e+08 visited) +3.4291111e+09 states, matched +3.6512561e+09 transitions (= visited+matched) +1.2885947e+10 atomic steps +hash conflicts: 7.2188776e+08 (resolved) + +Stats on memory usage (in Megabytes): + 7805.343 equivalent memory usage for states (stored*(State-vector + overhead)) + 6706.219 actual memory usage for states (compression: 85.92%) + state-vector as stored = 51 byte + 28 byte overhead + 2048.000 memory used for hash table (-w28) + 457.764 memory used for DFS stack (-m10000000) + 1.122 memory lost to fragmentation + 9210.861 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 256, "(1)" + line 418, "pan.___", state 286, "(1)" + line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 395, "(1)" + line 418, "pan.___", state 425, "(1)" + line 540, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 70, "(1)" + line 418, "pan.___", state 100, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 247, "(1)" + line 418, "pan.___", state 277, "(1)" + line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 359, "(1)" + line 418, "pan.___", state 389, "(1)" + line 614, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 370, "(1)" + line 164, "pan.___", state 378, "(1)" + line 168, "pan.___", state 390, "(1)" + line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 449, "(1)" + line 413, "pan.___", state 462, "(1)" + line 418, "pan.___", state 479, "(1)" + line 399, "pan.___", state 498, "(1)" + line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 554, "(1)" + line 418, "pan.___", state 571, "(1)" + line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 647, "(1)" + line 418, "pan.___", state 664, "(1)" + line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 710, "(1)" + line 164, "pan.___", state 718, "(1)" + line 168, "pan.___", state 730, "(1)" + line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 840, "(1)" + line 164, "pan.___", state 848, "(1)" + line 168, "pan.___", state 860, "(1)" + line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 884, "(1)" + line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 885, "else" + line 399, "pan.___", state 888, "(1)" + line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 898, "(1)" + line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 899, "else" + line 403, "pan.___", state 902, "(1)" + line 403, "pan.___", state 903, "(1)" + line 403, "pan.___", state 903, "(1)" + line 401, "pan.___", state 908, "((i<1))" + line 401, "pan.___", state 908, "((i>=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1040, "(1)" + line 418, "pan.___", state 1057, "(1)" + line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1130, "(1)" + line 418, "pan.___", state 1147, "(1)" + line 399, "pan.___", state 1166, "(1)" + line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1222, "(1)" + line 418, "pan.___", state 1239, "(1)" + line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1315, "(1)" + line 418, "pan.___", state 1332, "(1)" + line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1378, "(1)" + line 164, "pan.___", state 1386, "(1)" + line 168, "pan.___", state 1398, "(1)" + line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1508, "(1)" + line 164, "pan.___", state 1516, "(1)" + line 168, "pan.___", state 1528, "(1)" + line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1552, "(1)" + line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1553, "else" + line 399, "pan.___", state 1556, "(1)" + line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1566, "(1)" + line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1567, "else" + line 403, "pan.___", state 1570, "(1)" + line 403, "pan.___", state 1571, "(1)" + line 403, "pan.___", state 1571, "(1)" + line 401, "pan.___", state 1576, "((i<1))" + line 401, "pan.___", state 1576, "((i>=1))" + line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1595, "(1)" + line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 1596, "else" + line 409, "pan.___", state 1599, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 413, "pan.___", state 1608, "(1)" + line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 1609, "else" + line 413, "pan.___", state 1612, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 411, "pan.___", state 1618, "((i<1))" + line 411, "pan.___", state 1618, "((i>=1))" + line 418, "pan.___", state 1625, "(1)" + line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 1626, "else" + line 418, "pan.___", state 1629, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1681, "(1)" + line 164, "pan.___", state 1689, "(1)" + line 168, "pan.___", state 1701, "(1)" + line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1811, "(1)" + line 164, "pan.___", state 1819, "(1)" + line 168, "pan.___", state 1831, "(1)" + line 702, "pan.___", state 1856, "-end-" + (158 of 1856 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 751, "pan.___", state 11, "-end-" + (1 of 11 states) + +pan: elapsed time 3.36e+03 seconds +pan: rate 66138.803 states/second +pan: avg transition delay 9.1989e-07 usec +cp .input.spin urcu_progress_reader.spin.input +cp .input.spin.trail urcu_progress_reader.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input new file mode 100644 index 0000000..91b1126 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input @@ -0,0 +1,723 @@ +#define READER_PROGRESS + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input.trail new file mode 100644 index 0000000..7c42af1 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_reader.spin.input.trail @@ -0,0 +1,1270 @@ +-2:4:-2 +-4:-4:-4 +1:0:4401 +2:4:4353 +3:4:4356 +4:4:4356 +5:4:4359 +6:4:4367 +7:4:4367 +8:4:4370 +9:4:4376 +10:4:4380 +11:4:4380 +12:4:4383 +13:4:4391 +14:4:4395 +15:4:4396 +16:0:4401 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+1252:0:4405 +1253:1:105 +1254:0:4405 +1255:3:4347 +1256:0:4405 +1257:3:4346 +1258:0:4405 +1259:2:1348 +1260:0:4405 +1261:3:4347 +1262:0:4405 +1263:2:1347 +1264:0:4405 +1265:3:4346 +1266:0:4405 +1267:1:104 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.define new file mode 100644 index 0000000..1e4417f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.define @@ -0,0 +1 @@ +#define WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.log new file mode 100644 index 0000000..fc83245 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.log @@ -0,0 +1,524 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +depth 15: Claim reached state 9 (line 749) +depth 1194: Claim reached state 9 (line 748) +Depth= 3253 States= 1e+06 Transitions= 1.06e+07 Memory= 484.416 t= 9.64 R= 1e+05 +Depth= 3253 States= 2e+06 Transitions= 2.04e+07 Memory= 501.311 t= 18.6 R= 1e+05 +Depth= 3253 States= 3e+06 Transitions= 3.44e+07 Memory= 516.252 t= 31.6 R= 9e+04 +pan: resizing hashtable to -w22.. done +Depth= 7995 States= 4e+06 Transitions= 4.66e+07 Memory= 563.486 t= 42.8 R= 9e+04 +Depth= 7995 States= 5e+06 Transitions= 6.05e+07 Memory= 580.674 t= 55.6 R= 9e+04 +Depth= 7995 States= 6e+06 Transitions= 7.12e+07 Memory= 599.229 t= 65.5 R= 9e+04 +Depth= 7995 States= 7e+06 Transitions= 8.58e+07 Memory= 613.975 t= 78.9 R= 9e+04 +Depth= 7995 States= 8e+06 Transitions= 9.62e+07 Memory= 631.846 t= 88.7 R= 9e+04 +Depth= 7995 States= 9e+06 Transitions= 1.1e+08 Memory= 646.592 t= 101 R= 9e+04 +pan: resizing hashtable to -w24.. done +Depth= 7995 States= 1e+07 Transitions= 1.32e+08 Memory= 783.869 t= 122 R= 8e+04 +Depth= 7995 States= 1.1e+07 Transitions= 1.52e+08 Memory= 799.104 t= 140 R= 8e+04 +Depth= 7995 States= 1.2e+07 Transitions= 1.71e+08 Memory= 814.533 t= 157 R= 8e+04 +Depth= 7995 States= 1.3e+07 Transitions= 1.9e+08 Memory= 829.670 t= 174 R= 7e+04 +Depth= 7995 States= 1.4e+07 Transitions= 2.01e+08 Memory= 848.029 t= 185 R= 8e+04 +Depth= 7995 States= 1.5e+07 Transitions= 2.21e+08 Memory= 862.287 t= 203 R= 7e+04 +Depth= 7995 States= 1.6e+07 Transitions= 2.35e+08 Memory= 877.815 t= 215 R= 7e+04 +Depth= 7995 States= 1.7e+07 Transitions= 2.44e+08 Memory= 897.736 t= 223 R= 8e+04 +Depth= 7995 States= 1.8e+07 Transitions= 2.57e+08 Memory= 911.115 t= 235 R= 8e+04 +Depth= 7995 States= 1.9e+07 Transitions= 2.69e+08 Memory= 927.033 t= 246 R= 8e+04 +Depth= 8341 States= 2e+07 Transitions= 2.83e+08 Memory= 943.440 t= 259 R= 8e+04 +Depth= 8341 States= 2.1e+07 Transitions= 2.96e+08 Memory= 961.604 t= 271 R= 8e+04 +Depth= 8341 States= 2.2e+07 Transitions= 3.07e+08 Memory= 978.791 t= 281 R= 8e+04 +Depth= 8341 States= 2.3e+07 Transitions= 3.2e+08 Memory= 996.369 t= 293 R= 8e+04 +Depth= 8341 States= 2.4e+07 Transitions= 3.32e+08 Memory= 1013.264 t= 304 R= 8e+04 +Depth= 8341 States= 2.5e+07 Transitions= 3.48e+08 Memory= 1024.885 t= 319 R= 8e+04 +Depth= 8341 States= 2.6e+07 Transitions= 3.72e+08 Memory= 1038.947 t= 341 R= 8e+04 +Depth= 8341 States= 2.7e+07 Transitions= 3.91e+08 Memory= 1055.158 t= 358 R= 8e+04 +Depth= 8341 States= 2.8e+07 Transitions= 4.09e+08 Memory= 1069.904 t= 374 R= 7e+04 +Depth= 8341 States= 2.9e+07 Transitions= 4.25e+08 Memory= 1086.701 t= 389 R= 7e+04 +Depth= 8341 States= 3e+07 Transitions= 4.43e+08 Memory= 1102.131 t= 405 R= 7e+04 +Depth= 8341 States= 3.1e+07 Transitions= 4.58e+08 Memory= 1117.268 t= 419 R= 7e+04 +Depth= 8341 States= 3.2e+07 Transitions= 4.68e+08 Memory= 1136.213 t= 429 R= 7e+04 +Depth= 8341 States= 3.3e+07 Transitions= 4.8e+08 Memory= 1151.154 t= 440 R= 8e+04 +Depth= 8341 States= 3.4e+07 Transitions= 4.92e+08 Memory= 1166.779 t= 451 R= 8e+04 +pan: resizing hashtable to -w26.. done +Depth= 8687 States= 3.5e+07 Transitions= 5.05e+08 Memory= 1679.658 t= 464 R= 8e+04 +Depth= 8687 States= 3.6e+07 Transitions= 5.18e+08 Memory= 1697.432 t= 477 R= 8e+04 +Depth= 8687 States= 3.7e+07 Transitions= 5.29e+08 Memory= 1714.326 t= 487 R= 8e+04 +Depth= 8687 States= 3.8e+07 Transitions= 5.44e+08 Memory= 1730.244 t= 500 R= 8e+04 +Depth= 8687 States= 3.9e+07 Transitions= 5.55e+08 Memory= 1747.920 t= 511 R= 8e+04 +Depth= 8687 States= 4e+07 Transitions= 5.69e+08 Memory= 1761.885 t= 523 R= 8e+04 +Depth= 8687 States= 4.1e+07 Transitions= 5.92e+08 Memory= 1775.850 t= 544 R= 8e+04 +Depth= 8687 States= 4.2e+07 Transitions= 6.12e+08 Memory= 1790.498 t= 562 R= 7e+04 +Depth= 8687 States= 4.3e+07 Transitions= 6.29e+08 Memory= 1807.783 t= 578 R= 7e+04 +Depth= 8687 States= 4.4e+07 Transitions= 6.48e+08 Memory= 1822.432 t= 595 R= 7e+04 +Depth= 8687 States= 4.5e+07 Transitions= 6.61e+08 Memory= 1838.838 t= 606 R= 7e+04 +Depth= 8687 States= 4.6e+07 Transitions= 6.81e+08 Memory= 1853.291 t= 625 R= 7e+04 +Depth= 8687 States= 4.7e+07 Transitions= 6.93e+08 Memory= 1870.772 t= 635 R= 7e+04 +Depth= 8687 States= 4.8e+07 Transitions= 7.02e+08 Memory= 1889.912 t= 644 R= 7e+04 +Depth= 8687 States= 4.9e+07 Transitions= 7.15e+08 Memory= 1902.998 t= 656 R= 7e+04 +Depth= 8687 States= 5e+07 Transitions= 7.27e+08 Memory= 1919.600 t= 667 R= 7e+04 +Depth= 9033 States= 5.1e+07 Transitions= 7.42e+08 Memory= 1935.518 t= 681 R= 7e+04 +Depth= 9033 States= 5.2e+07 Transitions= 7.53e+08 Memory= 1954.170 t= 691 R= 8e+04 +Depth= 9033 States= 5.3e+07 Transitions= 7.66e+08 Memory= 1969.990 t= 703 R= 8e+04 +Depth= 9033 States= 5.4e+07 Transitions= 7.77e+08 Memory= 1988.545 t= 713 R= 8e+04 +Depth= 9033 States= 5.5e+07 Transitions= 7.9e+08 Memory= 2004.756 t= 725 R= 8e+04 +Depth= 9033 States= 5.6e+07 Transitions= 8.1e+08 Memory= 2016.084 t= 743 R= 8e+04 +Depth= 9033 States= 5.7e+07 Transitions= 8.32e+08 Memory= 2030.440 t= 763 R= 7e+04 +Depth= 9033 States= 5.8e+07 Transitions= 8.51e+08 Memory= 2046.260 t= 781 R= 7e+04 +Depth= 9033 States= 5.9e+07 Transitions= 8.7e+08 Memory= 2061.592 t= 797 R= 7e+04 +Depth= 9033 States= 6e+07 Transitions= 8.83e+08 Memory= 2078.779 t= 809 R= 7e+04 +Depth= 9033 States= 6.1e+07 Transitions= 9.01e+08 Memory= 2094.014 t= 826 R= 7e+04 +Depth= 9033 States= 6.2e+07 Transitions= 9.16e+08 Memory= 2108.467 t= 840 R= 7e+04 +Depth= 9033 States= 6.3e+07 Transitions= 9.26e+08 Memory= 2126.924 t= 849 R= 7e+04 +Depth= 9033 States= 6.4e+07 Transitions= 9.38e+08 Memory= 2142.158 t= 860 R= 7e+04 +Depth= 9033 States= 6.5e+07 Transitions= 9.51e+08 Memory= 2157.295 t= 871 R= 7e+04 +Depth= 9379 States= 6.6e+07 Transitions= 9.63e+08 Memory= 2173.115 t= 883 R= 7e+04 +Depth= 9379 States= 6.7e+07 Transitions= 9.77e+08 Memory= 2190.401 t= 895 R= 7e+04 +Depth= 9379 States= 6.8e+07 Transitions= 9.88e+08 Memory= 2208.955 t= 905 R= 8e+04 +Depth= 9379 States= 6.9e+07 Transitions= 1e+09 Memory= 2223.311 t= 919 R= 8e+04 +Depth= 9379 States= 7e+07 Transitions= 1.01e+09 Memory= 2242.256 t= 928 R= 8e+04 +Depth= 9379 States= 7.1e+07 Transitions= 1.03e+09 Memory= 2257.295 t= 940 R= 8e+04 +Depth= 9379 States= 7.2e+07 Transitions= 1.05e+09 Memory= 2269.307 t= 960 R= 8e+04 +Depth= 9379 States= 7.3e+07 Transitions= 1.07e+09 Memory= 2283.760 t= 979 R= 7e+04 +Depth= 9379 States= 7.4e+07 Transitions= 1.09e+09 Memory= 2299.385 t= 996 R= 7e+04 +Depth= 9379 States= 7.5e+07 Transitions= 1.11e+09 Memory= 2314.619 t= 1.01e+03 R= 7e+04 +Depth= 9379 States= 7.6e+07 Transitions= 1.12e+09 Memory= 2333.369 t= 1.02e+03 R= 7e+04 +Depth= 9379 States= 7.7e+07 Transitions= 1.14e+09 Memory= 2347.139 t= 1.04e+03 R= 7e+04 +Depth= 9379 States= 7.8e+07 Transitions= 1.15e+09 Memory= 2385.029 t= 1.06e+03 R= 7e+04 +Depth= 9379 States= 7.9e+07 Transitions= 1.17e+09 Memory= 2453.682 t= 1.07e+03 R= 7e+04 +Depth= 9379 States= 8e+07 Transitions= 1.18e+09 Memory= 2522.236 t= 1.08e+03 R= 7e+04 +Depth= 9379 States= 8.1e+07 Transitions= 1.2e+09 Memory= 2590.889 t= 1.1e+03 R= 7e+04 +Depth= 9379 States= 8.2e+07 Transitions= 1.22e+09 Memory= 2624.287 t= 1.12e+03 R= 7e+04 +Depth= 9379 States= 8.3e+07 Transitions= 1.23e+09 Memory= 2640.303 t= 1.13e+03 R= 7e+04 +Depth= 9379 States= 8.4e+07 Transitions= 1.25e+09 Memory= 2654.170 t= 1.15e+03 R= 7e+04 +Depth= 9379 States= 8.5e+07 Transitions= 1.27e+09 Memory= 2669.111 t= 1.16e+03 R= 7e+04 +Depth= 9379 States= 8.6e+07 Transitions= 1.29e+09 Memory= 2684.053 t= 1.18e+03 R= 7e+04 +Depth= 9379 States= 8.7e+07 Transitions= 1.31e+09 Memory= 2698.604 t= 1.2e+03 R= 7e+04 +Depth= 9379 States= 8.8e+07 Transitions= 1.33e+09 Memory= 2719.697 t= 1.22e+03 R= 7e+04 +Depth= 9379 States= 8.9e+07 Transitions= 1.35e+09 Memory= 2788.350 t= 1.24e+03 R= 7e+04 +Depth= 9379 States= 9e+07 Transitions= 1.37e+09 Memory= 2819.990 t= 1.26e+03 R= 7e+04 +Depth= 9379 States= 9.1e+07 Transitions= 1.39e+09 Memory= 2846.553 t= 1.27e+03 R= 7e+04 +Depth= 9379 States= 9.2e+07 Transitions= 1.4e+09 Memory= 2864.912 t= 1.28e+03 R= 7e+04 +Depth= 9379 States= 9.3e+07 Transitions= 1.41e+09 Memory= 2877.901 t= 1.3e+03 R= 7e+04 +Depth= 9379 States= 9.4e+07 Transitions= 1.44e+09 Memory= 2892.842 t= 1.31e+03 R= 7e+04 +Depth= 9379 States= 9.5e+07 Transitions= 1.45e+09 Memory= 2908.076 t= 1.33e+03 R= 7e+04 +Depth= 9379 States= 9.6e+07 Transitions= 1.47e+09 Memory= 2922.627 t= 1.35e+03 R= 7e+04 +Depth= 9379 States= 9.7e+07 Transitions= 1.49e+09 Memory= 2940.693 t= 1.36e+03 R= 7e+04 +Depth= 9379 States= 9.8e+07 Transitions= 1.51e+09 Memory= 2953.291 t= 1.38e+03 R= 7e+04 +Depth= 9379 States= 9.9e+07 Transitions= 1.53e+09 Memory= 2968.526 t= 1.4e+03 R= 7e+04 +Depth= 9379 States= 1e+08 Transitions= 1.56e+09 Memory= 2981.709 t= 1.42e+03 R= 7e+04 +Depth= 9379 States= 1.01e+08 Transitions= 1.57e+09 Memory= 2997.236 t= 1.44e+03 R= 7e+04 +Depth= 9379 States= 1.02e+08 Transitions= 1.59e+09 Memory= 3011.592 t= 1.46e+03 R= 7e+04 +Depth= 9379 States= 1.03e+08 Transitions= 1.61e+09 Memory= 3037.861 t= 1.47e+03 R= 7e+04 +Depth= 9379 States= 1.04e+08 Transitions= 1.63e+09 Memory= 3106.514 t= 1.49e+03 R= 7e+04 +Depth= 9379 States= 1.05e+08 Transitions= 1.65e+09 Memory= 3175.166 t= 1.51e+03 R= 7e+04 +Depth= 9379 States= 1.06e+08 Transitions= 1.67e+09 Memory= 3223.897 t= 1.52e+03 R= 7e+04 +Depth= 9379 States= 1.07e+08 Transitions= 1.68e+09 Memory= 3246.846 t= 1.54e+03 R= 7e+04 +Depth= 9379 States= 1.08e+08 Transitions= 1.7e+09 Memory= 3283.467 t= 1.56e+03 R= 7e+04 +Depth= 9379 States= 1.09e+08 Transitions= 1.72e+09 Memory= 3316.670 t= 1.57e+03 R= 7e+04 +Depth= 9379 States= 1.1e+08 Transitions= 1.73e+09 Memory= 3344.209 t= 1.59e+03 R= 7e+04 +Depth= 9379 States= 1.11e+08 Transitions= 1.75e+09 Memory= 3376.338 t= 1.6e+03 R= 7e+04 +Depth= 9379 States= 1.12e+08 Transitions= 1.76e+09 Memory= 3396.943 t= 1.62e+03 R= 7e+04 +Depth= 9379 States= 1.13e+08 Transitions= 1.78e+09 Memory= 3426.143 t= 1.63e+03 R= 7e+04 +Depth= 9379 States= 1.14e+08 Transitions= 1.8e+09 Memory= 3452.705 t= 1.65e+03 R= 7e+04 +Depth= 9379 States= 1.15e+08 Transitions= 1.81e+09 Memory= 3493.818 t= 1.66e+03 R= 7e+04 +Depth= 9379 States= 1.16e+08 Transitions= 1.83e+09 Memory= 3533.369 t= 1.67e+03 R= 7e+04 +Depth= 9379 States= 1.17e+08 Transitions= 1.84e+09 Memory= 3566.182 t= 1.69e+03 R= 7e+04 +Depth= 9379 States= 1.18e+08 Transitions= 1.86e+09 Memory= 3582.881 t= 1.7e+03 R= 7e+04 +Depth= 9379 States= 1.19e+08 Transitions= 1.88e+09 Memory= 3630.830 t= 1.72e+03 R= 7e+04 +Depth= 9379 States= 1.2e+08 Transitions= 1.89e+09 Memory= 3692.744 t= 1.74e+03 R= 7e+04 +Depth= 9379 States= 1.21e+08 Transitions= 1.91e+09 Memory= 3750.361 t= 1.75e+03 R= 7e+04 +Depth= 9379 States= 1.22e+08 Transitions= 1.92e+09 Memory= 3767.354 t= 1.76e+03 R= 7e+04 +Depth= 9379 States= 1.23e+08 Transitions= 1.94e+09 Memory= 3781.904 t= 1.78e+03 R= 7e+04 +Depth= 9379 States= 1.24e+08 Transitions= 1.96e+09 Memory= 3797.529 t= 1.8e+03 R= 7e+04 +Depth= 9379 States= 1.25e+08 Transitions= 1.98e+09 Memory= 3810.908 t= 1.82e+03 R= 7e+04 +Depth= 9379 States= 1.26e+08 Transitions= 2e+09 Memory= 3826.143 t= 1.83e+03 R= 7e+04 +Depth= 9379 States= 1.27e+08 Transitions= 2.02e+09 Memory= 3839.717 t= 1.86e+03 R= 7e+04 +Depth= 9379 States= 1.28e+08 Transitions= 2.04e+09 Memory= 3881.709 t= 1.87e+03 R= 7e+04 +Depth= 9379 States= 1.29e+08 Transitions= 2.06e+09 Memory= 3946.553 t= 1.89e+03 R= 7e+04 +Depth= 9379 States= 1.3e+08 Transitions= 2.08e+09 Memory= 3970.479 t= 1.91e+03 R= 7e+04 +Depth= 9379 States= 1.31e+08 Transitions= 2.09e+09 Memory= 3991.768 t= 1.92e+03 R= 7e+04 +Depth= 9379 States= 1.32e+08 Transitions= 2.1e+09 Memory= 4007.490 t= 1.93e+03 R= 7e+04 +Depth= 9379 States= 1.33e+08 Transitions= 2.13e+09 Memory= 4020.772 t= 1.95e+03 R= 7e+04 +Depth= 9379 States= 1.34e+08 Transitions= 2.14e+09 Memory= 4036.201 t= 1.97e+03 R= 7e+04 +Depth= 9379 States= 1.35e+08 Transitions= 2.16e+09 Memory= 4051.924 t= 1.98e+03 R= 7e+04 +pan: resizing hashtable to -w28.. done +Depth= 9379 States= 1.36e+08 Transitions= 2.18e+09 Memory= 6099.924 t= 2.02e+03 R= 7e+04 +Depth= 9379 States= 1.37e+08 Transitions= 2.2e+09 Memory= 6099.924 t= 2.03e+03 R= 7e+04 +Depth= 9379 States= 1.38e+08 Transitions= 2.22e+09 Memory= 6099.924 t= 2.05e+03 R= 7e+04 +Depth= 9379 States= 1.39e+08 Transitions= 2.24e+09 Memory= 6099.924 t= 2.07e+03 R= 7e+04 +Depth= 9379 States= 1.4e+08 Transitions= 2.26e+09 Memory= 6108.518 t= 2.09e+03 R= 7e+04 +Depth= 9379 States= 1.41e+08 Transitions= 2.28e+09 Memory= 6124.729 t= 2.1e+03 R= 7e+04 +Depth= 9379 States= 1.42e+08 Transitions= 2.3e+09 Memory= 6138.889 t= 2.12e+03 R= 7e+04 +Depth= 9379 States= 1.43e+08 Transitions= 2.31e+09 Memory= 6178.928 t= 2.13e+03 R= 7e+04 +Depth= 9379 States= 1.44e+08 Transitions= 2.33e+09 Memory= 6247.483 t= 2.15e+03 R= 7e+04 +Depth= 9379 States= 1.45e+08 Transitions= 2.35e+09 Memory= 6316.135 t= 2.17e+03 R= 7e+04 +Depth= 9379 States= 1.46e+08 Transitions= 2.37e+09 Memory= 6353.440 t= 2.19e+03 R= 7e+04 +Depth= 9379 States= 1.47e+08 Transitions= 2.39e+09 Memory= 6381.662 t= 2.21e+03 R= 7e+04 +Depth= 9379 States= 1.48e+08 Transitions= 2.41e+09 Memory= 6422.190 t= 2.22e+03 R= 7e+04 +Depth= 9379 States= 1.49e+08 Transitions= 2.42e+09 Memory= 6449.143 t= 2.23e+03 R= 7e+04 +Depth= 9379 States= 1.5e+08 Transitions= 2.44e+09 Memory= 6472.580 t= 2.25e+03 R= 7e+04 +Depth= 9379 States= 1.51e+08 Transitions= 2.45e+09 Memory= 6503.733 t= 2.26e+03 R= 7e+04 +Depth= 9379 States= 1.52e+08 Transitions= 2.47e+09 Memory= 6531.369 t= 2.28e+03 R= 7e+04 +Depth= 9379 States= 1.53e+08 Transitions= 2.49e+09 Memory= 6554.123 t= 2.29e+03 R= 7e+04 +Depth= 9379 States= 1.54e+08 Transitions= 2.5e+09 Memory= 6585.373 t= 2.31e+03 R= 7e+04 +Depth= 9379 States= 1.55e+08 Transitions= 2.52e+09 Memory= 6622.776 t= 2.32e+03 R= 7e+04 +Depth= 9379 States= 1.56e+08 Transitions= 2.54e+09 Memory= 6671.213 t= 2.34e+03 R= 7e+04 +Depth= 9379 States= 1.57e+08 Transitions= 2.55e+09 Memory= 6696.115 t= 2.35e+03 R= 7e+04 +Depth= 9379 States= 1.58e+08 Transitions= 2.57e+09 Memory= 6722.776 t= 2.37e+03 R= 7e+04 +Depth= 9379 States= 1.59e+08 Transitions= 2.58e+09 Memory= 6764.572 t= 2.38e+03 R= 7e+04 +Depth= 9379 States= 1.6e+08 Transitions= 2.6e+09 Memory= 6830.490 t= 2.4e+03 R= 7e+04 +Depth= 9379 States= 1.61e+08 Transitions= 2.62e+09 Memory= 6879.026 t= 2.41e+03 R= 7e+04 +Depth= 9379 States= 1.62e+08 Transitions= 2.63e+09 Memory= 6895.432 t= 2.42e+03 R= 7e+04 +Depth= 9379 States= 1.63e+08 Transitions= 2.65e+09 Memory= 6909.787 t= 2.44e+03 R= 7e+04 +Depth= 9379 States= 1.64e+08 Transitions= 2.67e+09 Memory= 6925.217 t= 2.46e+03 R= 7e+04 +Depth= 9379 States= 1.65e+08 Transitions= 2.69e+09 Memory= 6938.986 t= 2.48e+03 R= 7e+04 +Depth= 9379 States= 1.66e+08 Transitions= 2.71e+09 Memory= 6953.537 t= 2.5e+03 R= 7e+04 +Depth= 9379 States= 1.67e+08 Transitions= 2.73e+09 Memory= 6967.893 t= 2.52e+03 R= 7e+04 +Depth= 9379 States= 1.68e+08 Transitions= 2.75e+09 Memory= 7022.190 t= 2.53e+03 R= 7e+04 +Depth= 9379 States= 1.69e+08 Transitions= 2.77e+09 Memory= 7076.779 t= 2.55e+03 R= 7e+04 +Depth= 9379 States= 1.7e+08 Transitions= 2.79e+09 Memory= 7102.365 t= 2.57e+03 R= 7e+04 +Depth= 9379 States= 1.71e+08 Transitions= 2.8e+09 Memory= 7119.162 t= 2.58e+03 R= 7e+04 +Depth= 9379 States= 1.72e+08 Transitions= 2.81e+09 Memory= 7135.178 t= 2.59e+03 R= 7e+04 +Depth= 9379 States= 1.73e+08 Transitions= 2.84e+09 Memory= 7150.022 t= 2.61e+03 R= 7e+04 +Depth= 9379 States= 1.74e+08 Transitions= 2.85e+09 Memory= 7164.475 t= 2.63e+03 R= 7e+04 +Depth= 9379 States= 1.75e+08 Transitions= 2.87e+09 Memory= 7180.295 t= 2.64e+03 R= 7e+04 +Depth= 9379 States= 1.76e+08 Transitions= 2.89e+09 Memory= 7198.264 t= 2.66e+03 R= 7e+04 +Depth= 9379 States= 1.77e+08 Transitions= 2.9e+09 Memory= 7211.447 t= 2.67e+03 R= 7e+04 +Depth= 9379 States= 1.78e+08 Transitions= 2.93e+09 Memory= 7224.338 t= 2.7e+03 R= 7e+04 +Depth= 9379 States= 1.79e+08 Transitions= 2.95e+09 Memory= 7239.084 t= 2.72e+03 R= 7e+04 +Depth= 9379 States= 1.8e+08 Transitions= 2.97e+09 Memory= 7253.342 t= 2.74e+03 R= 7e+04 +Depth= 9379 States= 1.81e+08 Transitions= 2.99e+09 Memory= 7268.283 t= 2.75e+03 R= 7e+04 +Depth= 9379 States= 1.82e+08 Transitions= 3.01e+09 Memory= 7283.615 t= 2.77e+03 R= 7e+04 +Depth= 9379 States= 1.83e+08 Transitions= 3.02e+09 Memory= 7335.276 t= 2.78e+03 R= 7e+04 +Depth= 9379 States= 1.84e+08 Transitions= 3.04e+09 Memory= 7403.928 t= 2.8e+03 R= 7e+04 +Depth= 9379 States= 1.85e+08 Transitions= 3.06e+09 Memory= 7472.580 t= 2.82e+03 R= 7e+04 +Depth= 9379 States= 1.86e+08 Transitions= 3.08e+09 Memory= 7501.877 t= 2.84e+03 R= 7e+04 +Depth= 9379 States= 1.87e+08 Transitions= 3.1e+09 Memory= 7528.147 t= 2.85e+03 R= 7e+04 +Depth= 9379 States= 1.88e+08 Transitions= 3.11e+09 Memory= 7566.135 t= 2.87e+03 R= 7e+04 +Depth= 9379 States= 1.89e+08 Transitions= 3.13e+09 Memory= 7593.479 t= 2.88e+03 R= 7e+04 +Depth= 9379 States= 1.9e+08 Transitions= 3.15e+09 Memory= 7625.119 t= 2.9e+03 R= 7e+04 +Depth= 9379 States= 1.91e+08 Transitions= 3.16e+09 Memory= 7647.483 t= 2.91e+03 R= 7e+04 +Depth= 9379 States= 1.92e+08 Transitions= 3.18e+09 Memory= 7677.951 t= 2.93e+03 R= 7e+04 +Depth= 9379 States= 1.93e+08 Transitions= 3.2e+09 Memory= 7698.947 t= 2.94e+03 R= 7e+04 +Depth= 9379 States= 1.94e+08 Transitions= 3.21e+09 Memory= 7732.443 t= 2.96e+03 R= 7e+04 +Depth= 9379 States= 1.95e+08 Transitions= 3.23e+09 Memory= 7772.092 t= 2.97e+03 R= 7e+04 +Depth= 9379 States= 1.96e+08 Transitions= 3.24e+09 Memory= 7815.451 t= 2.98e+03 R= 7e+04 +Depth= 9379 States= 1.97e+08 Transitions= 3.26e+09 Memory= 7839.865 t= 3e+03 R= 7e+04 +Depth= 9379 States= 1.98e+08 Transitions= 3.28e+09 Memory= 7869.651 t= 3.01e+03 R= 7e+04 +Depth= 9379 States= 1.99e+08 Transitions= 3.29e+09 Memory= 7921.018 t= 3.03e+03 R= 7e+04 +Depth= 9379 States= 2e+08 Transitions= 3.31e+09 Memory= 7986.740 t= 3.05e+03 R= 7e+04 +Depth= 9379 States= 2.01e+08 Transitions= 3.33e+09 Memory= 8023.752 t= 3.06e+03 R= 7e+04 +Depth= 9379 States= 2.02e+08 Transitions= 3.34e+09 Memory= 8039.768 t= 3.07e+03 R= 7e+04 +Depth= 9379 States= 2.03e+08 Transitions= 3.36e+09 Memory= 8053.830 t= 3.09e+03 R= 7e+04 +Depth= 9379 States= 2.04e+08 Transitions= 3.38e+09 Memory= 8068.772 t= 3.11e+03 R= 7e+04 +Depth= 9379 States= 2.05e+08 Transitions= 3.4e+09 Memory= 8083.127 t= 3.13e+03 R= 7e+04 +Depth= 9379 States= 2.06e+08 Transitions= 3.42e+09 Memory= 8098.068 t= 3.15e+03 R= 7e+04 +Depth= 9379 States= 2.07e+08 Transitions= 3.44e+09 Memory= 8115.744 t= 3.16e+03 R= 7e+04 +Depth= 9379 States= 2.08e+08 Transitions= 3.46e+09 Memory= 8178.537 t= 3.18e+03 R= 7e+04 +Depth= 9379 States= 2.09e+08 Transitions= 3.48e+09 Memory= 8220.627 t= 3.2e+03 R= 7e+04 +Depth= 9379 States= 2.1e+08 Transitions= 3.49e+09 Memory= 8246.799 t= 3.21e+03 R= 7e+04 +Depth= 9379 States= 2.11e+08 Transitions= 3.5e+09 Memory= 8263.791 t= 3.22e+03 R= 7e+04 +Depth= 9379 States= 2.12e+08 Transitions= 3.52e+09 Memory= 8279.514 t= 3.24e+03 R= 7e+04 +Depth= 9379 States= 2.13e+08 Transitions= 3.54e+09 Memory= 8293.772 t= 3.26e+03 R= 7e+04 +Depth= 9379 States= 2.14e+08 Transitions= 3.56e+09 Memory= 8309.201 t= 3.28e+03 R= 7e+04 +Depth= 9379 States= 2.15e+08 Transitions= 3.58e+09 Memory= 8323.752 t= 3.29e+03 R= 7e+04 +Depth= 9379 States= 2.16e+08 Transitions= 3.6e+09 Memory= 8342.990 t= 3.31e+03 R= 7e+04 +Depth= 9379 States= 2.17e+08 Transitions= 3.61e+09 Memory= 8355.197 t= 3.32e+03 R= 7e+04 +Depth= 9379 States= 2.18e+08 Transitions= 3.64e+09 Memory= 8368.674 t= 3.35e+03 R= 7e+04 +Depth= 9379 States= 2.19e+08 Transitions= 3.66e+09 Memory= 8382.932 t= 3.37e+03 R= 7e+04 +Depth= 9379 States= 2.2e+08 Transitions= 3.68e+09 Memory= 8398.459 t= 3.38e+03 R= 7e+04 +Depth= 9379 States= 2.21e+08 Transitions= 3.7e+09 Memory= 8412.912 t= 3.4e+03 R= 6e+04 +Depth= 9379 States= 2.22e+08 Transitions= 3.71e+09 Memory= 8428.244 t= 3.42e+03 R= 6e+04 +Depth= 9379 States= 2.23e+08 Transitions= 3.73e+09 Memory= 8491.721 t= 3.43e+03 R= 6e+04 +Depth= 9379 States= 2.24e+08 Transitions= 3.75e+09 Memory= 8560.373 t= 3.45e+03 R= 6e+04 +Depth= 9379 States= 2.25e+08 Transitions= 3.77e+09 Memory= 8621.604 t= 3.47e+03 R= 6e+04 +Depth= 9379 States= 2.26e+08 Transitions= 3.79e+09 Memory= 8648.850 t= 3.48e+03 R= 6e+04 +Depth= 9379 States= 2.27e+08 Transitions= 3.81e+09 Memory= 8671.994 t= 3.5e+03 R= 6e+04 +Depth= 9379 States= 2.28e+08 Transitions= 3.82e+09 Memory= 8710.861 t= 3.51e+03 R= 6e+04 +Depth= 9379 States= 2.29e+08 Transitions= 3.84e+09 Memory= 8742.893 t= 3.53e+03 R= 6e+04 +Depth= 9379 States= 2.3e+08 Transitions= 3.85e+09 Memory= 8771.799 t= 3.54e+03 R= 6e+04 +Depth= 9379 States= 2.31e+08 Transitions= 3.87e+09 Memory= 8792.600 t= 3.56e+03 R= 6e+04 +Depth= 9379 States= 2.32e+08 Transitions= 3.89e+09 Memory= 8828.733 t= 3.57e+03 R= 6e+04 +Depth= 9379 States= 2.33e+08 Transitions= 3.9e+09 Memory= 8843.869 t= 3.59e+03 R= 6e+04 +Depth= 9379 States= 2.34e+08 Transitions= 3.92e+09 Memory= 8884.787 t= 3.6e+03 R= 6e+04 +Depth= 9379 States= 2.35e+08 Transitions= 3.93e+09 Memory= 8924.240 t= 3.62e+03 R= 6e+04 +Depth= 9379 States= 2.36e+08 Transitions= 3.95e+09 Memory= 8960.276 t= 3.63e+03 R= 6e+04 +Depth= 9379 States= 2.37e+08 Transitions= 3.97e+09 Memory= 8984.494 t= 3.65e+03 R= 6e+04 +Depth= 9379 States= 2.38e+08 Transitions= 3.98e+09 Memory= 9016.428 t= 3.66e+03 R= 6e+04 +Depth= 9379 States= 2.39e+08 Transitions= 4e+09 Memory= 9077.365 t= 3.68e+03 R= 6e+04 +Depth= 9379 States= 2.4e+08 Transitions= 4.02e+09 Memory= 9143.088 t= 3.7e+03 R= 6e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 9379, errors: 0 + 88114592 states, stored (2.40192e+08 visited) +3.782223e+09 states, matched +4.0224152e+09 transitions (= visited+matched) +1.4282782e+10 atomic steps +hash conflicts: 5.384059e+08 (resolved) + +Stats on memory usage (in Megabytes): + 7731.001 equivalent memory usage for states (stored*(State-vector + overhead)) + 6648.180 actual memory usage for states (compression: 85.99%) + state-vector as stored = 51 byte + 28 byte overhead + 2048.000 memory used for hash table (-w28) + 457.764 memory used for DFS stack (-m10000000) + 1.188 memory lost to fragmentation + 9152.756 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 256, "(1)" + line 418, "pan.___", state 286, "(1)" + line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 395, "(1)" + line 418, "pan.___", state 425, "(1)" + line 540, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 70, "(1)" + line 418, "pan.___", state 100, "(1)" + line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 158, "(1)" + line 418, "pan.___", state 188, "(1)" + line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 247, "(1)" + line 418, "pan.___", state 277, "(1)" + line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 359, "(1)" + line 418, "pan.___", state 389, "(1)" + line 614, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 370, "(1)" + line 164, "pan.___", state 378, "(1)" + line 168, "pan.___", state 390, "(1)" + line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 449, "(1)" + line 413, "pan.___", state 462, "(1)" + line 418, "pan.___", state 479, "(1)" + line 399, "pan.___", state 498, "(1)" + line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 554, "(1)" + line 418, "pan.___", state 571, "(1)" + line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 647, "(1)" + line 418, "pan.___", state 664, "(1)" + line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 710, "(1)" + line 164, "pan.___", state 718, "(1)" + line 168, "pan.___", state 730, "(1)" + line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 840, "(1)" + line 164, "pan.___", state 848, "(1)" + line 168, "pan.___", state 860, "(1)" + line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 884, "(1)" + line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 885, "else" + line 399, "pan.___", state 888, "(1)" + line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 898, "(1)" + line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 899, "else" + line 403, "pan.___", state 902, "(1)" + line 403, "pan.___", state 903, "(1)" + line 403, "pan.___", state 903, "(1)" + line 401, "pan.___", state 908, "((i<1))" + line 401, "pan.___", state 908, "((i>=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1040, "(1)" + line 418, "pan.___", state 1057, "(1)" + line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1130, "(1)" + line 418, "pan.___", state 1147, "(1)" + line 399, "pan.___", state 1166, "(1)" + line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1222, "(1)" + line 418, "pan.___", state 1239, "(1)" + line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 413, "pan.___", state 1315, "(1)" + line 418, "pan.___", state 1332, "(1)" + line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1378, "(1)" + line 164, "pan.___", state 1386, "(1)" + line 168, "pan.___", state 1398, "(1)" + line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1508, "(1)" + line 164, "pan.___", state 1516, "(1)" + line 168, "pan.___", state 1528, "(1)" + line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1552, "(1)" + line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 399, "pan.___", state 1553, "else" + line 399, "pan.___", state 1556, "(1)" + line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1566, "(1)" + line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 403, "pan.___", state 1567, "else" + line 403, "pan.___", state 1570, "(1)" + line 403, "pan.___", state 1571, "(1)" + line 403, "pan.___", state 1571, "(1)" + line 401, "pan.___", state 1576, "((i<1))" + line 401, "pan.___", state 1576, "((i>=1))" + line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1595, "(1)" + line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 409, "pan.___", state 1596, "else" + line 409, "pan.___", state 1599, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 413, "pan.___", state 1608, "(1)" + line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 413, "pan.___", state 1609, "else" + line 413, "pan.___", state 1612, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 411, "pan.___", state 1618, "((i<1))" + line 411, "pan.___", state 1618, "((i>=1))" + line 418, "pan.___", state 1625, "(1)" + line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 418, "pan.___", state 1626, "else" + line 418, "pan.___", state 1629, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1681, "(1)" + line 164, "pan.___", state 1689, "(1)" + line 168, "pan.___", state 1701, "(1)" + line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 160, "pan.___", state 1811, "(1)" + line 164, "pan.___", state 1819, "(1)" + line 168, "pan.___", state 1831, "(1)" + line 702, "pan.___", state 1856, "-end-" + (158 of 1856 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 751, "pan.___", state 11, "-end-" + (1 of 11 states) + +pan: elapsed time 3.7e+03 seconds +pan: rate 64918.749 states/second +pan: avg transition delay 9.1982e-07 usec +cp .input.spin urcu_progress_writer.spin.input +cp .input.spin.trail urcu_progress_writer.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input new file mode 100644 index 0000000..43221e7 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input @@ -0,0 +1,723 @@ +#define WRITER_PROGRESS + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input.trail new file mode 100644 index 0000000..e65d663 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer.spin.input.trail @@ -0,0 +1,9 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:1:2675 +5:1:2676 +6:0:2685 +7:5:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.define b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.define new file mode 100644 index 0000000..8d304f5 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.define @@ -0,0 +1,2 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.log b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.log new file mode 100644 index 0000000..f870a6e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.log @@ -0,0 +1,535 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer_error.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 745) +depth 15: Claim reached state 9 (line 750) +depth 1194: Claim reached state 9 (line 749) +Depth= 3253 States= 1e+06 Transitions= 1.06e+07 Memory= 484.416 t= 9.57 R= 1e+05 +Depth= 3253 States= 2e+06 Transitions= 2.04e+07 Memory= 501.311 t= 18.5 R= 1e+05 +pan: acceptance cycle (at depth 1938) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 64 byte, depth reached 23684, errors: 1 + 682672 states, stored (2.81536e+06 visited) + 30226122 states, matched + 33041487 transitions (= visited+matched) +1.1631626e+08 atomic steps +hash conflicts: 6056013 (resolved) + +Stats on memory usage (in Megabytes): + 59.896 equivalent memory usage for states (stored*(State-vector + overhead)) + 47.456 actual memory usage for states (compression: 79.23%) + state-vector as stored = 45 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 513.127 total actual memory usage + +unreached in proctype urcu_reader + line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 61, "(1)" + line 419, "pan.___", state 91, "(1)" + line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 158, "(1)" + line 419, "pan.___", state 188, "(1)" + line 400, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 256, "(1)" + line 419, "pan.___", state 286, "(1)" + line 400, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 395, "(1)" + line 419, "pan.___", state 425, "(1)" + line 541, "pan.___", state 456, "-end-" + (17 of 456 states) +unreached in proctype urcu_reader_sig + line 400, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 70, "(1)" + line 419, "pan.___", state 100, "(1)" + line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 158, "(1)" + line 419, "pan.___", state 188, "(1)" + line 400, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 247, "(1)" + line 419, "pan.___", state 277, "(1)" + line 400, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 359, "(1)" + line 419, "pan.___", state 389, "(1)" + line 615, "pan.___", state 411, "-end-" + (17 of 411 states) +unreached in proctype urcu_writer + line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 20, "(1)" + line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 34, "(1)" + line 404, "pan.___", state 35, "(1)" + line 404, "pan.___", state 35, "(1)" + line 402, "pan.___", state 40, "((i<1))" + line 402, "pan.___", state 40, "((i>=1))" + line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 59, "(1)" + line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 60, "else" + line 410, "pan.___", state 63, "(1)" + line 410, "pan.___", state 64, "(1)" + line 410, "pan.___", state 64, "(1)" + line 414, "pan.___", state 72, "(1)" + line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 73, "else" + line 414, "pan.___", state 76, "(1)" + line 414, "pan.___", state 77, "(1)" + line 414, "pan.___", state 77, "(1)" + line 412, "pan.___", state 82, "((i<1))" + line 412, "pan.___", state 82, "((i>=1))" + line 419, "pan.___", state 89, "(1)" + line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 90, "else" + line 419, "pan.___", state 93, "(1)" + line 419, "pan.___", state 94, "(1)" + line 419, "pan.___", state 94, "(1)" + line 370, "pan.___", state 99, "(1)" + line 640, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)" + line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]" + line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 114, "(1)" + line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 128, "(1)" + line 404, "pan.___", state 129, "(1)" + line 404, "pan.___", state 129, "(1)" + line 402, "pan.___", state 134, "((i<1))" + line 402, "pan.___", state 134, "((i>=1))" + line 410, "pan.___", state 153, "(1)" + line 410, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 154, "else" + line 410, "pan.___", state 157, "(1)" + line 410, "pan.___", state 158, "(1)" + line 410, "pan.___", state 158, "(1)" + line 414, "pan.___", state 166, "(1)" + line 414, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 167, "else" + line 414, "pan.___", state 170, "(1)" + line 414, "pan.___", state 171, "(1)" + line 414, "pan.___", state 171, "(1)" + line 412, "pan.___", state 176, "((i<1))" + line 412, "pan.___", state 176, "((i>=1))" + line 419, "pan.___", state 183, "(1)" + line 419, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 184, "else" + line 419, "pan.___", state 187, "(1)" + line 419, "pan.___", state 188, "(1)" + line 419, "pan.___", state 188, "(1)" + line 421, "pan.___", state 191, "(1)" + line 421, "pan.___", state 191, "(1)" + line 370, "pan.___", state 193, "(1)" + line 653, "pan.___", state 199, "(1)" + line 647, "pan.___", state 202, "((write_lock==0))" + line 647, "pan.___", state 202, "else" + line 645, "pan.___", state 203, "(1)" + line 176, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 180, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 178, "pan.___", state 225, "((j<1))" + line 178, "pan.___", state 225, "((j>=1))" + line 184, "pan.___", state 230, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 161, "pan.___", state 240, "(1)" + line 165, "pan.___", state 248, "(1)" + line 165, "pan.___", state 249, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 165, "pan.___", state 249, "else" + line 163, "pan.___", state 254, "((j<1))" + line 163, "pan.___", state 254, "((j>=1))" + line 169, "pan.___", state 260, "(1)" + line 169, "pan.___", state 261, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 169, "pan.___", state 261, "else" + line 171, "pan.___", state 264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 171, "pan.___", state 264, "else" + line 176, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 184, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 169, "pan.___", state 323, "(1)" + line 169, "pan.___", state 324, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 176, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 180, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 178, "pan.___", state 355, "((j<1))" + line 178, "pan.___", state 355, "((j>=1))" + line 184, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 161, "pan.___", state 370, "(1)" + line 165, "pan.___", state 378, "(1)" + line 165, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 165, "pan.___", state 379, "else" + line 163, "pan.___", state 384, "((j<1))" + line 163, "pan.___", state 384, "((j>=1))" + line 169, "pan.___", state 390, "(1)" + line 169, "pan.___", state 391, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 169, "pan.___", state 391, "else" + line 171, "pan.___", state 394, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 171, "pan.___", state 394, "else" + line 400, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 410, "(1)" + line 404, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 424, "(1)" + line 404, "pan.___", state 425, "(1)" + line 404, "pan.___", state 425, "(1)" + line 402, "pan.___", state 430, "((i<1))" + line 402, "pan.___", state 430, "((i>=1))" + line 409, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 449, "(1)" + line 410, "pan.___", state 450, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 450, "else" + line 410, "pan.___", state 453, "(1)" + line 410, "pan.___", state 454, "(1)" + line 410, "pan.___", state 454, "(1)" + line 414, "pan.___", state 462, "(1)" + line 414, "pan.___", state 463, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 463, "else" + line 414, "pan.___", state 466, "(1)" + line 414, "pan.___", state 467, "(1)" + line 414, "pan.___", state 467, "(1)" + line 412, "pan.___", state 472, "((i<1))" + line 412, "pan.___", state 472, "((i>=1))" + line 419, "pan.___", state 479, "(1)" + line 419, "pan.___", state 480, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 480, "else" + line 419, "pan.___", state 483, "(1)" + line 419, "pan.___", state 484, "(1)" + line 419, "pan.___", state 484, "(1)" + line 421, "pan.___", state 487, "(1)" + line 421, "pan.___", state 487, "(1)" + line 370, "pan.___", state 489, "(1)" + line 662, "pan.___", state 492, "cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )] = (tmp^(1<<7))" + line 400, "pan.___", state 498, "(1)" + line 400, "pan.___", state 499, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 499, "else" + line 400, "pan.___", state 502, "(1)" + line 404, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 516, "(1)" + line 404, "pan.___", state 517, "(1)" + line 404, "pan.___", state 517, "(1)" + line 402, "pan.___", state 522, "((i<1))" + line 402, "pan.___", state 522, "((i>=1))" + line 409, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 541, "(1)" + line 410, "pan.___", state 542, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 542, "else" + line 410, "pan.___", state 545, "(1)" + line 410, "pan.___", state 546, "(1)" + line 410, "pan.___", state 546, "(1)" + line 414, "pan.___", state 554, "(1)" + line 414, "pan.___", state 555, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 555, "else" + line 414, "pan.___", state 558, "(1)" + line 414, "pan.___", state 559, "(1)" + line 414, "pan.___", state 559, "(1)" + line 412, "pan.___", state 564, "((i<1))" + line 412, "pan.___", state 564, "((i>=1))" + line 419, "pan.___", state 571, "(1)" + line 419, "pan.___", state 572, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 572, "else" + line 419, "pan.___", state 575, "(1)" + line 419, "pan.___", state 576, "(1)" + line 419, "pan.___", state 576, "(1)" + line 421, "pan.___", state 579, "(1)" + line 421, "pan.___", state 579, "(1)" + line 370, "pan.___", state 581, "(1)" + line 400, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 595, "(1)" + line 404, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 609, "(1)" + line 404, "pan.___", state 610, "(1)" + line 404, "pan.___", state 610, "(1)" + line 402, "pan.___", state 615, "((i<1))" + line 402, "pan.___", state 615, "((i>=1))" + line 409, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 634, "(1)" + line 410, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 635, "else" + line 410, "pan.___", state 638, "(1)" + line 410, "pan.___", state 639, "(1)" + line 410, "pan.___", state 639, "(1)" + line 414, "pan.___", state 647, "(1)" + line 414, "pan.___", state 648, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 648, "else" + line 414, "pan.___", state 651, "(1)" + line 414, "pan.___", state 652, "(1)" + line 414, "pan.___", state 652, "(1)" + line 412, "pan.___", state 657, "((i<1))" + line 412, "pan.___", state 657, "((i>=1))" + line 419, "pan.___", state 664, "(1)" + line 419, "pan.___", state 665, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 665, "else" + line 419, "pan.___", state 668, "(1)" + line 419, "pan.___", state 669, "(1)" + line 419, "pan.___", state 669, "(1)" + line 421, "pan.___", state 672, "(1)" + line 421, "pan.___", state 672, "(1)" + line 370, "pan.___", state 674, "(1)" + line 400, "pan.___", state 679, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 681, "(1)" + line 400, "pan.___", state 682, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 682, "else" + line 400, "pan.___", state 685, "(1)" + line 404, "pan.___", state 693, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 695, "(1)" + line 404, "pan.___", state 696, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 696, "else" + line 404, "pan.___", state 699, "(1)" + line 404, "pan.___", state 700, "(1)" + line 404, "pan.___", state 700, "(1)" + line 402, "pan.___", state 705, "((i<1))" + line 402, "pan.___", state 705, "((i>=1))" + line 409, "pan.___", state 711, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 724, "(1)" + line 410, "pan.___", state 725, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 725, "else" + line 410, "pan.___", state 728, "(1)" + line 410, "pan.___", state 729, "(1)" + line 410, "pan.___", state 729, "(1)" + line 414, "pan.___", state 737, "(1)" + line 414, "pan.___", state 738, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 738, "else" + line 414, "pan.___", state 741, "(1)" + line 414, "pan.___", state 742, "(1)" + line 414, "pan.___", state 742, "(1)" + line 412, "pan.___", state 747, "((i<1))" + line 412, "pan.___", state 747, "((i>=1))" + line 419, "pan.___", state 754, "(1)" + line 419, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 755, "else" + line 419, "pan.___", state 758, "(1)" + line 419, "pan.___", state 759, "(1)" + line 419, "pan.___", state 759, "(1)" + line 421, "pan.___", state 762, "(1)" + line 421, "pan.___", state 762, "(1)" + line 370, "pan.___", state 764, "(1)" + line 430, "pan.___", state 767, "(((tmp2&((1<<7)-1))&&((tmp2^cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )])&(1<<7))))" + line 430, "pan.___", state 767, "else" + line 400, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 779, "(1)" + line 400, "pan.___", state 780, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 780, "else" + line 400, "pan.___", state 783, "(1)" + line 404, "pan.___", state 791, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 793, "(1)" + line 404, "pan.___", state 794, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 794, "else" + line 404, "pan.___", state 797, "(1)" + line 404, "pan.___", state 798, "(1)" + line 404, "pan.___", state 798, "(1)" + line 402, "pan.___", state 803, "((i<1))" + line 402, "pan.___", state 803, "((i>=1))" + line 409, "pan.___", state 809, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 822, "(1)" + line 410, "pan.___", state 823, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 823, "else" + line 410, "pan.___", state 826, "(1)" + line 410, "pan.___", state 827, "(1)" + line 410, "pan.___", state 827, "(1)" + line 414, "pan.___", state 835, "(1)" + line 414, "pan.___", state 836, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 836, "else" + line 414, "pan.___", state 839, "(1)" + line 414, "pan.___", state 840, "(1)" + line 414, "pan.___", state 840, "(1)" + line 412, "pan.___", state 845, "((i<1))" + line 412, "pan.___", state 845, "((i>=1))" + line 419, "pan.___", state 852, "(1)" + line 419, "pan.___", state 853, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 853, "else" + line 419, "pan.___", state 856, "(1)" + line 419, "pan.___", state 857, "(1)" + line 419, "pan.___", state 857, "(1)" + line 421, "pan.___", state 860, "(1)" + line 421, "pan.___", state 860, "(1)" + line 370, "pan.___", state 862, "(1)" + line 449, "pan.___", state 870, "((tmp<1))" + line 449, "pan.___", state 870, "((tmp>=1))" + line 462, "pan.___", state 873, "tmp = 0" + line 400, "pan.___", state 877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 883, "(1)" + line 404, "pan.___", state 891, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 897, "(1)" + line 404, "pan.___", state 898, "(1)" + line 404, "pan.___", state 898, "(1)" + line 402, "pan.___", state 903, "((i<1))" + line 402, "pan.___", state 903, "((i>=1))" + line 409, "pan.___", state 909, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 922, "(1)" + line 410, "pan.___", state 923, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 923, "else" + line 410, "pan.___", state 926, "(1)" + line 410, "pan.___", state 927, "(1)" + line 410, "pan.___", state 927, "(1)" + line 414, "pan.___", state 935, "(1)" + line 414, "pan.___", state 936, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 936, "else" + line 414, "pan.___", state 939, "(1)" + line 414, "pan.___", state 940, "(1)" + line 414, "pan.___", state 940, "(1)" + line 412, "pan.___", state 945, "((i<1))" + line 412, "pan.___", state 945, "((i>=1))" + line 419, "pan.___", state 952, "(1)" + line 419, "pan.___", state 953, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 953, "else" + line 419, "pan.___", state 956, "(1)" + line 419, "pan.___", state 957, "(1)" + line 419, "pan.___", state 957, "(1)" + line 421, "pan.___", state 960, "(1)" + line 421, "pan.___", state 960, "(1)" + line 370, "pan.___", state 962, "(1)" + line 671, "pan.___", state 963, "tmp = cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )]" + line 400, "pan.___", state 967, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 973, "(1)" + line 404, "pan.___", state 981, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 987, "(1)" + line 404, "pan.___", state 988, "(1)" + line 404, "pan.___", state 988, "(1)" + line 402, "pan.___", state 993, "((i<1))" + line 402, "pan.___", state 993, "((i>=1))" + line 409, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 1012, "(1)" + line 410, "pan.___", state 1013, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 1013, "else" + line 410, "pan.___", state 1016, "(1)" + line 410, "pan.___", state 1017, "(1)" + line 410, "pan.___", state 1017, "(1)" + line 414, "pan.___", state 1025, "(1)" + line 414, "pan.___", state 1026, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 1026, "else" + line 414, "pan.___", state 1029, "(1)" + line 414, "pan.___", state 1030, "(1)" + line 414, "pan.___", state 1030, "(1)" + line 412, "pan.___", state 1035, "((i<1))" + line 412, "pan.___", state 1035, "((i>=1))" + line 419, "pan.___", state 1042, "(1)" + line 419, "pan.___", state 1043, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 1043, "else" + line 419, "pan.___", state 1046, "(1)" + line 419, "pan.___", state 1047, "(1)" + line 419, "pan.___", state 1047, "(1)" + line 421, "pan.___", state 1050, "(1)" + line 421, "pan.___", state 1050, "(1)" + line 370, "pan.___", state 1052, "(1)" + line 400, "pan.___", state 1061, "(1)" + line 404, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1117, "(1)" + line 419, "pan.___", state 1134, "(1)" + line 404, "pan.___", state 1166, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1184, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 414, "pan.___", state 1210, "(1)" + line 419, "pan.___", state 1227, "(1)" + line 400, "pan.___", state 1242, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1256, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 409, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 1287, "(1)" + line 414, "pan.___", state 1300, "(1)" + line 419, "pan.___", state 1317, "(1)" + line 400, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1342, "(1)" + line 400, "pan.___", state 1343, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 400, "pan.___", state 1343, "else" + line 400, "pan.___", state 1346, "(1)" + line 404, "pan.___", state 1354, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1356, "(1)" + line 404, "pan.___", state 1357, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))" + line 404, "pan.___", state 1357, "else" + line 404, "pan.___", state 1360, "(1)" + line 404, "pan.___", state 1361, "(1)" + line 404, "pan.___", state 1361, "(1)" + line 402, "pan.___", state 1366, "((i<1))" + line 402, "pan.___", state 1366, "((i>=1))" + line 409, "pan.___", state 1372, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 410, "pan.___", state 1385, "(1)" + line 410, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 410, "pan.___", state 1386, "else" + line 410, "pan.___", state 1389, "(1)" + line 410, "pan.___", state 1390, "(1)" + line 410, "pan.___", state 1390, "(1)" + line 414, "pan.___", state 1398, "(1)" + line 414, "pan.___", state 1399, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 414, "pan.___", state 1399, "else" + line 414, "pan.___", state 1402, "(1)" + line 414, "pan.___", state 1403, "(1)" + line 414, "pan.___", state 1403, "(1)" + line 412, "pan.___", state 1408, "((i<1))" + line 412, "pan.___", state 1408, "((i>=1))" + line 419, "pan.___", state 1415, "(1)" + line 419, "pan.___", state 1416, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))" + line 419, "pan.___", state 1416, "else" + line 419, "pan.___", state 1419, "(1)" + line 419, "pan.___", state 1420, "(1)" + line 419, "pan.___", state 1420, "(1)" + line 421, "pan.___", state 1423, "(1)" + line 421, "pan.___", state 1423, "(1)" + line 180, "pan.___", state 1448, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 184, "pan.___", state 1461, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 161, "pan.___", state 1471, "(1)" + line 165, "pan.___", state 1479, "(1)" + line 169, "pan.___", state 1491, "(1)" + line 176, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< (0) : (1) ))))" + line 180, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 184, "pan.___", state 1591, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))" + line 161, "pan.___", state 1601, "(1)" + line 165, "pan.___", state 1609, "(1)" + line 169, "pan.___", state 1621, "(1)" + line 370, "pan.___", state 1642, "(1)" + line 696, "pan.___", state 1643, "(1)" + line 703, "pan.___", state 1646, "-end-" + (308 of 1646 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 752, "pan.___", state 11, "-end-" + (1 of 11 states) + +pan: elapsed time 30.2 seconds +pan: rate 93347.646 states/second +pan: avg transition delay 9.1279e-07 usec +cp .input.spin urcu_progress_writer_error.spin.input +cp .input.spin.trail urcu_progress_writer_error.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input new file mode 100644 index 0000000..eb1d4e6 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input @@ -0,0 +1,724 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +//#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail new file mode 100644 index 0000000..c5a6fbf --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail @@ -0,0 +1,23572 @@ +-2:4:-2 +-4:-4:-4 +1:0:2561 +2:4:2513 +3:4:2516 +4:4:2516 +5:4:2519 +6:4:2527 +7:4:2527 +8:4:2530 +9:4:2536 +10:4:2540 +11:4:2540 +12:4:2543 +13:4:2551 +14:4:2555 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+23556:3:2161 +23557:3:2169 +23558:3:2170 +23559:3:2174 +23560:3:2179 +23561:3:2180 +23562:0:2565 +23563:3:2192 +23564:0:2565 +23565:3:2013 +23566:0:2565 +23567:3:2014 +23568:0:2565 +23569:1:206 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/DEFINES b/formal-model/urcu-nosched-model/result-signal-over-writer/DEFINES new file mode 100644 index 0000000..ec600f0 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/DEFINES @@ -0,0 +1,16 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +#endif + +#define REMOTE_BARRIERS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/Makefile b/formal-model/urcu-nosched-model/result-signal-over-writer/Makefile new file mode 100644 index 0000000..8af320d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/Makefile @@ -0,0 +1,172 @@ +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) Mathieu Desnoyers, 2009 +# +# Authors: Mathieu Desnoyers + +#CFLAGS=-DSAFETY +#for multi-core verif, 15.5GB shared mem, use files if full +#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2 +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8 + +#liveness +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 +CFLAGS=-DHASH64 + +SPINFILE=urcu.spin + +default: + make urcu_free | tee urcu_free.log + #nested useless with signal test. + #make urcu_free_nested | tee urcu_free_nested.log + make urcu_free_no_rmb | tee urcu_free_no_rmb.log + make urcu_free_no_wmb | tee urcu_free_no_wmb.log + make urcu_free_no_mb | tee urcu_free_no_mb.log + make urcu_free_single_flip | tee urcu_free_single_flip.log + make urcu_progress_writer | tee urcu_progress_writer.log + make urcu_progress_reader | tee urcu_progress_reader.log + make urcu_progress_writer_error | tee urcu_progress_writer_error.log + make asserts | tee asserts.log + make summary + +#show trail : spin -v -t -N pan.ltl input.spin +# after each individual make. + +summary: + @echo + @echo "Verification summary" + @grep errors: *.log + +asserts: clean + cat DEFINES > .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X .input.spin + gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c + ./pan -v -c1 -X -m10000000 -w20 + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free: clean urcu_free_ltl run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested_define: + cp urcu_free_nested.define .input.define + +urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_rmb_define: + cp urcu_free_no_rmb.define .input.define + +urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_wmb_define: + cp urcu_free_no_wmb.define .input.define + +urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_mb_define: + cp urcu_free_no_mb.define .input.define + +urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_single_flip_define: + cp urcu_free_single_flip.define .input.define + +urcu_free_ltl: + touch .input.define + cat .input.define >> pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl + +# Progress checks + +urcu_progress_writer: clean urcu_progress_writer_ltl \ + urcu_progress_writer_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_define: + cp urcu_progress_writer.define .input.define + +urcu_progress_writer_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_reader: clean urcu_progress_reader_ltl \ + urcu_progress_reader_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_reader_define: + cp urcu_progress_reader.define .input.define + +urcu_progress_reader_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \ + urcu_progress_writer_error_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_error_define: + cp urcu_progress_writer_error.define .input.define + +urcu_progress_writer_error_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + + +run_weak_fair: pan + ./pan -a -f -v -c1 -X -m10000000 -w20 + +run: pan + ./pan -a -v -c1 -X -m10000000 -w20 + +pan: pan.c + gcc -O2 -w ${CFLAGS} -o pan pan.c + +pan.c: pan.ltl ${SPINFILE} + cat .input.define > .input.spin + cat DEFINES >> .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X -N pan.ltl .input.spin + +.PHONY: clean default distclean summary +clean: + rm -f pan* trail.out .input.spin* *.spin.trail .input.define +distclean: + rm -f *.trail *.input *.log diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.log b/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.log new file mode 100644 index 0000000..c102ffb --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.log @@ -0,0 +1,334 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +cat DEFINES > .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w20 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim - (none specified) + assertion violations + + cycle checks - (disabled by -DSAFETY) + invalid end states + + +State-vector 40 byte, depth reached 7872, errors: 0 + 20128 states, stored + 191477 states, matched + 211605 transitions (= stored+matched) + 712166 atomic steps +hash conflicts: 942 (resolved) + +Stats on memory usage (in Megabytes): + 1.305 equivalent memory usage for states (stored*(State-vector + overhead)) + 1.467 actual memory usage for states (unsuccessful compression: 112.36%) + state-vector as stored = 48 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 467.229 total actual memory usage + +unreached in proctype urcu_reader_sig + line 401, ".input.spin", state 330, "(1)" + line 612, ".input.spin", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 397, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 406, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 59, "(1)" + line 416, ".input.spin", state 89, "(1)" + line 397, ".input.spin", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 160, "(1)" + line 650, ".input.spin", state 213, "(1)" + line 173, ".input.spin", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 177, ".input.spin", state 233, "(1)" + line 158, ".input.spin", state 254, "(1)" + line 162, ".input.spin", state 262, "(1)" + line 166, ".input.spin", state 274, "(1)" + line 173, ".input.spin", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 752, "(1)" + line 162, ".input.spin", state 760, "(1)" + line 162, ".input.spin", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 761, "else" + line 160, ".input.spin", state 766, "((j<1))" + line 160, ".input.spin", state 766, "((j>=1))" + line 166, ".input.spin", state 772, "(1)" + line 166, ".input.spin", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 773, "else" + line 168, ".input.spin", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 776, "else" + line 173, ".input.spin", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, ".input.spin", state 835, "(1)" + line 166, ".input.spin", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, ".input.spin", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 852, "(1)" + line 177, ".input.spin", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 861, "(1)" + line 177, ".input.spin", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 862, "else" + line 175, ".input.spin", state 867, "((j<1))" + line 175, ".input.spin", state 867, "((j>=1))" + line 181, ".input.spin", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 882, "(1)" + line 162, ".input.spin", state 890, "(1)" + line 162, ".input.spin", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 891, "else" + line 160, ".input.spin", state 896, "((j<1))" + line 160, ".input.spin", state 896, "((j>=1))" + line 166, ".input.spin", state 902, "(1)" + line 166, ".input.spin", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 903, "else" + line 168, ".input.spin", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 906, "else" + line 200, ".input.spin", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, ".input.spin", state 908, "else" + line 219, ".input.spin", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, ".input.spin", state 909, "else" + line 354, ".input.spin", state 915, "((sighand_exec==1))" + line 354, ".input.spin", state 915, "else" + line 360, ".input.spin", state 918, "sighand_exec = 1" + line 397, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, ".input.spin", state 933, "(1)" + line 397, ".input.spin", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, ".input.spin", state 934, "else" + line 397, ".input.spin", state 937, "(1)" + line 401, ".input.spin", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, ".input.spin", state 947, "(1)" + line 401, ".input.spin", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, ".input.spin", state 948, "else" + line 401, ".input.spin", state 951, "(1)" + line 401, ".input.spin", state 952, "(1)" + line 401, ".input.spin", state 952, "(1)" + line 399, ".input.spin", state 957, "((i<1))" + line 399, ".input.spin", state 957, "((i>=1))" + line 406, ".input.spin", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 976, "(1)" + line 407, ".input.spin", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, ".input.spin", state 977, "else" + line 407, ".input.spin", state 980, "(1)" + line 407, ".input.spin", state 981, "(1)" + line 407, ".input.spin", state 981, "(1)" + line 411, ".input.spin", state 989, "(1)" + line 411, ".input.spin", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, ".input.spin", state 990, "else" + line 411, ".input.spin", state 993, "(1)" + line 411, ".input.spin", state 994, "(1)" + line 411, ".input.spin", state 994, "(1)" + line 409, ".input.spin", state 999, "((i<1))" + line 409, ".input.spin", state 999, "((i>=1))" + line 416, ".input.spin", state 1006, "(1)" + line 416, ".input.spin", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, ".input.spin", state 1007, "else" + line 416, ".input.spin", state 1010, "(1)" + line 416, ".input.spin", state 1011, "(1)" + line 416, ".input.spin", state 1011, "(1)" + line 418, ".input.spin", state 1014, "(1)" + line 418, ".input.spin", state 1014, "(1)" + line 360, ".input.spin", state 1023, "sighand_exec = 1" + line 401, ".input.spin", state 1054, "(1)" + line 406, ".input.spin", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1113, "(1)" + line 401, ".input.spin", state 1151, "(1)" + line 406, ".input.spin", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1210, "(1)" + line 397, ".input.spin", state 1236, "(1)" + line 401, ".input.spin", state 1250, "(1)" + line 406, ".input.spin", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1309, "(1)" + line 401, ".input.spin", state 1350, "(1)" + line 406, ".input.spin", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1409, "(1)" + line 173, ".input.spin", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 1432, "(1)" + line 177, ".input.spin", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 1441, "(1)" + line 177, ".input.spin", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 1442, "else" + line 175, ".input.spin", state 1447, "((j<1))" + line 175, ".input.spin", state 1447, "((j>=1))" + line 181, ".input.spin", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1462, "(1)" + line 162, ".input.spin", state 1470, "(1)" + line 162, ".input.spin", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 1471, "else" + line 160, ".input.spin", state 1476, "((j<1))" + line 160, ".input.spin", state 1476, "((j>=1))" + line 166, ".input.spin", state 1482, "(1)" + line 166, ".input.spin", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 1483, "else" + line 168, ".input.spin", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 1486, "else" + line 173, ".input.spin", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, ".input.spin", state 1545, "(1)" + line 166, ".input.spin", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, ".input.spin", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 1562, "(1)" + line 177, ".input.spin", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 1571, "(1)" + line 177, ".input.spin", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 1572, "else" + line 175, ".input.spin", state 1577, "((j<1))" + line 175, ".input.spin", state 1577, "((j>=1))" + line 181, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1592, "(1)" + line 162, ".input.spin", state 1600, "(1)" + line 162, ".input.spin", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 1601, "else" + line 160, ".input.spin", state 1606, "((j<1))" + line 160, ".input.spin", state 1606, "((j>=1))" + line 166, ".input.spin", state 1612, "(1)" + line 166, ".input.spin", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 1613, "else" + line 168, ".input.spin", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 1616, "else" + line 200, ".input.spin", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, ".input.spin", state 1618, "else" + line 219, ".input.spin", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, ".input.spin", state 1619, "else" + line 354, ".input.spin", state 1625, "((sighand_exec==1))" + line 354, ".input.spin", state 1625, "else" + line 360, ".input.spin", state 1628, "sighand_exec = 1" + line 397, ".input.spin", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, ".input.spin", state 1643, "(1)" + line 397, ".input.spin", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, ".input.spin", state 1644, "else" + line 397, ".input.spin", state 1647, "(1)" + line 401, ".input.spin", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, ".input.spin", state 1657, "(1)" + line 401, ".input.spin", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, ".input.spin", state 1658, "else" + line 401, ".input.spin", state 1661, "(1)" + line 401, ".input.spin", state 1662, "(1)" + line 401, ".input.spin", state 1662, "(1)" + line 399, ".input.spin", state 1667, "((i<1))" + line 399, ".input.spin", state 1667, "((i>=1))" + line 406, ".input.spin", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 1686, "(1)" + line 407, ".input.spin", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, ".input.spin", state 1687, "else" + line 407, ".input.spin", state 1690, "(1)" + line 407, ".input.spin", state 1691, "(1)" + line 407, ".input.spin", state 1691, "(1)" + line 411, ".input.spin", state 1699, "(1)" + line 411, ".input.spin", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, ".input.spin", state 1700, "else" + line 411, ".input.spin", state 1703, "(1)" + line 411, ".input.spin", state 1704, "(1)" + line 411, ".input.spin", state 1704, "(1)" + line 409, ".input.spin", state 1709, "((i<1))" + line 409, ".input.spin", state 1709, "((i>=1))" + line 416, ".input.spin", state 1716, "(1)" + line 416, ".input.spin", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, ".input.spin", state 1717, "else" + line 416, ".input.spin", state 1720, "(1)" + line 416, ".input.spin", state 1721, "(1)" + line 416, ".input.spin", state 1721, "(1)" + line 418, ".input.spin", state 1724, "(1)" + line 418, ".input.spin", state 1724, "(1)" + line 360, ".input.spin", state 1733, "sighand_exec = 1" + line 177, ".input.spin", state 1758, "(1)" + line 181, ".input.spin", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1779, "(1)" + line 162, ".input.spin", state 1787, "(1)" + line 166, ".input.spin", state 1799, "(1)" + line 173, ".input.spin", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.spin.input.trail new file mode 100644 index 0000000..287e52a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/asserts.spin.input.trail @@ -0,0 +1,6 @@ +-4:-4:-4 +1:0:2673 +2:0:2674 +3:0:2675 +4:0:2676 +5:4:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/references.txt b/formal-model/urcu-nosched-model/result-signal-over-writer/references.txt new file mode 100644 index 0000000..72c67a2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/references.txt @@ -0,0 +1,13 @@ +http://spinroot.com/spin/Man/ltl.html +http://en.wikipedia.org/wiki/Linear_temporal_logic +http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt + +http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php +http://spinroot.com/spin/Man/index.html +http://spinroot.com/spin/Man/promela.html + +LTL vs CTL : + +http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18 +http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf + (downloaded) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/DEFINES b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/DEFINES new file mode 100644 index 0000000..ec600f0 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/DEFINES @@ -0,0 +1,16 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +#endif + +#define REMOTE_BARRIERS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/Makefile b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/Makefile new file mode 100644 index 0000000..8af320d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/Makefile @@ -0,0 +1,172 @@ +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) Mathieu Desnoyers, 2009 +# +# Authors: Mathieu Desnoyers + +#CFLAGS=-DSAFETY +#for multi-core verif, 15.5GB shared mem, use files if full +#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2 +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8 + +#liveness +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 +CFLAGS=-DHASH64 + +SPINFILE=urcu.spin + +default: + make urcu_free | tee urcu_free.log + #nested useless with signal test. + #make urcu_free_nested | tee urcu_free_nested.log + make urcu_free_no_rmb | tee urcu_free_no_rmb.log + make urcu_free_no_wmb | tee urcu_free_no_wmb.log + make urcu_free_no_mb | tee urcu_free_no_mb.log + make urcu_free_single_flip | tee urcu_free_single_flip.log + make urcu_progress_writer | tee urcu_progress_writer.log + make urcu_progress_reader | tee urcu_progress_reader.log + make urcu_progress_writer_error | tee urcu_progress_writer_error.log + make asserts | tee asserts.log + make summary + +#show trail : spin -v -t -N pan.ltl input.spin +# after each individual make. + +summary: + @echo + @echo "Verification summary" + @grep errors: *.log + +asserts: clean + cat DEFINES > .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X .input.spin + gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c + ./pan -v -c1 -X -m10000000 -w20 + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free: clean urcu_free_ltl run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested_define: + cp urcu_free_nested.define .input.define + +urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_rmb_define: + cp urcu_free_no_rmb.define .input.define + +urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_wmb_define: + cp urcu_free_no_wmb.define .input.define + +urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_mb_define: + cp urcu_free_no_mb.define .input.define + +urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_single_flip_define: + cp urcu_free_single_flip.define .input.define + +urcu_free_ltl: + touch .input.define + cat .input.define >> pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl + +# Progress checks + +urcu_progress_writer: clean urcu_progress_writer_ltl \ + urcu_progress_writer_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_define: + cp urcu_progress_writer.define .input.define + +urcu_progress_writer_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_reader: clean urcu_progress_reader_ltl \ + urcu_progress_reader_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_reader_define: + cp urcu_progress_reader.define .input.define + +urcu_progress_reader_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \ + urcu_progress_writer_error_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_error_define: + cp urcu_progress_writer_error.define .input.define + +urcu_progress_writer_error_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + + +run_weak_fair: pan + ./pan -a -f -v -c1 -X -m10000000 -w20 + +run: pan + ./pan -a -v -c1 -X -m10000000 -w20 + +pan: pan.c + gcc -O2 -w ${CFLAGS} -o pan pan.c + +pan.c: pan.ltl ${SPINFILE} + cat .input.define > .input.spin + cat DEFINES >> .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X -N pan.ltl .input.spin + +.PHONY: clean default distclean summary +clean: + rm -f pan* trail.out .input.spin* *.spin.trail .input.define +distclean: + rm -f *.trail *.input *.log diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.log b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.log new file mode 100644 index 0000000..c102ffb --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.log @@ -0,0 +1,334 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +cat DEFINES > .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w20 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim - (none specified) + assertion violations + + cycle checks - (disabled by -DSAFETY) + invalid end states + + +State-vector 40 byte, depth reached 7872, errors: 0 + 20128 states, stored + 191477 states, matched + 211605 transitions (= stored+matched) + 712166 atomic steps +hash conflicts: 942 (resolved) + +Stats on memory usage (in Megabytes): + 1.305 equivalent memory usage for states (stored*(State-vector + overhead)) + 1.467 actual memory usage for states (unsuccessful compression: 112.36%) + state-vector as stored = 48 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 467.229 total actual memory usage + +unreached in proctype urcu_reader_sig + line 401, ".input.spin", state 330, "(1)" + line 612, ".input.spin", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 397, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 406, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 59, "(1)" + line 416, ".input.spin", state 89, "(1)" + line 397, ".input.spin", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 160, "(1)" + line 650, ".input.spin", state 213, "(1)" + line 173, ".input.spin", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 177, ".input.spin", state 233, "(1)" + line 158, ".input.spin", state 254, "(1)" + line 162, ".input.spin", state 262, "(1)" + line 166, ".input.spin", state 274, "(1)" + line 173, ".input.spin", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 752, "(1)" + line 162, ".input.spin", state 760, "(1)" + line 162, ".input.spin", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 761, "else" + line 160, ".input.spin", state 766, "((j<1))" + line 160, ".input.spin", state 766, "((j>=1))" + line 166, ".input.spin", state 772, "(1)" + line 166, ".input.spin", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 773, "else" + line 168, ".input.spin", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 776, "else" + line 173, ".input.spin", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, ".input.spin", state 835, "(1)" + line 166, ".input.spin", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, ".input.spin", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 852, "(1)" + line 177, ".input.spin", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 861, "(1)" + line 177, ".input.spin", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 862, "else" + line 175, ".input.spin", state 867, "((j<1))" + line 175, ".input.spin", state 867, "((j>=1))" + line 181, ".input.spin", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 882, "(1)" + line 162, ".input.spin", state 890, "(1)" + line 162, ".input.spin", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 891, "else" + line 160, ".input.spin", state 896, "((j<1))" + line 160, ".input.spin", state 896, "((j>=1))" + line 166, ".input.spin", state 902, "(1)" + line 166, ".input.spin", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 903, "else" + line 168, ".input.spin", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 906, "else" + line 200, ".input.spin", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, ".input.spin", state 908, "else" + line 219, ".input.spin", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, ".input.spin", state 909, "else" + line 354, ".input.spin", state 915, "((sighand_exec==1))" + line 354, ".input.spin", state 915, "else" + line 360, ".input.spin", state 918, "sighand_exec = 1" + line 397, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, ".input.spin", state 933, "(1)" + line 397, ".input.spin", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, ".input.spin", state 934, "else" + line 397, ".input.spin", state 937, "(1)" + line 401, ".input.spin", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, ".input.spin", state 947, "(1)" + line 401, ".input.spin", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, ".input.spin", state 948, "else" + line 401, ".input.spin", state 951, "(1)" + line 401, ".input.spin", state 952, "(1)" + line 401, ".input.spin", state 952, "(1)" + line 399, ".input.spin", state 957, "((i<1))" + line 399, ".input.spin", state 957, "((i>=1))" + line 406, ".input.spin", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 976, "(1)" + line 407, ".input.spin", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, ".input.spin", state 977, "else" + line 407, ".input.spin", state 980, "(1)" + line 407, ".input.spin", state 981, "(1)" + line 407, ".input.spin", state 981, "(1)" + line 411, ".input.spin", state 989, "(1)" + line 411, ".input.spin", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, ".input.spin", state 990, "else" + line 411, ".input.spin", state 993, "(1)" + line 411, ".input.spin", state 994, "(1)" + line 411, ".input.spin", state 994, "(1)" + line 409, ".input.spin", state 999, "((i<1))" + line 409, ".input.spin", state 999, "((i>=1))" + line 416, ".input.spin", state 1006, "(1)" + line 416, ".input.spin", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, ".input.spin", state 1007, "else" + line 416, ".input.spin", state 1010, "(1)" + line 416, ".input.spin", state 1011, "(1)" + line 416, ".input.spin", state 1011, "(1)" + line 418, ".input.spin", state 1014, "(1)" + line 418, ".input.spin", state 1014, "(1)" + line 360, ".input.spin", state 1023, "sighand_exec = 1" + line 401, ".input.spin", state 1054, "(1)" + line 406, ".input.spin", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1113, "(1)" + line 401, ".input.spin", state 1151, "(1)" + line 406, ".input.spin", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1210, "(1)" + line 397, ".input.spin", state 1236, "(1)" + line 401, ".input.spin", state 1250, "(1)" + line 406, ".input.spin", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1309, "(1)" + line 401, ".input.spin", state 1350, "(1)" + line 406, ".input.spin", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, ".input.spin", state 1409, "(1)" + line 173, ".input.spin", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 1432, "(1)" + line 177, ".input.spin", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 1441, "(1)" + line 177, ".input.spin", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 1442, "else" + line 175, ".input.spin", state 1447, "((j<1))" + line 175, ".input.spin", state 1447, "((j>=1))" + line 181, ".input.spin", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1462, "(1)" + line 162, ".input.spin", state 1470, "(1)" + line 162, ".input.spin", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 1471, "else" + line 160, ".input.spin", state 1476, "((j<1))" + line 160, ".input.spin", state 1476, "((j>=1))" + line 166, ".input.spin", state 1482, "(1)" + line 166, ".input.spin", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 1483, "else" + line 168, ".input.spin", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 1486, "else" + line 173, ".input.spin", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, ".input.spin", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, ".input.spin", state 1545, "(1)" + line 166, ".input.spin", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, ".input.spin", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, ".input.spin", state 1562, "(1)" + line 177, ".input.spin", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, ".input.spin", state 1571, "(1)" + line 177, ".input.spin", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, ".input.spin", state 1572, "else" + line 175, ".input.spin", state 1577, "((j<1))" + line 175, ".input.spin", state 1577, "((j>=1))" + line 181, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1592, "(1)" + line 162, ".input.spin", state 1600, "(1)" + line 162, ".input.spin", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, ".input.spin", state 1601, "else" + line 160, ".input.spin", state 1606, "((j<1))" + line 160, ".input.spin", state 1606, "((j>=1))" + line 166, ".input.spin", state 1612, "(1)" + line 166, ".input.spin", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, ".input.spin", state 1613, "else" + line 168, ".input.spin", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, ".input.spin", state 1616, "else" + line 200, ".input.spin", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, ".input.spin", state 1618, "else" + line 219, ".input.spin", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, ".input.spin", state 1619, "else" + line 354, ".input.spin", state 1625, "((sighand_exec==1))" + line 354, ".input.spin", state 1625, "else" + line 360, ".input.spin", state 1628, "sighand_exec = 1" + line 397, ".input.spin", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, ".input.spin", state 1643, "(1)" + line 397, ".input.spin", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, ".input.spin", state 1644, "else" + line 397, ".input.spin", state 1647, "(1)" + line 401, ".input.spin", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, ".input.spin", state 1657, "(1)" + line 401, ".input.spin", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, ".input.spin", state 1658, "else" + line 401, ".input.spin", state 1661, "(1)" + line 401, ".input.spin", state 1662, "(1)" + line 401, ".input.spin", state 1662, "(1)" + line 399, ".input.spin", state 1667, "((i<1))" + line 399, ".input.spin", state 1667, "((i>=1))" + line 406, ".input.spin", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, ".input.spin", state 1686, "(1)" + line 407, ".input.spin", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, ".input.spin", state 1687, "else" + line 407, ".input.spin", state 1690, "(1)" + line 407, ".input.spin", state 1691, "(1)" + line 407, ".input.spin", state 1691, "(1)" + line 411, ".input.spin", state 1699, "(1)" + line 411, ".input.spin", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, ".input.spin", state 1700, "else" + line 411, ".input.spin", state 1703, "(1)" + line 411, ".input.spin", state 1704, "(1)" + line 411, ".input.spin", state 1704, "(1)" + line 409, ".input.spin", state 1709, "((i<1))" + line 409, ".input.spin", state 1709, "((i>=1))" + line 416, ".input.spin", state 1716, "(1)" + line 416, ".input.spin", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, ".input.spin", state 1717, "else" + line 416, ".input.spin", state 1720, "(1)" + line 416, ".input.spin", state 1721, "(1)" + line 416, ".input.spin", state 1721, "(1)" + line 418, ".input.spin", state 1724, "(1)" + line 418, ".input.spin", state 1724, "(1)" + line 360, ".input.spin", state 1733, "sighand_exec = 1" + line 177, ".input.spin", state 1758, "(1)" + line 181, ".input.spin", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, ".input.spin", state 1779, "(1)" + line 162, ".input.spin", state 1787, "(1)" + line 166, ".input.spin", state 1799, "(1)" + line 173, ".input.spin", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail new file mode 100644 index 0000000..287e52a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail @@ -0,0 +1,6 @@ +-4:-4:-4 +1:0:2673 +2:0:2674 +3:0:2675 +4:0:2676 +5:4:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/references.txt b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/references.txt new file mode 100644 index 0000000..72c67a2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/result-signal-over-writer/references.txt @@ -0,0 +1,13 @@ +http://spinroot.com/spin/Man/ltl.html +http://en.wikipedia.org/wiki/Linear_temporal_logic +http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt + +http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php +http://spinroot.com/spin/Man/index.html +http://spinroot.com/spin/Man/promela.html + +LTL vs CTL : + +http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18 +http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf + (downloaded) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/.input.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/.input.define new file mode 100644 index 0000000..e69de29 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/.input.spin b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/.input.spin new file mode 100644 index 0000000..f2737c4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/.input.spin @@ -0,0 +1,531 @@ + +#define NR_READERS 2 +#define NR_WRITERS 1 + +#define NR_PROCS 3 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/DEFINES b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/DEFINES new file mode 100644 index 0000000..12c751b --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/DEFINES @@ -0,0 +1,31 @@ + +#define NR_READERS 2 +#define NR_WRITERS 1 + +#define NR_PROCS 3 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/Makefile b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/Makefile new file mode 100644 index 0000000..ca932b7 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/Makefile @@ -0,0 +1,165 @@ +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) Mathieu Desnoyers, 2009 +# +# Authors: Mathieu Desnoyers + +#CFLAGS=-DSAFETY +CFLAGS=-DHASH64 + +SPINFILE=urcu.spin + +default: + make urcu_free | tee urcu_free.log + make urcu_free_nested | tee urcu_free_nested.log + make urcu_free_no_rmb | tee urcu_free_no_rmb.log + make urcu_free_no_wmb | tee urcu_free_no_wmb.log + make urcu_free_no_mb | tee urcu_free_no_mb.log + make urcu_free_single_flip | tee urcu_free_single_flip.log + make urcu_progress_writer | tee urcu_progress_writer.log + make urcu_progress_reader | tee urcu_progress_reader.log + make urcu_progress_writer_error | tee urcu_progress_writer_error.log + make asserts | tee asserts.log + make summary + +#show trail : spin -v -t -N pan.ltl input.spin +# after each individual make. + +summary: + @echo + @echo "Verification summary" + @grep errors: *.log + +asserts: clean + cat DEFINES > .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X .input.spin + gcc -w ${CFLAGS} -DSAFETY -o pan pan.c + ./pan -v -c1 -X -m10000000 -w20 + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free: clean urcu_free_ltl run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested_define: + cp urcu_free_nested.define .input.define + +urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_rmb_define: + cp urcu_free_no_rmb.define .input.define + +urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_wmb_define: + cp urcu_free_no_wmb.define .input.define + +urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_mb_define: + cp urcu_free_no_mb.define .input.define + +urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_single_flip_define: + cp urcu_free_single_flip.define .input.define + +urcu_free_ltl: + touch .input.define + cat .input.define >> pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl + +# Progress checks + +urcu_progress_writer: clean urcu_progress_writer_ltl \ + urcu_progress_writer_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_define: + cp urcu_progress_writer.define .input.define + +urcu_progress_writer_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_reader: clean urcu_progress_reader_ltl \ + urcu_progress_reader_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_reader_define: + cp urcu_progress_reader.define .input.define + +urcu_progress_reader_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \ + urcu_progress_writer_error_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_error_define: + cp urcu_progress_writer_error.define .input.define + +urcu_progress_writer_error_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + + +run_weak_fair: pan + ./pan -a -f -v -c1 -X -m10000000 -w20 + +run: pan + ./pan -a -v -c1 -X -m10000000 -w20 + +pan: pan.c + gcc -w ${CFLAGS} -o pan pan.c + +pan.c: pan.ltl ${SPINFILE} + cat .input.define > .input.spin + cat DEFINES >> .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X -N pan.ltl .input.spin + +.PHONY: clean default distclean summary +clean: + rm -f pan* trail.out .input.spin* *.spin.trail .input.define +distclean: + rm -f *.trail *.input *.log diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.log new file mode 100644 index 0000000..75f2427 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.log @@ -0,0 +1,10 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +cat DEFINES > .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X .input.spin +spin: line 295 replacement value: tmp +spin: line 295 ".input.spin", Error: formal par of wait_for_quiescent_state contains replacement value saw '-2'' near 'readerid' +spin: 1 error(s) - aborting +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input new file mode 100644 index 0000000..b06898a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input @@ -0,0 +1,409 @@ +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#define read_free_race (read_generation == last_free_gen) +#define read_free (free_done && data_access) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + if + :: (NR_READERS > 1) && (i < NR_READERS - 1) + -> ooo_mem(j); + :: else + -> skip; + fi; + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + smp_mb(i); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active [NR_WRITERS] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + smp_mb(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input.trail new file mode 100644 index 0000000..287e52a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/asserts.spin.input.trail @@ -0,0 +1,6 @@ +-4:-4:-4 +1:0:2673 +2:0:2674 +3:0:2675 +4:0:2676 +5:4:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/references.txt b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/references.txt new file mode 100644 index 0000000..72c67a2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/references.txt @@ -0,0 +1,13 @@ +http://spinroot.com/spin/Man/ltl.html +http://en.wikipedia.org/wiki/Linear_temporal_logic +http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt + +http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php +http://spinroot.com/spin/Man/index.html +http://spinroot.com/spin/Man/promela.html + +LTL vs CTL : + +http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18 +http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf + (downloaded) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.sh b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.sh new file mode 100644 index 0000000..65ff517 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.sh @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Compiles and runs the urcu.spin Promela model. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) IBM Corporation, 2009 +# Mathieu Desnoyers, 2009 +# +# Authors: Paul E. McKenney +# Mathieu Desnoyers + +# Basic execution, without LTL clauses. See Makefile. + +spin -a urcu.spin +cc -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w21 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin new file mode 100644 index 0000000..61d9052 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin @@ -0,0 +1,500 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp2 b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp2 new file mode 100644 index 0000000..b1c8311 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp2 @@ -0,0 +1,395 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_WRITERS 1 +#define NR_READERS 3 + +/* Number of reader and writer processes */ +#define NR_PROCS 5 + +/* Includes reader, writer and init process */ +#define MAX_NR_PROCS 5 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif + skip; + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif + skip; + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_writerid() (get_pid()) +#define get_readerid() (get_writerrid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + skip; +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2, nest) +{ + nest_i = 0; + do + :: nest_i < nest -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + ooo_mem(i); + smp_mb(i); + nest_i++; + :: nest_i >= nest -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < nest -> + ooo_mem(i); + smp_mb(i); + ooo_mem(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= nest -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [2] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2, 2); + od; +} + +/* Model the RCU update process. */ + +active [1] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + ooo_mem(i); + smp_mb(i); + ooo_mem(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp5 b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp5 new file mode 100644 index 0000000..324ee39 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu.spin.bkp5 @@ -0,0 +1,398 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + if + :: (NR_READERS > 1) && (i < NR_READERS - 1) + -> ooo_mem(j); + :: else + -> skip; + fi; + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + smp_mb(i); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active [NR_WRITERS] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + smp_mb(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.log new file mode 100644 index 0000000..6a04aba --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.log @@ -0,0 +1,414 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 566) +Depth= 4234 States= 1e+06 Transitions= 1.7e+07 Memory= 527.287 t= 31.3 R= 3e+04 +Depth= 4234 States= 2e+06 Transitions= 3.44e+07 Memory= 588.322 t= 63.9 R= 3e+04 +Depth= 4234 States= 3e+06 Transitions= 5.2e+07 Memory= 649.358 t= 97 R= 3e+04 +pan: resizing hashtable to -w22.. done +Depth= 4234 States= 4e+06 Transitions= 6.97e+07 Memory= 741.416 t= 130 R= 3e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 4234, errors: 0 + 4027146 states, stored + 66145121 states, matched + 70172267 transitions (= stored+matched) +2.6437688e+08 atomic steps +hash conflicts: 47318190 (resolved) + +Stats on memory usage (in Megabytes): + 322.609 equivalent memory usage for states (stored*(State-vector + overhead)) + 253.418 actual memory usage for states (compression: 78.55%) + state-vector as stored = 38 byte + 28 byte overhead + 32.000 memory used for hash table (-w22) + 457.764 memory used for DFS stack (-m10000000) + 743.076 total actual memory usage + +unreached in proctype urcu_reader + line 288, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 61, "(1)" + line 307, "pan.___", state 91, "(1)" + line 288, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 149, "(1)" + line 307, "pan.___", state 179, "(1)" + line 288, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 238, "(1)" + line 307, "pan.___", state 268, "(1)" + line 158, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 291, "(1)" + line 162, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 300, "(1)" + line 162, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 301, "else" + line 160, "pan.___", state 306, "((j<1))" + line 160, "pan.___", state 306, "((j>=1))" + line 166, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 321, "(1)" + line 147, "pan.___", state 329, "(1)" + line 147, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 330, "else" + line 145, "pan.___", state 335, "((j<1))" + line 145, "pan.___", state 335, "((j>=1))" + line 151, "pan.___", state 341, "(1)" + line 151, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 342, "else" + line 153, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 345, "else" + line 185, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 347, "else" + line 158, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 166, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 151, "pan.___", state 404, "(1)" + line 151, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 158, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 421, "(1)" + line 162, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 430, "(1)" + line 162, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 431, "else" + line 160, "pan.___", state 436, "((j<1))" + line 160, "pan.___", state 436, "((j>=1))" + line 166, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 451, "(1)" + line 147, "pan.___", state 459, "(1)" + line 147, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 460, "else" + line 145, "pan.___", state 465, "((j<1))" + line 145, "pan.___", state 465, "((j>=1))" + line 151, "pan.___", state 471, "(1)" + line 151, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 472, "else" + line 153, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 475, "else" + line 185, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 477, "else" + line 288, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 537, "(1)" + line 307, "pan.___", state 567, "(1)" + line 288, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 625, "(1)" + line 307, "pan.___", state 655, "(1)" + line 288, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 713, "(1)" + line 307, "pan.___", state 743, "(1)" + line 158, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 760, "(1)" + line 162, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 769, "(1)" + line 162, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 770, "else" + line 160, "pan.___", state 775, "((j<1))" + line 160, "pan.___", state 775, "((j>=1))" + line 166, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 790, "(1)" + line 147, "pan.___", state 798, "(1)" + line 147, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 799, "else" + line 145, "pan.___", state 804, "((j<1))" + line 145, "pan.___", state 804, "((j>=1))" + line 151, "pan.___", state 810, "(1)" + line 151, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 811, "else" + line 153, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 814, "else" + line 185, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 816, "else" + line 158, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 166, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 151, "pan.___", state 873, "(1)" + line 151, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 158, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 890, "(1)" + line 162, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 899, "(1)" + line 162, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 900, "else" + line 160, "pan.___", state 905, "((j<1))" + line 160, "pan.___", state 905, "((j>=1))" + line 166, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 920, "(1)" + line 147, "pan.___", state 928, "(1)" + line 147, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 929, "else" + line 145, "pan.___", state 934, "((j<1))" + line 145, "pan.___", state 934, "((j>=1))" + line 151, "pan.___", state 940, "(1)" + line 151, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 941, "else" + line 153, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 944, "else" + line 185, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 946, "else" + line 288, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1001, "(1)" + line 307, "pan.___", state 1031, "(1)" + line 288, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1097, "(1)" + line 307, "pan.___", state 1127, "(1)" + line 433, "pan.___", state 1140, "-end-" + (125 of 1140 states) +unreached in proctype urcu_writer + line 288, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 292, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 59, "(1)" + line 302, "pan.___", state 72, "(1)" + line 307, "pan.___", state 89, "(1)" + line 288, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 292, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 151, "(1)" + line 302, "pan.___", state 164, "(1)" + line 467, "pan.___", state 195, "(1)" + line 158, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 237, "(1)" + line 147, "pan.___", state 245, "(1)" + line 151, "pan.___", state 257, "(1)" + line 158, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 297, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 923, "(1)" + line 298, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 298, "pan.___", state 924, "else" + line 298, "pan.___", state 927, "(1)" + line 298, "pan.___", state 928, "(1)" + line 298, "pan.___", state 928, "(1)" + line 302, "pan.___", state 936, "(1)" + line 302, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 302, "pan.___", state 937, "else" + line 302, "pan.___", state 940, "(1)" + line 302, "pan.___", state 941, "(1)" + line 302, "pan.___", state 941, "(1)" + line 300, "pan.___", state 946, "((i<1))" + line 300, "pan.___", state 946, "((i>=1))" + line 307, "pan.___", state 953, "(1)" + line 307, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 307, "pan.___", state 954, "else" + line 307, "pan.___", state 957, "(1)" + line 307, "pan.___", state 958, "(1)" + line 307, "pan.___", state 958, "(1)" + line 309, "pan.___", state 961, "(1)" + line 309, "pan.___", state 961, "(1)" + line 292, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1008, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1034, "(1)" + line 307, "pan.___", state 1051, "(1)" + line 292, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1096, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1122, "(1)" + line 307, "pan.___", state 1139, "(1)" + line 288, "pan.___", state 1156, "(1)" + line 292, "pan.___", state 1168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1186, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1212, "(1)" + line 307, "pan.___", state 1229, "(1)" + line 292, "pan.___", state 1259, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1277, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1303, "(1)" + line 307, "pan.___", state 1320, "(1)" + line 162, "pan.___", state 1342, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 166, "pan.___", state 1355, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 1365, "(1)" + line 147, "pan.___", state 1373, "(1)" + line 151, "pan.___", state 1385, "(1)" + line 158, "pan.___", state 1396, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 297, "pan.___", state 1571, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1584, "(1)" + line 298, "pan.___", state 1585, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 298, "pan.___", state 1585, "else" + line 298, "pan.___", state 1588, "(1)" + line 298, "pan.___", state 1589, "(1)" + line 298, "pan.___", state 1589, "(1)" + line 302, "pan.___", state 1597, "(1)" + line 302, "pan.___", state 1598, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 302, "pan.___", state 1598, "else" + line 302, "pan.___", state 1601, "(1)" + line 302, "pan.___", state 1602, "(1)" + line 302, "pan.___", state 1602, "(1)" + line 300, "pan.___", state 1607, "((i<1))" + line 300, "pan.___", state 1607, "((i>=1))" + line 307, "pan.___", state 1614, "(1)" + line 307, "pan.___", state 1615, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 307, "pan.___", state 1615, "else" + line 307, "pan.___", state 1618, "(1)" + line 307, "pan.___", state 1619, "(1)" + line 307, "pan.___", state 1619, "(1)" + line 309, "pan.___", state 1622, "(1)" + line 309, "pan.___", state 1622, "(1)" + line 162, "pan.___", state 1646, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 166, "pan.___", state 1659, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 1669, "(1)" + line 147, "pan.___", state 1677, "(1)" + line 151, "pan.___", state 1689, "(1)" + line 158, "pan.___", state 1700, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< !read_free_race) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input new file mode 100644 index 0000000..18f99c4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input @@ -0,0 +1,531 @@ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input.trail new file mode 100644 index 0000000..0d22946 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free.spin.input.trail @@ -0,0 +1,1902 @@ +-2:3:-2 +-4:-4:-4 +1:0:3013 +2:2:1132 +3:0:3013 +4:1:0 +5:0:3013 +6:1:1 +7:0:3013 +8:1:2 +9:0:3013 +10:1:3 +11:0:3013 +12:3:2969 +13:0:3013 +14:3:2970 +15:0:3013 +16:3:2971 +17:0:3013 +18:3:2972 +19:0:3013 +20:3:2973 +21:0:3013 +22:3:2974 +23:0:3013 +24:3:2971 +25:0:3013 +26:3:2972 +27:0:3013 +28:3:2973 +29:0:3013 +30:3:2974 +31:0:3013 +32:3:2975 +33:0:3013 +34:3:2980 +35:0:3013 +36:3:2981 +37:0:3013 +38:3:2982 +39:0:3013 +40:3:2983 +41:0:3013 +42:3:2984 +43:0:3013 +44:3:2985 +45:0:3013 +46:3:2982 +47:0:3013 +48:3:2983 +49:0:3013 +50:3:2984 +51:0:3013 +52:3:2985 +53:0:3013 +54:3:2986 +55:0:3013 +56:3:2992 +57:0:3013 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b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.define new file mode 100644 index 0000000..e69de29 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.log new file mode 100644 index 0000000..708dee2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.log @@ -0,0 +1,415 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_nested.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 566) +Depth= 4234 States= 1e+06 Transitions= 1.7e+07 Memory= 527.287 t= 31.2 R= 3e+04 +Depth= 4234 States= 2e+06 Transitions= 3.44e+07 Memory= 588.322 t= 63.7 R= 3e+04 +Depth= 4234 States= 3e+06 Transitions= 5.2e+07 Memory= 649.358 t= 96.8 R= 3e+04 +pan: resizing hashtable to -w22.. done +Depth= 4234 States= 4e+06 Transitions= 6.97e+07 Memory= 741.416 t= 130 R= 3e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 4234, errors: 0 + 4027146 states, stored + 66145121 states, matched + 70172267 transitions (= stored+matched) +2.6437688e+08 atomic steps +hash conflicts: 47318190 (resolved) + +Stats on memory usage (in Megabytes): + 322.609 equivalent memory usage for states (stored*(State-vector + overhead)) + 253.418 actual memory usage for states (compression: 78.55%) + state-vector as stored = 38 byte + 28 byte overhead + 32.000 memory used for hash table (-w22) + 457.764 memory used for DFS stack (-m10000000) + 743.076 total actual memory usage + +unreached in proctype urcu_reader + line 288, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 61, "(1)" + line 307, "pan.___", state 91, "(1)" + line 288, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 149, "(1)" + line 307, "pan.___", state 179, "(1)" + line 288, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 238, "(1)" + line 307, "pan.___", state 268, "(1)" + line 158, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 291, "(1)" + line 162, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 300, "(1)" + line 162, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 301, "else" + line 160, "pan.___", state 306, "((j<1))" + line 160, "pan.___", state 306, "((j>=1))" + line 166, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 321, "(1)" + line 147, "pan.___", state 329, "(1)" + line 147, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 330, "else" + line 145, "pan.___", state 335, "((j<1))" + line 145, "pan.___", state 335, "((j>=1))" + line 151, "pan.___", state 341, "(1)" + line 151, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 342, "else" + line 153, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 345, "else" + line 185, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 347, "else" + line 158, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 166, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 151, "pan.___", state 404, "(1)" + line 151, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 158, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 421, "(1)" + line 162, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 430, "(1)" + line 162, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 431, "else" + line 160, "pan.___", state 436, "((j<1))" + line 160, "pan.___", state 436, "((j>=1))" + line 166, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 451, "(1)" + line 147, "pan.___", state 459, "(1)" + line 147, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 460, "else" + line 145, "pan.___", state 465, "((j<1))" + line 145, "pan.___", state 465, "((j>=1))" + line 151, "pan.___", state 471, "(1)" + line 151, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 472, "else" + line 153, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 475, "else" + line 185, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 477, "else" + line 288, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 537, "(1)" + line 307, "pan.___", state 567, "(1)" + line 288, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 625, "(1)" + line 307, "pan.___", state 655, "(1)" + line 288, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 713, "(1)" + line 307, "pan.___", state 743, "(1)" + line 158, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 760, "(1)" + line 162, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 769, "(1)" + line 162, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 770, "else" + line 160, "pan.___", state 775, "((j<1))" + line 160, "pan.___", state 775, "((j>=1))" + line 166, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 790, "(1)" + line 147, "pan.___", state 798, "(1)" + line 147, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 799, "else" + line 145, "pan.___", state 804, "((j<1))" + line 145, "pan.___", state 804, "((j>=1))" + line 151, "pan.___", state 810, "(1)" + line 151, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 811, "else" + line 153, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 814, "else" + line 185, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 816, "else" + line 158, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 166, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 151, "pan.___", state 873, "(1)" + line 151, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 158, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 158, "pan.___", state 890, "(1)" + line 162, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 899, "(1)" + line 162, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 162, "pan.___", state 900, "else" + line 160, "pan.___", state 905, "((j<1))" + line 160, "pan.___", state 905, "((j>=1))" + line 166, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 920, "(1)" + line 147, "pan.___", state 928, "(1)" + line 147, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 147, "pan.___", state 929, "else" + line 145, "pan.___", state 934, "((j<1))" + line 145, "pan.___", state 934, "((j>=1))" + line 151, "pan.___", state 940, "(1)" + line 151, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 151, "pan.___", state 941, "else" + line 153, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 153, "pan.___", state 944, "else" + line 185, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 185, "pan.___", state 946, "else" + line 288, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1001, "(1)" + line 307, "pan.___", state 1031, "(1)" + line 288, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1097, "(1)" + line 307, "pan.___", state 1127, "(1)" + line 433, "pan.___", state 1140, "-end-" + (125 of 1140 states) +unreached in proctype urcu_writer + line 288, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 292, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 59, "(1)" + line 302, "pan.___", state 72, "(1)" + line 307, "pan.___", state 89, "(1)" + line 288, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 292, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 151, "(1)" + line 302, "pan.___", state 164, "(1)" + line 467, "pan.___", state 195, "(1)" + line 158, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 162, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 237, "(1)" + line 147, "pan.___", state 245, "(1)" + line 151, "pan.___", state 257, "(1)" + line 158, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 297, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 923, "(1)" + line 298, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 298, "pan.___", state 924, "else" + line 298, "pan.___", state 927, "(1)" + line 298, "pan.___", state 928, "(1)" + line 298, "pan.___", state 928, "(1)" + line 302, "pan.___", state 936, "(1)" + line 302, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 302, "pan.___", state 937, "else" + line 302, "pan.___", state 940, "(1)" + line 302, "pan.___", state 941, "(1)" + line 302, "pan.___", state 941, "(1)" + line 300, "pan.___", state 946, "((i<1))" + line 300, "pan.___", state 946, "((i>=1))" + line 307, "pan.___", state 953, "(1)" + line 307, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 307, "pan.___", state 954, "else" + line 307, "pan.___", state 957, "(1)" + line 307, "pan.___", state 958, "(1)" + line 307, "pan.___", state 958, "(1)" + line 309, "pan.___", state 961, "(1)" + line 309, "pan.___", state 961, "(1)" + line 292, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1008, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1034, "(1)" + line 307, "pan.___", state 1051, "(1)" + line 292, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1096, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1122, "(1)" + line 307, "pan.___", state 1139, "(1)" + line 288, "pan.___", state 1156, "(1)" + line 292, "pan.___", state 1168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1186, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1212, "(1)" + line 307, "pan.___", state 1229, "(1)" + line 292, "pan.___", state 1259, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 297, "pan.___", state 1277, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 302, "pan.___", state 1303, "(1)" + line 307, "pan.___", state 1320, "(1)" + line 162, "pan.___", state 1342, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 166, "pan.___", state 1355, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 1365, "(1)" + line 147, "pan.___", state 1373, "(1)" + line 151, "pan.___", state 1385, "(1)" + line 158, "pan.___", state 1396, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 297, "pan.___", state 1571, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1584, "(1)" + line 298, "pan.___", state 1585, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 298, "pan.___", state 1585, "else" + line 298, "pan.___", state 1588, "(1)" + line 298, "pan.___", state 1589, "(1)" + line 298, "pan.___", state 1589, "(1)" + line 302, "pan.___", state 1597, "(1)" + line 302, "pan.___", state 1598, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 302, "pan.___", state 1598, "else" + line 302, "pan.___", state 1601, "(1)" + line 302, "pan.___", state 1602, "(1)" + line 302, "pan.___", state 1602, "(1)" + line 300, "pan.___", state 1607, "((i<1))" + line 300, "pan.___", state 1607, "((i>=1))" + line 307, "pan.___", state 1614, "(1)" + line 307, "pan.___", state 1615, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 307, "pan.___", state 1615, "else" + line 307, "pan.___", state 1618, "(1)" + line 307, "pan.___", state 1619, "(1)" + line 307, "pan.___", state 1619, "(1)" + line 309, "pan.___", state 1622, "(1)" + line 309, "pan.___", state 1622, "(1)" + line 162, "pan.___", state 1646, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 166, "pan.___", state 1659, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 143, "pan.___", state 1669, "(1)" + line 147, "pan.___", state 1677, "(1)" + line 151, "pan.___", state 1689, "(1)" + line 158, "pan.___", state 1700, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail new file mode 100644 index 0000000..2cefe6b --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail @@ -0,0 +1,7 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:0:2679 +5:3:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.define new file mode 100644 index 0000000..136ef67 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.define @@ -0,0 +1,2 @@ +#define NO_RMB +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.log new file mode 100644 index 0000000..c722840 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.log @@ -0,0 +1,16 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_mb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +spin: line 291 "pan.___", Error: syntax error saw 'operator: =' +spin: line 291 "pan.___", Error: syntax error saw 'operator: =' +spin: 2 error(s) - aborting +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input new file mode 100644 index 0000000..1346c4e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input @@ -0,0 +1,533 @@ +#define NO_RMB +#define NO_WMB + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail new file mode 100644 index 0000000..3d2a95e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail @@ -0,0 +1,2082 @@ +-2:3:-2 +-4:-4:-4 +1:0:3537 +2:3:3489 +3:3:3492 +4:3:3492 +5:3:3495 +6:3:3503 +7:3:3503 +8:3:3506 +9:3:3512 +10:3:3516 +11:3:3516 +12:3:3519 +13:3:3527 +14:3:3531 +15:3:3532 +16:0:3537 +17:3:3534 +18:0:3537 +19:2:1310 +20:0:3537 +21:2:1316 +22:0:3537 +23:2:1317 +24:0:3537 +25:2:1318 +26:2:1322 +27:2:1323 +28:2:1331 +29:2:1332 +30:2:1336 +31:2:1337 +32:2:1345 +33:2:1350 +34:2:1354 +35:2:1355 +36:2:1362 +37:2:1363 +38:2:1374 +39:2:1375 +40:2:1376 +41:2:1387 +42:2:1392 +43:2:1393 +44:0:3537 +45:2:1405 +46:2:1406 +47:0:3537 +48:2:1410 +49:2:1414 +50:2:1415 +51:2:1423 +52:2:1424 +53:2:1428 +54:2:1429 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+2065:1:704 +2066:1:705 +2067:1:716 +2068:1:717 +2069:1:718 +2070:1:729 +2071:1:734 +2072:1:735 +2073:0:3537 +2074:2:3483 +2075:0:3537 +2076:1:747 +2077:0:3535 +2078:2:3484 +2079:0:3541 +2080:1:1280 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.define new file mode 100644 index 0000000..73e61a4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.define @@ -0,0 +1 @@ +#define NO_RMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.log new file mode 100644 index 0000000..6a46f80 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.log @@ -0,0 +1,369 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_rmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 567) +Depth= 5645 States= 1e+06 Transitions= 1.47e+07 Memory= 527.287 t= 27.1 R= 4e+04 +pan: claim violated! (at depth 1736) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 5645, errors: 1 + 1039881 states, stored + 14441478 states, matched + 15481359 transitions (= stored+matched) + 57000435 atomic steps +hash conflicts: 2892596 (resolved) + +Stats on memory usage (in Megabytes): + 83.303 equivalent memory usage for states (stored*(State-vector + overhead)) + 64.050 actual memory usage for states (compression: 76.89%) + state-vector as stored = 37 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 529.729 total actual memory usage + +unreached in proctype urcu_reader + line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 61, "(1)" + line 308, "pan.___", state 91, "(1)" + line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 149, "(1)" + line 308, "pan.___", state 179, "(1)" + line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 238, "(1)" + line 308, "pan.___", state 268, "(1)" + line 159, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 291, "(1)" + line 163, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 300, "(1)" + line 163, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 301, "else" + line 161, "pan.___", state 306, "((j<1))" + line 161, "pan.___", state 306, "((j>=1))" + line 167, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 313, "(1)" + line 167, "pan.___", state 314, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))" + line 167, "pan.___", state 314, "else" + line 177, "pan.___", state 319, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 177, "pan.___", state 319, "else" + line 159, "pan.___", state 324, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 167, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 159, "pan.___", state 363, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 365, "(1)" + line 163, "pan.___", state 372, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 374, "(1)" + line 163, "pan.___", state 375, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 375, "else" + line 161, "pan.___", state 380, "((j<1))" + line 161, "pan.___", state 380, "((j>=1))" + line 167, "pan.___", state 385, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 387, "(1)" + line 167, "pan.___", state 388, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))" + line 167, "pan.___", state 388, "else" + line 177, "pan.___", state 393, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 177, "pan.___", state 393, "else" + line 289, "pan.___", state 408, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 440, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 453, "(1)" + line 308, "pan.___", state 483, "(1)" + line 289, "pan.___", state 496, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 541, "(1)" + line 308, "pan.___", state 571, "(1)" + line 289, "pan.___", state 584, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 629, "(1)" + line 308, "pan.___", state 659, "(1)" + line 159, "pan.___", state 674, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 676, "(1)" + line 163, "pan.___", state 683, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 685, "(1)" + line 163, "pan.___", state 686, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 686, "else" + line 161, "pan.___", state 691, "((j<1))" + line 161, "pan.___", state 691, "((j>=1))" + line 167, "pan.___", state 696, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 698, "(1)" + line 167, "pan.___", state 699, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))" + line 167, "pan.___", state 699, "else" + line 177, "pan.___", state 704, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 177, "pan.___", state 704, "else" + line 159, "pan.___", state 709, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 167, "pan.___", state 731, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 159, "pan.___", state 748, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 750, "(1)" + line 163, "pan.___", state 757, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 759, "(1)" + line 163, "pan.___", state 760, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 760, "else" + line 161, "pan.___", state 765, "((j<1))" + line 161, "pan.___", state 765, "((j>=1))" + line 167, "pan.___", state 770, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 772, "(1)" + line 167, "pan.___", state 773, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))" + line 167, "pan.___", state 773, "else" + line 177, "pan.___", state 778, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 177, "pan.___", state 778, "else" + line 289, "pan.___", state 788, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 820, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 833, "(1)" + line 308, "pan.___", state 863, "(1)" + line 289, "pan.___", state 884, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 916, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 929, "(1)" + line 308, "pan.___", state 959, "(1)" + line 434, "pan.___", state 972, "-end-" + (95 of 972 states) +unreached in proctype urcu_writer + line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 20, "(1)" + line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 34, "(1)" + line 293, "pan.___", state 35, "(1)" + line 293, "pan.___", state 35, "(1)" + line 291, "pan.___", state 40, "((i<1))" + line 291, "pan.___", state 40, "((i>=1))" + line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 59, "(1)" + line 299, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 60, "else" + line 299, "pan.___", state 63, "(1)" + line 299, "pan.___", state 64, "(1)" + line 299, "pan.___", state 64, "(1)" + line 303, "pan.___", state 72, "(1)" + line 303, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 73, "else" + line 303, "pan.___", state 76, "(1)" + line 303, "pan.___", state 77, "(1)" + line 303, "pan.___", state 77, "(1)" + line 301, "pan.___", state 82, "((i<1))" + line 301, "pan.___", state 82, "((i>=1))" + line 308, "pan.___", state 89, "(1)" + line 308, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 90, "else" + line 308, "pan.___", state 93, "(1)" + line 308, "pan.___", state 94, "(1)" + line 308, "pan.___", state 94, "(1)" + line 310, "pan.___", state 97, "(1)" + line 310, "pan.___", state 97, "(1)" + line 456, "pan.___", state 101, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 454, "pan.___", state 102, "old_gen = cached_generation_ptr.val[_pid]" + line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 112, "(1)" + line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 126, "(1)" + line 293, "pan.___", state 127, "(1)" + line 293, "pan.___", state 127, "(1)" + line 299, "pan.___", state 151, "(1)" + line 303, "pan.___", state 164, "(1)" + line 310, "pan.___", state 189, "(1)" + line 310, "pan.___", state 189, "(1)" + line 468, "pan.___", state 195, "(1)" + line 159, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 240, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 298, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 755, "(1)" + line 299, "pan.___", state 756, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 756, "else" + line 299, "pan.___", state 759, "(1)" + line 299, "pan.___", state 760, "(1)" + line 299, "pan.___", state 760, "(1)" + line 303, "pan.___", state 768, "(1)" + line 303, "pan.___", state 769, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 769, "else" + line 303, "pan.___", state 772, "(1)" + line 303, "pan.___", state 773, "(1)" + line 303, "pan.___", state 773, "(1)" + line 301, "pan.___", state 778, "((i<1))" + line 301, "pan.___", state 778, "((i>=1))" + line 308, "pan.___", state 785, "(1)" + line 308, "pan.___", state 786, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 786, "else" + line 308, "pan.___", state 789, "(1)" + line 308, "pan.___", state 790, "(1)" + line 308, "pan.___", state 790, "(1)" + line 310, "pan.___", state 793, "(1)" + line 310, "pan.___", state 793, "(1)" + line 293, "pan.___", state 822, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 840, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 866, "(1)" + line 308, "pan.___", state 883, "(1)" + line 293, "pan.___", state 910, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 928, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 954, "(1)" + line 308, "pan.___", state 971, "(1)" + line 289, "pan.___", state 988, "(1)" + line 293, "pan.___", state 1000, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1018, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 1044, "(1)" + line 308, "pan.___", state 1061, "(1)" + line 293, "pan.___", state 1091, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1109, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 1135, "(1)" + line 308, "pan.___", state 1152, "(1)" + line 163, "pan.___", state 1174, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 1187, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 1200, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 298, "pan.___", state 1319, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 1332, "(1)" + line 299, "pan.___", state 1333, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 1333, "else" + line 299, "pan.___", state 1336, "(1)" + line 299, "pan.___", state 1337, "(1)" + line 299, "pan.___", state 1337, "(1)" + line 303, "pan.___", state 1345, "(1)" + line 303, "pan.___", state 1346, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 1346, "else" + line 303, "pan.___", state 1349, "(1)" + line 303, "pan.___", state 1350, "(1)" + line 303, "pan.___", state 1350, "(1)" + line 301, "pan.___", state 1355, "((i<1))" + line 301, "pan.___", state 1355, "((i>=1))" + line 308, "pan.___", state 1362, "(1)" + line 308, "pan.___", state 1363, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 1363, "else" + line 308, "pan.___", state 1366, "(1)" + line 308, "pan.___", state 1367, "(1)" + line 308, "pan.___", state 1367, "(1)" + line 310, "pan.___", state 1370, "(1)" + line 310, "pan.___", state 1370, "(1)" + line 163, "pan.___", state 1394, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 1407, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 1420, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=2))" + line 519, "pan.___", state 20, "((j<2))" + line 519, "pan.___", state 20, "((j>=2))" + line 524, "pan.___", state 33, "((j<2))" + line 524, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 572, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 28.5 seconds +pan: rate 36487.053 states/second +pan: avg transition delay 1.8409e-06 usec +cp .input.spin urcu_free_no_rmb.spin.input +cp .input.spin.trail urcu_free_no_rmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input new file mode 100644 index 0000000..899fdb4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input @@ -0,0 +1,532 @@ +#define NO_RMB + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git 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b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.define @@ -0,0 +1 @@ +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.log new file mode 100644 index 0000000..477c85d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.log @@ -0,0 +1,381 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_wmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 567) +pan: claim violated! (at depth 1889) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 6646, errors: 1 + 377244 states, stored + 5291719 states, matched + 5668963 transitions (= stored+matched) + 20822372 atomic steps +hash conflicts: 405371 (resolved) + +Stats on memory usage (in Megabytes): + 30.221 equivalent memory usage for states (stored*(State-vector + overhead)) + 23.526 actual memory usage for states (compression: 77.85%) + state-vector as stored = 37 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 489.201 total actual memory usage + +unreached in proctype urcu_reader + line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 61, "(1)" + line 308, "pan.___", state 91, "(1)" + line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 149, "(1)" + line 308, "pan.___", state 179, "(1)" + line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 238, "(1)" + line 308, "pan.___", state 268, "(1)" + line 144, "pan.___", state 290, "(1)" + line 148, "pan.___", state 298, "(1)" + line 148, "pan.___", state 299, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 299, "else" + line 146, "pan.___", state 304, "((j<1))" + line 146, "pan.___", state 304, "((j>=1))" + line 152, "pan.___", state 310, "(1)" + line 152, "pan.___", state 311, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 311, "else" + line 186, "pan.___", state 316, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 186, "pan.___", state 316, "else" + line 144, "pan.___", state 322, "(1)" + line 148, "pan.___", state 330, "(1)" + line 148, "pan.___", state 331, "(!((cache_dirty_urcu_active_readers.bitfield&(1<=1))" + line 152, "pan.___", state 342, "(1)" + line 152, "pan.___", state 343, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 144, "pan.___", state 358, "(1)" + line 148, "pan.___", state 366, "(1)" + line 148, "pan.___", state 367, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 367, "else" + line 146, "pan.___", state 372, "((j<1))" + line 146, "pan.___", state 372, "((j>=1))" + line 152, "pan.___", state 378, "(1)" + line 152, "pan.___", state 379, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 379, "else" + line 186, "pan.___", state 384, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 186, "pan.___", state 384, "else" + line 289, "pan.___", state 399, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 415, "(1)" + line 298, "pan.___", state 431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 444, "(1)" + line 308, "pan.___", state 474, "(1)" + line 289, "pan.___", state 487, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 519, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 532, "(1)" + line 308, "pan.___", state 562, "(1)" + line 289, "pan.___", state 575, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 607, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 620, "(1)" + line 308, "pan.___", state 650, "(1)" + line 144, "pan.___", state 666, "(1)" + line 148, "pan.___", state 674, "(1)" + line 148, "pan.___", state 675, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 675, "else" + line 146, "pan.___", state 680, "((j<1))" + line 146, "pan.___", state 680, "((j>=1))" + line 152, "pan.___", state 686, "(1)" + line 152, "pan.___", state 687, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 687, "else" + line 186, "pan.___", state 692, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 186, "pan.___", state 692, "else" + line 144, "pan.___", state 698, "(1)" + line 148, "pan.___", state 706, "(1)" + line 148, "pan.___", state 707, "(!((cache_dirty_urcu_active_readers.bitfield&(1<=1))" + line 152, "pan.___", state 718, "(1)" + line 152, "pan.___", state 719, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 144, "pan.___", state 734, "(1)" + line 148, "pan.___", state 742, "(1)" + line 148, "pan.___", state 743, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 743, "else" + line 146, "pan.___", state 748, "((j<1))" + line 146, "pan.___", state 748, "((j>=1))" + line 152, "pan.___", state 754, "(1)" + line 152, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 755, "else" + line 186, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 186, "pan.___", state 760, "else" + line 289, "pan.___", state 770, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 802, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 815, "(1)" + line 308, "pan.___", state 845, "(1)" + line 289, "pan.___", state 866, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 882, "(1)" + line 298, "pan.___", state 898, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 911, "(1)" + line 308, "pan.___", state 941, "(1)" + line 434, "pan.___", state 954, "-end-" + (79 of 954 states) +unreached in proctype urcu_writer + line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 20, "(1)" + line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 34, "(1)" + line 293, "pan.___", state 35, "(1)" + line 293, "pan.___", state 35, "(1)" + line 291, "pan.___", state 40, "((i<1))" + line 291, "pan.___", state 40, "((i>=1))" + line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 59, "(1)" + line 299, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 60, "else" + line 299, "pan.___", state 63, "(1)" + line 299, "pan.___", state 64, "(1)" + line 299, "pan.___", state 64, "(1)" + line 303, "pan.___", state 72, "(1)" + line 303, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 73, "else" + line 303, "pan.___", state 76, "(1)" + line 303, "pan.___", state 77, "(1)" + line 303, "pan.___", state 77, "(1)" + line 301, "pan.___", state 82, "((i<1))" + line 301, "pan.___", state 82, "((i>=1))" + line 308, "pan.___", state 89, "(1)" + line 308, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 90, "else" + line 308, "pan.___", state 93, "(1)" + line 308, "pan.___", state 94, "(1)" + line 308, "pan.___", state 94, "(1)" + line 310, "pan.___", state 97, "(1)" + line 310, "pan.___", state 97, "(1)" + line 456, "pan.___", state 101, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 454, "pan.___", state 102, "old_gen = cached_generation_ptr.val[_pid]" + line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 112, "(1)" + line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 126, "(1)" + line 293, "pan.___", state 127, "(1)" + line 293, "pan.___", state 127, "(1)" + line 291, "pan.___", state 132, "((i<1))" + line 291, "pan.___", state 132, "((i>=1))" + line 299, "pan.___", state 151, "(1)" + line 299, "pan.___", state 152, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 152, "else" + line 299, "pan.___", state 155, "(1)" + line 299, "pan.___", state 156, "(1)" + line 299, "pan.___", state 156, "(1)" + line 303, "pan.___", state 164, "(1)" + line 303, "pan.___", state 165, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 165, "else" + line 303, "pan.___", state 168, "(1)" + line 303, "pan.___", state 169, "(1)" + line 303, "pan.___", state 169, "(1)" + line 301, "pan.___", state 174, "((i<1))" + line 301, "pan.___", state 174, "((i>=1))" + line 308, "pan.___", state 181, "(1)" + line 308, "pan.___", state 182, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 182, "else" + line 308, "pan.___", state 185, "(1)" + line 308, "pan.___", state 186, "(1)" + line 308, "pan.___", state 186, "(1)" + line 310, "pan.___", state 189, "(1)" + line 310, "pan.___", state 189, "(1)" + line 468, "pan.___", state 195, "(1)" + line 462, "pan.___", state 198, "((write_lock==0))" + line 462, "pan.___", state 198, "else" + line 460, "pan.___", state 199, "(1)" + line 144, "pan.___", state 206, "(1)" + line 148, "pan.___", state 214, "(1)" + line 148, "pan.___", state 215, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 215, "else" + line 146, "pan.___", state 220, "((j<1))" + line 146, "pan.___", state 220, "((j>=1))" + line 152, "pan.___", state 226, "(1)" + line 152, "pan.___", state 227, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 227, "else" + line 186, "pan.___", state 232, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 186, "pan.___", state 232, "else" + line 144, "pan.___", state 238, "(1)" + line 152, "pan.___", state 258, "(1)" + line 144, "pan.___", state 274, "(1)" + line 148, "pan.___", state 282, "(1)" + line 152, "pan.___", state 294, "(1)" + line 289, "pan.___", state 310, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 324, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 342, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 355, "(1)" + line 303, "pan.___", state 368, "(1)" + line 308, "pan.___", state 385, "(1)" + line 289, "pan.___", state 402, "(1)" + line 293, "pan.___", state 414, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 432, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 458, "(1)" + line 308, "pan.___", state 475, "(1)" + line 293, "pan.___", state 505, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 523, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 549, "(1)" + line 308, "pan.___", state 566, "(1)" + line 148, "pan.___", state 588, "(1)" + line 152, "pan.___", state 600, "(1)" + line 144, "pan.___", state 612, "(1)" + line 152, "pan.___", state 632, "(1)" + line 148, "pan.___", state 656, "(1)" + line 152, "pan.___", state 668, "(1)" + line 289, "pan.___", state 692, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 694, "(1)" + line 289, "pan.___", state 695, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 289, "pan.___", state 695, "else" + line 289, "pan.___", state 698, "(1)" + line 293, "pan.___", state 706, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 708, "(1)" + line 293, "pan.___", state 709, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 293, "pan.___", state 709, "else" + line 293, "pan.___", state 712, "(1)" + line 293, "pan.___", state 713, "(1)" + line 293, "pan.___", state 713, "(1)" + line 291, "pan.___", state 718, "((i<1))" + line 291, "pan.___", state 718, "((i>=1))" + line 298, "pan.___", state 724, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 737, "(1)" + line 299, "pan.___", state 738, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 738, "else" + line 299, "pan.___", state 741, "(1)" + line 299, "pan.___", state 742, "(1)" + line 299, "pan.___", state 742, "(1)" + line 303, "pan.___", state 750, "(1)" + line 303, "pan.___", state 751, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 751, "else" + line 303, "pan.___", state 754, "(1)" + line 303, "pan.___", state 755, "(1)" + line 303, "pan.___", state 755, "(1)" + line 301, "pan.___", state 760, "((i<1))" + line 301, "pan.___", state 760, "((i>=1))" + line 308, "pan.___", state 767, "(1)" + line 308, "pan.___", state 768, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 768, "else" + line 308, "pan.___", state 771, "(1)" + line 308, "pan.___", state 772, "(1)" + line 308, "pan.___", state 772, "(1)" + line 310, "pan.___", state 775, "(1)" + line 310, "pan.___", state 775, "(1)" + line 293, "pan.___", state 804, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 822, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 848, "(1)" + line 308, "pan.___", state 865, "(1)" + line 293, "pan.___", state 892, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 936, "(1)" + line 308, "pan.___", state 953, "(1)" + line 289, "pan.___", state 970, "(1)" + line 293, "pan.___", state 982, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1000, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 1026, "(1)" + line 308, "pan.___", state 1043, "(1)" + line 293, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 303, "pan.___", state 1117, "(1)" + line 308, "pan.___", state 1134, "(1)" + line 148, "pan.___", state 1156, "(1)" + line 152, "pan.___", state 1168, "(1)" + line 144, "pan.___", state 1180, "(1)" + line 152, "pan.___", state 1200, "(1)" + line 148, "pan.___", state 1224, "(1)" + line 152, "pan.___", state 1236, "(1)" + line 289, "pan.___", state 1260, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 289, "pan.___", state 1262, "(1)" + line 289, "pan.___", state 1263, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 289, "pan.___", state 1263, "else" + line 289, "pan.___", state 1266, "(1)" + line 293, "pan.___", state 1274, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 1276, "(1)" + line 293, "pan.___", state 1277, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 293, "pan.___", state 1277, "else" + line 293, "pan.___", state 1280, "(1)" + line 293, "pan.___", state 1281, "(1)" + line 293, "pan.___", state 1281, "(1)" + line 291, "pan.___", state 1286, "((i<1))" + line 291, "pan.___", state 1286, "((i>=1))" + line 298, "pan.___", state 1292, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 1305, "(1)" + line 299, "pan.___", state 1306, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 1306, "else" + line 299, "pan.___", state 1309, "(1)" + line 299, "pan.___", state 1310, "(1)" + line 299, "pan.___", state 1310, "(1)" + line 303, "pan.___", state 1318, "(1)" + line 303, "pan.___", state 1319, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 1319, "else" + line 303, "pan.___", state 1322, "(1)" + line 303, "pan.___", state 1323, "(1)" + line 303, "pan.___", state 1323, "(1)" + line 301, "pan.___", state 1328, "((i<1))" + line 301, "pan.___", state 1328, "((i>=1))" + line 308, "pan.___", state 1335, "(1)" + line 308, "pan.___", state 1336, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 1336, "else" + line 308, "pan.___", state 1339, "(1)" + line 308, "pan.___", state 1340, "(1)" + line 308, "pan.___", state 1340, "(1)" + line 310, "pan.___", state 1343, "(1)" + line 310, "pan.___", state 1343, "(1)" + line 148, "pan.___", state 1367, "(1)" + line 152, "pan.___", state 1379, "(1)" + line 144, "pan.___", state 1391, "(1)" + line 152, "pan.___", state 1411, "(1)" + line 148, "pan.___", state 1435, "(1)" + line 152, "pan.___", state 1447, "(1)" + line 511, "pan.___", state 1473, "-end-" + (159 of 1473 states) +unreached in proctype :init: + line 518, "pan.___", state 9, "((j<2))" + line 518, "pan.___", state 9, "((j>=2))" + line 519, "pan.___", state 20, "((j<2))" + line 519, "pan.___", state 20, "((j>=2))" + line 524, "pan.___", state 33, "((j<2))" + line 524, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 572, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 10.4 seconds +pan: rate 36378.399 states/second +pan: avg transition delay 1.8293e-06 usec +cp .input.spin urcu_free_no_wmb.spin.input +cp .input.spin.trail urcu_free_no_wmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input new file mode 100644 index 0000000..12cde50 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input @@ -0,0 +1,532 @@ +#define NO_WMB + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail new file mode 100644 index 0000000..ec82525 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail @@ -0,0 +1,1892 @@ +-2:3:-2 +-4:-4:-4 +1:0:2475 +2:3:2427 +3:3:2430 +4:3:2430 +5:3:2433 +6:3:2441 +7:3:2441 +8:3:2444 +9:3:2450 +10:3:2454 +11:3:2454 +12:3:2457 +13:3:2465 +14:3:2469 +15:3:2470 +16:0:2475 +17:3:2472 +18:0:2475 +19:2:956 +20:0:2475 +21:2:962 +22:0:2475 +23:2:963 +24:0:2475 +25:2:964 +26:2:968 +27:2:969 +28:2:977 +29:2:978 +30:2:982 +31:2:983 +32:2:991 +33:2:996 +34:2:1000 +35:2:1001 +36:2:1008 +37:2:1009 +38:2:1020 +39:2:1021 +40:2:1022 +41:2:1033 +42:2:1038 +43:2:1039 +44:0:2475 +45:2:1051 +46:2:1052 +47:0:2475 +48:2:1056 +49:2:1060 +50:2:1061 +51:2:1069 +52:2:1070 +53:2:1074 +54:2:1075 +55:2:1083 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+1856:0:2475 +1857:2:2412 +1858:0:2475 +1859:2:2413 +1860:0:2475 +1861:2:2416 +1862:0:2475 +1863:2:2421 +1864:0:2475 +1865:1:483 +1866:1:487 +1867:1:488 +1868:1:496 +1869:1:497 +1870:1:498 +1871:1:510 +1872:1:515 +1873:1:519 +1874:1:520 +1875:1:527 +1876:1:528 +1877:1:539 +1878:1:540 +1879:1:541 +1880:1:552 +1881:1:557 +1882:1:558 +1883:0:2475 +1884:2:2422 +1885:0:2475 +1886:1:570 +1887:0:2473 +1888:2:2421 +1889:0:2479 +1890:1:151 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.define new file mode 100644 index 0000000..5e642ef --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.define @@ -0,0 +1 @@ +#define SINGLE_FLIP diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.log new file mode 100644 index 0000000..6a9d040 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.log @@ -0,0 +1,349 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_single_flip.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 567) +pan: claim violated! (at depth 1353) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 3705, errors: 1 + 216253 states, stored + 2924019 states, matched + 3140272 transitions (= stored+matched) + 11791015 atomic steps +hash conflicts: 155585 (resolved) + +Stats on memory usage (in Megabytes): + 17.324 equivalent memory usage for states (stored*(State-vector + overhead)) + 13.576 actual memory usage for states (compression: 78.37%) + state-vector as stored = 38 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 479.338 total actual memory usage + +unreached in proctype urcu_reader + line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 61, "(1)" + line 308, "pan.___", state 91, "(1)" + line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 149, "(1)" + line 308, "pan.___", state 179, "(1)" + line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 238, "(1)" + line 308, "pan.___", state 268, "(1)" + line 159, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 291, "(1)" + line 163, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 300, "(1)" + line 163, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 301, "else" + line 161, "pan.___", state 306, "((j<1))" + line 161, "pan.___", state 306, "((j>=1))" + line 167, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 321, "(1)" + line 148, "pan.___", state 329, "(1)" + line 148, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 330, "else" + line 146, "pan.___", state 335, "((j<1))" + line 146, "pan.___", state 335, "((j>=1))" + line 152, "pan.___", state 341, "(1)" + line 152, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 342, "else" + line 154, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 154, "pan.___", state 345, "else" + line 186, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 186, "pan.___", state 347, "else" + line 159, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 167, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 152, "pan.___", state 404, "(1)" + line 152, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 159, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 421, "(1)" + line 163, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 430, "(1)" + line 163, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 431, "else" + line 161, "pan.___", state 436, "((j<1))" + line 161, "pan.___", state 436, "((j>=1))" + line 167, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 451, "(1)" + line 148, "pan.___", state 459, "(1)" + line 148, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 460, "else" + line 146, "pan.___", state 465, "((j<1))" + line 146, "pan.___", state 465, "((j>=1))" + line 152, "pan.___", state 471, "(1)" + line 152, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 472, "else" + line 154, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 154, "pan.___", state 475, "else" + line 186, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 186, "pan.___", state 477, "else" + line 289, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 537, "(1)" + line 308, "pan.___", state 567, "(1)" + line 289, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 625, "(1)" + line 308, "pan.___", state 655, "(1)" + line 289, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 713, "(1)" + line 308, "pan.___", state 743, "(1)" + line 159, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 760, "(1)" + line 163, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 769, "(1)" + line 163, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 770, "else" + line 161, "pan.___", state 775, "((j<1))" + line 161, "pan.___", state 775, "((j>=1))" + line 167, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 790, "(1)" + line 148, "pan.___", state 798, "(1)" + line 148, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 799, "else" + line 146, "pan.___", state 804, "((j<1))" + line 146, "pan.___", state 804, "((j>=1))" + line 152, "pan.___", state 810, "(1)" + line 152, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 811, "else" + line 154, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 154, "pan.___", state 814, "else" + line 186, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 186, "pan.___", state 816, "else" + line 159, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 167, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 152, "pan.___", state 873, "(1)" + line 152, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 159, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 890, "(1)" + line 163, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 899, "(1)" + line 163, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 163, "pan.___", state 900, "else" + line 161, "pan.___", state 905, "((j<1))" + line 161, "pan.___", state 905, "((j>=1))" + line 167, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 920, "(1)" + line 148, "pan.___", state 928, "(1)" + line 148, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 148, "pan.___", state 929, "else" + line 146, "pan.___", state 934, "((j<1))" + line 146, "pan.___", state 934, "((j>=1))" + line 152, "pan.___", state 940, "(1)" + line 152, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 152, "pan.___", state 941, "else" + line 154, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 154, "pan.___", state 944, "else" + line 186, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 186, "pan.___", state 946, "else" + line 289, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 1001, "(1)" + line 308, "pan.___", state 1031, "(1)" + line 289, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 1097, "(1)" + line 308, "pan.___", state 1127, "(1)" + line 434, "pan.___", state 1140, "-end-" + (125 of 1140 states) +unreached in proctype urcu_writer + line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 59, "(1)" + line 303, "pan.___", state 72, "(1)" + line 308, "pan.___", state 89, "(1)" + line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 151, "(1)" + line 303, "pan.___", state 164, "(1)" + line 468, "pan.___", state 195, "(1)" + line 159, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 163, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 237, "(1)" + line 148, "pan.___", state 245, "(1)" + line 152, "pan.___", state 257, "(1)" + line 159, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 298, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 299, "pan.___", state 923, "(1)" + line 299, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 299, "pan.___", state 924, "else" + line 299, "pan.___", state 927, "(1)" + line 299, "pan.___", state 928, "(1)" + line 299, "pan.___", state 928, "(1)" + line 303, "pan.___", state 936, "(1)" + line 303, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 303, "pan.___", state 937, "else" + line 303, "pan.___", state 940, "(1)" + line 303, "pan.___", state 941, "(1)" + line 303, "pan.___", state 941, "(1)" + line 301, "pan.___", state 946, "((i<1))" + line 301, "pan.___", state 946, "((i>=1))" + line 308, "pan.___", state 953, "(1)" + line 308, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 308, "pan.___", state 954, "else" + line 308, "pan.___", state 957, "(1)" + line 308, "pan.___", state 958, "(1)" + line 308, "pan.___", state 958, "(1)" + line 310, "pan.___", state 961, "(1)" + line 310, "pan.___", state 961, "(1)" + line 163, "pan.___", state 985, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 167, "pan.___", state 998, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 144, "pan.___", state 1008, "(1)" + line 148, "pan.___", state 1016, "(1)" + line 152, "pan.___", state 1028, "(1)" + line 159, "pan.___", state 1039, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=2))" + line 519, "pan.___", state 20, "((j<2))" + line 519, "pan.___", state 20, "((j>=2))" + line 524, "pan.___", state 33, "((j<2))" + line 524, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 572, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 5.58 seconds +pan: rate 38755.018 states/second +pan: avg transition delay 1.7769e-06 usec +cp .input.spin urcu_free_single_flip.spin.input +cp .input.spin.trail urcu_free_single_flip.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input new file mode 100644 index 0000000..244a7b2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input @@ -0,0 +1,532 @@ +#define SINGLE_FLIP + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + + +#if (NR_READERS == 1) + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#elif (NR_READERS == 2) + +#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen) +#define read_free (free_done && (data_access[0] || data_access[1])) + +#else + +#error "Too many readers" + +#endif + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + atomic { + if + :: get_readerid() == 0 -> +progress_reader: + skip; + :: else -> + skip; + fi; + } +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail new file mode 100644 index 0000000..363553e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail @@ -0,0 +1,1356 @@ +-2:3:-2 +-4:-4:-4 +1:0:2372 +2:3:2324 +3:3:2327 +4:3:2327 +5:3:2330 +6:3:2338 +7:3:2338 +8:3:2341 +9:3:2347 +10:3:2351 +11:3:2351 +12:3:2354 +13:3:2362 +14:3:2366 +15:3:2367 +16:0:2372 +17:3:2369 +18:0:2372 +19:2:1142 +20:0:2372 +21:2:1148 +22:0:2372 +23:2:1149 +24:0:2372 +25:2:1150 +26:2:1154 +27:2:1155 +28:2:1163 +29:2:1164 +30:2:1168 +31:2:1169 +32:2:1177 +33:2:1182 +34:2:1186 +35:2:1187 +36:2:1194 +37:2:1195 +38:2:1206 +39:2:1207 +40:2:1208 +41:2:1219 +42:2:1224 +43:2:1225 +44:0:2372 +45:2:1237 +46:2:1238 +47:0:2372 +48:2:1242 +49:2:1246 +50:2:1247 +51:2:1255 +52:2:1256 +53:2:1260 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0000000..8718641 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress.ltl @@ -0,0 +1 @@ +([] <> !np_) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.define new file mode 100644 index 0000000..ff3f783 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.define @@ -0,0 +1 @@ +#define READER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.log new file mode 100644 index 0000000..ceb438f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.log @@ -0,0 +1,16 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_reader.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +spin: line 296 replacement value: tmp +spin: line 296 "pan.___", Error: formal par of wait_for_quiescent_state contains replacement value saw '-2'' near 'readerid' +spin: 1 error(s) - aborting +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input new file mode 100644 index 0000000..cc55960 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input @@ -0,0 +1,410 @@ +#define READER_PROGRESS +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#define read_free_race (read_generation == last_free_gen) +#define read_free (free_done && data_access) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + if + :: (NR_READERS > 1) && (i < NR_READERS - 1) + -> ooo_mem(j); + :: else + -> skip; + fi; + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + smp_mb(i); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active [NR_WRITERS] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + smp_mb(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail new file mode 100644 index 0000000..e65d663 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail @@ -0,0 +1,9 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:1:2675 +5:1:2676 +6:0:2685 +7:5:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.define new file mode 100644 index 0000000..1e4417f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.define @@ -0,0 +1 @@ +#define WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.log new file mode 100644 index 0000000..985f839 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.log @@ -0,0 +1,14 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input new file mode 100644 index 0000000..28f1299 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input @@ -0,0 +1,410 @@ +#define WRITER_PROGRESS +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#define read_free_race (read_generation == last_free_gen) +#define read_free (free_done && data_access) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + if + :: (NR_READERS > 1) && (i < NR_READERS - 1) + -> ooo_mem(j); + :: else + -> skip; + fi; + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + smp_mb(i); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active [NR_WRITERS] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + smp_mb(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail new file mode 100644 index 0000000..e65d663 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail @@ -0,0 +1,9 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:1:2675 +5:1:2676 +6:0:2685 +7:5:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.define b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.define new file mode 100644 index 0000000..8d304f5 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.define @@ -0,0 +1,2 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.log b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.log new file mode 100644 index 0000000..26b6236 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.log @@ -0,0 +1,16 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer_error.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +spin: line 297 replacement value: tmp +spin: line 297 "pan.___", Error: formal par of wait_for_quiescent_state contains replacement value saw '-2'' near 'readerid' +spin: 1 error(s) - aborting +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input new file mode 100644 index 0000000..43e979c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input @@ -0,0 +1,411 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#define read_free_race (read_generation == last_free_gen) +#define read_free (free_done && data_access) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define get_pid() (_pid) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces + * both. + */ + +#define DECLARE_CACHED_VAR(type, x, v) \ + type mem_##x = v; \ + type cached_##x[NR_PROCS] = v; \ + bit cache_dirty_##x[NR_PROCS] = 0 + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id]) + +#define READ_CACHED_VAR(x) (cached_##x[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x[get_pid()] = v; \ + cache_dirty_##x[get_pid()] = 1; \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x[id]; \ + cache_dirty_##x[id] = 0; \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + CACHE_READ_FROM_MEM(urcu_active_readers_one, i); + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, i); + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i); +#endif +#ifndef NO_RMB + smp_rmb_pid(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid()); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid()); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid()); + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid()); + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i); +#endif +#ifndef NO_RMB + smp_rmb(i); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1); +/* Note ! currently only one reader */ +DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr, 0); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation = 1; +bit data_access = 0; + +bit write_lock = 0; + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one, + get_pid()); + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, id, i) +{ + do + :: 1 -> + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (tmp & RCU_GP_CTR_NEST_MASK) + && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i); +#else + ooo_mem(i); +#endif + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, i, j) +{ + i = 0; + do + :: i < NR_READERS -> + wait_for_reader(tmp, i, j); + if + :: (NR_READERS > 1) && (i < NR_READERS - 1) + -> ooo_mem(j); + :: else + -> skip; + fi; + i++ + :: i >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers_one, + tmp + 1); + fi; + smp_mb(i); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access = 1; + ooo_mem(i); + data_access = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i); + tmp2 = READ_CACHED_VAR(urcu_active_readers_one); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active [NR_READERS] proctype urcu_reader() +{ + byte i, nest_i; + byte tmp, tmp2; + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, nest_i, tmp, tmp2); + od; +} + +/* Model the RCU update process. */ + +active [NR_WRITERS] proctype urcu_writer() +{ + byte i, j; + byte tmp; + byte old_gen; + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + //smp_mc(i); + wait_for_quiescent_state(tmp, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + wait_for_quiescent_state(tmp, i, j); +#endif + smp_mb(i); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + skip; + od; +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input.trail new file mode 100644 index 0000000..ff6f1c5 --- /dev/null +++ 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+4563:2:1931 +4564:2:1932 +4565:2:1949 +4566:2:1950 +4567:2:1953 +4568:2:1954 +4569:0:2227 +4570:2:1821 +4571:0:2227 +4572:2:1822 +4573:0:2227 +4574:1:4 +4575:1:8 +4576:1:9 +4577:1:16 +4578:1:17 +4579:1:28 +4580:1:32 +4581:1:33 +4582:1:40 +4583:1:41 +4584:1:51 +4585:1:52 +4586:1:62 +4587:1:63 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.sh b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.sh new file mode 100644 index 0000000..65ff517 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.sh @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Compiles and runs the urcu.spin Promela model. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) IBM Corporation, 2009 +# Mathieu Desnoyers, 2009 +# +# Authors: Paul E. McKenney +# Mathieu Desnoyers + +# Basic execution, without LTL clauses. See Makefile. + +spin -a urcu.spin +cc -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w21 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.spin b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.spin new file mode 100644 index 0000000..2cfcb70 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu.spin @@ -0,0 +1,705 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.log new file mode 100644 index 0000000..9a22c47 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.log @@ -0,0 +1,345 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 741) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10669, errors: 0 + 20146 states, stored + 191615 states, matched + 211761 transitions (= stored+matched) + 712676 atomic steps +hash conflicts: 1523 (resolved) + +Stats on memory usage (in Megabytes): + 1.614 equivalent memory usage for states (stored*(State-vector + overhead)) + 1.661 actual memory usage for states (unsuccessful compression: 102.92%) + state-vector as stored = 58 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 467.326 total actual memory usage + +unreached in proctype urcu_reader_sig + line 401, "pan.___", state 330, "(1)" + line 612, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 397, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 406, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, "pan.___", state 59, "(1)" + line 416, "pan.___", state 89, "(1)" + line 397, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, "pan.___", state 160, "(1)" + line 650, "pan.___", state 213, "(1)" + line 173, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 177, "pan.___", state 233, "(1)" + line 158, "pan.___", state 254, "(1)" + line 162, "pan.___", state 262, "(1)" + line 166, "pan.___", state 274, "(1)" + line 173, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, "pan.___", state 752, "(1)" + line 162, "pan.___", state 760, "(1)" + line 162, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, "pan.___", state 761, "else" + line 160, "pan.___", state 766, "((j<1))" + line 160, "pan.___", state 766, "((j>=1))" + line 166, "pan.___", state 772, "(1)" + line 166, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, "pan.___", state 773, "else" + line 168, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, "pan.___", state 776, "else" + line 173, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, "pan.___", state 835, "(1)" + line 166, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, "pan.___", state 852, "(1)" + line 177, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, "pan.___", state 861, "(1)" + line 177, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, "pan.___", state 862, "else" + line 175, "pan.___", state 867, "((j<1))" + line 175, "pan.___", state 867, "((j>=1))" + line 181, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, "pan.___", state 882, "(1)" + line 162, "pan.___", state 890, "(1)" + line 162, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, "pan.___", state 891, "else" + line 160, "pan.___", state 896, "((j<1))" + line 160, "pan.___", state 896, "((j>=1))" + line 166, "pan.___", state 902, "(1)" + line 166, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, "pan.___", state 903, "else" + line 168, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, "pan.___", state 906, "else" + line 200, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, "pan.___", state 908, "else" + line 219, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, "pan.___", state 909, "else" + line 354, "pan.___", state 915, "((sighand_exec==1))" + line 354, "pan.___", state 915, "else" + line 360, "pan.___", state 918, "sighand_exec = 1" + line 397, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, "pan.___", state 933, "(1)" + line 397, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, "pan.___", state 934, "else" + line 397, "pan.___", state 937, "(1)" + line 401, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, "pan.___", state 947, "(1)" + line 401, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, "pan.___", state 948, "else" + line 401, "pan.___", state 951, "(1)" + line 401, "pan.___", state 952, "(1)" + line 401, "pan.___", state 952, "(1)" + line 399, "pan.___", state 957, "((i<1))" + line 399, "pan.___", state 957, "((i>=1))" + line 406, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, "pan.___", state 976, "(1)" + line 407, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, "pan.___", state 977, "else" + line 407, "pan.___", state 980, "(1)" + line 407, "pan.___", state 981, "(1)" + line 407, "pan.___", state 981, "(1)" + line 411, "pan.___", state 989, "(1)" + line 411, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, "pan.___", state 990, "else" + line 411, "pan.___", state 993, "(1)" + line 411, "pan.___", state 994, "(1)" + line 411, "pan.___", state 994, "(1)" + line 409, "pan.___", state 999, "((i<1))" + line 409, "pan.___", state 999, "((i>=1))" + line 416, "pan.___", state 1006, "(1)" + line 416, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, "pan.___", state 1007, "else" + line 416, "pan.___", state 1010, "(1)" + line 416, "pan.___", state 1011, "(1)" + line 416, "pan.___", state 1011, "(1)" + line 418, "pan.___", state 1014, "(1)" + line 418, "pan.___", state 1014, "(1)" + line 360, "pan.___", state 1023, "sighand_exec = 1" + line 401, "pan.___", state 1054, "(1)" + line 406, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, "pan.___", state 1113, "(1)" + line 401, "pan.___", state 1151, "(1)" + line 406, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, "pan.___", state 1210, "(1)" + line 397, "pan.___", state 1236, "(1)" + line 401, "pan.___", state 1250, "(1)" + line 406, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, "pan.___", state 1309, "(1)" + line 401, "pan.___", state 1350, "(1)" + line 406, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 416, "pan.___", state 1409, "(1)" + line 173, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, "pan.___", state 1432, "(1)" + line 177, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, "pan.___", state 1441, "(1)" + line 177, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, "pan.___", state 1442, "else" + line 175, "pan.___", state 1447, "((j<1))" + line 175, "pan.___", state 1447, "((j>=1))" + line 181, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, "pan.___", state 1462, "(1)" + line 162, "pan.___", state 1470, "(1)" + line 162, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, "pan.___", state 1471, "else" + line 160, "pan.___", state 1476, "((j<1))" + line 160, "pan.___", state 1476, "((j>=1))" + line 166, "pan.___", state 1482, "(1)" + line 166, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, "pan.___", state 1483, "else" + line 168, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, "pan.___", state 1486, "else" + line 173, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 181, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 166, "pan.___", state 1545, "(1)" + line 166, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 173, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 173, "pan.___", state 1562, "(1)" + line 177, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 177, "pan.___", state 1571, "(1)" + line 177, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 177, "pan.___", state 1572, "else" + line 175, "pan.___", state 1577, "((j<1))" + line 175, "pan.___", state 1577, "((j>=1))" + line 181, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, "pan.___", state 1592, "(1)" + line 162, "pan.___", state 1600, "(1)" + line 162, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 162, "pan.___", state 1601, "else" + line 160, "pan.___", state 1606, "((j<1))" + line 160, "pan.___", state 1606, "((j>=1))" + line 166, "pan.___", state 1612, "(1)" + line 166, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 166, "pan.___", state 1613, "else" + line 168, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 168, "pan.___", state 1616, "else" + line 200, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 200, "pan.___", state 1618, "else" + line 219, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 219, "pan.___", state 1619, "else" + line 354, "pan.___", state 1625, "((sighand_exec==1))" + line 354, "pan.___", state 1625, "else" + line 360, "pan.___", state 1628, "sighand_exec = 1" + line 397, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 397, "pan.___", state 1643, "(1)" + line 397, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 397, "pan.___", state 1644, "else" + line 397, "pan.___", state 1647, "(1)" + line 401, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 401, "pan.___", state 1657, "(1)" + line 401, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 401, "pan.___", state 1658, "else" + line 401, "pan.___", state 1661, "(1)" + line 401, "pan.___", state 1662, "(1)" + line 401, "pan.___", state 1662, "(1)" + line 399, "pan.___", state 1667, "((i<1))" + line 399, "pan.___", state 1667, "((i>=1))" + line 406, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 407, "pan.___", state 1686, "(1)" + line 407, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 407, "pan.___", state 1687, "else" + line 407, "pan.___", state 1690, "(1)" + line 407, "pan.___", state 1691, "(1)" + line 407, "pan.___", state 1691, "(1)" + line 411, "pan.___", state 1699, "(1)" + line 411, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 411, "pan.___", state 1700, "else" + line 411, "pan.___", state 1703, "(1)" + line 411, "pan.___", state 1704, "(1)" + line 411, "pan.___", state 1704, "(1)" + line 409, "pan.___", state 1709, "((i<1))" + line 409, "pan.___", state 1709, "((i>=1))" + line 416, "pan.___", state 1716, "(1)" + line 416, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 416, "pan.___", state 1717, "else" + line 416, "pan.___", state 1720, "(1)" + line 416, "pan.___", state 1721, "(1)" + line 416, "pan.___", state 1721, "(1)" + line 418, "pan.___", state 1724, "(1)" + line 418, "pan.___", state 1724, "(1)" + line 360, "pan.___", state 1733, "sighand_exec = 1" + line 177, "pan.___", state 1758, "(1)" + line 181, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 158, "pan.___", state 1779, "(1)" + line 162, "pan.___", state 1787, "(1)" + line 166, "pan.___", state 1799, "(1)" + line 173, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< !read_free_race) diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input new file mode 100644 index 0000000..953115f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input @@ -0,0 +1,721 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input.trail new file mode 100644 index 0000000..837f3d9 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free.spin.input.trail @@ -0,0 +1,15043 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 +18:4:4344 +19:4:4344 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diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.log new file mode 100644 index 0000000..1bc5996 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.log @@ -0,0 +1,232 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_nested.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 715) +Depth= 22961 States= 1e+06 Transitions= 8.79e+06 Memory= 535.002 t= 17.2 R= 6e+04 +Depth= 22961 States= 2e+06 Transitions= 1.79e+07 Memory= 603.654 t= 34.7 R= 6e+04 +Depth= 25030 States= 3e+06 Transitions= 2.69e+07 Memory= 672.404 t= 52.6 R= 6e+04 +pan: resizing hashtable to -w22.. done +Depth= 25030 States= 4e+06 Transitions= 3.73e+07 Memory= 772.080 t= 74.4 R= 5e+04 +Depth= 25030 States= 5e+06 Transitions= 4.77e+07 Memory= 840.830 t= 96.2 R= 5e+04 +Depth= 25030 States= 6e+06 Transitions= 5.45e+07 Memory= 909.483 t= 110 R= 5e+04 +Depth= 25030 States= 7e+06 Transitions= 6.05e+07 Memory= 978.135 t= 122 R= 6e+04 +Depth= 25030 States= 8e+06 Transitions= 6.68e+07 Memory= 1046.787 t= 135 R= 6e+04 +Depth= 25030 States= 9e+06 Transitions= 7.29e+07 Memory= 1115.537 t= 148 R= 6e+04 +pan: resizing hashtable to -w24.. done +Depth= 25030 States= 1e+07 Transitions= 7.91e+07 Memory= 1308.283 t= 162 R= 6e+04 +Depth= 25030 States= 1.1e+07 Transitions= 8.5e+07 Memory= 1376.936 t= 174 R= 6e+04 +Depth= 25030 States= 1.2e+07 Transitions= 9.12e+07 Memory= 1445.588 t= 186 R= 6e+04 +Depth= 25030 States= 1.3e+07 Transitions= 9.79e+07 Memory= 1514.240 t= 200 R= 7e+04 +Depth= 25030 States= 1.4e+07 Transitions= 1.09e+08 Memory= 1582.990 t= 222 R= 6e+04 +Depth= 25030 States= 1.5e+07 Transitions= 1.18e+08 Memory= 1651.643 t= 240 R= 6e+04 +Depth= 25030 States= 1.6e+07 Transitions= 1.27e+08 Memory= 1720.295 t= 258 R= 6e+04 +Depth= 25030 States= 1.7e+07 Transitions= 1.36e+08 Memory= 1788.947 t= 276 R= 6e+04 +Depth= 25030 States= 1.8e+07 Transitions= 1.44e+08 Memory= 1857.697 t= 292 R= 6e+04 +Depth= 25030 States= 1.9e+07 Transitions= 1.54e+08 Memory= 1926.350 t= 313 R= 6e+04 +Depth= 25030 States= 2e+07 Transitions= 1.64e+08 Memory= 1995.002 t= 333 R= 6e+04 +Depth= 25104 States= 2.1e+07 Transitions= 1.73e+08 Memory= 2063.654 t= 350 R= 6e+04 +Depth= 25104 States= 2.2e+07 Transitions= 1.83e+08 Memory= 2132.404 t= 370 R= 6e+04 +Depth= 25104 States= 2.3e+07 Transitions= 1.89e+08 Memory= 2201.057 t= 384 R= 6e+04 +Depth= 25152 States= 2.4e+07 Transitions= 1.98e+08 Memory= 2269.709 t= 402 R= 6e+04 +Depth= 25152 States= 2.5e+07 Transitions= 2.08e+08 Memory= 2338.361 t= 421 R= 6e+04 +Depth= 25152 States= 2.6e+07 Transitions= 2.15e+08 Memory= 2407.111 t= 436 R= 6e+04 +Depth= 25152 States= 2.7e+07 Transitions= 2.24e+08 Memory= 2475.764 t= 454 R= 6e+04 +Depth= 25152 States= 2.8e+07 Transitions= 2.33e+08 Memory= 2544.416 t= 471 R= 6e+04 +Depth= 25152 States= 2.9e+07 Transitions= 2.42e+08 Memory= 2613.068 t= 490 R= 6e+04 +Depth= 32255 States= 3e+07 Transitions= 2.5e+08 Memory= 2681.818 t= 506 R= 6e+04 +Depth= 33413 States= 3.1e+07 Transitions= 2.61e+08 Memory= 2750.471 t= 530 R= 6e+04 +Depth= 33413 States= 3.2e+07 Transitions= 2.73e+08 Memory= 2819.123 t= 555 R= 6e+04 +Depth= 33413 States= 3.3e+07 Transitions= 2.83e+08 Memory= 2887.873 t= 576 R= 6e+04 +Depth= 33413 States= 3.4e+07 Transitions= 2.94e+08 Memory= 2956.526 t= 598 R= 6e+04 +pan: resizing hashtable to -w26.. done +Depth= 33413 States= 3.5e+07 Transitions= 3.03e+08 Memory= 3521.260 t= 624 R= 6e+04 +Depth= 33413 States= 3.6e+07 Transitions= 3.15e+08 Memory= 3589.912 t= 648 R= 6e+04 +Depth= 33413 States= 3.7e+07 Transitions= 3.25e+08 Memory= 3658.565 t= 667 R= 6e+04 +Depth= 33413 States= 3.8e+07 Transitions= 3.34e+08 Memory= 3727.315 t= 687 R= 6e+04 +Depth= 33413 States= 3.9e+07 Transitions= 3.4e+08 Memory= 3795.967 t= 699 R= 6e+04 +Depth= 33413 States= 4e+07 Transitions= 3.48e+08 Memory= 3864.619 t= 715 R= 6e+04 +Depth= 33413 States= 4.1e+07 Transitions= 3.58e+08 Memory= 3933.272 t= 735 R= 6e+04 +Depth= 33413 States= 4.2e+07 Transitions= 3.64e+08 Memory= 4002.022 t= 747 R= 6e+04 +Depth= 33413 States= 4.3e+07 Transitions= 3.72e+08 Memory= 4070.674 t= 762 R= 6e+04 +Depth= 33413 States= 4.4e+07 Transitions= 3.82e+08 Memory= 4139.326 t= 783 R= 6e+04 +Depth= 33413 States= 4.5e+07 Transitions= 3.89e+08 Memory= 4207.979 t= 799 R= 6e+04 +Depth= 33413 States= 4.6e+07 Transitions= 3.95e+08 Memory= 4276.631 t= 810 R= 6e+04 +Depth= 33413 States= 4.7e+07 Transitions= 4.01e+08 Memory= 4345.381 t= 823 R= 6e+04 +Depth= 33413 States= 4.8e+07 Transitions= 4.07e+08 Memory= 4414.033 t= 835 R= 6e+04 +Depth= 33413 States= 4.9e+07 Transitions= 4.16e+08 Memory= 4482.686 t= 852 R= 6e+04 +Depth= 33413 States= 5e+07 Transitions= 4.25e+08 Memory= 4551.338 t= 871 R= 6e+04 +Depth= 33413 States= 5.1e+07 Transitions= 4.31e+08 Memory= 4620.088 t= 883 R= 6e+04 +Depth= 33413 States= 5.2e+07 Transitions= 4.37e+08 Memory= 4688.740 t= 896 R= 6e+04 +Depth= 33413 States= 5.3e+07 Transitions= 4.43e+08 Memory= 4757.393 t= 907 R= 6e+04 +Depth= 33413 States= 5.4e+07 Transitions= 4.5e+08 Memory= 4826.045 t= 922 R= 6e+04 +Depth= 33413 States= 5.5e+07 Transitions= 4.62e+08 Memory= 4894.795 t= 947 R= 6e+04 +Depth= 33413 States= 5.6e+07 Transitions= 4.71e+08 Memory= 4963.447 t= 966 R= 6e+04 +Depth= 33413 States= 5.7e+07 Transitions= 4.81e+08 Memory= 5032.100 t= 987 R= 6e+04 +Depth= 33413 States= 5.8e+07 Transitions= 4.92e+08 Memory= 5100.752 t= 1.01e+03 R= 6e+04 +Depth= 33413 States= 5.9e+07 Transitions= 5.05e+08 Memory= 5169.502 t= 1.03e+03 R= 6e+04 +Depth= 33413 States= 6e+07 Transitions= 5.18e+08 Memory= 5238.154 t= 1.06e+03 R= 6e+04 +Depth= 33413 States= 6.1e+07 Transitions= 5.27e+08 Memory= 5306.807 t= 1.08e+03 R= 6e+04 +Depth= 33413 States= 6.2e+07 Transitions= 5.37e+08 Memory= 5375.459 t= 1.1e+03 R= 6e+04 +Depth= 33413 States= 6.3e+07 Transitions= 5.47e+08 Memory= 5444.111 t= 1.12e+03 R= 6e+04 +Depth= 33413 States= 6.4e+07 Transitions= 5.54e+08 Memory= 5512.861 t= 1.13e+03 R= 6e+04 +Depth= 33413 States= 6.5e+07 Transitions= 5.6e+08 Memory= 5581.514 t= 1.14e+03 R= 6e+04 +Depth= 33413 States= 6.6e+07 Transitions= 5.66e+08 Memory= 5650.166 t= 1.16e+03 R= 6e+04 +Depth= 33413 States= 6.7e+07 Transitions= 5.73e+08 Memory= 5718.818 t= 1.17e+03 R= 6e+04 +Depth= 33413 States= 6.8e+07 Transitions= 5.82e+08 Memory= 5787.568 t= 1.19e+03 R= 6e+04 +Depth= 33413 States= 6.9e+07 Transitions= 5.9e+08 Memory= 5856.221 t= 1.21e+03 R= 6e+04 +Depth= 33413 States= 7e+07 Transitions= 5.99e+08 Memory= 5924.873 t= 1.22e+03 R= 6e+04 +Depth= 33413 States= 7.1e+07 Transitions= 6.08e+08 Memory= 5993.526 t= 1.24e+03 R= 6e+04 +Depth= 33413 States= 7.2e+07 Transitions= 6.18e+08 Memory= 6062.276 t= 1.26e+03 R= 6e+04 +Depth= 33413 States= 7.3e+07 Transitions= 6.27e+08 Memory= 6130.928 t= 1.28e+03 R= 6e+04 +Depth= 33413 States= 7.4e+07 Transitions= 6.33e+08 Memory= 6199.580 t= 1.29e+03 R= 6e+04 +Depth= 33413 States= 7.5e+07 Transitions= 6.39e+08 Memory= 6268.233 t= 1.31e+03 R= 6e+04 +Depth= 33413 States= 7.6e+07 Transitions= 6.45e+08 Memory= 6336.983 t= 1.32e+03 R= 6e+04 +Depth= 33413 States= 7.7e+07 Transitions= 6.55e+08 Memory= 6405.635 t= 1.34e+03 R= 6e+04 +Depth= 33413 States= 7.8e+07 Transitions= 6.61e+08 Memory= 6474.287 t= 1.35e+03 R= 6e+04 +Depth= 33413 States= 7.9e+07 Transitions= 6.71e+08 Memory= 6542.940 t= 1.37e+03 R= 6e+04 +Depth= 33413 States= 8e+07 Transitions= 6.77e+08 Memory= 6611.592 t= 1.38e+03 R= 6e+04 +Depth= 33413 States= 8.1e+07 Transitions= 6.83e+08 Memory= 6680.342 t= 1.4e+03 R= 6e+04 +Depth= 33413 States= 8.2e+07 Transitions= 6.91e+08 Memory= 6748.994 t= 1.41e+03 R= 6e+04 +Depth= 33413 States= 8.3e+07 Transitions= 6.97e+08 Memory= 6817.647 t= 1.43e+03 R= 6e+04 +Depth= 33413 States= 8.4e+07 Transitions= 7.06e+08 Memory= 6886.299 t= 1.44e+03 R= 6e+04 +Depth= 33413 States= 8.5e+07 Transitions= 7.15e+08 Memory= 6955.049 t= 1.46e+03 R= 6e+04 +Depth= 33413 States= 8.6e+07 Transitions= 7.24e+08 Memory= 7023.701 t= 1.48e+03 R= 6e+04 +Depth= 33413 States= 8.7e+07 Transitions= 7.35e+08 Memory= 7092.354 t= 1.5e+03 R= 6e+04 +Depth= 33413 States= 8.8e+07 Transitions= 7.46e+08 Memory= 7161.006 t= 1.52e+03 R= 6e+04 +Depth= 33413 States= 8.9e+07 Transitions= 7.61e+08 Memory= 7229.756 t= 1.56e+03 R= 6e+04 +Depth= 33413 States= 9e+07 Transitions= 7.83e+08 Memory= 7298.408 t= 1.6e+03 R= 6e+04 +Depth= 33413 States= 9.1e+07 Transitions= 7.97e+08 Memory= 7367.061 t= 1.63e+03 R= 6e+04 +Depth= 33413 States= 9.2e+07 Transitions= 8.12e+08 Memory= 7435.713 t= 1.66e+03 R= 6e+04 +Depth= 33413 States= 9.3e+07 Transitions= 8.24e+08 Memory= 7504.463 t= 1.68e+03 R= 6e+04 +Depth= 33413 States= 9.4e+07 Transitions= 8.32e+08 Memory= 7573.115 t= 1.7e+03 R= 6e+04 +Depth= 33413 States= 9.5e+07 Transitions= 8.46e+08 Memory= 7641.768 t= 1.73e+03 R= 5e+04 +Depth= 33413 States= 9.6e+07 Transitions= 8.57e+08 Memory= 7710.420 t= 1.75e+03 R= 5e+04 +Depth= 33413 States= 9.7e+07 Transitions= 8.71e+08 Memory= 7779.072 t= 1.78e+03 R= 5e+04 +Depth= 33413 States= 9.8e+07 Transitions= 8.84e+08 Memory= 7847.822 t= 1.81e+03 R= 5e+04 +Depth= 33413 States= 9.9e+07 Transitions= 8.97e+08 Memory= 7916.475 t= 1.83e+03 R= 5e+04 +Depth= 33413 States= 1e+08 Transitions= 9.08e+08 Memory= 7985.127 t= 1.85e+03 R= 5e+04 +Depth= 33413 States= 1.01e+08 Transitions= 9.22e+08 Memory= 8053.779 t= 1.88e+03 R= 5e+04 +Depth= 33413 States= 1.02e+08 Transitions= 9.35e+08 Memory= 8122.529 t= 1.91e+03 R= 5e+04 +Depth= 33413 States= 1.03e+08 Transitions= 9.47e+08 Memory= 8191.182 t= 1.93e+03 R= 5e+04 +Depth= 33413 States= 1.04e+08 Transitions= 9.59e+08 Memory= 8259.834 t= 1.96e+03 R= 5e+04 +Depth= 33413 States= 1.05e+08 Transitions= 9.68e+08 Memory= 8328.486 t= 1.97e+03 R= 5e+04 +Depth= 33413 States= 1.06e+08 Transitions= 9.78e+08 Memory= 8397.236 t= 2e+03 R= 5e+04 +Depth= 33413 States= 1.07e+08 Transitions= 9.97e+08 Memory= 8465.889 t= 2.04e+03 R= 5e+04 +Depth= 33413 States= 1.08e+08 Transitions= 1.01e+09 Memory= 8534.541 t= 2.06e+03 R= 5e+04 +Depth= 33413 States= 1.09e+08 Transitions= 1.02e+09 Memory= 8603.193 t= 2.09e+03 R= 5e+04 +Depth= 33413 States= 1.1e+08 Transitions= 1.03e+09 Memory= 8671.846 t= 2.1e+03 R= 5e+04 +Depth= 33413 States= 1.11e+08 Transitions= 1.05e+09 Memory= 8740.596 t= 2.13e+03 R= 5e+04 +Depth= 33413 States= 1.12e+08 Transitions= 1.06e+09 Memory= 8809.248 t= 2.17e+03 R= 5e+04 +Depth= 33413 States= 1.13e+08 Transitions= 1.08e+09 Memory= 8877.901 t= 2.19e+03 R= 5e+04 +Depth= 33413 States= 1.14e+08 Transitions= 1.09e+09 Memory= 8946.553 t= 2.22e+03 R= 5e+04 +Depth= 33413 States= 1.15e+08 Transitions= 1.1e+09 Memory= 9015.303 t= 2.24e+03 R= 5e+04 +Depth= 33413 States= 1.16e+08 Transitions= 1.11e+09 Memory= 9083.955 t= 2.26e+03 R= 5e+04 +Depth= 33413 States= 1.17e+08 Transitions= 1.11e+09 Memory= 9152.608 t= 2.27e+03 R= 5e+04 +Depth= 33413 States= 1.18e+08 Transitions= 1.12e+09 Memory= 9221.260 t= 2.29e+03 R= 5e+04 +Depth= 33413 States= 1.19e+08 Transitions= 1.13e+09 Memory= 9290.010 t= 2.3e+03 R= 5e+04 +Depth= 33413 States= 1.2e+08 Transitions= 1.14e+09 Memory= 9358.662 t= 2.32e+03 R= 5e+04 +Depth= 33413 States= 1.21e+08 Transitions= 1.15e+09 Memory= 9427.315 t= 2.34e+03 R= 5e+04 +Depth= 33413 States= 1.22e+08 Transitions= 1.17e+09 Memory= 9495.967 t= 2.38e+03 R= 5e+04 +Depth= 33413 States= 1.23e+08 Transitions= 1.18e+09 Memory= 9564.717 t= 2.41e+03 R= 5e+04 +Depth= 33413 States= 1.24e+08 Transitions= 1.19e+09 Memory= 9633.369 t= 2.43e+03 R= 5e+04 +Depth= 33413 States= 1.25e+08 Transitions= 1.2e+09 Memory= 9702.022 t= 2.46e+03 R= 5e+04 +Depth= 33413 States= 1.26e+08 Transitions= 1.22e+09 Memory= 9770.674 t= 2.48e+03 R= 5e+04 +Depth= 33413 States= 1.27e+08 Transitions= 1.23e+09 Memory= 9839.326 t= 2.51e+03 R= 5e+04 +Depth= 33413 States= 1.28e+08 Transitions= 1.24e+09 Memory= 9908.076 t= 2.54e+03 R= 5e+04 +Depth= 33413 States= 1.29e+08 Transitions= 1.25e+09 Memory= 9976.729 t= 2.56e+03 R= 5e+04 +Depth= 33413 States= 1.3e+08 Transitions= 1.26e+09 Memory= 10045.381 t= 2.58e+03 R= 5e+04 +Depth= 33413 States= 1.31e+08 Transitions= 1.27e+09 Memory= 10114.033 t= 2.61e+03 R= 5e+04 +Depth= 33413 States= 1.32e+08 Transitions= 1.28e+09 Memory= 10182.783 t= 2.62e+03 R= 5e+04 +Depth= 33413 States= 1.33e+08 Transitions= 1.29e+09 Memory= 10251.436 t= 2.64e+03 R= 5e+04 +Depth= 33413 States= 1.34e+08 Transitions= 1.3e+09 Memory= 10320.088 t= 2.66e+03 R= 5e+04 +Depth= 33413 States= 1.35e+08 Transitions= 1.31e+09 Memory= 10388.740 t= 2.68e+03 R= 5e+04 +pan: resizing hashtable to -w28.. done +Depth= 33413 States= 1.36e+08 Transitions= 1.32e+09 Memory= 12441.428 t= 2.73e+03 R= 5e+04 +Depth= 33413 States= 1.37e+08 Transitions= 1.32e+09 Memory= 12510.178 t= 2.75e+03 R= 5e+04 +Depth= 33413 States= 1.38e+08 Transitions= 1.33e+09 Memory= 12578.830 t= 2.77e+03 R= 5e+04 +Depth= 33413 States= 1.39e+08 Transitions= 1.35e+09 Memory= 12647.483 t= 2.79e+03 R= 5e+04 +Depth= 33413 States= 1.4e+08 Transitions= 1.36e+09 Memory= 12716.135 t= 2.82e+03 R= 5e+04 +Depth= 33413 States= 1.41e+08 Transitions= 1.37e+09 Memory= 12784.787 t= 2.84e+03 R= 5e+04 +Depth= 33413 States= 1.42e+08 Transitions= 1.38e+09 Memory= 12853.537 t= 2.86e+03 R= 5e+04 +Depth= 33413 States= 1.43e+08 Transitions= 1.4e+09 Memory= 12922.190 t= 2.9e+03 R= 5e+04 +Depth= 33413 States= 1.44e+08 Transitions= 1.41e+09 Memory= 12990.842 t= 2.91e+03 R= 5e+04 +Depth= 33413 States= 1.45e+08 Transitions= 1.42e+09 Memory= 13059.494 t= 2.93e+03 R= 5e+04 +Depth= 33413 States= 1.46e+08 Transitions= 1.43e+09 Memory= 13128.244 t= 2.96e+03 R= 5e+04 +Depth= 33413 States= 1.47e+08 Transitions= 1.45e+09 Memory= 13196.897 t= 3e+03 R= 5e+04 +Depth= 33413 States= 1.48e+08 Transitions= 1.47e+09 Memory= 13265.549 t= 3.03e+03 R= 5e+04 +Depth= 33413 States= 1.49e+08 Transitions= 1.48e+09 Memory= 13334.201 t= 3.06e+03 R= 5e+04 +Depth= 33413 States= 1.5e+08 Transitions= 1.5e+09 Memory= 13402.951 t= 3.09e+03 R= 5e+04 +Depth= 33413 States= 1.51e+08 Transitions= 1.5e+09 Memory= 13471.604 t= 3.11e+03 R= 5e+04 +Depth= 33413 States= 1.52e+08 Transitions= 1.52e+09 Memory= 13540.256 t= 3.13e+03 R= 5e+04 +Depth= 33413 States= 1.53e+08 Transitions= 1.53e+09 Memory= 13608.908 t= 3.15e+03 R= 5e+04 +Depth= 33413 States= 1.54e+08 Transitions= 1.55e+09 Memory= 13677.658 t= 3.19e+03 R= 5e+04 +Depth= 33413 States= 1.55e+08 Transitions= 1.56e+09 Memory= 13746.311 t= 3.22e+03 R= 5e+04 +Depth= 33413 States= 1.56e+08 Transitions= 1.58e+09 Memory= 13814.963 t= 3.25e+03 R= 5e+04 +Depth= 33413 States= 1.57e+08 Transitions= 1.59e+09 Memory= 13883.615 t= 3.29e+03 R= 5e+04 +Depth= 33413 States= 1.58e+08 Transitions= 1.6e+09 Memory= 13952.268 t= 3.31e+03 R= 5e+04 +Depth= 33413 States= 1.59e+08 Transitions= 1.61e+09 Memory= 14021.018 t= 3.33e+03 R= 5e+04 +Depth= 33413 States= 1.6e+08 Transitions= 1.63e+09 Memory= 14089.670 t= 3.36e+03 R= 5e+04 +Depth= 33413 States= 1.61e+08 Transitions= 1.64e+09 Memory= 14158.322 t= 3.39e+03 R= 5e+04 +Depth= 33413 States= 1.62e+08 Transitions= 1.66e+09 Memory= 14226.975 t= 3.42e+03 R= 5e+04 +Depth= 33413 States= 1.63e+08 Transitions= 1.67e+09 Memory= 14295.725 t= 3.45e+03 R= 5e+04 +Depth= 33413 States= 1.64e+08 Transitions= 1.69e+09 Memory= 14364.377 t= 3.48e+03 R= 5e+04 +Depth= 33413 States= 1.65e+08 Transitions= 1.7e+09 Memory= 14433.029 t= 3.5e+03 R= 5e+04 +Depth= 33413 States= 1.66e+08 Transitions= 1.71e+09 Memory= 14501.682 t= 3.52e+03 R= 5e+04 +Depth= 33413 States= 1.67e+08 Transitions= 1.72e+09 Memory= 14570.432 t= 3.55e+03 R= 5e+04 +Depth= 33413 States= 1.68e+08 Transitions= 1.73e+09 Memory= 14639.084 t= 3.57e+03 R= 5e+04 +Depth= 33413 States= 1.69e+08 Transitions= 1.74e+09 Memory= 14707.736 t= 3.59e+03 R= 5e+04 +Depth= 33413 States= 1.7e+08 Transitions= 1.76e+09 Memory= 14776.389 t= 3.62e+03 R= 5e+04 +Depth= 33413 States= 1.71e+08 Transitions= 1.77e+09 Memory= 14845.041 t= 3.64e+03 R= 5e+04 +Depth= 33413 States= 1.72e+08 Transitions= 1.77e+09 Memory= 14913.791 t= 3.65e+03 R= 5e+04 +Depth= 33413 States= 1.73e+08 Transitions= 1.78e+09 Memory= 14982.443 t= 3.66e+03 R= 5e+04 +Depth= 33413 States= 1.74e+08 Transitions= 1.79e+09 Memory= 15051.096 t= 3.68e+03 R= 5e+04 +Depth= 33413 States= 1.75e+08 Transitions= 1.79e+09 Memory= 15119.748 t= 3.69e+03 R= 5e+04 +Depth= 33413 States= 1.76e+08 Transitions= 1.8e+09 Memory= 15188.498 t= 3.71e+03 R= 5e+04 +Depth= 33413 States= 1.77e+08 Transitions= 1.8e+09 Memory= 15257.151 t= 3.72e+03 R= 5e+04 +Depth= 33413 States= 1.78e+08 Transitions= 1.81e+09 Memory= 15325.803 t= 3.73e+03 R= 5e+04 +Depth= 33413 States= 1.79e+08 Transitions= 1.82e+09 Memory= 15394.455 t= 3.75e+03 R= 5e+04 +Depth= 33413 States= 1.8e+08 Transitions= 1.83e+09 Memory= 15463.205 t= 3.76e+03 R= 5e+04 +Depth= 33413 States= 1.81e+08 Transitions= 1.83e+09 Memory= 15531.858 t= 3.77e+03 R= 5e+04 +Depth= 33413 States= 1.82e+08 Transitions= 1.84e+09 Memory= 15600.510 t= 3.79e+03 R= 5e+04 +Depth= 33413 States= 1.83e+08 Transitions= 1.85e+09 Memory= 15669.162 t= 3.8e+03 R= 5e+04 +Depth= 33413 States= 1.84e+08 Transitions= 1.86e+09 Memory= 15737.912 t= 3.82e+03 R= 5e+04 +Depth= 33413 States= 1.85e+08 Transitions= 1.87e+09 Memory= 15806.565 t= 3.84e+03 R= 5e+04 +Depth= 33413 States= 1.86e+08 Transitions= 1.88e+09 Memory= 15875.217 t= 3.87e+03 R= 5e+04 +Depth= 33413 States= 1.87e+08 Transitions= 1.89e+09 Memory= 15943.869 t= 3.89e+03 R= 5e+04 +Depth= 33413 States= 1.88e+08 Transitions= 1.9e+09 Memory= 16012.522 t= 3.91e+03 R= 5e+04 +Depth= 33413 States= 1.89e+08 Transitions= 1.91e+09 Memory= 16081.272 t= 3.94e+03 R= 5e+04 +Depth= 33413 States= 1.9e+08 Transitions= 1.92e+09 Memory= 16149.924 t= 3.96e+03 R= 5e+04 +Depth= 33413 States= 1.91e+08 Transitions= 1.94e+09 Memory= 16218.576 t= 3.98e+03 R= 5e+04 +Depth= 33413 States= 1.92e+08 Transitions= 1.95e+09 Memory= 16287.229 t= 4.02e+03 R= 5e+04 +Depth= 33413 States= 1.93e+08 Transitions= 1.96e+09 Memory= 16355.979 t= 4.05e+03 R= 5e+04 +Depth= 33413 States= 1.94e+08 Transitions= 1.97e+09 Memory= 16424.631 t= 4.09e+03 R= 5e+04 +Depth= 33413 States= 1.95e+08 Transitions= 1.99e+09 Memory= 16493.283 t= 4.17e+03 R= 5e+04 +Depth= 33413 States= 1.96e+08 Transitions= 2e+09 Memory= 16561.936 t= 4.26e+03 R= 5e+04 +Depth= 33413 States= 1.97e+08 Transitions= 2.02e+09 Memory= 16630.686 t= 4.36e+03 R= 5e+04 +Depth= 33413 States= 1.98e+08 Transitions= 2.04e+09 Memory= 16699.338 t= 4.45e+03 R= 4e+04 +Depth= 33413 States= 1.99e+08 Transitions= 2.05e+09 Memory= 16767.990 t= 4.53e+03 R= 4e+04 +Depth= 33413 States= 2e+08 Transitions= 2.06e+09 Memory= 16836.643 t= 4.59e+03 R= 4e+04 +Depth= 33413 States= 2.01e+08 Transitions= 2.07e+09 Memory= 16905.393 t= 4.64e+03 R= 4e+04 +Depth= 33413 States= 2.02e+08 Transitions= 2.07e+09 Memory= 16974.045 t= 4.7e+03 R= 4e+04 +Depth= 33413 States= 2.03e+08 Transitions= 2.08e+09 Memory= 17042.697 t= 4.78e+03 R= 4e+04 +Depth= 33413 States= 2.04e+08 Transitions= 2.1e+09 Memory= 17111.350 t= 4.9e+03 R= 4e+04 +Depth= 33413 States= 2.05e+08 Transitions= 2.11e+09 Memory= 17180.002 t= 5.05e+03 R= 4e+04 +Depth= 33413 States= 2.06e+08 Transitions= 2.13e+09 Memory= 17248.752 t= 5.25e+03 R= 4e+04 +Depth= 33413 States= 2.07e+08 Transitions= 2.14e+09 Memory= 17317.404 t= 5.45e+03 R= 4e+04 +Depth= 33413 States= 2.08e+08 Transitions= 2.15e+09 Memory= 17386.057 t= 5.65e+03 R= 4e+04 +Depth= 33413 States= 2.09e+08 Transitions= 2.16e+09 Memory= 17454.709 t= 5.86e+03 R= 4e+04 +Depth= 33413 States= 2.1e+08 Transitions= 2.17e+09 Memory= 17523.459 t= 6.1e+03 R= 3e+04 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input new file mode 100644 index 0000000..c94928c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input @@ -0,0 +1,696 @@ +#define READER_NEST_LEVEL 1 + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE +#define get_pid() ((_pid < 1) -> 0 : 1) +#elif defined(TEST_SIGNAL_ON_READ) +#define get_pid() ((_pid < 2) -> 0 : 1) +#else +#define get_pid() (_pid) +#endif + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + dispatch_sighand_read_exec(); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 1; + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input.trail new file mode 100644 index 0000000..6f29ad2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_nested.spin.input.trail @@ -0,0 +1,11161 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 +18:4:4344 +19:4:4344 +20:4:4347 +21:4:4355 +22:4:4359 +23:4:4360 +24:0:4365 +25:4:4362 +26:0:4365 +27:3:2331 +28:0:4365 +29:3:2337 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b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.define new file mode 100644 index 0000000..136ef67 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.define @@ -0,0 +1,2 @@ +#define NO_RMB +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.log new file mode 100644 index 0000000..4cee7dc --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.log @@ -0,0 +1,382 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_mb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 743) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 72 byte, depth reached 10856, errors: 0 + 161519 states, stored + 1724866 states, matched + 1886385 transitions (= stored+matched) + 6692565 atomic steps +hash conflicts: 84009 (resolved) + +Stats on memory usage (in Megabytes): + 15.404 equivalent memory usage for states (stored*(State-vector + overhead)) + 10.421 actual memory usage for states (compression: 67.65%) + state-vector as stored = 40 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 476.115 total actual memory usage + +unreached in proctype urcu_reader_sig + line 403, "pan.___", state 330, "(1)" + line 614, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 652, "pan.___", state 213, "(1)" + line 403, "pan.___", state 239, "(1)" + line 403, "pan.___", state 525, "(1)" + line 399, "pan.___", state 610, "(1)" + line 403, "pan.___", state 624, "(1)" + line 403, "pan.___", state 724, "(1)" + line 399, "pan.___", state 805, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 807, "(1)" + line 399, "pan.___", state 808, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 808, "else" + line 399, "pan.___", state 811, "(1)" + line 403, "pan.___", state 819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 821, "(1)" + line 403, "pan.___", state 822, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 822, "else" + line 403, "pan.___", state 825, "(1)" + line 403, "pan.___", state 826, "(1)" + line 403, "pan.___", state 826, "(1)" + line 401, "pan.___", state 831, "((j<1))" + line 401, "pan.___", state 831, "((j>=1))" + line 408, "pan.___", state 837, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 850, "(1)" + line 409, "pan.___", state 851, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 851, "else" + line 409, "pan.___", state 854, "(1)" + line 409, "pan.___", state 855, "(1)" + line 409, "pan.___", state 855, "(1)" + line 413, "pan.___", state 863, "(1)" + line 413, "pan.___", state 864, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 864, "else" + line 413, "pan.___", state 867, "(1)" + line 413, "pan.___", state 868, "(1)" + line 413, "pan.___", state 868, "(1)" + line 411, "pan.___", state 873, "((j<1))" + line 411, "pan.___", state 873, "((j>=1))" + line 418, "pan.___", state 880, "(1)" + line 418, "pan.___", state 881, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 881, "else" + line 418, "pan.___", state 884, "(1)" + line 418, "pan.___", state 885, "(1)" + line 418, "pan.___", state 885, "(1)" + line 399, "pan.___", state 896, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 898, "(1)" + line 399, "pan.___", state 899, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 899, "else" + line 399, "pan.___", state 902, "(1)" + line 403, "pan.___", state 910, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 912, "(1)" + line 403, "pan.___", state 913, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 913, "else" + line 403, "pan.___", state 916, "(1)" + line 403, "pan.___", state 917, "(1)" + line 403, "pan.___", state 917, "(1)" + line 401, "pan.___", state 922, "((j<1))" + line 401, "pan.___", state 922, "((j>=1))" + line 408, "pan.___", state 928, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 941, "(1)" + line 409, "pan.___", state 942, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 942, "else" + line 409, "pan.___", state 945, "(1)" + line 409, "pan.___", state 946, "(1)" + line 409, "pan.___", state 946, "(1)" + line 413, "pan.___", state 954, "(1)" + line 413, "pan.___", state 955, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 955, "else" + line 413, "pan.___", state 958, "(1)" + line 413, "pan.___", state 959, "(1)" + line 413, "pan.___", state 959, "(1)" + line 411, "pan.___", state 964, "((j<1))" + line 411, "pan.___", state 964, "((j>=1))" + line 418, "pan.___", state 971, "(1)" + line 418, "pan.___", state 972, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 972, "else" + line 418, "pan.___", state 975, "(1)" + line 418, "pan.___", state 976, "(1)" + line 418, "pan.___", state 976, "(1)" + line 194, "pan.___", state 981, "(1)" + line 194, "pan.___", state 981, "(1)" + line 214, "pan.___", state 985, "((i<1))" + line 214, "pan.___", state 985, "((i>=1))" + line 399, "pan.___", state 991, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 993, "(1)" + line 399, "pan.___", state 994, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 994, "else" + line 399, "pan.___", state 997, "(1)" + line 403, "pan.___", state 1005, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1007, "(1)" + line 403, "pan.___", state 1008, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1008, "else" + line 403, "pan.___", state 1011, "(1)" + line 403, "pan.___", state 1012, "(1)" + line 403, "pan.___", state 1012, "(1)" + line 401, "pan.___", state 1017, "((j<1))" + line 401, "pan.___", state 1017, "((j>=1))" + line 408, "pan.___", state 1023, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1036, "(1)" + line 409, "pan.___", state 1037, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1037, "else" + line 409, "pan.___", state 1040, "(1)" + line 409, "pan.___", state 1041, "(1)" + line 409, "pan.___", state 1041, "(1)" + line 413, "pan.___", state 1049, "(1)" + line 413, "pan.___", state 1050, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1050, "else" + line 413, "pan.___", state 1053, "(1)" + line 413, "pan.___", state 1054, "(1)" + line 413, "pan.___", state 1054, "(1)" + line 411, "pan.___", state 1059, "((j<1))" + line 411, "pan.___", state 1059, "((j>=1))" + line 418, "pan.___", state 1066, "(1)" + line 418, "pan.___", state 1067, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1067, "else" + line 418, "pan.___", state 1070, "(1)" + line 418, "pan.___", state 1071, "(1)" + line 418, "pan.___", state 1071, "(1)" + line 194, "pan.___", state 1076, "(1)" + line 194, "pan.___", state 1076, "(1)" + line 221, "pan.___", state 1077, "(1)" + line 221, "pan.___", state 1077, "(1)" + line 356, "pan.___", state 1083, "((sighand_exec==1))" + line 356, "pan.___", state 1083, "else" + line 362, "pan.___", state 1086, "sighand_exec = 1" + line 399, "pan.___", state 1099, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1101, "(1)" + line 399, "pan.___", state 1102, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1102, "else" + line 399, "pan.___", state 1105, "(1)" + line 403, "pan.___", state 1113, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1115, "(1)" + line 403, "pan.___", state 1116, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1116, "else" + line 403, "pan.___", state 1119, "(1)" + line 403, "pan.___", state 1120, "(1)" + line 403, "pan.___", state 1120, "(1)" + line 401, "pan.___", state 1125, "((i<1))" + line 401, "pan.___", state 1125, "((i>=1))" + line 408, "pan.___", state 1131, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1144, "(1)" + line 409, "pan.___", state 1145, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1145, "else" + line 409, "pan.___", state 1148, "(1)" + line 409, "pan.___", state 1149, "(1)" + line 409, "pan.___", state 1149, "(1)" + line 413, "pan.___", state 1157, "(1)" + line 413, "pan.___", state 1158, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1158, "else" + line 413, "pan.___", state 1161, "(1)" + line 413, "pan.___", state 1162, "(1)" + line 413, "pan.___", state 1162, "(1)" + line 411, "pan.___", state 1167, "((i<1))" + line 411, "pan.___", state 1167, "((i>=1))" + line 418, "pan.___", state 1174, "(1)" + line 418, "pan.___", state 1175, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1175, "else" + line 418, "pan.___", state 1178, "(1)" + line 418, "pan.___", state 1179, "(1)" + line 418, "pan.___", state 1179, "(1)" + line 420, "pan.___", state 1182, "(1)" + line 420, "pan.___", state 1182, "(1)" + line 362, "pan.___", state 1191, "sighand_exec = 1" + line 403, "pan.___", state 1222, "(1)" + line 403, "pan.___", state 1319, "(1)" + line 399, "pan.___", state 1404, "(1)" + line 403, "pan.___", state 1418, "(1)" + line 403, "pan.___", state 1518, "(1)" + line 399, "pan.___", state 1599, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1601, "(1)" + line 399, "pan.___", state 1602, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1602, "else" + line 399, "pan.___", state 1605, "(1)" + line 403, "pan.___", state 1613, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1615, "(1)" + line 403, "pan.___", state 1616, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1616, "else" + line 403, "pan.___", state 1619, "(1)" + line 403, "pan.___", state 1620, "(1)" + line 403, "pan.___", state 1620, "(1)" + line 401, "pan.___", state 1625, "((j<1))" + line 401, "pan.___", state 1625, "((j>=1))" + line 408, "pan.___", state 1631, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1644, "(1)" + line 409, "pan.___", state 1645, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1645, "else" + line 409, "pan.___", state 1648, "(1)" + line 409, "pan.___", state 1649, "(1)" + line 409, "pan.___", state 1649, "(1)" + line 413, "pan.___", state 1657, "(1)" + line 413, "pan.___", state 1658, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1658, "else" + line 413, "pan.___", state 1661, "(1)" + line 413, "pan.___", state 1662, "(1)" + line 413, "pan.___", state 1662, "(1)" + line 411, "pan.___", state 1667, "((j<1))" + line 411, "pan.___", state 1667, "((j>=1))" + line 418, "pan.___", state 1674, "(1)" + line 418, "pan.___", state 1675, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1675, "else" + line 418, "pan.___", state 1678, "(1)" + line 418, "pan.___", state 1679, "(1)" + line 418, "pan.___", state 1679, "(1)" + line 399, "pan.___", state 1690, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1692, "(1)" + line 399, "pan.___", state 1693, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1693, "else" + line 399, "pan.___", state 1696, "(1)" + line 403, "pan.___", state 1704, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1706, "(1)" + line 403, "pan.___", state 1707, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1707, "else" + line 403, "pan.___", state 1710, "(1)" + line 403, "pan.___", state 1711, "(1)" + line 403, "pan.___", state 1711, "(1)" + line 401, "pan.___", state 1716, "((j<1))" + line 401, "pan.___", state 1716, "((j>=1))" + line 408, "pan.___", state 1722, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1735, "(1)" + line 409, "pan.___", state 1736, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1736, "else" + line 409, "pan.___", state 1739, "(1)" + line 409, "pan.___", state 1740, "(1)" + line 409, "pan.___", state 1740, "(1)" + line 413, "pan.___", state 1748, "(1)" + line 413, "pan.___", state 1749, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1749, "else" + line 413, "pan.___", state 1752, "(1)" + line 413, "pan.___", state 1753, "(1)" + line 413, "pan.___", state 1753, "(1)" + line 411, "pan.___", state 1758, "((j<1))" + line 411, "pan.___", state 1758, "((j>=1))" + line 418, "pan.___", state 1765, "(1)" + line 418, "pan.___", state 1766, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1766, "else" + line 418, "pan.___", state 1769, "(1)" + line 418, "pan.___", state 1770, "(1)" + line 418, "pan.___", state 1770, "(1)" + line 194, "pan.___", state 1775, "(1)" + line 194, "pan.___", state 1775, "(1)" + line 214, "pan.___", state 1779, "((i<1))" + line 214, "pan.___", state 1779, "((i>=1))" + line 399, "pan.___", state 1785, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1787, "(1)" + line 399, "pan.___", state 1788, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1788, "else" + line 399, "pan.___", state 1791, "(1)" + line 403, "pan.___", state 1799, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1801, "(1)" + line 403, "pan.___", state 1802, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1802, "else" + line 403, "pan.___", state 1805, "(1)" + line 403, "pan.___", state 1806, "(1)" + line 403, "pan.___", state 1806, "(1)" + line 401, "pan.___", state 1811, "((j<1))" + line 401, "pan.___", state 1811, "((j>=1))" + line 408, "pan.___", state 1817, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1830, "(1)" + line 409, "pan.___", state 1831, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1831, "else" + line 409, "pan.___", state 1834, "(1)" + line 409, "pan.___", state 1835, "(1)" + line 409, "pan.___", state 1835, "(1)" + line 413, "pan.___", state 1843, "(1)" + line 413, "pan.___", state 1844, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1844, "else" + line 413, "pan.___", state 1847, "(1)" + line 413, "pan.___", state 1848, "(1)" + line 413, "pan.___", state 1848, "(1)" + line 411, "pan.___", state 1853, "((j<1))" + line 411, "pan.___", state 1853, "((j>=1))" + line 418, "pan.___", state 1860, "(1)" + line 418, "pan.___", state 1861, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1861, "else" + line 418, "pan.___", state 1864, "(1)" + line 418, "pan.___", state 1865, "(1)" + line 418, "pan.___", state 1865, "(1)" + line 194, "pan.___", state 1870, "(1)" + line 194, "pan.___", state 1870, "(1)" + line 221, "pan.___", state 1871, "(1)" + line 221, "pan.___", state 1871, "(1)" + line 356, "pan.___", state 1877, "((sighand_exec==1))" + line 356, "pan.___", state 1877, "else" + line 362, "pan.___", state 1880, "sighand_exec = 1" + line 399, "pan.___", state 1893, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1895, "(1)" + line 399, "pan.___", state 1896, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1896, "else" + line 399, "pan.___", state 1899, "(1)" + line 403, "pan.___", state 1907, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1909, "(1)" + line 403, "pan.___", state 1910, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1910, "else" + line 403, "pan.___", state 1913, "(1)" + line 403, "pan.___", state 1914, "(1)" + line 403, "pan.___", state 1914, "(1)" + line 401, "pan.___", state 1919, "((i<1))" + line 401, "pan.___", state 1919, "((i>=1))" + line 408, "pan.___", state 1925, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1938, "(1)" + line 409, "pan.___", state 1939, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1939, "else" + line 409, "pan.___", state 1942, "(1)" + line 409, "pan.___", state 1943, "(1)" + line 409, "pan.___", state 1943, "(1)" + line 413, "pan.___", state 1951, "(1)" + line 413, "pan.___", state 1952, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1952, "else" + line 413, "pan.___", state 1955, "(1)" + line 413, "pan.___", state 1956, "(1)" + line 413, "pan.___", state 1956, "(1)" + line 411, "pan.___", state 1961, "((i<1))" + line 411, "pan.___", state 1961, "((i>=1))" + line 418, "pan.___", state 1968, "(1)" + line 418, "pan.___", state 1969, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1969, "else" + line 418, "pan.___", state 1972, "(1)" + line 418, "pan.___", state 1973, "(1)" + line 418, "pan.___", state 1973, "(1)" + line 420, "pan.___", state 1976, "(1)" + line 420, "pan.___", state 1976, "(1)" + line 362, "pan.___", state 1985, "sighand_exec = 1" + line 403, "pan.___", state 2016, "(1)" + line 702, "pan.___", state 2304, "-end-" + (221 of 2304 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 748, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 1.47 seconds +pan: rate 109876.87 states/second +pan: avg transition delay 7.7927e-07 usec +cp .input.spin urcu_free_no_mb.spin.input +cp .input.spin.trail urcu_free_no_mb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input new file mode 100644 index 0000000..48411ec --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input @@ -0,0 +1,723 @@ +#define NO_RMB +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input.trail new file mode 100644 index 0000000..00fba51 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_mb.spin.input.trail @@ -0,0 +1,2172 @@ +-2:4:-2 +-4:-4:-4 +1:0:4249 +2:4:4201 +3:4:4204 +4:4:4204 +5:4:4207 +6:4:4215 +7:4:4215 +8:4:4218 +9:4:4224 +10:4:4228 +11:4:4228 +12:4:4231 +13:4:4239 +14:4:4243 +15:4:4244 +16:0:4249 +17:4:4246 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a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.define new file mode 100644 index 0000000..73e61a4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.define @@ -0,0 +1 @@ +#define NO_RMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.log new file mode 100644 index 0000000..5eb694e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.log @@ -0,0 +1,280 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_rmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10519, errors: 0 + 20146 states, stored + 191615 states, matched + 211761 transitions (= stored+matched) + 711676 atomic steps +hash conflicts: 1222 (resolved) + +Stats on memory usage (in Megabytes): + 1.614 equivalent memory usage for states (stored*(State-vector + overhead)) + 1.509 actual memory usage for states (compression: 93.51%) + state-vector as stored = 51 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 467.229 total actual memory usage + +unreached in proctype urcu_reader_sig + line 402, "pan.___", state 330, "(1)" + line 613, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 59, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 408, "pan.___", state 160, "(1)" + line 651, "pan.___", state 213, "(1)" + line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 178, "pan.___", state 233, "(1)" + line 174, "pan.___", state 257, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 658, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 182, "pan.___", state 660, "(1)" + line 182, "pan.___", state 661, "((cache_dirty_generation_ptr.bitfield&(1<<0)))" + line 182, "pan.___", state 661, "else" + line 174, "pan.___", state 671, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 693, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 174, "pan.___", state 710, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 712, "(1)" + line 178, "pan.___", state 719, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 721, "(1)" + line 178, "pan.___", state 722, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 722, "else" + line 176, "pan.___", state 727, "((j<1))" + line 176, "pan.___", state 727, "((j>=1))" + line 182, "pan.___", state 732, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 182, "pan.___", state 734, "(1)" + line 182, "pan.___", state 735, "((cache_dirty_generation_ptr.bitfield&(1<<0)))" + line 182, "pan.___", state 735, "else" + line 192, "pan.___", state 740, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 192, "pan.___", state 740, "else" + line 220, "pan.___", state 741, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 741, "else" + line 355, "pan.___", state 747, "((sighand_exec==1))" + line 355, "pan.___", state 747, "else" + line 361, "pan.___", state 750, "sighand_exec = 1" + line 398, "pan.___", state 763, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 765, "(1)" + line 398, "pan.___", state 766, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 766, "else" + line 398, "pan.___", state 769, "(1)" + line 402, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 779, "(1)" + line 402, "pan.___", state 780, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 780, "else" + line 402, "pan.___", state 783, "(1)" + line 402, "pan.___", state 784, "(1)" + line 402, "pan.___", state 784, "(1)" + line 400, "pan.___", state 789, "((i<1))" + line 400, "pan.___", state 789, "((i>=1))" + line 407, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 808, "(1)" + line 408, "pan.___", state 809, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 809, "else" + line 408, "pan.___", state 812, "(1)" + line 408, "pan.___", state 813, "(1)" + line 408, "pan.___", state 813, "(1)" + line 412, "pan.___", state 821, "(1)" + line 412, "pan.___", state 822, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 822, "else" + line 412, "pan.___", state 825, "(1)" + line 412, "pan.___", state 826, "(1)" + line 412, "pan.___", state 826, "(1)" + line 410, "pan.___", state 831, "((i<1))" + line 410, "pan.___", state 831, "((i>=1))" + line 417, "pan.___", state 838, "(1)" + line 417, "pan.___", state 839, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 839, "else" + line 417, "pan.___", state 842, "(1)" + line 417, "pan.___", state 843, "(1)" + line 417, "pan.___", state 843, "(1)" + line 419, "pan.___", state 846, "(1)" + line 419, "pan.___", state 846, "(1)" + line 361, "pan.___", state 855, "sighand_exec = 1" + line 402, "pan.___", state 886, "(1)" + line 407, "pan.___", state 902, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 945, "(1)" + line 402, "pan.___", state 983, "(1)" + line 407, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1042, "(1)" + line 398, "pan.___", state 1068, "(1)" + line 402, "pan.___", state 1082, "(1)" + line 407, "pan.___", state 1098, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1141, "(1)" + line 402, "pan.___", state 1182, "(1)" + line 407, "pan.___", state 1198, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1241, "(1)" + line 174, "pan.___", state 1262, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1264, "(1)" + line 178, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1273, "(1)" + line 178, "pan.___", state 1274, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1274, "else" + line 176, "pan.___", state 1279, "((j<1))" + line 176, "pan.___", state 1279, "((j>=1))" + line 182, "pan.___", state 1284, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 182, "pan.___", state 1286, "(1)" + line 182, "pan.___", state 1287, "((cache_dirty_generation_ptr.bitfield&(1<<0)))" + line 182, "pan.___", state 1287, "else" + line 174, "pan.___", state 1297, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 1319, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 174, "pan.___", state 1336, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1338, "(1)" + line 178, "pan.___", state 1345, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1347, "(1)" + line 178, "pan.___", state 1348, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1348, "else" + line 176, "pan.___", state 1353, "((j<1))" + line 176, "pan.___", state 1353, "((j>=1))" + line 182, "pan.___", state 1358, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 182, "pan.___", state 1360, "(1)" + line 182, "pan.___", state 1361, "((cache_dirty_generation_ptr.bitfield&(1<<0)))" + line 182, "pan.___", state 1361, "else" + line 192, "pan.___", state 1366, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 192, "pan.___", state 1366, "else" + line 220, "pan.___", state 1367, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 1367, "else" + line 355, "pan.___", state 1373, "((sighand_exec==1))" + line 355, "pan.___", state 1373, "else" + line 361, "pan.___", state 1376, "sighand_exec = 1" + line 398, "pan.___", state 1389, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 1391, "(1)" + line 398, "pan.___", state 1392, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 1392, "else" + line 398, "pan.___", state 1395, "(1)" + line 402, "pan.___", state 1403, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 1405, "(1)" + line 402, "pan.___", state 1406, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 1406, "else" + line 402, "pan.___", state 1409, "(1)" + line 402, "pan.___", state 1410, "(1)" + line 402, "pan.___", state 1410, "(1)" + line 400, "pan.___", state 1415, "((i<1))" + line 400, "pan.___", state 1415, "((i>=1))" + line 407, "pan.___", state 1421, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 1434, "(1)" + line 408, "pan.___", state 1435, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 1435, "else" + line 408, "pan.___", state 1438, "(1)" + line 408, "pan.___", state 1439, "(1)" + line 408, "pan.___", state 1439, "(1)" + line 412, "pan.___", state 1447, "(1)" + line 412, "pan.___", state 1448, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 1448, "else" + line 412, "pan.___", state 1451, "(1)" + line 412, "pan.___", state 1452, "(1)" + line 412, "pan.___", state 1452, "(1)" + line 410, "pan.___", state 1457, "((i<1))" + line 410, "pan.___", state 1457, "((i>=1))" + line 417, "pan.___", state 1464, "(1)" + line 417, "pan.___", state 1465, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1465, "else" + line 417, "pan.___", state 1468, "(1)" + line 417, "pan.___", state 1469, "(1)" + line 417, "pan.___", state 1469, "(1)" + line 419, "pan.___", state 1472, "(1)" + line 419, "pan.___", state 1472, "(1)" + line 361, "pan.___", state 1481, "sighand_exec = 1" + line 178, "pan.___", state 1506, "(1)" + line 182, "pan.___", state 1517, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1530, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail new file mode 100644 index 0000000..8219815 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail @@ -0,0 +1,1805 @@ +-2:4:-2 +-4:-4:-4 +1:0:2905 +2:4:2857 +3:4:2860 +4:4:2860 +5:4:2863 +6:4:2871 +7:4:2871 +8:4:2874 +9:4:2880 +10:4:2884 +11:4:2884 +12:4:2887 +13:4:2895 +14:4:2899 +15:4:2900 +16:0:2905 +17:4:2902 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+1797:3:2850 +1798:0:2905 +1799:2:1098 +1800:0:2903 +1801:3:2851 +1802:0:2909 +1803:3:1630 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.define new file mode 100644 index 0000000..710f29d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.define @@ -0,0 +1 @@ +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.log new file mode 100644 index 0000000..a346ed9 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.log @@ -0,0 +1,224 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_wmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10499, errors: 0 + 159431 states, stored + 1505398 states, matched + 1664829 transitions (= stored+matched) + 5794809 atomic steps +hash conflicts: 62144 (resolved) + +Stats on memory usage (in Megabytes): + 12.772 equivalent memory usage for states (stored*(State-vector + overhead)) + 8.936 actual memory usage for states (compression: 69.96%) + state-vector as stored = 31 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 474.651 total actual memory usage + +unreached in proctype urcu_reader_sig + line 402, "pan.___", state 330, "(1)" + line 613, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 651, "pan.___", state 213, "(1)" + line 402, "pan.___", state 348, "(1)" + line 398, "pan.___", state 433, "(1)" + line 402, "pan.___", state 447, "(1)" + line 402, "pan.___", state 547, "(1)" + line 159, "pan.___", state 628, "(1)" + line 163, "pan.___", state 636, "(1)" + line 163, "pan.___", state 637, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 637, "else" + line 161, "pan.___", state 642, "((j<1))" + line 161, "pan.___", state 642, "((j>=1))" + line 167, "pan.___", state 648, "(1)" + line 167, "pan.___", state 649, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 649, "else" + line 159, "pan.___", state 660, "(1)" + line 163, "pan.___", state 668, "(1)" + line 163, "pan.___", state 669, "(!((cache_dirty_urcu_active_readers.bitfield&(1<=1))" + line 167, "pan.___", state 680, "(1)" + line 167, "pan.___", state 681, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 159, "pan.___", state 696, "(1)" + line 163, "pan.___", state 704, "(1)" + line 163, "pan.___", state 705, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 705, "else" + line 161, "pan.___", state 710, "((j<1))" + line 161, "pan.___", state 710, "((j>=1))" + line 167, "pan.___", state 716, "(1)" + line 167, "pan.___", state 717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 717, "else" + line 201, "pan.___", state 722, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 201, "pan.___", state 722, "else" + line 220, "pan.___", state 723, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 220, "pan.___", state 723, "else" + line 355, "pan.___", state 729, "((sighand_exec==1))" + line 355, "pan.___", state 729, "else" + line 361, "pan.___", state 732, "sighand_exec = 1" + line 398, "pan.___", state 745, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 747, "(1)" + line 398, "pan.___", state 748, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 748, "else" + line 398, "pan.___", state 751, "(1)" + line 402, "pan.___", state 759, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 761, "(1)" + line 402, "pan.___", state 762, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 762, "else" + line 402, "pan.___", state 765, "(1)" + line 402, "pan.___", state 766, "(1)" + line 402, "pan.___", state 766, "(1)" + line 400, "pan.___", state 771, "((i<1))" + line 400, "pan.___", state 771, "((i>=1))" + line 407, "pan.___", state 777, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 790, "(1)" + line 408, "pan.___", state 791, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 791, "else" + line 408, "pan.___", state 794, "(1)" + line 408, "pan.___", state 795, "(1)" + line 408, "pan.___", state 795, "(1)" + line 412, "pan.___", state 803, "(1)" + line 412, "pan.___", state 804, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 804, "else" + line 412, "pan.___", state 807, "(1)" + line 412, "pan.___", state 808, "(1)" + line 412, "pan.___", state 808, "(1)" + line 410, "pan.___", state 813, "((i<1))" + line 410, "pan.___", state 813, "((i>=1))" + line 417, "pan.___", state 820, "(1)" + line 417, "pan.___", state 821, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 821, "else" + line 417, "pan.___", state 824, "(1)" + line 417, "pan.___", state 825, "(1)" + line 417, "pan.___", state 825, "(1)" + line 419, "pan.___", state 828, "(1)" + line 419, "pan.___", state 828, "(1)" + line 361, "pan.___", state 837, "sighand_exec = 1" + line 402, "pan.___", state 868, "(1)" + line 402, "pan.___", state 965, "(1)" + line 398, "pan.___", state 1050, "(1)" + line 402, "pan.___", state 1064, "(1)" + line 402, "pan.___", state 1164, "(1)" + line 159, "pan.___", state 1245, "(1)" + line 163, "pan.___", state 1253, "(1)" + line 163, "pan.___", state 1254, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1254, "else" + line 161, "pan.___", state 1259, "((j<1))" + line 161, "pan.___", state 1259, "((j>=1))" + line 167, "pan.___", state 1265, "(1)" + line 167, "pan.___", state 1266, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1266, "else" + line 159, "pan.___", state 1277, "(1)" + line 163, "pan.___", state 1285, "(1)" + line 163, "pan.___", state 1286, "(!((cache_dirty_urcu_active_readers.bitfield&(1<=1))" + line 167, "pan.___", state 1297, "(1)" + line 167, "pan.___", state 1298, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 159, "pan.___", state 1313, "(1)" + line 163, "pan.___", state 1321, "(1)" + line 163, "pan.___", state 1322, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1322, "else" + line 161, "pan.___", state 1327, "((j<1))" + line 161, "pan.___", state 1327, "((j>=1))" + line 167, "pan.___", state 1333, "(1)" + line 167, "pan.___", state 1334, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1334, "else" + line 201, "pan.___", state 1339, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 201, "pan.___", state 1339, "else" + line 220, "pan.___", state 1340, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 220, "pan.___", state 1340, "else" + line 355, "pan.___", state 1346, "((sighand_exec==1))" + line 355, "pan.___", state 1346, "else" + line 361, "pan.___", state 1349, "sighand_exec = 1" + line 398, "pan.___", state 1362, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 1364, "(1)" + line 398, "pan.___", state 1365, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 1365, "else" + line 398, "pan.___", state 1368, "(1)" + line 402, "pan.___", state 1376, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 1378, "(1)" + line 402, "pan.___", state 1379, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 1379, "else" + line 402, "pan.___", state 1382, "(1)" + line 402, "pan.___", state 1383, "(1)" + line 402, "pan.___", state 1383, "(1)" + line 400, "pan.___", state 1388, "((i<1))" + line 400, "pan.___", state 1388, "((i>=1))" + line 407, "pan.___", state 1394, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 1407, "(1)" + line 408, "pan.___", state 1408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 1408, "else" + line 408, "pan.___", state 1411, "(1)" + line 408, "pan.___", state 1412, "(1)" + line 408, "pan.___", state 1412, "(1)" + line 412, "pan.___", state 1420, "(1)" + line 412, "pan.___", state 1421, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 1421, "else" + line 412, "pan.___", state 1424, "(1)" + line 412, "pan.___", state 1425, "(1)" + line 412, "pan.___", state 1425, "(1)" + line 410, "pan.___", state 1430, "((i<1))" + line 410, "pan.___", state 1430, "((i>=1))" + line 417, "pan.___", state 1437, "(1)" + line 417, "pan.___", state 1438, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1438, "else" + line 417, "pan.___", state 1441, "(1)" + line 417, "pan.___", state 1442, "(1)" + line 417, "pan.___", state 1442, "(1)" + line 419, "pan.___", state 1445, "(1)" + line 419, "pan.___", state 1445, "(1)" + line 361, "pan.___", state 1454, "sighand_exec = 1" + line 701, "pan.___", state 1596, "-end-" + (111 of 1596 states) +unreached in proctype :init: + (0 of 46 states) +unreached in proctype :never: + line 747, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 1.23 seconds +pan: rate 129618.7 states/second +pan: avg transition delay 7.3881e-07 usec +cp .input.spin urcu_free_no_wmb.spin.input +cp .input.spin.trail urcu_free_no_wmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input new file mode 100644 index 0000000..808154e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input @@ -0,0 +1,722 @@ +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 1 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail new file mode 100644 index 0000000..522df0a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail @@ -0,0 +1,1677 @@ +-2:4:-2 +-4:-4:-4 +1:0:2833 +2:4:2785 +3:4:2788 +4:4:2788 +5:4:2791 +6:4:2799 +7:4:2799 +8:4:2802 +9:4:2808 +10:4:2812 +11:4:2812 +12:4:2815 +13:4:2823 +14:4:2827 +15:4:2828 +16:0:2833 +17:4:2830 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+1644:3:2695 +1645:0:2833 +1646:3:2696 +1647:3:2703 +1648:3:2706 +1649:3:2707 +1650:3:2711 +1651:3:2716 +1652:0:2833 +1653:3:2727 +1654:0:2833 +1655:3:2732 +1656:3:2739 +1657:3:2740 +1658:3:2747 +1659:3:2752 +1660:0:2833 +1661:3:2767 +1662:0:2833 +1663:3:2769 +1664:0:2833 +1665:3:2770 +1666:0:2833 +1667:3:2773 +1668:0:2833 +1669:3:2778 +1670:0:2833 +1671:2:1071 +1672:0:2831 +1673:3:2779 +1674:0:2837 +1675:1:288 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.define new file mode 100644 index 0000000..5e642ef --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.define @@ -0,0 +1 @@ +#define SINGLE_FLIP diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.log new file mode 100644 index 0000000..f854175 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.log @@ -0,0 +1,224 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_single_flip.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 6934, errors: 0 + 7626 states, stored + 67235 states, matched + 74861 transitions (= stored+matched) + 248896 atomic steps +hash conflicts: 113 (resolved) + +Stats on memory usage (in Megabytes): + 0.611 equivalent memory usage for states (stored*(State-vector + overhead)) + 0.867 actual memory usage for states (unsuccessful compression: 141.88%) + state-vector as stored = 91 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 466.545 total actual memory usage + +unreached in proctype urcu_reader_sig + line 402, "pan.___", state 330, "(1)" + line 613, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 59, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 408, "pan.___", state 160, "(1)" + line 651, "pan.___", state 213, "(1)" + line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 178, "pan.___", state 233, "(1)" + line 159, "pan.___", state 254, "(1)" + line 163, "pan.___", state 262, "(1)" + line 167, "pan.___", state 274, "(1)" + line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 752, "(1)" + line 163, "pan.___", state 760, "(1)" + line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 761, "else" + line 161, "pan.___", state 766, "((j<1))" + line 161, "pan.___", state 766, "((j>=1))" + line 167, "pan.___", state 772, "(1)" + line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 773, "else" + line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 776, "else" + line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 167, "pan.___", state 835, "(1)" + line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 852, "(1)" + line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 861, "(1)" + line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 862, "else" + line 176, "pan.___", state 867, "((j<1))" + line 176, "pan.___", state 867, "((j>=1))" + line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 882, "(1)" + line 163, "pan.___", state 890, "(1)" + line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 891, "else" + line 161, "pan.___", state 896, "((j<1))" + line 161, "pan.___", state 896, "((j>=1))" + line 167, "pan.___", state 902, "(1)" + line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 903, "else" + line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 906, "else" + line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 201, "pan.___", state 908, "else" + line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 909, "else" + line 355, "pan.___", state 915, "((sighand_exec==1))" + line 355, "pan.___", state 915, "else" + line 361, "pan.___", state 918, "sighand_exec = 1" + line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 933, "(1)" + line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 934, "else" + line 398, "pan.___", state 937, "(1)" + line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 947, "(1)" + line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 948, "else" + line 402, "pan.___", state 951, "(1)" + line 402, "pan.___", state 952, "(1)" + line 402, "pan.___", state 952, "(1)" + line 400, "pan.___", state 957, "((i<1))" + line 400, "pan.___", state 957, "((i>=1))" + line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 976, "(1)" + line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 977, "else" + line 408, "pan.___", state 980, "(1)" + line 408, "pan.___", state 981, "(1)" + line 408, "pan.___", state 981, "(1)" + line 412, "pan.___", state 989, "(1)" + line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 990, "else" + line 412, "pan.___", state 993, "(1)" + line 412, "pan.___", state 994, "(1)" + line 412, "pan.___", state 994, "(1)" + line 410, "pan.___", state 999, "((i<1))" + line 410, "pan.___", state 999, "((i>=1))" + line 417, "pan.___", state 1006, "(1)" + line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1007, "else" + line 417, "pan.___", state 1010, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 361, "pan.___", state 1023, "sighand_exec = 1" + line 178, "pan.___", state 1048, "(1)" + line 182, "pan.___", state 1059, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1069, "(1)" + line 163, "pan.___", state 1077, "(1)" + line 167, "pan.___", state 1089, "(1)" + line 174, "pan.___", state 1100, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.spin.input.trail new file mode 100644 index 0000000..84cf653 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_free_single_flip.spin.input.trail @@ -0,0 +1,1379 @@ +-2:4:-2 +-4:-4:-4 +1:0:2904 +2:4:2856 +3:4:2859 +4:4:2859 +5:4:2862 +6:4:2870 +7:4:2870 +8:4:2873 +9:4:2879 +10:4:2883 +11:4:2883 +12:4:2886 +13:4:2894 +14:4:2898 +15:4:2899 +16:0:2904 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a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.define new file mode 100644 index 0000000..ff3f783 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.define @@ -0,0 +1 @@ +#define READER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.log new file mode 100644 index 0000000..a1a6122 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.log @@ -0,0 +1,348 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_reader.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) +depth 12: Claim reached state 9 (line 747) +depth 86: Claim reached state 9 (line 746) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10679, errors: 0 + 38182 states, stored (88898 visited) + 997091 states, matched + 1085989 transitions (= visited+matched) + 3694897 atomic steps +hash conflicts: 9602 (resolved) + +Stats on memory usage (in Megabytes): + 3.059 equivalent memory usage for states (stored*(State-vector + overhead)) + 2.930 actual memory usage for states (compression: 95.79%) + state-vector as stored = 52 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 468.596 total actual memory usage + +unreached in proctype urcu_reader_sig + line 402, "pan.___", state 330, "(1)" + line 613, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 59, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 408, "pan.___", state 160, "(1)" + line 651, "pan.___", state 213, "(1)" + line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 178, "pan.___", state 233, "(1)" + line 159, "pan.___", state 254, "(1)" + line 163, "pan.___", state 262, "(1)" + line 167, "pan.___", state 274, "(1)" + line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 752, "(1)" + line 163, "pan.___", state 760, "(1)" + line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 761, "else" + line 161, "pan.___", state 766, "((j<1))" + line 161, "pan.___", state 766, "((j>=1))" + line 167, "pan.___", state 772, "(1)" + line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 773, "else" + line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 776, "else" + line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 167, "pan.___", state 835, "(1)" + line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 852, "(1)" + line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 861, "(1)" + line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 862, "else" + line 176, "pan.___", state 867, "((j<1))" + line 176, "pan.___", state 867, "((j>=1))" + line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 882, "(1)" + line 163, "pan.___", state 890, "(1)" + line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 891, "else" + line 161, "pan.___", state 896, "((j<1))" + line 161, "pan.___", state 896, "((j>=1))" + line 167, "pan.___", state 902, "(1)" + line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 903, "else" + line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 906, "else" + line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 201, "pan.___", state 908, "else" + line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 909, "else" + line 355, "pan.___", state 915, "((sighand_exec==1))" + line 355, "pan.___", state 915, "else" + line 361, "pan.___", state 918, "sighand_exec = 1" + line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 933, "(1)" + line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 934, "else" + line 398, "pan.___", state 937, "(1)" + line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 947, "(1)" + line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 948, "else" + line 402, "pan.___", state 951, "(1)" + line 402, "pan.___", state 952, "(1)" + line 402, "pan.___", state 952, "(1)" + line 400, "pan.___", state 957, "((i<1))" + line 400, "pan.___", state 957, "((i>=1))" + line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 976, "(1)" + line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 977, "else" + line 408, "pan.___", state 980, "(1)" + line 408, "pan.___", state 981, "(1)" + line 408, "pan.___", state 981, "(1)" + line 412, "pan.___", state 989, "(1)" + line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 990, "else" + line 412, "pan.___", state 993, "(1)" + line 412, "pan.___", state 994, "(1)" + line 412, "pan.___", state 994, "(1)" + line 410, "pan.___", state 999, "((i<1))" + line 410, "pan.___", state 999, "((i>=1))" + line 417, "pan.___", state 1006, "(1)" + line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1007, "else" + line 417, "pan.___", state 1010, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 361, "pan.___", state 1023, "sighand_exec = 1" + line 402, "pan.___", state 1054, "(1)" + line 407, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1113, "(1)" + line 402, "pan.___", state 1151, "(1)" + line 407, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1210, "(1)" + line 398, "pan.___", state 1236, "(1)" + line 402, "pan.___", state 1250, "(1)" + line 407, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1309, "(1)" + line 402, "pan.___", state 1350, "(1)" + line 407, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1409, "(1)" + line 174, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1432, "(1)" + line 178, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1441, "(1)" + line 178, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1442, "else" + line 176, "pan.___", state 1447, "((j<1))" + line 176, "pan.___", state 1447, "((j>=1))" + line 182, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1462, "(1)" + line 163, "pan.___", state 1470, "(1)" + line 163, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1471, "else" + line 161, "pan.___", state 1476, "((j<1))" + line 161, "pan.___", state 1476, "((j>=1))" + line 167, "pan.___", state 1482, "(1)" + line 167, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1483, "else" + line 169, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 1486, "else" + line 174, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 167, "pan.___", state 1545, "(1)" + line 167, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 174, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1562, "(1)" + line 178, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1571, "(1)" + line 178, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1572, "else" + line 176, "pan.___", state 1577, "((j<1))" + line 176, "pan.___", state 1577, "((j>=1))" + line 182, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1592, "(1)" + line 163, "pan.___", state 1600, "(1)" + line 163, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1601, "else" + line 161, "pan.___", state 1606, "((j<1))" + line 161, "pan.___", state 1606, "((j>=1))" + line 167, "pan.___", state 1612, "(1)" + line 167, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1613, "else" + line 169, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 1616, "else" + line 201, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 201, "pan.___", state 1618, "else" + line 220, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 1619, "else" + line 355, "pan.___", state 1625, "((sighand_exec==1))" + line 355, "pan.___", state 1625, "else" + line 361, "pan.___", state 1628, "sighand_exec = 1" + line 398, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 1643, "(1)" + line 398, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 1644, "else" + line 398, "pan.___", state 1647, "(1)" + line 402, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 1657, "(1)" + line 402, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 1658, "else" + line 402, "pan.___", state 1661, "(1)" + line 402, "pan.___", state 1662, "(1)" + line 402, "pan.___", state 1662, "(1)" + line 400, "pan.___", state 1667, "((i<1))" + line 400, "pan.___", state 1667, "((i>=1))" + line 407, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 1686, "(1)" + line 408, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 1687, "else" + line 408, "pan.___", state 1690, "(1)" + line 408, "pan.___", state 1691, "(1)" + line 408, "pan.___", state 1691, "(1)" + line 412, "pan.___", state 1699, "(1)" + line 412, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 1700, "else" + line 412, "pan.___", state 1703, "(1)" + line 412, "pan.___", state 1704, "(1)" + line 412, "pan.___", state 1704, "(1)" + line 410, "pan.___", state 1709, "((i<1))" + line 410, "pan.___", state 1709, "((i>=1))" + line 417, "pan.___", state 1716, "(1)" + line 417, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1717, "else" + line 417, "pan.___", state 1720, "(1)" + line 417, "pan.___", state 1721, "(1)" + line 417, "pan.___", state 1721, "(1)" + line 419, "pan.___", state 1724, "(1)" + line 419, "pan.___", state 1724, "(1)" + line 361, "pan.___", state 1733, "sighand_exec = 1" + line 178, "pan.___", state 1758, "(1)" + line 182, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1779, "(1)" + line 163, "pan.___", state 1787, "(1)" + line 167, "pan.___", state 1799, "(1)" + line 174, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.spin.input.trail new file mode 100644 index 0000000..7c42af1 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_reader.spin.input.trail @@ -0,0 +1,1270 @@ +-2:4:-2 +-4:-4:-4 +1:0:4401 +2:4:4353 +3:4:4356 +4:4:4356 +5:4:4359 +6:4:4367 +7:4:4367 +8:4:4370 +9:4:4376 +10:4:4380 +11:4:4380 +12:4:4383 +13:4:4391 +14:4:4395 +15:4:4396 +16:0:4401 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+1252:0:4405 +1253:1:105 +1254:0:4405 +1255:3:4347 +1256:0:4405 +1257:3:4346 +1258:0:4405 +1259:2:1348 +1260:0:4405 +1261:3:4347 +1262:0:4405 +1263:2:1347 +1264:0:4405 +1265:3:4346 +1266:0:4405 +1267:1:104 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.define new file mode 100644 index 0000000..1e4417f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.define @@ -0,0 +1 @@ +#define WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.log new file mode 100644 index 0000000..02c53cf --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.log @@ -0,0 +1,348 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) +depth 12: Claim reached state 9 (line 747) +depth 28: Claim reached state 9 (line 746) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10679, errors: 0 + 38555 states, stored (92500 visited) + 1044204 states, matched + 1136704 transitions (= visited+matched) + 3867169 atomic steps +hash conflicts: 8572 (resolved) + +Stats on memory usage (in Megabytes): + 3.089 equivalent memory usage for states (stored*(State-vector + overhead)) + 2.930 actual memory usage for states (compression: 94.87%) + state-vector as stored = 52 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 468.596 total actual memory usage + +unreached in proctype urcu_reader_sig + line 402, "pan.___", state 330, "(1)" + line 613, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 59, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 408, "pan.___", state 160, "(1)" + line 651, "pan.___", state 213, "(1)" + line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 178, "pan.___", state 233, "(1)" + line 159, "pan.___", state 254, "(1)" + line 163, "pan.___", state 262, "(1)" + line 167, "pan.___", state 274, "(1)" + line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 752, "(1)" + line 163, "pan.___", state 760, "(1)" + line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 761, "else" + line 161, "pan.___", state 766, "((j<1))" + line 161, "pan.___", state 766, "((j>=1))" + line 167, "pan.___", state 772, "(1)" + line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 773, "else" + line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 776, "else" + line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 167, "pan.___", state 835, "(1)" + line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 852, "(1)" + line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 861, "(1)" + line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 862, "else" + line 176, "pan.___", state 867, "((j<1))" + line 176, "pan.___", state 867, "((j>=1))" + line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 882, "(1)" + line 163, "pan.___", state 890, "(1)" + line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 891, "else" + line 161, "pan.___", state 896, "((j<1))" + line 161, "pan.___", state 896, "((j>=1))" + line 167, "pan.___", state 902, "(1)" + line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 903, "else" + line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 906, "else" + line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 201, "pan.___", state 908, "else" + line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 909, "else" + line 355, "pan.___", state 915, "((sighand_exec==1))" + line 355, "pan.___", state 915, "else" + line 361, "pan.___", state 918, "sighand_exec = 1" + line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 933, "(1)" + line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 934, "else" + line 398, "pan.___", state 937, "(1)" + line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 947, "(1)" + line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 948, "else" + line 402, "pan.___", state 951, "(1)" + line 402, "pan.___", state 952, "(1)" + line 402, "pan.___", state 952, "(1)" + line 400, "pan.___", state 957, "((i<1))" + line 400, "pan.___", state 957, "((i>=1))" + line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 976, "(1)" + line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 977, "else" + line 408, "pan.___", state 980, "(1)" + line 408, "pan.___", state 981, "(1)" + line 408, "pan.___", state 981, "(1)" + line 412, "pan.___", state 989, "(1)" + line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 990, "else" + line 412, "pan.___", state 993, "(1)" + line 412, "pan.___", state 994, "(1)" + line 412, "pan.___", state 994, "(1)" + line 410, "pan.___", state 999, "((i<1))" + line 410, "pan.___", state 999, "((i>=1))" + line 417, "pan.___", state 1006, "(1)" + line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1007, "else" + line 417, "pan.___", state 1010, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 417, "pan.___", state 1011, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 419, "pan.___", state 1014, "(1)" + line 361, "pan.___", state 1023, "sighand_exec = 1" + line 402, "pan.___", state 1054, "(1)" + line 407, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1113, "(1)" + line 402, "pan.___", state 1151, "(1)" + line 407, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1210, "(1)" + line 398, "pan.___", state 1236, "(1)" + line 402, "pan.___", state 1250, "(1)" + line 407, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1309, "(1)" + line 402, "pan.___", state 1350, "(1)" + line 407, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 417, "pan.___", state 1409, "(1)" + line 174, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1432, "(1)" + line 178, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1441, "(1)" + line 178, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1442, "else" + line 176, "pan.___", state 1447, "((j<1))" + line 176, "pan.___", state 1447, "((j>=1))" + line 182, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1462, "(1)" + line 163, "pan.___", state 1470, "(1)" + line 163, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1471, "else" + line 161, "pan.___", state 1476, "((j<1))" + line 161, "pan.___", state 1476, "((j>=1))" + line 167, "pan.___", state 1482, "(1)" + line 167, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1483, "else" + line 169, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 1486, "else" + line 174, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 182, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 167, "pan.___", state 1545, "(1)" + line 167, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 174, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 174, "pan.___", state 1562, "(1)" + line 178, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 178, "pan.___", state 1571, "(1)" + line 178, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 178, "pan.___", state 1572, "else" + line 176, "pan.___", state 1577, "((j<1))" + line 176, "pan.___", state 1577, "((j>=1))" + line 182, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1592, "(1)" + line 163, "pan.___", state 1600, "(1)" + line 163, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 163, "pan.___", state 1601, "else" + line 161, "pan.___", state 1606, "((j<1))" + line 161, "pan.___", state 1606, "((j>=1))" + line 167, "pan.___", state 1612, "(1)" + line 167, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 167, "pan.___", state 1613, "else" + line 169, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 169, "pan.___", state 1616, "else" + line 201, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 201, "pan.___", state 1618, "else" + line 220, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 220, "pan.___", state 1619, "else" + line 355, "pan.___", state 1625, "((sighand_exec==1))" + line 355, "pan.___", state 1625, "else" + line 361, "pan.___", state 1628, "sighand_exec = 1" + line 398, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 398, "pan.___", state 1643, "(1)" + line 398, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 398, "pan.___", state 1644, "else" + line 398, "pan.___", state 1647, "(1)" + line 402, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 402, "pan.___", state 1657, "(1)" + line 402, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 402, "pan.___", state 1658, "else" + line 402, "pan.___", state 1661, "(1)" + line 402, "pan.___", state 1662, "(1)" + line 402, "pan.___", state 1662, "(1)" + line 400, "pan.___", state 1667, "((i<1))" + line 400, "pan.___", state 1667, "((i>=1))" + line 407, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 408, "pan.___", state 1686, "(1)" + line 408, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 408, "pan.___", state 1687, "else" + line 408, "pan.___", state 1690, "(1)" + line 408, "pan.___", state 1691, "(1)" + line 408, "pan.___", state 1691, "(1)" + line 412, "pan.___", state 1699, "(1)" + line 412, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 412, "pan.___", state 1700, "else" + line 412, "pan.___", state 1703, "(1)" + line 412, "pan.___", state 1704, "(1)" + line 412, "pan.___", state 1704, "(1)" + line 410, "pan.___", state 1709, "((i<1))" + line 410, "pan.___", state 1709, "((i>=1))" + line 417, "pan.___", state 1716, "(1)" + line 417, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 417, "pan.___", state 1717, "else" + line 417, "pan.___", state 1720, "(1)" + line 417, "pan.___", state 1721, "(1)" + line 417, "pan.___", state 1721, "(1)" + line 419, "pan.___", state 1724, "(1)" + line 419, "pan.___", state 1724, "(1)" + line 361, "pan.___", state 1733, "sighand_exec = 1" + line 178, "pan.___", state 1758, "(1)" + line 182, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 159, "pan.___", state 1779, "(1)" + line 163, "pan.___", state 1787, "(1)" + line 167, "pan.___", state 1799, "(1)" + line 174, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.spin.input.trail new file mode 100644 index 0000000..e65d663 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer.spin.input.trail @@ -0,0 +1,9 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:1:2675 +5:1:2676 +6:0:2685 +7:5:1129 diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.define b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.define new file mode 100644 index 0000000..8d304f5 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.define @@ -0,0 +1,2 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.log b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.log new file mode 100644 index 0000000..cd4e32b --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.log @@ -0,0 +1,286 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer_error.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 743) +depth 12: Claim reached state 9 (line 748) +depth 28: Claim reached state 9 (line 747) + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 10679, errors: 0 + 38555 states, stored (92500 visited) + 1044204 states, matched + 1136704 transitions (= visited+matched) + 3867169 atomic steps +hash conflicts: 6390 (resolved) + +Stats on memory usage (in Megabytes): + 3.089 equivalent memory usage for states (stored*(State-vector + overhead)) + 2.767 actual memory usage for states (compression: 89.58%) + state-vector as stored = 47 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 468.498 total actual memory usage + +unreached in proctype urcu_reader_sig + line 403, "pan.___", state 330, "(1)" + line 614, "pan.___", state 411, "-end-" + (2 of 411 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 59, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 409, "pan.___", state 160, "(1)" + line 652, "pan.___", state 213, "(1)" + line 175, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 179, "pan.___", state 233, "(1)" + line 160, "pan.___", state 254, "(1)" + line 164, "pan.___", state 262, "(1)" + line 168, "pan.___", state 274, "(1)" + line 175, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 753, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 766, "(1)" + line 409, "pan.___", state 767, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 767, "else" + line 409, "pan.___", state 770, "(1)" + line 409, "pan.___", state 771, "(1)" + line 409, "pan.___", state 771, "(1)" + line 413, "pan.___", state 779, "(1)" + line 413, "pan.___", state 780, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 780, "else" + line 413, "pan.___", state 783, "(1)" + line 413, "pan.___", state 784, "(1)" + line 413, "pan.___", state 784, "(1)" + line 411, "pan.___", state 789, "((i<1))" + line 411, "pan.___", state 789, "((i>=1))" + line 418, "pan.___", state 796, "(1)" + line 418, "pan.___", state 797, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 797, "else" + line 418, "pan.___", state 800, "(1)" + line 418, "pan.___", state 801, "(1)" + line 418, "pan.___", state 801, "(1)" + line 420, "pan.___", state 804, "(1)" + line 420, "pan.___", state 804, "(1)" + line 356, "pan.___", state 810, "((sighand_exec==1))" + line 356, "pan.___", state 810, "else" + line 362, "pan.___", state 813, "sighand_exec = 1" + line 399, "pan.___", state 826, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 828, "(1)" + line 399, "pan.___", state 829, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 829, "else" + line 399, "pan.___", state 832, "(1)" + line 403, "pan.___", state 840, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 842, "(1)" + line 403, "pan.___", state 843, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 843, "else" + line 403, "pan.___", state 846, "(1)" + line 403, "pan.___", state 847, "(1)" + line 403, "pan.___", state 847, "(1)" + line 401, "pan.___", state 852, "((i<1))" + line 401, "pan.___", state 852, "((i>=1))" + line 408, "pan.___", state 858, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 871, "(1)" + line 409, "pan.___", state 872, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 872, "else" + line 409, "pan.___", state 875, "(1)" + line 409, "pan.___", state 876, "(1)" + line 409, "pan.___", state 876, "(1)" + line 413, "pan.___", state 884, "(1)" + line 413, "pan.___", state 885, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 885, "else" + line 413, "pan.___", state 888, "(1)" + line 413, "pan.___", state 889, "(1)" + line 413, "pan.___", state 889, "(1)" + line 411, "pan.___", state 894, "((i<1))" + line 411, "pan.___", state 894, "((i>=1))" + line 418, "pan.___", state 901, "(1)" + line 418, "pan.___", state 902, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 902, "else" + line 418, "pan.___", state 905, "(1)" + line 418, "pan.___", state 906, "(1)" + line 418, "pan.___", state 906, "(1)" + line 420, "pan.___", state 909, "(1)" + line 420, "pan.___", state 909, "(1)" + line 362, "pan.___", state 918, "sighand_exec = 1" + line 403, "pan.___", state 949, "(1)" + line 408, "pan.___", state 965, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 418, "pan.___", state 1008, "(1)" + line 403, "pan.___", state 1046, "(1)" + line 408, "pan.___", state 1062, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 418, "pan.___", state 1105, "(1)" + line 399, "pan.___", state 1131, "(1)" + line 403, "pan.___", state 1145, "(1)" + line 408, "pan.___", state 1161, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 418, "pan.___", state 1204, "(1)" + line 403, "pan.___", state 1245, "(1)" + line 408, "pan.___", state 1261, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 418, "pan.___", state 1304, "(1)" + line 399, "pan.___", state 1326, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1328, "(1)" + line 399, "pan.___", state 1329, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1329, "else" + line 399, "pan.___", state 1332, "(1)" + line 403, "pan.___", state 1340, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1342, "(1)" + line 403, "pan.___", state 1343, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1343, "else" + line 403, "pan.___", state 1346, "(1)" + line 403, "pan.___", state 1347, "(1)" + line 403, "pan.___", state 1347, "(1)" + line 401, "pan.___", state 1352, "((i<1))" + line 401, "pan.___", state 1352, "((i>=1))" + line 408, "pan.___", state 1358, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1371, "(1)" + line 409, "pan.___", state 1372, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1372, "else" + line 409, "pan.___", state 1375, "(1)" + line 409, "pan.___", state 1376, "(1)" + line 409, "pan.___", state 1376, "(1)" + line 413, "pan.___", state 1384, "(1)" + line 413, "pan.___", state 1385, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1385, "else" + line 413, "pan.___", state 1388, "(1)" + line 413, "pan.___", state 1389, "(1)" + line 413, "pan.___", state 1389, "(1)" + line 411, "pan.___", state 1394, "((i<1))" + line 411, "pan.___", state 1394, "((i>=1))" + line 418, "pan.___", state 1401, "(1)" + line 418, "pan.___", state 1402, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1402, "else" + line 418, "pan.___", state 1405, "(1)" + line 418, "pan.___", state 1406, "(1)" + line 418, "pan.___", state 1406, "(1)" + line 420, "pan.___", state 1409, "(1)" + line 420, "pan.___", state 1409, "(1)" + line 356, "pan.___", state 1415, "((sighand_exec==1))" + line 356, "pan.___", state 1415, "else" + line 362, "pan.___", state 1418, "sighand_exec = 1" + line 399, "pan.___", state 1431, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))" + line 399, "pan.___", state 1433, "(1)" + line 399, "pan.___", state 1434, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))" + line 399, "pan.___", state 1434, "else" + line 399, "pan.___", state 1437, "(1)" + line 403, "pan.___", state 1445, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))" + line 403, "pan.___", state 1447, "(1)" + line 403, "pan.___", state 1448, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))" + line 403, "pan.___", state 1448, "else" + line 403, "pan.___", state 1451, "(1)" + line 403, "pan.___", state 1452, "(1)" + line 403, "pan.___", state 1452, "(1)" + line 401, "pan.___", state 1457, "((i<1))" + line 401, "pan.___", state 1457, "((i>=1))" + line 408, "pan.___", state 1463, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 409, "pan.___", state 1476, "(1)" + line 409, "pan.___", state 1477, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))" + line 409, "pan.___", state 1477, "else" + line 409, "pan.___", state 1480, "(1)" + line 409, "pan.___", state 1481, "(1)" + line 409, "pan.___", state 1481, "(1)" + line 413, "pan.___", state 1489, "(1)" + line 413, "pan.___", state 1490, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))" + line 413, "pan.___", state 1490, "else" + line 413, "pan.___", state 1493, "(1)" + line 413, "pan.___", state 1494, "(1)" + line 413, "pan.___", state 1494, "(1)" + line 411, "pan.___", state 1499, "((i<1))" + line 411, "pan.___", state 1499, "((i>=1))" + line 418, "pan.___", state 1506, "(1)" + line 418, "pan.___", state 1507, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))" + line 418, "pan.___", state 1507, "else" + line 418, "pan.___", state 1510, "(1)" + line 418, "pan.___", state 1511, "(1)" + line 418, "pan.___", state 1511, "(1)" + line 420, "pan.___", state 1514, "(1)" + line 420, "pan.___", state 1514, "(1)" + line 362, "pan.___", state 1523, "sighand_exec = 1" + line 179, "pan.___", state 1548, "(1)" + line 183, "pan.___", state 1559, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))" + line 160, "pan.___", state 1569, "(1)" + line 164, "pan.___", state 1577, "(1)" + line 168, "pan.___", state 1589, "(1)" + line 175, "pan.___", state 1600, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail new file mode 100644 index 0000000..5b0eadd --- /dev/null +++ b/formal-model/urcu-nosched-model/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail @@ -0,0 +1,4231 @@ +-2:3:-2 +-4:-4:-4 +1:0:2965 +2:3:2917 +3:3:2920 +4:3:2920 +5:3:2920 +6:3:2923 +7:3:2931 +8:3:2931 +9:3:2931 +10:3:2934 +11:3:2940 +12:3:2944 +13:3:2944 +14:3:2944 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RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/Makefile b/formal-model/urcu-nosched-model/result-standard-execution-nest/Makefile new file mode 100644 index 0000000..8af320d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/Makefile @@ -0,0 +1,172 @@ +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) Mathieu Desnoyers, 2009 +# +# Authors: Mathieu Desnoyers + +#CFLAGS=-DSAFETY +#for multi-core verif, 15.5GB shared mem, use files if full +#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2 +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8 + +#liveness +#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 +CFLAGS=-DHASH64 + +SPINFILE=urcu.spin + +default: + make urcu_free | tee urcu_free.log + #nested useless with signal test. + #make urcu_free_nested | tee urcu_free_nested.log + make urcu_free_no_rmb | tee urcu_free_no_rmb.log + make urcu_free_no_wmb | tee urcu_free_no_wmb.log + make urcu_free_no_mb | tee urcu_free_no_mb.log + make urcu_free_single_flip | tee urcu_free_single_flip.log + make urcu_progress_writer | tee urcu_progress_writer.log + make urcu_progress_reader | tee urcu_progress_reader.log + make urcu_progress_writer_error | tee urcu_progress_writer_error.log + make asserts | tee asserts.log + make summary + +#show trail : spin -v -t -N pan.ltl input.spin +# after each individual make. + +summary: + @echo + @echo "Verification summary" + @grep errors: *.log + +asserts: clean + cat DEFINES > .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X .input.spin + gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c + ./pan -v -c1 -X -m10000000 -w20 + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free: clean urcu_free_ltl run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_nested_define: + cp urcu_free_nested.define .input.define + +urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_rmb_define: + cp urcu_free_no_rmb.define .input.define + +urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_wmb_define: + cp urcu_free_no_wmb.define .input.define + +urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_no_mb_define: + cp urcu_free_no_mb.define .input.define + +urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_free_single_flip_define: + cp urcu_free_single_flip.define .input.define + +urcu_free_ltl: + touch .input.define + cat .input.define >> pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl + +# Progress checks + +urcu_progress_writer: clean urcu_progress_writer_ltl \ + urcu_progress_writer_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_define: + cp urcu_progress_writer.define .input.define + +urcu_progress_writer_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_reader: clean urcu_progress_reader_ltl \ + urcu_progress_reader_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_reader_define: + cp urcu_progress_reader.define .input.define + +urcu_progress_reader_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + +urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \ + urcu_progress_writer_error_define run_weak_fair + cp .input.spin $@.spin.input + -cp .input.spin.trail $@.spin.input.trail + +urcu_progress_writer_error_define: + cp urcu_progress_writer_error.define .input.define + +urcu_progress_writer_error_ltl: + touch .input.define + cat .input.define > pan.ltl + cat DEFINES >> pan.ltl + spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl + + +run_weak_fair: pan + ./pan -a -f -v -c1 -X -m10000000 -w20 + +run: pan + ./pan -a -v -c1 -X -m10000000 -w20 + +pan: pan.c + gcc -O2 -w ${CFLAGS} -o pan pan.c + +pan.c: pan.ltl ${SPINFILE} + cat .input.define > .input.spin + cat DEFINES >> .input.spin + cat ${SPINFILE} >> .input.spin + rm -f .input.spin.trail + spin -a -X -N pan.ltl .input.spin + +.PHONY: clean default distclean summary +clean: + rm -f pan* trail.out .input.spin* *.spin.trail .input.define +distclean: + rm -f *.trail *.input *.log diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.log new file mode 100644 index 0000000..51f1ac0 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.log @@ -0,0 +1,250 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +cat DEFINES > .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w20 +Depth= 3212 States= 1e+06 Transitions= 1.17e+07 Memory= 519.572 t= 7.66 R= 1e+05 +Depth= 3212 States= 2e+06 Transitions= 2.38e+07 Memory= 572.990 t= 16 R= 1e+05 +Depth= 3212 States= 3e+06 Transitions= 3.62e+07 Memory= 626.408 t= 24.9 R= 1e+05 +pan: resizing hashtable to -w22.. done + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim - (none specified) + assertion violations + + cycle checks - (disabled by -DSAFETY) + invalid end states + + +State-vector 48 byte, depth reached 3212, errors: 0 + 3539988 states, stored + 39085459 states, matched + 42625447 transitions (= stored+matched) +1.5602888e+08 atomic steps +hash conflicts: 28971442 (resolved) + +Stats on memory usage (in Megabytes): + 256.576 equivalent memory usage for states (stored*(State-vector + overhead)) + 196.718 actual memory usage for states (compression: 76.67%) + state-vector as stored = 30 byte + 28 byte overhead + 32.000 memory used for hash table (-w22) + 457.764 memory used for DFS stack (-m10000000) + 686.338 total actual memory usage + +unreached in proctype urcu_reader + line 398, ".input.spin", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 61, "(1)" + line 417, ".input.spin", state 91, "(1)" + line 398, ".input.spin", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 151, "(1)" + line 417, ".input.spin", state 181, "(1)" + line 398, ".input.spin", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 242, "(1)" + line 417, ".input.spin", state 272, "(1)" + line 398, ".input.spin", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 360, "(1)" + line 417, ".input.spin", state 390, "(1)" + line 539, ".input.spin", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 398, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 402, ".input.spin", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 59, "(1)" + line 412, ".input.spin", state 72, "(1)" + line 417, ".input.spin", state 89, "(1)" + line 398, ".input.spin", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 402, ".input.spin", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 153, "(1)" + line 412, ".input.spin", state 166, "(1)" + line 651, ".input.spin", state 199, "(1)" + line 174, ".input.spin", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 178, ".input.spin", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 159, ".input.spin", state 240, "(1)" + line 163, ".input.spin", state 248, "(1)" + line 167, ".input.spin", state 260, "(1)" + line 174, ".input.spin", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 407, ".input.spin", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 927, "(1)" + line 408, ".input.spin", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 408, ".input.spin", state 928, "else" + line 408, ".input.spin", state 931, "(1)" + line 408, ".input.spin", state 932, "(1)" + line 408, ".input.spin", state 932, "(1)" + line 412, ".input.spin", state 940, "(1)" + line 412, ".input.spin", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 412, ".input.spin", state 941, "else" + line 412, ".input.spin", state 944, "(1)" + line 412, ".input.spin", state 945, "(1)" + line 412, ".input.spin", state 945, "(1)" + line 410, ".input.spin", state 950, "((i<1))" + line 410, ".input.spin", state 950, "((i>=1))" + line 417, ".input.spin", state 957, "(1)" + line 417, ".input.spin", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 417, ".input.spin", state 958, "else" + line 417, ".input.spin", state 961, "(1)" + line 417, ".input.spin", state 962, "(1)" + line 417, ".input.spin", state 962, "(1)" + line 419, ".input.spin", state 965, "(1)" + line 419, ".input.spin", state 965, "(1)" + line 402, ".input.spin", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, ".input.spin", state 1040, "(1)" + line 417, ".input.spin", state 1057, "(1)" + line 402, ".input.spin", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, ".input.spin", state 1130, "(1)" + line 417, ".input.spin", state 1147, "(1)" + line 398, ".input.spin", state 1166, "(1)" + line 402, ".input.spin", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, ".input.spin", state 1222, "(1)" + line 417, ".input.spin", state 1239, "(1)" + line 402, ".input.spin", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, ".input.spin", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, ".input.spin", state 1315, "(1)" + line 417, ".input.spin", state 1332, "(1)" + line 178, ".input.spin", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 182, ".input.spin", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, ".input.spin", state 1378, "(1)" + line 163, ".input.spin", state 1386, "(1)" + line 167, ".input.spin", state 1398, "(1)" + line 174, ".input.spin", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 407, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, ".input.spin", state 1595, "(1)" + line 408, ".input.spin", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 408, ".input.spin", state 1596, "else" + line 408, ".input.spin", state 1599, "(1)" + line 408, ".input.spin", state 1600, "(1)" + line 408, ".input.spin", state 1600, "(1)" + line 412, ".input.spin", state 1608, "(1)" + line 412, ".input.spin", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 412, ".input.spin", state 1609, "else" + line 412, ".input.spin", state 1612, "(1)" + line 412, ".input.spin", state 1613, "(1)" + line 412, ".input.spin", state 1613, "(1)" + line 410, ".input.spin", state 1618, "((i<1))" + line 410, ".input.spin", state 1618, "((i>=1))" + line 417, ".input.spin", state 1625, "(1)" + line 417, ".input.spin", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 417, ".input.spin", state 1626, "else" + line 417, ".input.spin", state 1629, "(1)" + line 417, ".input.spin", state 1630, "(1)" + line 417, ".input.spin", state 1630, "(1)" + line 419, ".input.spin", state 1633, "(1)" + line 419, ".input.spin", state 1633, "(1)" + line 178, ".input.spin", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 182, ".input.spin", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, ".input.spin", state 1681, "(1)" + line 163, ".input.spin", state 1689, "(1)" + line 167, ".input.spin", state 1701, "(1)" + line 174, ".input.spin", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.spin.input.trail new file mode 100644 index 0000000..287e52a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/asserts.spin.input.trail @@ -0,0 +1,6 @@ +-4:-4:-4 +1:0:2673 +2:0:2674 +3:0:2675 +4:0:2676 +5:4:1129 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/references.txt b/formal-model/urcu-nosched-model/result-standard-execution-nest/references.txt new file mode 100644 index 0000000..72c67a2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/references.txt @@ -0,0 +1,13 @@ +http://spinroot.com/spin/Man/ltl.html +http://en.wikipedia.org/wiki/Linear_temporal_logic +http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt + +http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php +http://spinroot.com/spin/Man/index.html +http://spinroot.com/spin/Man/promela.html + +LTL vs CTL : + +http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18 +http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf + (downloaded) diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.sh b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.sh new file mode 100644 index 0000000..65ff517 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.sh @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Compiles and runs the urcu.spin Promela model. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Copyright (C) IBM Corporation, 2009 +# Mathieu Desnoyers, 2009 +# +# Authors: Paul E. McKenney +# Mathieu Desnoyers + +# Basic execution, without LTL clauses. See Makefile. + +spin -a urcu.spin +cc -DSAFETY -o pan pan.c +./pan -v -c1 -X -m10000000 -w21 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.spin b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.spin new file mode 100644 index 0000000..2cfcb70 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu.spin @@ -0,0 +1,705 @@ +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.log new file mode 100644 index 0000000..884b15e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.log @@ -0,0 +1,262 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 743) +Depth= 3880 States= 1e+06 Transitions= 1.18e+07 Memory= 527.190 t= 9.53 R= 1e+05 +Depth= 3880 States= 2e+06 Transitions= 2.39e+07 Memory= 588.225 t= 19.8 R= 1e+05 +Depth= 3880 States= 3e+06 Transitions= 3.61e+07 Memory= 649.260 t= 30.5 R= 1e+05 +pan: resizing hashtable to -w22.. done +Depth= 3880 States= 4e+06 Transitions= 4.84e+07 Memory= 741.318 t= 41.1 R= 1e+05 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 3880, errors: 0 + 4015564 states, stored + 44539121 states, matched + 48554685 transitions (= stored+matched) +1.7777933e+08 atomic steps +hash conflicts: 33629695 (resolved) + +Stats on memory usage (in Megabytes): + 321.681 equivalent memory usage for states (stored*(State-vector + overhead)) + 252.629 actual memory usage for states (compression: 78.53%) + state-vector as stored = 38 byte + 28 byte overhead + 32.000 memory used for hash table (-w22) + 457.764 memory used for DFS stack (-m10000000) + 742.295 total actual memory usage + +unreached in proctype urcu_reader + line 398, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 61, "(1)" + line 417, "pan.___", state 91, "(1)" + line 398, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 151, "(1)" + line 417, "pan.___", state 181, "(1)" + line 398, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 242, "(1)" + line 417, "pan.___", state 272, "(1)" + line 398, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 360, "(1)" + line 417, "pan.___", state 390, "(1)" + line 539, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 402, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 59, "(1)" + line 412, "pan.___", state 72, "(1)" + line 417, "pan.___", state 89, "(1)" + line 398, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 402, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 153, "(1)" + line 412, "pan.___", state 166, "(1)" + line 651, "pan.___", state 199, "(1)" + line 174, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 178, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 240, "(1)" + line 163, "pan.___", state 248, "(1)" + line 167, "pan.___", state 260, "(1)" + line 174, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 407, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 927, "(1)" + line 408, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 408, "pan.___", state 928, "else" + line 408, "pan.___", state 931, "(1)" + line 408, "pan.___", state 932, "(1)" + line 408, "pan.___", state 932, "(1)" + line 412, "pan.___", state 940, "(1)" + line 412, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 412, "pan.___", state 941, "else" + line 412, "pan.___", state 944, "(1)" + line 412, "pan.___", state 945, "(1)" + line 412, "pan.___", state 945, "(1)" + line 410, "pan.___", state 950, "((i<1))" + line 410, "pan.___", state 950, "((i>=1))" + line 417, "pan.___", state 957, "(1)" + line 417, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 417, "pan.___", state 958, "else" + line 417, "pan.___", state 961, "(1)" + line 417, "pan.___", state 962, "(1)" + line 417, "pan.___", state 962, "(1)" + line 419, "pan.___", state 965, "(1)" + line 419, "pan.___", state 965, "(1)" + line 402, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, "pan.___", state 1040, "(1)" + line 417, "pan.___", state 1057, "(1)" + line 402, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, "pan.___", state 1130, "(1)" + line 417, "pan.___", state 1147, "(1)" + line 398, "pan.___", state 1166, "(1)" + line 402, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, "pan.___", state 1222, "(1)" + line 417, "pan.___", state 1239, "(1)" + line 402, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 407, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 412, "pan.___", state 1315, "(1)" + line 417, "pan.___", state 1332, "(1)" + line 178, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 182, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 1378, "(1)" + line 163, "pan.___", state 1386, "(1)" + line 167, "pan.___", state 1398, "(1)" + line 174, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 407, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1595, "(1)" + line 408, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 408, "pan.___", state 1596, "else" + line 408, "pan.___", state 1599, "(1)" + line 408, "pan.___", state 1600, "(1)" + line 408, "pan.___", state 1600, "(1)" + line 412, "pan.___", state 1608, "(1)" + line 412, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 412, "pan.___", state 1609, "else" + line 412, "pan.___", state 1612, "(1)" + line 412, "pan.___", state 1613, "(1)" + line 412, "pan.___", state 1613, "(1)" + line 410, "pan.___", state 1618, "((i<1))" + line 410, "pan.___", state 1618, "((i>=1))" + line 417, "pan.___", state 1625, "(1)" + line 417, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 417, "pan.___", state 1626, "else" + line 417, "pan.___", state 1629, "(1)" + line 417, "pan.___", state 1630, "(1)" + line 417, "pan.___", state 1630, "(1)" + line 419, "pan.___", state 1633, "(1)" + line 419, "pan.___", state 1633, "(1)" + line 178, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 182, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 159, "pan.___", state 1681, "(1)" + line 163, "pan.___", state 1689, "(1)" + line 167, "pan.___", state 1701, "(1)" + line 174, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< !read_free_race) diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input new file mode 100644 index 0000000..f2f00e4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input @@ -0,0 +1,722 @@ + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +//#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input.trail new file mode 100644 index 0000000..837f3d9 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free.spin.input.trail @@ -0,0 +1,15043 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 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+#define READER_NEST_LEVEL 2 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.log new file mode 100644 index 0000000..d503334 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.log @@ -0,0 +1,20 @@ +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_nested.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 742) +Depth= 3880 States= 1e+06 Transitions= 1.18e+07 Memory= 527.190 t= 9.48 R= 1e+05 +Depth= 3880 States= 2e+06 Transitions= 2.39e+07 Memory= 588.225 t= 19.6 R= 1e+05 +Depth= 3880 States= 3e+06 Transitions= 3.61e+07 Memory= 649.260 t= 30.3 R= 1e+05 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input new file mode 100644 index 0000000..c94928c --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input @@ -0,0 +1,696 @@ +#define READER_NEST_LEVEL 1 + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +#define TEST_SIGNAL +#define TEST_SIGNAL_ON_READ + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE +#define get_pid() ((_pid < 1) -> 0 : 1) +#elif defined(TEST_SIGNAL_ON_READ) +#define get_pid() ((_pid < 2) -> 0 : 1) +#else +#define get_pid() (_pid) +#endif + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb(i, j) +{ + if + :: get_pid() >= NR_READERS -> + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); + :: else -> skip; + fi; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +#define get_readerid() (get_pid()) +#define get_writerid() (get_readerid() + NR_READERS) + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + dispatch_sighand_read_exec(); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 1; + ooo_mem(i); + dispatch_sighand_read_exec(); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + ooo_mem(i); + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + ooo_mem(i); + data_access[get_readerid()] = 1; + ooo_mem(i); + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS + /* Only test progress of one random reader. They are all the + * same. */ + if + :: get_readerid() == 0 -> +progress_reader: + skip; + fi; +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input.trail new file mode 100644 index 0000000..6f29ad2 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_nested.spin.input.trail @@ -0,0 +1,11161 @@ +-2:4:-2 +-4:-4:-4 +1:0:4365 +2:4:4317 +3:4:4320 +4:4:4320 +5:4:4320 +6:4:4323 +7:4:4331 +8:4:4331 +9:4:4331 +10:4:4334 +11:4:4340 +12:4:4344 +13:4:4344 +14:4:4344 +15:4:4347 +16:4:4340 +17:4:4344 +18:4:4344 +19:4:4344 +20:4:4347 +21:4:4355 +22:4:4359 +23:4:4360 +24:0:4365 +25:4:4362 +26:0:4365 +27:3:2331 +28:0:4365 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b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.define new file mode 100644 index 0000000..136ef67 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.define @@ -0,0 +1,2 @@ +#define NO_RMB +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.log new file mode 100644 index 0000000..27a963a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.log @@ -0,0 +1,267 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_mb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 745) +Depth= 11386 States= 1e+06 Transitions= 1.56e+07 Memory= 527.287 t= 12.8 R= 8e+04 +pan: claim violated! (at depth 2146) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 72 byte, depth reached 11386, errors: 1 + 1223588 states, stored + 17987399 states, matched + 19210987 transitions (= stored+matched) + 70012127 atomic steps +hash conflicts: 4173157 (resolved) + +Stats on memory usage (in Megabytes): + 116.690 equivalent memory usage for states (stored*(State-vector + overhead)) + 75.177 actual memory usage for states (compression: 64.42%) + state-vector as stored = 36 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 540.861 total actual memory usage + +unreached in proctype urcu_reader + line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 61, "(1)" + line 419, "pan.___", state 91, "(1)" + line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 151, "(1)" + line 419, "pan.___", state 181, "(1)" + line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 242, "(1)" + line 419, "pan.___", state 272, "(1)" + line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 331, "(1)" + line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 360, "(1)" + line 419, "pan.___", state 390, "(1)" + line 541, "pan.___", state 414, "-end-" + (18 of 414 states) +unreached in proctype urcu_writer + line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 20, "(1)" + line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 34, "(1)" + line 404, "pan.___", state 35, "(1)" + line 404, "pan.___", state 35, "(1)" + line 402, "pan.___", state 40, "((i<1))" + line 402, "pan.___", state 40, "((i>=1))" + line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 59, "(1)" + line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 60, "else" + line 410, "pan.___", state 63, "(1)" + line 410, "pan.___", state 64, "(1)" + line 410, "pan.___", state 64, "(1)" + line 414, "pan.___", state 72, "(1)" + line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 73, "else" + line 414, "pan.___", state 76, "(1)" + line 414, "pan.___", state 77, "(1)" + line 414, "pan.___", state 77, "(1)" + line 412, "pan.___", state 82, "((i<1))" + line 412, "pan.___", state 82, "((i>=1))" + line 419, "pan.___", state 89, "(1)" + line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 90, "else" + line 419, "pan.___", state 93, "(1)" + line 419, "pan.___", state 94, "(1)" + line 419, "pan.___", state 94, "(1)" + line 421, "pan.___", state 97, "(1)" + line 421, "pan.___", state 97, "(1)" + line 370, "pan.___", state 99, "(1)" + line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]" + line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 114, "(1)" + line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 128, "(1)" + line 404, "pan.___", state 129, "(1)" + line 404, "pan.___", state 129, "(1)" + line 410, "pan.___", state 153, "(1)" + line 414, "pan.___", state 166, "(1)" + line 421, "pan.___", state 191, "(1)" + line 421, "pan.___", state 191, "(1)" + line 653, "pan.___", state 199, "(1)" + line 400, "pan.___", state 209, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 223, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 254, "(1)" + line 414, "pan.___", state 267, "(1)" + line 400, "pan.___", state 300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 314, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 345, "(1)" + line 414, "pan.___", state 358, "(1)" + line 400, "pan.___", state 395, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 409, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 440, "(1)" + line 414, "pan.___", state 453, "(1)" + line 400, "pan.___", state 488, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 533, "(1)" + line 414, "pan.___", state 546, "(1)" + line 400, "pan.___", state 582, "(1)" + line 404, "pan.___", state 594, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 638, "(1)" + line 404, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 731, "(1)" + line 404, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 821, "(1)" + line 419, "pan.___", state 838, "(1)" + line 404, "pan.___", state 868, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 886, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 912, "(1)" + line 419, "pan.___", state 929, "(1)" + line 404, "pan.___", state 963, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 981, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1007, "(1)" + line 419, "pan.___", state 1024, "(1)" + line 400, "pan.___", state 1050, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 1052, "(1)" + line 400, "pan.___", state 1053, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 1053, "else" + line 400, "pan.___", state 1056, "(1)" + line 404, "pan.___", state 1064, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 1066, "(1)" + line 404, "pan.___", state 1067, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 404, "pan.___", state 1067, "else" + line 404, "pan.___", state 1070, "(1)" + line 404, "pan.___", state 1071, "(1)" + line 404, "pan.___", state 1071, "(1)" + line 402, "pan.___", state 1076, "((i<1))" + line 402, "pan.___", state 1076, "((i>=1))" + line 409, "pan.___", state 1082, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 1095, "(1)" + line 410, "pan.___", state 1096, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 1096, "else" + line 410, "pan.___", state 1099, "(1)" + line 410, "pan.___", state 1100, "(1)" + line 410, "pan.___", state 1100, "(1)" + line 414, "pan.___", state 1108, "(1)" + line 414, "pan.___", state 1109, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 1109, "else" + line 414, "pan.___", state 1112, "(1)" + line 414, "pan.___", state 1113, "(1)" + line 414, "pan.___", state 1113, "(1)" + line 412, "pan.___", state 1118, "((i<1))" + line 412, "pan.___", state 1118, "((i>=1))" + line 419, "pan.___", state 1125, "(1)" + line 419, "pan.___", state 1126, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 1126, "else" + line 419, "pan.___", state 1129, "(1)" + line 419, "pan.___", state 1130, "(1)" + line 419, "pan.___", state 1130, "(1)" + line 421, "pan.___", state 1133, "(1)" + line 421, "pan.___", state 1133, "(1)" + line 404, "pan.___", state 1164, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1208, "(1)" + line 404, "pan.___", state 1254, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1298, "(1)" + line 400, "pan.___", state 1334, "(1)" + line 404, "pan.___", state 1346, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1390, "(1)" + line 404, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1483, "(1)" + line 404, "pan.___", state 1529, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1547, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1573, "(1)" + line 419, "pan.___", state 1590, "(1)" + line 404, "pan.___", state 1620, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1638, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1664, "(1)" + line 419, "pan.___", state 1681, "(1)" + line 404, "pan.___", state 1715, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1733, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1759, "(1)" + line 419, "pan.___", state 1776, "(1)" + line 400, "pan.___", state 1802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 1804, "(1)" + line 400, "pan.___", state 1805, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 1805, "else" + line 400, "pan.___", state 1808, "(1)" + line 404, "pan.___", state 1816, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 1818, "(1)" + line 404, "pan.___", state 1819, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 404, "pan.___", state 1819, "else" + line 404, "pan.___", state 1822, "(1)" + line 404, "pan.___", state 1823, "(1)" + line 404, "pan.___", state 1823, "(1)" + line 402, "pan.___", state 1828, "((i<1))" + line 402, "pan.___", state 1828, "((i>=1))" + line 409, "pan.___", state 1834, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 1847, "(1)" + line 410, "pan.___", state 1848, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 1848, "else" + line 410, "pan.___", state 1851, "(1)" + line 410, "pan.___", state 1852, "(1)" + line 410, "pan.___", state 1852, "(1)" + line 414, "pan.___", state 1860, "(1)" + line 414, "pan.___", state 1861, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 1861, "else" + line 414, "pan.___", state 1864, "(1)" + line 414, "pan.___", state 1865, "(1)" + line 414, "pan.___", state 1865, "(1)" + line 412, "pan.___", state 1870, "((i<1))" + line 412, "pan.___", state 1870, "((i>=1))" + line 419, "pan.___", state 1877, "(1)" + line 419, "pan.___", state 1878, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 1878, "else" + line 419, "pan.___", state 1881, "(1)" + line 419, "pan.___", state 1882, "(1)" + line 419, "pan.___", state 1882, "(1)" + line 421, "pan.___", state 1885, "(1)" + line 421, "pan.___", state 1885, "(1)" + line 404, "pan.___", state 1916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1960, "(1)" + line 404, "pan.___", state 2007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 2051, "(1)" + line 404, "pan.___", state 2102, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 2146, "(1)" + line 703, "pan.___", state 2192, "-end-" + (144 of 2192 states) +unreached in proctype :init: + line 710, "pan.___", state 9, "((j<2))" + line 710, "pan.___", state 9, "((j>=2))" + line 711, "pan.___", state 20, "((j<2))" + line 711, "pan.___", state 20, "((j>=2))" + line 716, "pan.___", state 33, "((j<2))" + line 716, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 750, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 15.9 seconds +pan: rate 77100.693 states/second +pan: avg transition delay 8.2609e-07 usec +cp .input.spin urcu_free_no_mb.spin.input +cp .input.spin.trail urcu_free_no_mb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input new file mode 100644 index 0000000..927df3f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input @@ -0,0 +1,724 @@ +#define NO_RMB +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +//#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail new file mode 100644 index 0000000..04e7425 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail @@ -0,0 +1,2149 @@ +-2:3:-2 +-4:-4:-4 +1:0:2654 +2:3:2606 +3:3:2609 +4:3:2609 +5:3:2612 +6:3:2620 +7:3:2620 +8:3:2623 +9:3:2629 +10:3:2633 +11:3:2633 +12:3:2636 +13:3:2644 +14:3:2648 +15:3:2649 +16:0:2654 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b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.define new file mode 100644 index 0000000..73e61a4 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.define @@ -0,0 +1 @@ +#define NO_RMB diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.log new file mode 100644 index 0000000..b7f3b80 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.log @@ -0,0 +1,266 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_rmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +Depth= 5439 States= 1e+06 Transitions= 1.03e+07 Memory= 527.190 t= 8.16 R= 1e+05 +pan: claim violated! (at depth 1801) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 5439, errors: 1 + 1006552 states, stored + 9396280 states, matched + 10402832 transitions (= stored+matched) + 36844262 atomic steps +hash conflicts: 1832712 (resolved) + +Stats on memory usage (in Megabytes): + 80.634 equivalent memory usage for states (stored*(State-vector + overhead)) + 61.871 actual memory usage for states (compression: 76.73%) + state-vector as stored = 36 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 527.580 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 151, "(1)" + line 418, "pan.___", state 181, "(1)" + line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 242, "(1)" + line 418, "pan.___", state 272, "(1)" + line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 360, "(1)" + line 418, "pan.___", state 390, "(1)" + line 540, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 20, "(1)" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 34, "(1)" + line 403, "pan.___", state 35, "(1)" + line 403, "pan.___", state 35, "(1)" + line 401, "pan.___", state 40, "((i<1))" + line 401, "pan.___", state 40, "((i>=1))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 59, "(1)" + line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 60, "else" + line 409, "pan.___", state 63, "(1)" + line 409, "pan.___", state 64, "(1)" + line 409, "pan.___", state 64, "(1)" + line 413, "pan.___", state 72, "(1)" + line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 73, "else" + line 413, "pan.___", state 76, "(1)" + line 413, "pan.___", state 77, "(1)" + line 413, "pan.___", state 77, "(1)" + line 411, "pan.___", state 82, "((i<1))" + line 411, "pan.___", state 82, "((i>=1))" + line 418, "pan.___", state 89, "(1)" + line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 90, "else" + line 418, "pan.___", state 93, "(1)" + line 418, "pan.___", state 94, "(1)" + line 418, "pan.___", state 94, "(1)" + line 420, "pan.___", state 97, "(1)" + line 420, "pan.___", state 97, "(1)" + line 369, "pan.___", state 99, "(1)" + line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 114, "(1)" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 128, "(1)" + line 403, "pan.___", state 129, "(1)" + line 403, "pan.___", state 129, "(1)" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 420, "pan.___", state 191, "(1)" + line 420, "pan.___", state 191, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 175, "pan.___", state 243, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 746, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 759, "(1)" + line 409, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 760, "else" + line 409, "pan.___", state 763, "(1)" + line 409, "pan.___", state 764, "(1)" + line 409, "pan.___", state 764, "(1)" + line 413, "pan.___", state 772, "(1)" + line 413, "pan.___", state 773, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 773, "else" + line 413, "pan.___", state 776, "(1)" + line 413, "pan.___", state 777, "(1)" + line 413, "pan.___", state 777, "(1)" + line 411, "pan.___", state 782, "((i<1))" + line 411, "pan.___", state 782, "((i>=1))" + line 418, "pan.___", state 789, "(1)" + line 418, "pan.___", state 790, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 790, "else" + line 418, "pan.___", state 793, "(1)" + line 418, "pan.___", state 794, "(1)" + line 418, "pan.___", state 794, "(1)" + line 420, "pan.___", state 797, "(1)" + line 420, "pan.___", state 797, "(1)" + line 403, "pan.___", state 828, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 846, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 872, "(1)" + line 418, "pan.___", state 889, "(1)" + line 403, "pan.___", state 918, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 936, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 962, "(1)" + line 418, "pan.___", state 979, "(1)" + line 399, "pan.___", state 998, "(1)" + line 403, "pan.___", state 1010, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1028, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1054, "(1)" + line 418, "pan.___", state 1071, "(1)" + line 403, "pan.___", state 1103, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1121, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1147, "(1)" + line 418, "pan.___", state 1164, "(1)" + line 179, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1200, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 175, "pan.___", state 1213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 1330, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1343, "(1)" + line 409, "pan.___", state 1344, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 1344, "else" + line 409, "pan.___", state 1347, "(1)" + line 409, "pan.___", state 1348, "(1)" + line 409, "pan.___", state 1348, "(1)" + line 413, "pan.___", state 1356, "(1)" + line 413, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 1357, "else" + line 413, "pan.___", state 1360, "(1)" + line 413, "pan.___", state 1361, "(1)" + line 413, "pan.___", state 1361, "(1)" + line 411, "pan.___", state 1366, "((i<1))" + line 411, "pan.___", state 1366, "((i>=1))" + line 418, "pan.___", state 1373, "(1)" + line 418, "pan.___", state 1374, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 1374, "else" + line 418, "pan.___", state 1377, "(1)" + line 418, "pan.___", state 1378, "(1)" + line 418, "pan.___", state 1378, "(1)" + line 420, "pan.___", state 1381, "(1)" + line 420, "pan.___", state 1381, "(1)" + line 179, "pan.___", state 1406, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1419, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 175, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 8.24 seconds +pan: rate 122154.37 states/second +pan: avg transition delay 7.9209e-07 usec +cp .input.spin urcu_free_no_rmb.spin.input +cp .input.spin.trail urcu_free_no_rmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input new file mode 100644 index 0000000..6dea6e1 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input @@ -0,0 +1,723 @@ +#define NO_RMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +//#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail new file mode 100644 index 0000000..071a19e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail @@ -0,0 +1,1804 @@ +-2:3:-2 +-4:-4:-4 +1:0:1982 +2:3:1934 +3:3:1937 +4:3:1937 +5:3:1940 +6:3:1948 +7:3:1948 +8:3:1951 +9:3:1957 +10:3:1961 +11:3:1961 +12:3:1964 +13:3:1972 +14:3:1976 +15:3:1977 +16:0:1982 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+1772:2:1927 +1773:0:1982 +1774:1:285 +1775:0:1982 +1776:2:1928 +1777:0:1982 +1778:1:286 +1779:0:1982 +1780:2:1927 +1781:0:1982 +1782:1:291 +1783:0:1982 +1784:2:1928 +1785:0:1982 +1786:1:293 +1787:0:1982 +1788:2:1927 +1789:0:1982 +1790:1:296 +1791:0:1982 +1792:2:1928 +1793:0:1982 +1794:1:301 +1795:0:1982 +1796:2:1927 +1797:0:1982 +1798:1:302 +1799:0:1980 +1800:2:1928 +1801:0:1986 +1802:1:124 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.define b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.define new file mode 100644 index 0000000..710f29d --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.define @@ -0,0 +1 @@ +#define NO_WMB diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.log new file mode 100644 index 0000000..4dd3892 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.log @@ -0,0 +1,294 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_no_wmb.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +pan: claim violated! (at depth 1882) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 4174, errors: 1 + 367189 states, stored + 3431533 states, matched + 3798722 transitions (= stored+matched) + 13407384 atomic steps +hash conflicts: 253700 (resolved) + +Stats on memory usage (in Megabytes): + 29.415 equivalent memory usage for states (stored*(State-vector + overhead)) + 22.811 actual memory usage for states (compression: 77.55%) + state-vector as stored = 37 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 488.518 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 151, "(1)" + line 418, "pan.___", state 181, "(1)" + line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 242, "(1)" + line 418, "pan.___", state 272, "(1)" + line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 331, "(1)" + line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 360, "(1)" + line 418, "pan.___", state 390, "(1)" + line 540, "pan.___", state 414, "-end-" + (18 of 414 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 20, "(1)" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 34, "(1)" + line 403, "pan.___", state 35, "(1)" + line 403, "pan.___", state 35, "(1)" + line 401, "pan.___", state 40, "((i<1))" + line 401, "pan.___", state 40, "((i>=1))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 59, "(1)" + line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 60, "else" + line 409, "pan.___", state 63, "(1)" + line 409, "pan.___", state 64, "(1)" + line 409, "pan.___", state 64, "(1)" + line 413, "pan.___", state 72, "(1)" + line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 73, "else" + line 413, "pan.___", state 76, "(1)" + line 413, "pan.___", state 77, "(1)" + line 413, "pan.___", state 77, "(1)" + line 411, "pan.___", state 82, "((i<1))" + line 411, "pan.___", state 82, "((i>=1))" + line 418, "pan.___", state 89, "(1)" + line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 90, "else" + line 418, "pan.___", state 93, "(1)" + line 418, "pan.___", state 94, "(1)" + line 418, "pan.___", state 94, "(1)" + line 420, "pan.___", state 97, "(1)" + line 420, "pan.___", state 97, "(1)" + line 369, "pan.___", state 99, "(1)" + line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 114, "(1)" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 128, "(1)" + line 403, "pan.___", state 129, "(1)" + line 403, "pan.___", state 129, "(1)" + line 401, "pan.___", state 134, "((i<1))" + line 401, "pan.___", state 134, "((i>=1))" + line 409, "pan.___", state 153, "(1)" + line 409, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 154, "else" + line 409, "pan.___", state 157, "(1)" + line 409, "pan.___", state 158, "(1)" + line 409, "pan.___", state 158, "(1)" + line 413, "pan.___", state 166, "(1)" + line 413, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 167, "else" + line 413, "pan.___", state 170, "(1)" + line 413, "pan.___", state 171, "(1)" + line 413, "pan.___", state 171, "(1)" + line 411, "pan.___", state 176, "((i<1))" + line 411, "pan.___", state 176, "((i>=1))" + line 418, "pan.___", state 183, "(1)" + line 418, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 184, "else" + line 418, "pan.___", state 187, "(1)" + line 418, "pan.___", state 188, "(1)" + line 418, "pan.___", state 188, "(1)" + line 420, "pan.___", state 191, "(1)" + line 420, "pan.___", state 191, "(1)" + line 369, "pan.___", state 193, "(1)" + line 652, "pan.___", state 199, "(1)" + line 646, "pan.___", state 202, "((write_lock==0))" + line 646, "pan.___", state 202, "else" + line 644, "pan.___", state 203, "(1)" + line 160, "pan.___", state 209, "(1)" + line 164, "pan.___", state 217, "(1)" + line 164, "pan.___", state 218, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 164, "pan.___", state 218, "else" + line 162, "pan.___", state 223, "((j<1))" + line 162, "pan.___", state 223, "((j>=1))" + line 168, "pan.___", state 229, "(1)" + line 168, "pan.___", state 230, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 168, "pan.___", state 230, "else" + line 160, "pan.___", state 241, "(1)" + line 168, "pan.___", state 261, "(1)" + line 160, "pan.___", state 277, "(1)" + line 164, "pan.___", state 285, "(1)" + line 168, "pan.___", state 297, "(1)" + line 399, "pan.___", state 311, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 325, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 343, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 356, "(1)" + line 413, "pan.___", state 369, "(1)" + line 418, "pan.___", state 386, "(1)" + line 399, "pan.___", state 405, "(1)" + line 403, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 461, "(1)" + line 418, "pan.___", state 478, "(1)" + line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 554, "(1)" + line 418, "pan.___", state 571, "(1)" + line 164, "pan.___", state 594, "(1)" + line 168, "pan.___", state 606, "(1)" + line 160, "pan.___", state 618, "(1)" + line 168, "pan.___", state 638, "(1)" + line 164, "pan.___", state 662, "(1)" + line 168, "pan.___", state 674, "(1)" + line 399, "pan.___", state 696, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 698, "(1)" + line 399, "pan.___", state 699, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 399, "pan.___", state 699, "else" + line 399, "pan.___", state 702, "(1)" + line 403, "pan.___", state 710, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 712, "(1)" + line 403, "pan.___", state 713, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 403, "pan.___", state 713, "else" + line 403, "pan.___", state 716, "(1)" + line 403, "pan.___", state 717, "(1)" + line 403, "pan.___", state 717, "(1)" + line 401, "pan.___", state 722, "((i<1))" + line 401, "pan.___", state 722, "((i>=1))" + line 408, "pan.___", state 728, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 741, "(1)" + line 409, "pan.___", state 742, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 742, "else" + line 409, "pan.___", state 745, "(1)" + line 409, "pan.___", state 746, "(1)" + line 409, "pan.___", state 746, "(1)" + line 413, "pan.___", state 754, "(1)" + line 413, "pan.___", state 755, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 755, "else" + line 413, "pan.___", state 758, "(1)" + line 413, "pan.___", state 759, "(1)" + line 413, "pan.___", state 759, "(1)" + line 411, "pan.___", state 764, "((i<1))" + line 411, "pan.___", state 764, "((i>=1))" + line 418, "pan.___", state 771, "(1)" + line 418, "pan.___", state 772, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 772, "else" + line 418, "pan.___", state 775, "(1)" + line 418, "pan.___", state 776, "(1)" + line 418, "pan.___", state 776, "(1)" + line 420, "pan.___", state 779, "(1)" + line 420, "pan.___", state 779, "(1)" + line 403, "pan.___", state 810, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 828, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 854, "(1)" + line 418, "pan.___", state 871, "(1)" + line 403, "pan.___", state 900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 918, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 944, "(1)" + line 418, "pan.___", state 961, "(1)" + line 399, "pan.___", state 980, "(1)" + line 403, "pan.___", state 992, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1010, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1036, "(1)" + line 418, "pan.___", state 1053, "(1)" + line 403, "pan.___", state 1085, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1103, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1129, "(1)" + line 418, "pan.___", state 1146, "(1)" + line 164, "pan.___", state 1169, "(1)" + line 168, "pan.___", state 1181, "(1)" + line 160, "pan.___", state 1193, "(1)" + line 168, "pan.___", state 1213, "(1)" + line 164, "pan.___", state 1237, "(1)" + line 168, "pan.___", state 1249, "(1)" + line 399, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 399, "pan.___", state 1273, "(1)" + line 399, "pan.___", state 1274, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 399, "pan.___", state 1274, "else" + line 399, "pan.___", state 1277, "(1)" + line 403, "pan.___", state 1285, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 1287, "(1)" + line 403, "pan.___", state 1288, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 403, "pan.___", state 1288, "else" + line 403, "pan.___", state 1291, "(1)" + line 403, "pan.___", state 1292, "(1)" + line 403, "pan.___", state 1292, "(1)" + line 401, "pan.___", state 1297, "((i<1))" + line 401, "pan.___", state 1297, "((i>=1))" + line 408, "pan.___", state 1303, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1316, "(1)" + line 409, "pan.___", state 1317, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 1317, "else" + line 409, "pan.___", state 1320, "(1)" + line 409, "pan.___", state 1321, "(1)" + line 409, "pan.___", state 1321, "(1)" + line 413, "pan.___", state 1329, "(1)" + line 413, "pan.___", state 1330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 1330, "else" + line 413, "pan.___", state 1333, "(1)" + line 413, "pan.___", state 1334, "(1)" + line 413, "pan.___", state 1334, "(1)" + line 411, "pan.___", state 1339, "((i<1))" + line 411, "pan.___", state 1339, "((i>=1))" + line 418, "pan.___", state 1346, "(1)" + line 418, "pan.___", state 1347, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 1347, "else" + line 418, "pan.___", state 1350, "(1)" + line 418, "pan.___", state 1351, "(1)" + line 418, "pan.___", state 1351, "(1)" + line 420, "pan.___", state 1354, "(1)" + line 420, "pan.___", state 1354, "(1)" + line 164, "pan.___", state 1379, "(1)" + line 168, "pan.___", state 1391, "(1)" + line 160, "pan.___", state 1403, "(1)" + line 168, "pan.___", state 1423, "(1)" + line 164, "pan.___", state 1447, "(1)" + line 168, "pan.___", state 1459, "(1)" + line 702, "pan.___", state 1484, "-end-" + (160 of 1484 states) +unreached in proctype :init: + line 709, "pan.___", state 9, "((j<2))" + line 709, "pan.___", state 9, "((j>=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 2.96 seconds +pan: rate 124050.34 states/second +pan: avg transition delay 7.7921e-07 usec +cp .input.spin urcu_free_no_wmb.spin.input +cp .input.spin.trail urcu_free_no_wmb.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input new file mode 100644 index 0000000..f4d8acb --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input @@ -0,0 +1,723 @@ +#define NO_WMB + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +//#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail new file mode 100644 index 0000000..f73a838 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail @@ -0,0 +1,1885 @@ +-2:3:-2 +-4:-4:-4 +1:0:1946 +2:3:1898 +3:3:1901 +4:3:1901 +5:3:1904 +6:3:1912 +7:3:1912 +8:3:1915 +9:3:1921 +10:3:1925 +11:3:1925 +12:3:1928 +13:3:1936 +14:3:1940 +15:3:1941 +16:0:1946 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+1864:2:1856 +1865:2:1857 +1866:2:1864 +1867:2:1869 +1868:0:1946 +1869:2:1880 +1870:0:1946 +1871:2:1882 +1872:0:1946 +1873:2:1883 +1874:0:1946 +1875:2:1886 +1876:0:1946 +1877:2:1891 +1878:0:1946 +1879:1:302 +1880:0:1944 +1881:2:1892 +1882:0:1950 +1883:1:143 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.define b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.define new file mode 100644 index 0000000..5e642ef --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.define @@ -0,0 +1 @@ +#define SINGLE_FLIP diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.log new file mode 100644 index 0000000..2a80112 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.log @@ -0,0 +1,197 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define >> pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_free_single_flip.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +pan: claim violated! (at depth 1371) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness disabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 3387, errors: 1 + 206295 states, stored + 1902753 states, matched + 2109048 transitions (= stored+matched) + 7663223 atomic steps +hash conflicts: 101109 (resolved) + +Stats on memory usage (in Megabytes): + 16.526 equivalent memory usage for states (stored*(State-vector + overhead)) + 13.080 actual memory usage for states (compression: 79.15%) + state-vector as stored = 38 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 478.752 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 151, "(1)" + line 418, "pan.___", state 181, "(1)" + line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 242, "(1)" + line 418, "pan.___", state 272, "(1)" + line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 360, "(1)" + line 418, "pan.___", state 390, "(1)" + line 540, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 179, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1003, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 1013, "(1)" + line 164, "pan.___", state 1021, "(1)" + line 168, "pan.___", state 1033, "(1)" + line 175, "pan.___", state 1044, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=2))" + line 710, "pan.___", state 20, "((j<2))" + line 710, "pan.___", state 20, "((j>=2))" + line 715, "pan.___", state 33, "((j<2))" + line 715, "pan.___", state 33, "((j>=2))" + (3 of 46 states) +unreached in proctype :never: + line 749, "pan.___", state 8, "-end-" + (1 of 8 states) + +pan: elapsed time 1.66 seconds +pan: rate 124274.1 states/second +pan: avg transition delay 7.8708e-07 usec +cp .input.spin urcu_free_single_flip.spin.input +cp .input.spin.trail urcu_free_single_flip.spin.input.trail +make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input new file mode 100644 index 0000000..93aae44 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input @@ -0,0 +1,723 @@ +#define SINGLE_FLIP + +#define read_free_race (read_generation[0] == last_free_gen) +#define read_free (free_done && data_access[0]) + +//#define TEST_SIGNAL +//#define TEST_SIGNAL_ON_READ +//#define TEST_SIGNAL_ON_WRITE + +#define RCU_GP_CTR_BIT (1 << 7) +#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1) + +#ifndef READER_NEST_LEVEL +//#define READER_NEST_LEVEL 1 +#define READER_NEST_LEVEL 2 +#endif + +#define REMOTE_BARRIERS +/* + * mem.spin: Promela code to validate memory barriers with OOO memory. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (c) 2009 Mathieu Desnoyers + */ + +/* Promela validation variables. */ + +/* specific defines "included" here */ +/* DEFINES file "included" here */ + +/* All signal readers have same PID and uses same reader variable */ +#ifdef TEST_SIGNAL_ON_WRITE + +#define NR_READERS 1 /* the writer is also a signal reader */ +#define NR_WRITERS 1 + +#define NR_PROCS 1 + +#define get_pid() (0) + +#elif defined(TEST_SIGNAL_ON_READ) + +#define get_pid() ((_pid < 2) -> 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail new file mode 100644 index 0000000..73c1400 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail @@ -0,0 +1,1374 @@ +-2:3:-2 +-4:-4:-4 +1:0:1650 +2:3:1602 +3:3:1605 +4:3:1605 +5:3:1608 +6:3:1616 +7:3:1616 +8:3:1619 +9:3:1625 +10:3:1629 +11:3:1629 +12:3:1632 +13:3:1640 +14:3:1644 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file mode 100644 index 0000000..8718641 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress.ltl @@ -0,0 +1 @@ +([] <> !np_) diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.define b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.define new file mode 100644 index 0000000..ff3f783 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.define @@ -0,0 +1 @@ +#define READER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.log new file mode 100644 index 0000000..9e98b9f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.log @@ -0,0 +1,275 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_reader.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +depth 15: Claim reached state 9 (line 749) +depth 1767: Claim reached state 9 (line 748) +Depth= 3880 States= 1e+06 Transitions= 1.71e+07 Memory= 499.651 t= 14.5 R= 7e+04 +Depth= 3880 States= 2e+06 Transitions= 3.79e+07 Memory= 532.365 t= 32.3 R= 6e+04 +Depth= 3880 States= 3e+06 Transitions= 5.83e+07 Memory= 564.983 t= 50.2 R= 6e+04 +pan: resizing hashtable to -w22.. done +Depth= 3880 States= 4e+06 Transitions= 7.76e+07 Memory= 629.307 t= 67 R= 6e+04 +Depth= 3880 States= 5e+06 Transitions= 9.78e+07 Memory= 662.315 t= 84.2 R= 6e+04 +Depth= 3880 States= 6e+06 Transitions= 1.19e+08 Memory= 694.736 t= 102 R= 6e+04 +Depth= 3880 States= 7e+06 Transitions= 1.38e+08 Memory= 727.842 t= 119 R= 6e+04 +Depth= 3880 States= 8e+06 Transitions= 1.59e+08 Memory= 760.752 t= 137 R= 6e+04 +Depth= 3880 States= 9e+06 Transitions= 1.79e+08 Memory= 793.174 t= 155 R= 6e+04 +pan: resizing hashtable to -w24.. done +Depth= 3880 States= 1e+07 Transitions= 1.98e+08 Memory= 950.568 t= 172 R= 6e+04 +Depth= 3880 States= 1.1e+07 Transitions= 2.19e+08 Memory= 983.479 t= 189 R= 6e+04 +Depth= 3880 States= 1.2e+07 Transitions= 2.4e+08 Memory= 1015.901 t= 207 R= 6e+04 +Depth= 3880 States= 1.3e+07 Transitions= 2.58e+08 Memory= 1049.397 t= 223 R= 6e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 3880, errors: 0 + 7197860 states, stored (1.33457e+07 visited) +2.5266654e+08 states, matched +2.6601223e+08 transitions (= visited+matched) +9.9067284e+08 atomic steps +hash conflicts: 87783920 (resolved) + +Stats on memory usage (in Megabytes): + 576.611 equivalent memory usage for states (stored*(State-vector + overhead)) + 474.839 actual memory usage for states (compression: 82.35%) + state-vector as stored = 41 byte + 28 byte overhead + 128.000 memory used for hash table (-w24) + 457.764 memory used for DFS stack (-m10000000) + 1060.529 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 151, "(1)" + line 418, "pan.___", state 181, "(1)" + line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 242, "(1)" + line 418, "pan.___", state 272, "(1)" + line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 360, "(1)" + line 418, "pan.___", state 390, "(1)" + line 540, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1040, "(1)" + line 418, "pan.___", state 1057, "(1)" + line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1130, "(1)" + line 418, "pan.___", state 1147, "(1)" + line 399, "pan.___", state 1166, "(1)" + line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1222, "(1)" + line 418, "pan.___", state 1239, "(1)" + line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1315, "(1)" + line 418, "pan.___", state 1332, "(1)" + line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 1378, "(1)" + line 164, "pan.___", state 1386, "(1)" + line 168, "pan.___", state 1398, "(1)" + line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1595, "(1)" + line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 1596, "else" + line 409, "pan.___", state 1599, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 413, "pan.___", state 1608, "(1)" + line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 1609, "else" + line 413, "pan.___", state 1612, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 411, "pan.___", state 1618, "((i<1))" + line 411, "pan.___", state 1618, "((i>=1))" + line 418, "pan.___", state 1625, "(1)" + line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 1626, "else" + line 418, "pan.___", state 1629, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 1681, "(1)" + line 164, "pan.___", state 1689, "(1)" + line 168, "pan.___", state 1701, "(1)" + line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.spin.input.trail new file mode 100644 index 0000000..7c42af1 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_reader.spin.input.trail @@ -0,0 +1,1270 @@ +-2:4:-2 +-4:-4:-4 +1:0:4401 +2:4:4353 +3:4:4356 +4:4:4356 +5:4:4359 +6:4:4367 +7:4:4367 +8:4:4370 +9:4:4376 +10:4:4380 +11:4:4380 +12:4:4383 +13:4:4391 +14:4:4395 +15:4:4396 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+1251:3:4346 +1252:0:4405 +1253:1:105 +1254:0:4405 +1255:3:4347 +1256:0:4405 +1257:3:4346 +1258:0:4405 +1259:2:1348 +1260:0:4405 +1261:3:4347 +1262:0:4405 +1263:2:1347 +1264:0:4405 +1265:3:4346 +1266:0:4405 +1267:1:104 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.define b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.define new file mode 100644 index 0000000..1e4417f --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.define @@ -0,0 +1 @@ +#define WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.log new file mode 100644 index 0000000..434151a --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.log @@ -0,0 +1,275 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 744) +depth 15: Claim reached state 9 (line 749) +depth 291: Claim reached state 9 (line 748) +Depth= 2677 States= 1e+06 Transitions= 1.57e+07 Memory= 487.932 t= 13.4 R= 7e+04 +Depth= 3023 States= 2e+06 Transitions= 3.19e+07 Memory= 509.709 t= 27.3 R= 7e+04 +Depth= 3610 States= 3e+06 Transitions= 4.84e+07 Memory= 531.486 t= 41.6 R= 7e+04 +pan: resizing hashtable to -w22.. done +Depth= 3956 States= 4e+06 Transitions= 6.63e+07 Memory= 595.029 t= 57 R= 7e+04 +Depth= 3956 States= 5e+06 Transitions= 8.67e+07 Memory= 617.783 t= 74.5 R= 7e+04 +Depth= 3956 States= 6e+06 Transitions= 1.08e+08 Memory= 660.850 t= 93 R= 6e+04 +Depth= 3956 States= 7e+06 Transitions= 1.28e+08 Memory= 690.928 t= 110 R= 6e+04 +Depth= 3956 States= 8e+06 Transitions= 1.51e+08 Memory= 729.600 t= 129 R= 6e+04 +Depth= 3956 States= 9e+06 Transitions= 1.7e+08 Memory= 765.830 t= 146 R= 6e+04 +pan: resizing hashtable to -w24.. done +Depth= 3956 States= 1e+07 Transitions= 1.92e+08 Memory= 919.611 t= 166 R= 6e+04 +Depth= 3956 States= 1.1e+07 Transitions= 2.13e+08 Memory= 958.576 t= 183 R= 6e+04 +Depth= 3956 States= 1.2e+07 Transitions= 2.33e+08 Memory= 985.627 t= 201 R= 6e+04 +Depth= 3956 States= 1.3e+07 Transitions= 2.55e+08 Memory= 1027.033 t= 220 R= 6e+04 + +(Spin Version 5.1.7 -- 23 December 2008) + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 3956, errors: 0 + 7045896 states, stored (1.35792e+07 visited) +2.5326206e+08 states, matched +2.668413e+08 transitions (= visited+matched) +9.9425626e+08 atomic steps +hash conflicts: 65494104 (resolved) + +Stats on memory usage (in Megabytes): + 564.437 equivalent memory usage for states (stored*(State-vector + overhead)) + 465.758 actual memory usage for states (compression: 82.52%) + state-vector as stored = 41 byte + 28 byte overhead + 128.000 memory used for hash table (-w24) + 457.764 memory used for DFS stack (-m10000000) + 1051.350 total actual memory usage + +unreached in proctype urcu_reader + line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 61, "(1)" + line 418, "pan.___", state 91, "(1)" + line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 151, "(1)" + line 418, "pan.___", state 181, "(1)" + line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 242, "(1)" + line 418, "pan.___", state 272, "(1)" + line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 360, "(1)" + line 418, "pan.___", state 390, "(1)" + line 540, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 59, "(1)" + line 413, "pan.___", state 72, "(1)" + line 418, "pan.___", state 89, "(1)" + line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 153, "(1)" + line 413, "pan.___", state 166, "(1)" + line 652, "pan.___", state 199, "(1)" + line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 240, "(1)" + line 164, "pan.___", state 248, "(1)" + line 168, "pan.___", state 260, "(1)" + line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 927, "(1)" + line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 928, "else" + line 409, "pan.___", state 931, "(1)" + line 409, "pan.___", state 932, "(1)" + line 409, "pan.___", state 932, "(1)" + line 413, "pan.___", state 940, "(1)" + line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 941, "else" + line 413, "pan.___", state 944, "(1)" + line 413, "pan.___", state 945, "(1)" + line 413, "pan.___", state 945, "(1)" + line 411, "pan.___", state 950, "((i<1))" + line 411, "pan.___", state 950, "((i>=1))" + line 418, "pan.___", state 957, "(1)" + line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 958, "else" + line 418, "pan.___", state 961, "(1)" + line 418, "pan.___", state 962, "(1)" + line 418, "pan.___", state 962, "(1)" + line 420, "pan.___", state 965, "(1)" + line 420, "pan.___", state 965, "(1)" + line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1040, "(1)" + line 418, "pan.___", state 1057, "(1)" + line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1130, "(1)" + line 418, "pan.___", state 1147, "(1)" + line 399, "pan.___", state 1166, "(1)" + line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1222, "(1)" + line 418, "pan.___", state 1239, "(1)" + line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 413, "pan.___", state 1315, "(1)" + line 418, "pan.___", state 1332, "(1)" + line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 1378, "(1)" + line 164, "pan.___", state 1386, "(1)" + line 168, "pan.___", state 1398, "(1)" + line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1595, "(1)" + line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 409, "pan.___", state 1596, "else" + line 409, "pan.___", state 1599, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 409, "pan.___", state 1600, "(1)" + line 413, "pan.___", state 1608, "(1)" + line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 413, "pan.___", state 1609, "else" + line 413, "pan.___", state 1612, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 413, "pan.___", state 1613, "(1)" + line 411, "pan.___", state 1618, "((i<1))" + line 411, "pan.___", state 1618, "((i>=1))" + line 418, "pan.___", state 1625, "(1)" + line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 418, "pan.___", state 1626, "else" + line 418, "pan.___", state 1629, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 418, "pan.___", state 1630, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 420, "pan.___", state 1633, "(1)" + line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 160, "pan.___", state 1681, "(1)" + line 164, "pan.___", state 1689, "(1)" + line 168, "pan.___", state 1701, "(1)" + line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.spin.input.trail new file mode 100644 index 0000000..e65d663 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer.spin.input.trail @@ -0,0 +1,9 @@ +-2:3:-2 +-4:-4:-4 +1:0:2679 +2:1:2673 +3:1:2674 +4:1:2675 +5:1:2676 +6:0:2685 +7:5:1129 diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.define b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.define new file mode 100644 index 0000000..8d304f5 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.define @@ -0,0 +1,2 @@ +#define WRITER_PROGRESS +#define GEN_ERROR_WRITER_PROGRESS diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.log b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.log new file mode 100644 index 0000000..7fafb9e --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.log @@ -0,0 +1,514 @@ +make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu' +rm -f pan* trail.out .input.spin* *.spin.trail .input.define +touch .input.define +cat .input.define > pan.ltl +cat DEFINES >> pan.ltl +spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl +cp urcu_progress_writer_error.define .input.define +cat .input.define > .input.spin +cat DEFINES >> .input.spin +cat urcu.spin >> .input.spin +rm -f .input.spin.trail +spin -a -X -N pan.ltl .input.spin +Exit-Status 0 +gcc -O2 -w -DHASH64 -o pan pan.c +./pan -a -f -v -c1 -X -m10000000 -w20 +warning: for p.o. reduction to be valid the never claim must be stutter-invariant +(never claims generated from LTL formulae are stutter-invariant) +depth 0: Claim reached state 5 (line 745) +depth 15: Claim reached state 9 (line 750) +depth 291: Claim reached state 9 (line 749) +pan: acceptance cycle (at depth 4308) +pan: wrote .input.spin.trail + +(Spin Version 5.1.7 -- 23 December 2008) +Warning: Search not completed + + Partial Order Reduction + +Full statespace search for: + never claim + + assertion violations + (if within scope of claim) + acceptance cycles + (fairness enabled) + invalid end states - (disabled by never claim) + +State-vector 56 byte, depth reached 4820, errors: 1 + 62091 states, stored (169917 visited) + 2179326 states, matched + 2349243 transitions (= visited+matched) + 8805349 atomic steps +hash conflicts: 50953 (resolved) + +Stats on memory usage (in Megabytes): + 4.974 equivalent memory usage for states (stored*(State-vector + overhead)) + 4.145 actual memory usage for states (compression: 83.33%) + state-vector as stored = 42 byte + 28 byte overhead + 8.000 memory used for hash table (-w20) + 457.764 memory used for DFS stack (-m10000000) + 469.865 total actual memory usage + +unreached in proctype urcu_reader + line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 61, "(1)" + line 419, "pan.___", state 91, "(1)" + line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 151, "(1)" + line 419, "pan.___", state 181, "(1)" + line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 242, "(1)" + line 419, "pan.___", state 272, "(1)" + line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 360, "(1)" + line 419, "pan.___", state 390, "(1)" + line 541, "pan.___", state 414, "-end-" + (17 of 414 states) +unreached in proctype urcu_writer + line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 20, "(1)" + line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 34, "(1)" + line 404, "pan.___", state 35, "(1)" + line 404, "pan.___", state 35, "(1)" + line 402, "pan.___", state 40, "((i<1))" + line 402, "pan.___", state 40, "((i>=1))" + line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 59, "(1)" + line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 60, "else" + line 410, "pan.___", state 63, "(1)" + line 410, "pan.___", state 64, "(1)" + line 410, "pan.___", state 64, "(1)" + line 414, "pan.___", state 72, "(1)" + line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 73, "else" + line 414, "pan.___", state 76, "(1)" + line 414, "pan.___", state 77, "(1)" + line 414, "pan.___", state 77, "(1)" + line 412, "pan.___", state 82, "((i<1))" + line 412, "pan.___", state 82, "((i>=1))" + line 419, "pan.___", state 89, "(1)" + line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 90, "else" + line 419, "pan.___", state 93, "(1)" + line 419, "pan.___", state 94, "(1)" + line 419, "pan.___", state 94, "(1)" + line 370, "pan.___", state 99, "(1)" + line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)" + line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]" + line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 114, "(1)" + line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 128, "(1)" + line 404, "pan.___", state 129, "(1)" + line 404, "pan.___", state 129, "(1)" + line 402, "pan.___", state 134, "((i<1))" + line 402, "pan.___", state 134, "((i>=1))" + line 410, "pan.___", state 153, "(1)" + line 410, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 154, "else" + line 410, "pan.___", state 157, "(1)" + line 410, "pan.___", state 158, "(1)" + line 410, "pan.___", state 158, "(1)" + line 414, "pan.___", state 166, "(1)" + line 414, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 167, "else" + line 414, "pan.___", state 170, "(1)" + line 414, "pan.___", state 171, "(1)" + line 414, "pan.___", state 171, "(1)" + line 412, "pan.___", state 176, "((i<1))" + line 412, "pan.___", state 176, "((i>=1))" + line 419, "pan.___", state 183, "(1)" + line 419, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 184, "else" + line 419, "pan.___", state 187, "(1)" + line 419, "pan.___", state 188, "(1)" + line 419, "pan.___", state 188, "(1)" + line 421, "pan.___", state 191, "(1)" + line 421, "pan.___", state 191, "(1)" + line 370, "pan.___", state 193, "(1)" + line 653, "pan.___", state 199, "(1)" + line 647, "pan.___", state 202, "((write_lock==0))" + line 647, "pan.___", state 202, "else" + line 645, "pan.___", state 203, "(1)" + line 176, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 180, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 178, "pan.___", state 225, "((j<1))" + line 178, "pan.___", state 225, "((j>=1))" + line 184, "pan.___", state 230, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 161, "pan.___", state 240, "(1)" + line 165, "pan.___", state 248, "(1)" + line 165, "pan.___", state 249, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 165, "pan.___", state 249, "else" + line 163, "pan.___", state 254, "((j<1))" + line 163, "pan.___", state 254, "((j>=1))" + line 169, "pan.___", state 260, "(1)" + line 169, "pan.___", state 261, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 169, "pan.___", state 261, "else" + line 171, "pan.___", state 264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 171, "pan.___", state 264, "else" + line 176, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<=1))" + line 184, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<=1))" + line 169, "pan.___", state 323, "(1)" + line 169, "pan.___", state 324, "(!((cache_dirty_generation_ptr.bitfield&(1<=1))" + line 176, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 180, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 178, "pan.___", state 355, "((j<1))" + line 178, "pan.___", state 355, "((j>=1))" + line 184, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 161, "pan.___", state 370, "(1)" + line 165, "pan.___", state 378, "(1)" + line 165, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 165, "pan.___", state 379, "else" + line 163, "pan.___", state 384, "((j<1))" + line 163, "pan.___", state 384, "((j>=1))" + line 169, "pan.___", state 390, "(1)" + line 169, "pan.___", state 391, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 169, "pan.___", state 391, "else" + line 171, "pan.___", state 394, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 171, "pan.___", state 394, "else" + line 400, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 410, "(1)" + line 404, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 424, "(1)" + line 404, "pan.___", state 425, "(1)" + line 404, "pan.___", state 425, "(1)" + line 402, "pan.___", state 430, "((i<1))" + line 402, "pan.___", state 430, "((i>=1))" + line 409, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 449, "(1)" + line 410, "pan.___", state 450, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 450, "else" + line 410, "pan.___", state 453, "(1)" + line 410, "pan.___", state 454, "(1)" + line 410, "pan.___", state 454, "(1)" + line 414, "pan.___", state 462, "(1)" + line 414, "pan.___", state 463, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 463, "else" + line 414, "pan.___", state 466, "(1)" + line 414, "pan.___", state 467, "(1)" + line 414, "pan.___", state 467, "(1)" + line 412, "pan.___", state 472, "((i<1))" + line 412, "pan.___", state 472, "((i>=1))" + line 419, "pan.___", state 479, "(1)" + line 419, "pan.___", state 480, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 480, "else" + line 419, "pan.___", state 483, "(1)" + line 419, "pan.___", state 484, "(1)" + line 419, "pan.___", state 484, "(1)" + line 421, "pan.___", state 487, "(1)" + line 421, "pan.___", state 487, "(1)" + line 370, "pan.___", state 489, "(1)" + line 662, "pan.___", state 492, "cached_urcu_gp_ctr.val[_pid] = (tmp^(1<<7))" + line 400, "pan.___", state 498, "(1)" + line 400, "pan.___", state 499, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 499, "else" + line 400, "pan.___", state 502, "(1)" + line 404, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 516, "(1)" + line 404, "pan.___", state 517, "(1)" + line 404, "pan.___", state 517, "(1)" + line 402, "pan.___", state 522, "((i<1))" + line 402, "pan.___", state 522, "((i>=1))" + line 409, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 541, "(1)" + line 410, "pan.___", state 542, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 542, "else" + line 410, "pan.___", state 545, "(1)" + line 410, "pan.___", state 546, "(1)" + line 410, "pan.___", state 546, "(1)" + line 414, "pan.___", state 554, "(1)" + line 414, "pan.___", state 555, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 555, "else" + line 414, "pan.___", state 558, "(1)" + line 414, "pan.___", state 559, "(1)" + line 414, "pan.___", state 559, "(1)" + line 412, "pan.___", state 564, "((i<1))" + line 412, "pan.___", state 564, "((i>=1))" + line 419, "pan.___", state 571, "(1)" + line 419, "pan.___", state 572, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 572, "else" + line 419, "pan.___", state 575, "(1)" + line 419, "pan.___", state 576, "(1)" + line 419, "pan.___", state 576, "(1)" + line 421, "pan.___", state 579, "(1)" + line 421, "pan.___", state 579, "(1)" + line 370, "pan.___", state 581, "(1)" + line 400, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 595, "(1)" + line 404, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 609, "(1)" + line 404, "pan.___", state 610, "(1)" + line 404, "pan.___", state 610, "(1)" + line 402, "pan.___", state 615, "((i<1))" + line 402, "pan.___", state 615, "((i>=1))" + line 409, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 634, "(1)" + line 410, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 635, "else" + line 410, "pan.___", state 638, "(1)" + line 410, "pan.___", state 639, "(1)" + line 410, "pan.___", state 639, "(1)" + line 414, "pan.___", state 647, "(1)" + line 414, "pan.___", state 648, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 648, "else" + line 414, "pan.___", state 651, "(1)" + line 414, "pan.___", state 652, "(1)" + line 414, "pan.___", state 652, "(1)" + line 412, "pan.___", state 657, "((i<1))" + line 412, "pan.___", state 657, "((i>=1))" + line 419, "pan.___", state 664, "(1)" + line 419, "pan.___", state 665, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 665, "else" + line 419, "pan.___", state 668, "(1)" + line 419, "pan.___", state 669, "(1)" + line 419, "pan.___", state 669, "(1)" + line 421, "pan.___", state 672, "(1)" + line 421, "pan.___", state 672, "(1)" + line 370, "pan.___", state 674, "(1)" + line 400, "pan.___", state 679, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 681, "(1)" + line 400, "pan.___", state 682, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 682, "else" + line 400, "pan.___", state 685, "(1)" + line 404, "pan.___", state 693, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 695, "(1)" + line 404, "pan.___", state 696, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 404, "pan.___", state 696, "else" + line 404, "pan.___", state 699, "(1)" + line 404, "pan.___", state 700, "(1)" + line 404, "pan.___", state 700, "(1)" + line 402, "pan.___", state 705, "((i<1))" + line 402, "pan.___", state 705, "((i>=1))" + line 409, "pan.___", state 711, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 724, "(1)" + line 410, "pan.___", state 725, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 725, "else" + line 410, "pan.___", state 728, "(1)" + line 410, "pan.___", state 729, "(1)" + line 410, "pan.___", state 729, "(1)" + line 414, "pan.___", state 737, "(1)" + line 414, "pan.___", state 738, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 738, "else" + line 414, "pan.___", state 741, "(1)" + line 414, "pan.___", state 742, "(1)" + line 414, "pan.___", state 742, "(1)" + line 412, "pan.___", state 747, "((i<1))" + line 412, "pan.___", state 747, "((i>=1))" + line 419, "pan.___", state 754, "(1)" + line 419, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 755, "else" + line 419, "pan.___", state 758, "(1)" + line 419, "pan.___", state 759, "(1)" + line 419, "pan.___", state 759, "(1)" + line 421, "pan.___", state 762, "(1)" + line 421, "pan.___", state 762, "(1)" + line 370, "pan.___", state 764, "(1)" + line 430, "pan.___", state 767, "(((tmp2&((1<<7)-1))&&((tmp2^cached_urcu_gp_ctr.val[_pid])&(1<<7))))" + line 430, "pan.___", state 767, "else" + line 400, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 779, "(1)" + line 400, "pan.___", state 780, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 780, "else" + line 400, "pan.___", state 783, "(1)" + line 404, "pan.___", state 791, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 793, "(1)" + line 404, "pan.___", state 794, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 404, "pan.___", state 794, "else" + line 404, "pan.___", state 797, "(1)" + line 404, "pan.___", state 798, "(1)" + line 404, "pan.___", state 798, "(1)" + line 402, "pan.___", state 803, "((i<1))" + line 402, "pan.___", state 803, "((i>=1))" + line 409, "pan.___", state 809, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 822, "(1)" + line 410, "pan.___", state 823, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 823, "else" + line 410, "pan.___", state 826, "(1)" + line 410, "pan.___", state 827, "(1)" + line 410, "pan.___", state 827, "(1)" + line 414, "pan.___", state 835, "(1)" + line 414, "pan.___", state 836, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 836, "else" + line 414, "pan.___", state 839, "(1)" + line 414, "pan.___", state 840, "(1)" + line 414, "pan.___", state 840, "(1)" + line 412, "pan.___", state 845, "((i<1))" + line 412, "pan.___", state 845, "((i>=1))" + line 419, "pan.___", state 852, "(1)" + line 419, "pan.___", state 853, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 853, "else" + line 419, "pan.___", state 856, "(1)" + line 419, "pan.___", state 857, "(1)" + line 419, "pan.___", state 857, "(1)" + line 421, "pan.___", state 860, "(1)" + line 421, "pan.___", state 860, "(1)" + line 370, "pan.___", state 862, "(1)" + line 449, "pan.___", state 870, "((tmp<1))" + line 449, "pan.___", state 870, "((tmp>=1))" + line 462, "pan.___", state 873, "tmp = 0" + line 400, "pan.___", state 877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 883, "(1)" + line 404, "pan.___", state 891, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 897, "(1)" + line 404, "pan.___", state 898, "(1)" + line 404, "pan.___", state 898, "(1)" + line 402, "pan.___", state 903, "((i<1))" + line 402, "pan.___", state 903, "((i>=1))" + line 409, "pan.___", state 909, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 922, "(1)" + line 410, "pan.___", state 923, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 923, "else" + line 410, "pan.___", state 926, "(1)" + line 410, "pan.___", state 927, "(1)" + line 410, "pan.___", state 927, "(1)" + line 414, "pan.___", state 935, "(1)" + line 414, "pan.___", state 936, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 936, "else" + line 414, "pan.___", state 939, "(1)" + line 414, "pan.___", state 940, "(1)" + line 414, "pan.___", state 940, "(1)" + line 412, "pan.___", state 945, "((i<1))" + line 412, "pan.___", state 945, "((i>=1))" + line 419, "pan.___", state 952, "(1)" + line 419, "pan.___", state 953, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 953, "else" + line 419, "pan.___", state 956, "(1)" + line 419, "pan.___", state 957, "(1)" + line 419, "pan.___", state 957, "(1)" + line 421, "pan.___", state 960, "(1)" + line 421, "pan.___", state 960, "(1)" + line 370, "pan.___", state 962, "(1)" + line 671, "pan.___", state 963, "tmp = cached_urcu_gp_ctr.val[_pid]" + line 400, "pan.___", state 967, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 973, "(1)" + line 404, "pan.___", state 981, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 987, "(1)" + line 404, "pan.___", state 988, "(1)" + line 404, "pan.___", state 988, "(1)" + line 402, "pan.___", state 993, "((i<1))" + line 402, "pan.___", state 993, "((i>=1))" + line 409, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 1012, "(1)" + line 410, "pan.___", state 1013, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 1013, "else" + line 410, "pan.___", state 1016, "(1)" + line 410, "pan.___", state 1017, "(1)" + line 410, "pan.___", state 1017, "(1)" + line 414, "pan.___", state 1025, "(1)" + line 414, "pan.___", state 1026, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 1026, "else" + line 414, "pan.___", state 1029, "(1)" + line 414, "pan.___", state 1030, "(1)" + line 414, "pan.___", state 1030, "(1)" + line 412, "pan.___", state 1035, "((i<1))" + line 412, "pan.___", state 1035, "((i>=1))" + line 419, "pan.___", state 1042, "(1)" + line 419, "pan.___", state 1043, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 1043, "else" + line 419, "pan.___", state 1046, "(1)" + line 419, "pan.___", state 1047, "(1)" + line 419, "pan.___", state 1047, "(1)" + line 421, "pan.___", state 1050, "(1)" + line 421, "pan.___", state 1050, "(1)" + line 370, "pan.___", state 1052, "(1)" + line 400, "pan.___", state 1061, "(1)" + line 404, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1117, "(1)" + line 419, "pan.___", state 1134, "(1)" + line 404, "pan.___", state 1166, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1184, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 414, "pan.___", state 1210, "(1)" + line 419, "pan.___", state 1227, "(1)" + line 400, "pan.___", state 1242, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 1256, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 409, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 1287, "(1)" + line 414, "pan.___", state 1300, "(1)" + line 419, "pan.___", state 1317, "(1)" + line 400, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))" + line 400, "pan.___", state 1342, "(1)" + line 400, "pan.___", state 1343, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))" + line 400, "pan.___", state 1343, "else" + line 400, "pan.___", state 1346, "(1)" + line 404, "pan.___", state 1354, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 404, "pan.___", state 1356, "(1)" + line 404, "pan.___", state 1357, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))" + line 404, "pan.___", state 1357, "else" + line 404, "pan.___", state 1360, "(1)" + line 404, "pan.___", state 1361, "(1)" + line 404, "pan.___", state 1361, "(1)" + line 402, "pan.___", state 1366, "((i<1))" + line 402, "pan.___", state 1366, "((i>=1))" + line 409, "pan.___", state 1372, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 410, "pan.___", state 1385, "(1)" + line 410, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))" + line 410, "pan.___", state 1386, "else" + line 410, "pan.___", state 1389, "(1)" + line 410, "pan.___", state 1390, "(1)" + line 410, "pan.___", state 1390, "(1)" + line 414, "pan.___", state 1398, "(1)" + line 414, "pan.___", state 1399, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))" + line 414, "pan.___", state 1399, "else" + line 414, "pan.___", state 1402, "(1)" + line 414, "pan.___", state 1403, "(1)" + line 414, "pan.___", state 1403, "(1)" + line 412, "pan.___", state 1408, "((i<1))" + line 412, "pan.___", state 1408, "((i>=1))" + line 419, "pan.___", state 1415, "(1)" + line 419, "pan.___", state 1416, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))" + line 419, "pan.___", state 1416, "else" + line 419, "pan.___", state 1419, "(1)" + line 419, "pan.___", state 1420, "(1)" + line 419, "pan.___", state 1420, "(1)" + line 421, "pan.___", state 1423, "(1)" + line 421, "pan.___", state 1423, "(1)" + line 180, "pan.___", state 1448, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))" + line 184, "pan.___", state 1461, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))" + line 161, "pan.___", state 1471, "(1)" + line 165, "pan.___", state 1479, "(1)" + line 169, "pan.___", state 1491, "(1)" + line 176, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1< 0 : 1) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#else + +#define get_pid() (_pid) + +#define NR_READERS 1 +#define NR_WRITERS 1 + +#define NR_PROCS 2 + +#endif + +#define get_readerid() (get_pid()) + +/* + * Each process have its own data in cache. Caches are randomly updated. + * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces + * both. + */ + +typedef per_proc_byte { + byte val[NR_PROCS]; +}; + +/* Bitfield has a maximum of 8 procs */ +typedef per_proc_bit { + byte bitfield; +}; + +#define DECLARE_CACHED_VAR(type, x) \ + type mem_##x; \ + per_proc_##type cached_##x; \ + per_proc_bit cache_dirty_##x; + +#define INIT_CACHED_VAR(x, v, j) \ + mem_##x = v; \ + cache_dirty_##x.bitfield = 0; \ + j = 0; \ + do \ + :: j < NR_PROCS -> \ + cached_##x.val[j] = v; \ + j++ \ + :: j >= NR_PROCS -> break \ + od; + +#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id)) + +#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()]) + +#define WRITE_CACHED_VAR(x, v) \ + atomic { \ + cached_##x.val[get_pid()] = v; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield | (1 << get_pid()); \ + } + +#define CACHE_WRITE_TO_MEM(x, id) \ + if \ + :: IS_CACHE_DIRTY(x, id) -> \ + mem_##x = cached_##x.val[id]; \ + cache_dirty_##x.bitfield = \ + cache_dirty_##x.bitfield & (~(1 << id)); \ + :: else -> \ + skip \ + fi; + +#define CACHE_READ_FROM_MEM(x, id) \ + if \ + :: !IS_CACHE_DIRTY(x, id) -> \ + cached_##x.val[id] = mem_##x;\ + :: else -> \ + skip \ + fi; + +/* + * May update other caches if cache is dirty, or not. + */ +#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\ + if \ + :: 1 -> CACHE_WRITE_TO_MEM(x, id); \ + :: 1 -> skip \ + fi; + +#define RANDOM_CACHE_READ_FROM_MEM(x, id)\ + if \ + :: 1 -> CACHE_READ_FROM_MEM(x, id); \ + :: 1 -> skip \ + fi; + +/* + * Remote barriers tests the scheme where a signal (or IPI) is sent to all + * reader threads to promote their compiler barrier to a smp_mb(). + */ +#ifdef REMOTE_BARRIERS + +inline smp_rmb_pid(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, i); + } +} + +inline smp_wmb_pid(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, i); + j = 0; + do + :: j < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[j], i); + j++ + :: j >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, i); + } +} + +inline smp_mb_pid(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb_pid(i, j); +#endif +#ifndef NO_RMB + smp_rmb_pid(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(j); +#endif +#endif + } +} + +/* + * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a + * signal or IPI to have all readers execute a smp_mb. + * We are not modeling the whole rendez-vous between readers and writers here, + * we just let the writer update each reader's caches remotely. + */ +inline smp_mb_writer(i, j) +{ + smp_mb_pid(get_pid(), j); + i = 0; + do + :: i < NR_READERS -> + smp_mb_pid(i, j); + i++; + :: i >= NR_READERS -> break + od; + smp_mb_pid(get_pid(), j); +} + +inline smp_mb_reader(i, j) +{ + skip; +} + +#else + +inline smp_rmb(i, j) +{ + atomic { + CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline smp_wmb(i, j) +{ + atomic { + CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid()); + i++ + :: i >= NR_READERS -> break + od; + CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + } +} + +inline smp_mb(i, j) +{ + atomic { +#ifndef NO_WMB + smp_wmb(i, j); +#endif +#ifndef NO_RMB + smp_rmb(i, j); +#endif +#ifdef NO_WMB +#ifdef NO_RMB + ooo_mem(i); +#endif +#endif + } +} + +inline smp_mb_writer(i, j) +{ + smp_mb(i, j); +} + +inline smp_mb_reader(i, j) +{ + smp_mb(i, j); +} + +#endif + +/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */ +DECLARE_CACHED_VAR(byte, urcu_gp_ctr); +/* Note ! currently only two readers */ +DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]); +/* pointer generation */ +DECLARE_CACHED_VAR(byte, generation_ptr); + +byte last_free_gen = 0; +bit free_done = 0; +byte read_generation[NR_READERS]; +bit data_access[NR_READERS]; + +bit write_lock = 0; + +bit init_done = 0; + +bit sighand_exec = 0; + +inline wait_init_done() +{ + do + :: init_done == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TEST_SIGNAL + +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> break; + od; +} + +#ifdef TOO_BIG_STATE_SPACE +inline wait_for_sighand_exec() +{ + sighand_exec = 0; + do + :: sighand_exec == 0 -> skip; + :: else -> + if + :: 1 -> break; + :: 1 -> sighand_exec = 0; + skip; + fi; + od; +} +#endif + +#else + +inline wait_for_sighand_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_WRITE +/* Block on signal handler execution */ +inline dispatch_sighand_write_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_write_exec() +{ + skip; +} + +#endif + +#ifdef TEST_SIGNAL_ON_READ +/* Block on signal handler execution */ +inline dispatch_sighand_read_exec() +{ + sighand_exec = 1; + do + :: sighand_exec == 1 -> + skip; + :: else -> + break; + od; +} + +#else + +inline dispatch_sighand_read_exec() +{ + skip; +} + +#endif + + +inline ooo_mem(i) +{ + atomic { + RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid()); + RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid()); + i = 0; + do + :: i < NR_READERS -> + RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i], + get_pid()); + i++ + :: i >= NR_READERS -> break + od; + RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid()); + } +} + +inline wait_for_reader(tmp, tmp2, i, j) +{ + do + :: 1 -> + tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]); + ooo_mem(i); + dispatch_sighand_write_exec(); + if + :: (tmp2 & RCU_GP_CTR_NEST_MASK) + && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr)) + & RCU_GP_CTR_BIT) -> +#ifndef GEN_ERROR_WRITER_PROGRESS + smp_mb_writer(i, j); +#else + ooo_mem(i); +#endif + dispatch_sighand_write_exec(); + :: else -> + break; + fi; + od; +} + +inline wait_for_quiescent_state(tmp, tmp2, i, j) +{ + tmp = 0; + do + :: tmp < NR_READERS -> + wait_for_reader(tmp, tmp2, i, j); + if + :: (NR_READERS > 1) && (tmp < NR_READERS - 1) + -> ooo_mem(i); + dispatch_sighand_write_exec(); + :: else + -> skip; + fi; + tmp++ + :: tmp >= NR_READERS -> break + od; +} + +/* Model the RCU read-side critical section. */ + +#ifndef TEST_SIGNAL_ON_WRITE + +inline urcu_one_read(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + dispatch_sighand_read_exec(); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + dispatch_sighand_read_exec(); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + dispatch_sighand_read_exec(); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //dispatch_sighand_read_exec(); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read(i, j, nest_i, tmp, tmp2); + od; +} + +#endif //!TEST_SIGNAL_ON_WRITE + +#ifdef TEST_SIGNAL +/* signal handler reader */ + +inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2) +{ + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + ooo_mem(i); + tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + if + :: (!(tmp & RCU_GP_CTR_NEST_MASK)) + -> + tmp2 = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp2); + :: else -> + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], + tmp + 1); + fi; + smp_mb_reader(i, j); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + + read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr); + data_access[get_readerid()] = 1; + data_access[get_readerid()] = 0; + + nest_i = 0; + do + :: nest_i < READER_NEST_LEVEL -> + smp_mb_reader(i, j); + tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); + ooo_mem(i); + WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1); + nest_i++; + :: nest_i >= READER_NEST_LEVEL -> break; + od; + //ooo_mem(i); + //smp_mc(i); /* added */ +} + +active proctype urcu_reader_sig() +{ + byte i, j, nest_i; + byte tmp, tmp2; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + +end_reader: + do + :: 1 -> + wait_for_sighand_exec(); + /* + * We do not test reader's progress here, because we are mainly + * interested in writer's progress. The reader never blocks + * anyway. We have to test for reader/writer's progress + * separately, otherwise we could think the writer is doing + * progress when it's blocked by an always progressing reader. + */ +#ifdef READER_PROGRESS +progress_reader: +#endif + urcu_one_read_sig(i, j, nest_i, tmp, tmp2); + od; +} + +#endif + +/* Model the RCU update process. */ + +active proctype urcu_writer() +{ + byte i, j; + byte tmp, tmp2; + byte old_gen; + + wait_init_done(); + + assert(get_pid() < NR_PROCS); + + do + :: (READ_CACHED_VAR(generation_ptr) < 5) -> +#ifdef WRITER_PROGRESS +progress_writer1: +#endif + ooo_mem(i); + dispatch_sighand_write_exec(); + atomic { + old_gen = READ_CACHED_VAR(generation_ptr); + WRITE_CACHED_VAR(generation_ptr, old_gen + 1); + } + ooo_mem(i); + dispatch_sighand_write_exec(); + + do + :: 1 -> + atomic { + if + :: write_lock == 0 -> + write_lock = 1; + break; + :: else -> + skip; + fi; + } + od; + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + ooo_mem(i); + dispatch_sighand_write_exec(); + //smp_mc(i); + wait_for_quiescent_state(tmp, tmp2, i, j); + //smp_mc(i); +#ifndef SINGLE_FLIP + ooo_mem(i); + dispatch_sighand_write_exec(); + tmp = READ_CACHED_VAR(urcu_gp_ctr); + ooo_mem(i); + dispatch_sighand_write_exec(); + WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT); + //smp_mc(i); + ooo_mem(i); + dispatch_sighand_write_exec(); + wait_for_quiescent_state(tmp, tmp2, i, j); +#endif + smp_mb_writer(i, j); + dispatch_sighand_write_exec(); + write_lock = 0; + /* free-up step, e.g., kfree(). */ + atomic { + last_free_gen = old_gen; + free_done = 1; + } + :: else -> break; + od; + /* + * Given the reader loops infinitely, let the writer also busy-loop + * with progress here so, with weak fairness, we can test the + * writer's progress. + */ +end_writer: + do + :: 1 -> +#ifdef WRITER_PROGRESS +progress_writer2: +#endif + dispatch_sighand_write_exec(); + od; +} + +/* Leave after the readers and writers so the pid count is ok. */ +init { + byte i, j; + + atomic { + INIT_CACHED_VAR(urcu_gp_ctr, 1, j); + INIT_CACHED_VAR(generation_ptr, 0, j); + + i = 0; + do + :: i < NR_READERS -> + INIT_CACHED_VAR(urcu_active_readers[i], 0, j); + read_generation[i] = 1; + data_access[i] = 0; + i++; + :: i >= NR_READERS -> break + od; + init_done = 1; + } +} diff --git a/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail new file mode 100644 index 0000000..5bb8316 --- /dev/null +++ b/formal-model/urcu-nosched-model/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail @@ -0,0 +1,4823 @@ +-2:3:-2 +-4:-4:-4 +1:0:2108 +2:3:2060 +3:3:2063 +4:3:2063 +5:3:2066 +6:3:2074 +7:3:2074 +8:3:2077 +9:3:2083 +10:3:2087 +11:3:2087 +12:3:2090 +13:3:2098 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