--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+#define READER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64 -DCOLLAPSE
+#CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ #make urcu_free | tee urcu_free.log
+ #make urcu_free_no_mb | tee urcu_free_no_mb.log
+ #make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ #make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ #make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ #make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+[] (!read_poison)
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+#define NO_RMB
--- /dev/null
+#define NO_WMB
--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+depth 7: Claim reached state 9 (line 1367)
+depth 136: Claim reached state 9 (line 1366)
+Depth= 115766 States= 1e+06 Transitions= 2.97e+08 Memory= 495.647 t= 461 R= 2e+03
+Depth= 115766 States= 2e+06 Transitions= 5.97e+08 Memory= 525.529 t= 939 R= 2e+03
+Depth= 115766 States= 3e+06 Transitions= 8.86e+08 Memory= 553.264 t= 1.41e+03 R= 2e+03
+pan: resizing hashtable to -w22.. done
+Depth= 115766 States= 4e+06 Transitions= 1.18e+09 Memory= 614.463 t= 1.87e+03 R= 2e+03
+Depth= 115766 States= 5e+06 Transitions= 1.48e+09 Memory= 644.541 t= 2.34e+03 R= 2e+03
+Depth= 115766 States= 6e+06 Transitions= 1.77e+09 Memory= 674.424 t= 2.8e+03 R= 2e+03
+Depth= 115766 States= 7e+06 Transitions= 2.07e+09 Memory= 701.865 t= 3.27e+03 R= 2e+03
+Depth= 115766 States= 8e+06 Transitions= 2.36e+09 Memory= 729.404 t= 3.75e+03 R= 2e+03
+Depth= 115766 States= 9e+06 Transitions= 2.66e+09 Memory= 757.920 t= 4.23e+03 R= 2e+03
+pan: resizing hashtable to -w24.. done
+Depth= 117893 States= 1e+07 Transitions= 2.95e+09 Memory= 909.846 t= 4.69e+03 R= 2e+03
+Depth= 117893 States= 1.1e+07 Transitions= 3.35e+09 Memory= 937.190 t= 5.31e+03 R= 2e+03
+Depth= 117893 States= 1.2e+07 Transitions= 3.69e+09 Memory= 964.826 t= 5.85e+03 R= 2e+03
+Depth= 117893 States= 1.3e+07 Transitions= 4.02e+09 Memory= 994.026 t= 6.37e+03 R= 2e+03
+Depth= 117893 States= 1.4e+07 Transitions= 4.32e+09 Memory= 1021.858 t= 6.84e+03 R= 2e+03
+Depth= 117893 States= 1.5e+07 Transitions= 4.63e+09 Memory= 1050.080 t= 7.33e+03 R= 2e+03
+Depth= 117893 States= 1.6e+07 Transitions= 4.95e+09 Memory= 1078.693 t= 7.83e+03 R= 2e+03
+Depth= 117893 States= 1.7e+07 Transitions= 5.24e+09 Memory= 1106.135 t= 8.28e+03 R= 2e+03
+Depth= 117893 States= 1.8e+07 Transitions= 5.54e+09 Memory= 1135.920 t= 8.74e+03 R= 2e+03
+Depth= 117893 States= 1.9e+07 Transitions= 5.82e+09 Memory= 1164.338 t= 9.19e+03 R= 2e+03
+Depth= 117893 States= 2e+07 Transitions= 6.12e+09 Memory= 1194.514 t= 9.66e+03 R= 2e+03
+Depth= 117893 States= 2.1e+07 Transitions= 6.42e+09 Memory= 1223.713 t= 1.01e+04 R= 2e+03
+Depth= 117893 States= 2.2e+07 Transitions= 6.72e+09 Memory= 1252.912 t= 1.06e+04 R= 2e+03
+Depth= 117893 States= 2.3e+07 Transitions= 7.01e+09 Memory= 1280.744 t= 1.11e+04 R= 2e+03
+Depth= 117893 States= 2.4e+07 Transitions= 7.3e+09 Memory= 1311.408 t= 1.15e+04 R= 2e+03
+Depth= 117893 States= 2.5e+07 Transitions= 7.61e+09 Memory= 1336.994 t= 1.2e+04 R= 2e+03
+Depth= 117893 States= 2.6e+07 Transitions= 7.89e+09 Memory= 1365.315 t= 1.24e+04 R= 2e+03
+Depth= 117893 States= 2.7e+07 Transitions= 8.35e+09 Memory= 1390.315 t= 1.32e+04 R= 2e+03
+Depth= 117893 States= 2.8e+07 Transitions= 8.84e+09 Memory= 1414.143 t= 1.4e+04 R= 2e+03
+Depth= 117893 States= 2.9e+07 Transitions= 9.64e+09 Memory= 1438.166 t= 1.53e+04 R= 2e+03
+Depth= 117893 States= 3e+07 Transitions= 1.02e+10 Memory= 1462.971 t= 1.62e+04 R= 2e+03
+Depth= 117893 States= 3.1e+07 Transitions= 1.06e+10 Memory= 1488.068 t= 1.69e+04 R= 2e+03
+Depth= 117893 States= 3.2e+07 Transitions= 1.14e+10 Memory= 1512.287 t= 1.82e+04 R= 2e+03
+Depth= 117893 States= 3.3e+07 Transitions= 1.24e+10 Memory= 1536.799 t= 1.99e+04 R= 2e+03
+Depth= 117893 States= 3.4e+07 Transitions= 1.27e+10 Memory= 1567.658 t= 2.04e+04 R= 2e+03
+pan: resizing hashtable to -w26.. done
+Depth= 117893 States= 3.5e+07 Transitions= 1.32e+10 Memory= 2089.424 t= 2.13e+04 R= 2e+03
+Depth= 117893 States= 3.6e+07 Transitions= 1.38e+10 Memory= 2116.768 t= 2.22e+04 R= 2e+03
+Depth= 117893 States= 3.7e+07 Transitions= 1.45e+10 Memory= 2142.158 t= 2.33e+04 R= 2e+03
+Depth= 117893 States= 3.8e+07 Transitions= 1.49e+10 Memory= 2170.674 t= 2.41e+04 R= 2e+03
+Depth= 117893 States= 3.9e+07 Transitions= 1.55e+10 Memory= 2197.725 t= 2.49e+04 R= 2e+03
+Depth= 117893 States= 4e+07 Transitions= 1.63e+10 Memory= 2219.014 t= 2.63e+04 R= 2e+03
+Depth= 117893 States= 4.1e+07 Transitions= 1.69e+10 Memory= 2242.061 t= 2.75e+04 R= 1e+03
+Depth= 117893 States= 4.2e+07 Transitions= 1.73e+10 Memory= 2269.600 t= 2.81e+04 R= 1e+03
+Depth= 117893 States= 4.3e+07 Transitions= 1.8e+10 Memory= 2295.967 t= 2.92e+04 R= 1e+03
+Depth= 117893 States= 4.4e+07 Transitions= 1.85e+10 Memory= 2323.213 t= 3e+04 R= 1e+03
+Depth= 117893 States= 4.5e+07 Transitions= 1.91e+10 Memory= 2348.994 t= 3.09e+04 R= 1e+03
+Depth= 117893 States= 4.6e+07 Transitions= 1.97e+10 Memory= 2374.190 t= 3.2e+04 R= 1e+03
+Depth= 117893 States= 4.7e+07 Transitions= 2.03e+10 Memory= 2399.483 t= 3.3e+04 R= 1e+03
+Depth= 117893 States= 4.8e+07 Transitions= 2.07e+10 Memory= 2428.486 t= 3.36e+04 R= 1e+03
+Depth= 117893 States= 4.9e+07 Transitions= 2.13e+10 Memory= 2454.951 t= 3.45e+04 R= 1e+03
+Depth= 117893 States= 5e+07 Transitions= 2.18e+10 Memory= 2482.686 t= 3.54e+04 R= 1e+03
+Depth= 117893 States= 5.1e+07 Transitions= 2.24e+10 Memory= 2509.151 t= 3.62e+04 R= 1e+03
+Depth= 117893 States= 5.2e+07 Transitions= 2.3e+10 Memory= 2535.420 t= 3.72e+04 R= 1e+03
+Depth= 117893 States= 5.3e+07 Transitions= 2.38e+10 Memory= 2560.518 t= 3.86e+04 R= 1e+03
+Depth= 117893 States= 5.4e+07 Transitions= 2.42e+10 Memory= 2586.592 t= 3.94e+04 R= 1e+03
+Depth= 117893 States= 5.5e+07 Transitions= 2.46e+10 Memory= 2610.713 t= 4e+04 R= 1e+03
+Depth= 117893 States= 5.6e+07 Transitions= 2.49e+10 Memory= 2638.545 t= 4.06e+04 R= 1e+03
+Depth= 117893 States= 5.7e+07 Transitions= 2.53e+10 Memory= 2668.135 t= 4.11e+04 R= 1e+03
+Depth= 117893 States= 5.8e+07 Transitions= 2.56e+10 Memory= 2698.213 t= 4.16e+04 R= 1e+03
+Depth= 117893 States= 5.9e+07 Transitions= 2.59e+10 Memory= 2723.897 t= 4.22e+04 R= 1e+03
+Depth= 117893 States= 6e+07 Transitions= 2.66e+10 Memory= 2747.627 t= 4.33e+04 R= 1e+03
+Depth= 117893 States= 6.1e+07 Transitions= 2.7e+10 Memory= 2774.678 t= 4.39e+04 R= 1e+03
+Depth= 117893 States= 6.2e+07 Transitions= 2.73e+10 Memory= 2803.584 t= 4.45e+04 R= 1e+03
+Depth= 117893 States= 6.3e+07 Transitions= 2.77e+10 Memory= 2831.221 t= 4.51e+04 R= 1e+03
+Depth= 117893 States= 6.4e+07 Transitions= 2.8e+10 Memory= 2860.225 t= 4.56e+04 R= 1e+03
+Depth= 117893 States= 6.5e+07 Transitions= 2.84e+10 Memory= 2885.225 t= 4.62e+04 R= 1e+03
+Depth= 117893 States= 6.6e+07 Transitions= 2.89e+10 Memory= 2908.760 t= 4.71e+04 R= 1e+03
+Depth= 117893 States= 6.7e+07 Transitions= 2.96e+10 Memory= 2932.686 t= 4.82e+04 R= 1e+03
+Depth= 117893 States= 6.8e+07 Transitions= 3.03e+10 Memory= 2956.123 t= 4.96e+04 R= 1e+03
+Depth= 117893 States= 6.9e+07 Transitions= 3.14e+10 Memory= 2985.908 t= 5.13e+04 R= 1e+03
+Depth= 117893 States= 7e+07 Transitions= 3.24e+10 Memory= 3015.303 t= 5.31e+04 R= 1e+03
+Depth= 117893 States= 7.1e+07 Transitions= 3.36e+10 Memory= 3039.912 t= 5.5e+04 R= 1e+03
+Depth= 117893 States= 7.2e+07 Transitions= 3.47e+10 Memory= 3065.401 t= 5.69e+04 R= 1e+03
+Depth= 117893 States= 7.3e+07 Transitions= 3.58e+10 Memory= 3086.690 t= 5.87e+04 R= 1e+03
+Depth= 117893 States= 7.4e+07 Transitions= 3.67e+10 Memory= 3108.272 t= 6.02e+04 R= 1e+03
+Depth= 117893 States= 7.5e+07 Transitions= 3.78e+10 Memory= 3127.608 t= 6.21e+04 R= 1e+03
+Depth= 117893 States= 7.6e+07 Transitions= 3.89e+10 Memory= 3147.627 t= 6.39e+04 R= 1e+03
+Depth= 117893 States= 7.7e+07 Transitions= 3.97e+10 Memory= 3167.647 t= 6.53e+04 R= 1e+03
+Depth= 117893 States= 7.8e+07 Transitions= 4.01e+10 Memory= 3195.772 t= 6.6e+04 R= 1e+03
+Depth= 117893 States= 7.9e+07 Transitions= 4.07e+10 Memory= 3221.065 t= 6.69e+04 R= 1e+03
+Depth= 117893 States= 8e+07 Transitions= 4.14e+10 Memory= 3245.869 t= 6.8e+04 R= 1e+03
+Depth= 117893 States= 8.1e+07 Transitions= 4.26e+10 Memory= 3270.186 t= 7e+04 R= 1e+03
+Depth= 117893 States= 8.2e+07 Transitions= 4.33e+10 Memory= 3293.135 t= 7.12e+04 R= 1e+03
+Depth= 117893 States= 8.3e+07 Transitions= 4.38e+10 Memory= 3323.701 t= 7.21e+04 R= 1e+03
+Depth= 117893 States= 8.4e+07 Transitions= 4.41e+10 Memory= 3350.752 t= 7.26e+04 R= 1e+03
+Depth= 117893 States= 8.5e+07 Transitions= 4.45e+10 Memory= 3375.166 t= 7.31e+04 R= 1e+03
+Depth= 117893 States= 8.6e+07 Transitions= 4.49e+10 Memory= 3397.432 t= 7.37e+04 R= 1e+03
+Depth= 117893 States= 8.7e+07 Transitions= 4.53e+10 Memory= 3424.287 t= 7.44e+04 R= 1e+03
+Depth= 117893 States= 8.8e+07 Transitions= 4.61e+10 Memory= 3449.385 t= 7.58e+04 R= 1e+03
+Depth= 117893 States= 8.9e+07 Transitions= 4.71e+10 Memory= 3469.795 t= 7.74e+04 R= 1e+03
+Depth= 117893 States= 9e+07 Transitions= 4.75e+10 Memory= 3498.018 t= 7.81e+04 R= 1e+03
+Depth= 117893 States= 9.1e+07 Transitions= 4.8e+10 Memory= 3524.678 t= 7.88e+04 R= 1e+03
+Depth= 117893 States= 9.2e+07 Transitions= 4.88e+10 Memory= 3549.776 t= 8.02e+04 R= 1e+03
+Depth= 117893 States= 9.3e+07 Transitions= 4.97e+10 Memory= 3573.897 t= 8.16e+04 R= 1e+03
+Depth= 117893 States= 9.4e+07 Transitions= 5.03e+10 Memory= 3598.311 t= 8.26e+04 R= 1e+03
+Depth= 117893 States= 9.5e+07 Transitions= 5.12e+10 Memory= 3621.358 t= 8.41e+04 R= 1e+03
+Depth= 117893 States= 9.6e+07 Transitions= 5.19e+10 Memory= 3645.381 t= 8.52e+04 R= 1e+03
+Depth= 117893 States= 9.7e+07 Transitions= 5.26e+10 Memory= 3669.502 t= 8.64e+04 R= 1e+03
+Depth= 117893 States= 9.8e+07 Transitions= 5.32e+10 Memory= 3693.233 t= 8.75e+04 R= 1e+03
+Depth= 117893 States= 9.9e+07 Transitions= 5.36e+10 Memory= 3723.115 t= 8.8e+04 R= 1e+03
+Depth= 117893 States= 1e+08 Transitions= 5.41e+10 Memory= 3748.799 t= 8.89e+04 R= 1e+03
+Depth= 117893 States= 1.01e+08 Transitions= 5.51e+10 Memory= 3771.943 t= 9.05e+04 R= 1e+03
+Depth= 117893 States= 1.02e+08 Transitions= 5.59e+10 Memory= 3796.651 t= 9.18e+04 R= 1e+03
+Depth= 117893 States= 1.03e+08 Transitions= 5.64e+10 Memory= 3820.967 t= 9.28e+04 R= 1e+03
+Depth= 117893 States= 1.04e+08 Transitions= 5.71e+10 Memory= 3845.283 t= 9.39e+04 R= 1e+03
+Depth= 117893 States= 1.05e+08 Transitions= 5.76e+10 Memory= 3872.041 t= 9.46e+04 R= 1e+03
+Depth= 117893 States= 1.06e+08 Transitions= 5.8e+10 Memory= 3901.436 t= 9.54e+04 R= 1e+03
+Depth= 117893 States= 1.07e+08 Transitions= 5.85e+10 Memory= 3931.026 t= 9.61e+04 R= 1e+03
+Depth= 117893 States= 1.08e+08 Transitions= 5.89e+10 Memory= 3956.318 t= 9.68e+04 R= 1e+03
+Depth= 117893 States= 1.09e+08 Transitions= 5.96e+10 Memory= 3978.486 t= 9.79e+04 R= 1e+03
+Depth= 117893 States= 1.1e+08 Transitions= 6.02e+10 Memory= 4002.901 t= 9.89e+04 R= 1e+03
+Depth= 117893 States= 1.11e+08 Transitions= 6.06e+10 Memory= 4027.803 t= 9.96e+04 R= 1e+03
+Depth= 117893 States= 1.12e+08 Transitions= 6.12e+10 Memory= 4051.924 t= 1.01e+05 R= 1e+03
+Depth= 117893 States= 1.13e+08 Transitions= 6.16e+10 Memory= 4079.365 t= 1.01e+05 R= 1e+03
+Depth= 117893 States= 1.14e+08 Transitions= 6.22e+10 Memory= 4104.756 t= 1.02e+05 R= 1e+03
+Depth= 117893 States= 1.15e+08 Transitions= 6.28e+10 Memory= 4129.268 t= 1.03e+05 R= 1e+03
+Depth= 117893 States= 1.16e+08 Transitions= 6.38e+10 Memory= 4155.537 t= 1.05e+05 R= 1e+03
+Depth= 117893 States= 1.17e+08 Transitions= 6.44e+10 Memory= 4184.443 t= 1.06e+05 R= 1e+03
+Depth= 117893 States= 1.18e+08 Transitions= 6.48e+10 Memory= 4211.397 t= 1.07e+05 R= 1e+03
+Depth= 117893 States= 1.19e+08 Transitions= 6.51e+10 Memory= 4234.248 t= 1.07e+05 R= 1e+03
+Depth= 117893 States= 1.2e+08 Transitions= 6.58e+10 Memory= 4262.471 t= 1.08e+05 R= 1e+03
+Depth= 117893 States= 1.21e+08 Transitions= 6.65e+10 Memory= 4289.912 t= 1.17e+05 R= 1e+03
+Depth= 117893 States= 1.22e+08 Transitions= 6.69e+10 Memory= 4315.791 t= 1.17e+05 R= 1e+03
+Depth= 117893 States= 1.23e+08 Transitions= 6.74e+10 Memory= 4343.330 t= 1.18e+05 R= 1e+03
+Depth= 117893 States= 1.24e+08 Transitions= 6.83e+10 Memory= 4368.623 t= 1.19e+05 R= 1e+03
+Depth= 117893 States= 1.25e+08 Transitions= 6.86e+10 Memory= 4395.674 t= 1.2e+05 R= 1e+03
+Depth= 117893 States= 1.26e+08 Transitions= 6.9e+10 Memory= 4419.990 t= 1.21e+05 R= 1e+03
+Depth= 117893 States= 1.27e+08 Transitions= 6.94e+10 Memory= 4448.115 t= 1.21e+05 R= 1e+03
+Depth= 117893 States= 1.28e+08 Transitions= 7.02e+10 Memory= 4473.994 t= 1.23e+05 R= 1e+03
+Depth= 117893 States= 1.29e+08 Transitions= 7.05e+10 Memory= 4500.947 t= 1.23e+05 R= 1e+03
+Depth= 117893 States= 1.3e+08 Transitions= 7.09e+10 Memory= 4526.826 t= 1.24e+05 R= 1e+03
+Depth= 117893 States= 1.31e+08 Transitions= 7.18e+10 Memory= 4553.291 t= 1.25e+05 R= 1e+03
+Depth= 117893 States= 1.32e+08 Transitions= 7.21e+10 Memory= 4581.221 t= 1.26e+05 R= 1e+03
+Depth= 117893 States= 1.33e+08 Transitions= 7.25e+10 Memory= 4605.830 t= 1.26e+05 R= 1e+03
+Depth= 117893 States= 1.34e+08 Transitions= 7.3e+10 Memory= 4632.197 t= 1.27e+05 R= 1e+03
+Depth= 117893 States= 1.35e+08 Transitions= 7.35e+10 Memory= 4657.588 t= 1.33e+05 R= 1e+03
+pan: resizing hashtable to -w28.. done
+Depth= 117893 States= 1.36e+08 Transitions= 7.38e+10 Memory= 6705.588 t= 1.33e+05 R= 1e+03
+Depth= 117893 States= 1.37e+08 Transitions= 7.46e+10 Memory= 6705.588 t= 1.35e+05 R= 1e+03
+Depth= 117893 States= 1.38e+08 Transitions= 7.54e+10 Memory= 6720.627 t= 1.36e+05 R= 1e+03
+Depth= 117893 States= 1.39e+08 Transitions= 7.57e+10 Memory= 6750.217 t= 1.37e+05 R= 1e+03
+Depth= 117893 States= 1.4e+08 Transitions= 7.61e+10 Memory= 6775.803 t= 1.37e+05 R= 1e+03
+Depth= 117893 States= 1.41e+08 Transitions= 7.65e+10 Memory= 6797.190 t= 1.38e+05 R= 1e+03
+Depth= 117893 States= 1.42e+08 Transitions= 7.71e+10 Memory= 6823.068 t= 1.39e+05 R= 1e+03
+Depth= 117893 States= 1.43e+08 Transitions= 7.76e+10 Memory= 6851.682 t= 1.4e+05 R= 1e+03
+Depth= 117893 States= 1.44e+08 Transitions= 7.83e+10 Memory= 6879.611 t= 1.41e+05 R= 1e+03
+Depth= 117893 States= 1.45e+08 Transitions= 7.87e+10 Memory= 6905.100 t= 1.41e+05 R= 1e+03
+Depth= 117893 States= 1.46e+08 Transitions= 7.91e+10 Memory= 6929.318 t= 1.42e+05 R= 1e+03
+Depth= 117893 States= 1.47e+08 Transitions= 7.96e+10 Memory= 6954.709 t= 1.43e+05 R= 1e+03
+Depth= 117893 States= 1.48e+08 Transitions= 8e+10 Memory= 6983.225 t= 1.44e+05 R= 1e+03
+Depth= 117893 States= 1.49e+08 Transitions= 8.05e+10 Memory= 7013.791 t= 1.44e+05 R= 1e+03
+Depth= 117893 States= 1.5e+08 Transitions= 8.15e+10 Memory= 7037.033 t= 1.46e+05 R= 1e+03
+Depth= 117893 States= 1.51e+08 Transitions= 8.19e+10 Memory= 7068.381 t= 1.47e+05 R= 1e+03
+Depth= 117893 States= 1.52e+08 Transitions= 8.22e+10 Memory= 7093.576 t= 1.47e+05 R= 1e+03
+Depth= 117893 States= 1.53e+08 Transitions= 8.26e+10 Memory= 7115.842 t= 1.48e+05 R= 1e+03
+Depth= 117893 States= 1.54e+08 Transitions= 8.3e+10 Memory= 7144.358 t= 1.48e+05 R= 1e+03
+Depth= 117893 States= 1.55e+08 Transitions= 8.39e+10 Memory= 7170.432 t= 1.5e+05 R= 1e+03
+Depth= 117893 States= 1.56e+08 Transitions= 8.42e+10 Memory= 7197.483 t= 1.5e+05 R= 1e+03
+Depth= 117893 States= 1.57e+08 Transitions= 8.46e+10 Memory= 7220.725 t= 1.51e+05 R= 1e+03
+Depth= 117893 States= 1.58e+08 Transitions= 8.51e+10 Memory= 7246.701 t= 1.52e+05 R= 1e+03
+Depth= 117893 States= 1.59e+08 Transitions= 8.55e+10 Memory= 7273.752 t= 1.52e+05 R= 1e+03
+Depth= 117893 States= 1.6e+08 Transitions= 8.58e+10 Memory= 7302.951 t= 1.53e+05 R= 1e+03
+Depth= 117893 States= 1.61e+08 Transitions= 8.64e+10 Memory= 7327.365 t= 1.54e+05 R= 1e+03
+Depth= 117893 States= 1.62e+08 Transitions= 8.69e+10 Memory= 7353.049 t= 1.55e+05 R= 1e+03
+Depth= 117893 States= 1.63e+08 Transitions= 8.73e+10 Memory= 7379.318 t= 1.55e+05 R= 1e+03
+Depth= 117893 States= 1.64e+08 Transitions= 8.77e+10 Memory= 7404.904 t= 1.56e+05 R= 1e+03
+Depth= 117893 States= 1.65e+08 Transitions= 8.82e+10 Memory= 7429.514 t= 1.57e+05 R= 1e+03
+Depth= 117893 States= 1.66e+08 Transitions= 8.87e+10 Memory= 7453.733 t= 1.58e+05 R= 1e+03
+Depth= 117893 States= 1.67e+08 Transitions= 8.95e+10 Memory= 7477.561 t= 1.59e+05 R= 1e+03
+Depth= 117893 States= 1.68e+08 Transitions= 9.02e+10 Memory= 7501.096 t= 1.6e+05 R= 1e+03
+Depth= 117893 States= 1.69e+08 Transitions= 9.07e+10 Memory= 7527.365 t= 1.61e+05 R= 1e+03
+Depth= 117893 States= 1.7e+08 Transitions= 9.11e+10 Memory= 7553.830 t= 1.61e+05 R= 1e+03
+Depth= 117893 States= 1.71e+08 Transitions= 9.16e+10 Memory= 7577.951 t= 1.62e+05 R= 1e+03
+Depth= 117893 States= 1.72e+08 Transitions= 9.24e+10 Memory= 7602.658 t= 1.63e+05 R= 1e+03
+Depth= 117893 States= 1.73e+08 Transitions= 9.35e+10 Memory= 7626.096 t= 1.65e+05 R= 1e+03
+Depth= 117893 States= 1.74e+08 Transitions= 9.39e+10 Memory= 7656.369 t= 1.66e+05 R= 1e+03
+Depth= 117893 States= 1.75e+08 Transitions= 9.43e+10 Memory= 7682.834 t= 1.67e+05 R= 1e+03
+Depth= 117893 States= 1.76e+08 Transitions= 9.49e+10 Memory= 7709.201 t= 1.67e+05 R= 1e+03
+Depth= 117893 States= 1.77e+08 Transitions= 9.55e+10 Memory= 7736.447 t= 1.68e+05 R= 1e+03
+Depth= 117893 States= 1.78e+08 Transitions= 9.61e+10 Memory= 7763.791 t= 1.69e+05 R= 1e+03
+Depth= 117893 States= 1.79e+08 Transitions= 9.66e+10 Memory= 7790.061 t= 1.7e+05 R= 1e+03
+Depth= 117893 States= 1.8e+08 Transitions= 9.72e+10 Memory= 7817.600 t= 1.71e+05 R= 1e+03
+Depth= 117893 States= 1.81e+08 Transitions= 9.8e+10 Memory= 7837.912 t= 1.73e+05 R= 1e+03
+Depth= 117893 States= 1.82e+08 Transitions= 9.88e+10 Memory= 7858.127 t= 1.74e+05 R= 1e+03
+Depth= 117893 States= 1.83e+08 Transitions= 9.95e+10 Memory= 7886.154 t= 1.75e+05 R= 1e+03
+Depth= 117893 States= 1.84e+08 Transitions= 1e+11 Memory= 7912.522 t= 1.76e+05 R= 1e+03
+Depth= 117893 States= 1.85e+08 Transitions= 1.01e+11 Memory= 7937.717 t= 1.77e+05 R= 1e+03
+Depth= 117893 States= 1.86e+08 Transitions= 1.02e+11 Memory= 7962.815 t= 1.78e+05 R= 1e+03
+Depth= 117893 States= 1.87e+08 Transitions= 1.02e+11 Memory= 7988.010 t= 1.79e+05 R= 1e+03
+Depth= 117893 States= 1.88e+08 Transitions= 1.03e+11 Memory= 8014.768 t= 1.8e+05 R= 1e+03
+Depth= 117893 States= 1.89e+08 Transitions= 1.03e+11 Memory= 8040.061 t= 1.81e+05 R= 1e+03
+Depth= 117893 States= 1.9e+08 Transitions= 1.04e+11 Memory= 8066.818 t= 1.82e+05 R= 1e+03
+Depth= 117893 States= 1.91e+08 Transitions= 1.05e+11 Memory= 8090.451 t= 1.83e+05 R= 1e+03
+Depth= 117893 States= 1.92e+08 Transitions= 1.05e+11 Memory= 8116.330 t= 1.84e+05 R= 1e+03
+Depth= 117893 States= 1.93e+08 Transitions= 1.06e+11 Memory= 8144.748 t= 1.85e+05 R= 1e+03
+Depth= 117893 States= 1.94e+08 Transitions= 1.07e+11 Memory= 8170.822 t= 1.86e+05 R= 1e+03
+Depth= 117893 States= 1.95e+08 Transitions= 1.07e+11 Memory= 8196.604 t= 1.87e+05 R= 1e+03
+Depth= 117893 States= 1.96e+08 Transitions= 1.07e+11 Memory= 8222.873 t= 1.87e+05 R= 1e+03
+Depth= 117893 States= 1.97e+08 Transitions= 1.08e+11 Memory= 8252.658 t= 1.88e+05 R= 1e+03
+Depth= 117893 States= 1.98e+08 Transitions= 1.08e+11 Memory= 8278.147 t= 1.89e+05 R= 1e+03
+Depth= 117893 States= 1.99e+08 Transitions= 1.08e+11 Memory= 8305.490 t= 1.89e+05 R= 1e+03
+Depth= 117893 States= 2e+08 Transitions= 1.09e+11 Memory= 8332.151 t= 1.9e+05 R= 1e+03
+Depth= 117893 States= 2.01e+08 Transitions= 1.09e+11 Memory= 8355.979 t= 1.91e+05 R= 1e+03
+Depth= 117893 States= 2.02e+08 Transitions= 1.1e+11 Memory= 8383.225 t= 1.91e+05 R= 1e+03
+Depth= 117893 States= 2.03e+08 Transitions= 1.1e+11 Memory= 8410.959 t= 1.92e+05 R= 1e+03
+Depth= 117893 States= 2.04e+08 Transitions= 1.11e+11 Memory= 8437.912 t= 1.93e+05 R= 1e+03
+Depth= 117893 States= 2.05e+08 Transitions= 1.11e+11 Memory= 8465.256 t= 1.94e+05 R= 1e+03
+Depth= 117893 States= 2.06e+08 Transitions= 1.12e+11 Memory= 8489.670 t= 1.94e+05 R= 1e+03
+Depth= 117893 States= 2.07e+08 Transitions= 1.12e+11 Memory= 8517.600 t= 1.95e+05 R= 1e+03
+Depth= 117893 States= 2.08e+08 Transitions= 1.12e+11 Memory= 8543.088 t= 1.96e+05 R= 1e+03
+Depth= 117893 States= 2.09e+08 Transitions= 1.13e+11 Memory= 8566.233 t= 1.97e+05 R= 1e+03
+Depth= 117893 States= 2.1e+08 Transitions= 1.14e+11 Memory= 8590.744 t= 1.98e+05 R= 1e+03
+Depth= 117893 States= 2.11e+08 Transitions= 1.14e+11 Memory= 8613.693 t= 1.99e+05 R= 1e+03
+Depth= 117893 States= 2.12e+08 Transitions= 1.15e+11 Memory= 8642.502 t= 2.01e+05 R= 1e+03
+Depth= 117893 States= 2.13e+08 Transitions= 1.16e+11 Memory= 8672.873 t= 2.02e+05 R= 1e+03
+Depth= 117893 States= 2.14e+08 Transitions= 1.18e+11 Memory= 8697.483 t= 2.04e+05 R= 1e+03
+Depth= 117893 States= 2.15e+08 Transitions= 1.19e+11 Memory= 8722.190 t= 2.06e+05 R= 1e+03
+Depth= 117893 States= 2.16e+08 Transitions= 1.2e+11 Memory= 8744.455 t= 2.08e+05 R= 1e+03
+Depth= 117893 States= 2.17e+08 Transitions= 1.21e+11 Memory= 8765.842 t= 2.09e+05 R= 1e+03
+Depth= 117893 States= 2.18e+08 Transitions= 1.22e+11 Memory= 8785.861 t= 2.11e+05 R= 1e+03
+Depth= 117893 States= 2.19e+08 Transitions= 1.23e+11 Memory= 8804.904 t= 2.13e+05 R= 1e+03
+Depth= 117893 States= 2.2e+08 Transitions= 1.24e+11 Memory= 8823.850 t= 2.15e+05 R= 1e+03
+Depth= 117893 States= 2.21e+08 Transitions= 1.24e+11 Memory= 8850.705 t= 2.15e+05 R= 1e+03
+Depth= 117893 States= 2.22e+08 Transitions= 1.25e+11 Memory= 8877.365 t= 2.16e+05 R= 1e+03
+Depth= 117893 States= 2.23e+08 Transitions= 1.25e+11 Memory= 8902.268 t= 2.17e+05 R= 1e+03
+Depth= 117893 States= 2.24e+08 Transitions= 1.26e+11 Memory= 8927.268 t= 2.19e+05 R= 1e+03
+Depth= 117893 States= 2.25e+08 Transitions= 1.27e+11 Memory= 8949.143 t= 2.2e+05 R= 1e+03
+Depth= 117893 States= 2.26e+08 Transitions= 1.28e+11 Memory= 8973.459 t= 2.22e+05 R= 1e+03
+Depth= 117893 States= 2.27e+08 Transitions= 1.29e+11 Memory= 9004.807 t= 2.22e+05 R= 1e+03
+Depth= 117893 States= 2.28e+08 Transitions= 1.29e+11 Memory= 9031.174 t= 2.23e+05 R= 1e+03
+Depth= 117893 States= 2.29e+08 Transitions= 1.29e+11 Memory= 9054.709 t= 2.23e+05 R= 1e+03
+Depth= 117893 States= 2.3e+08 Transitions= 1.3e+11 Memory= 9077.756 t= 2.24e+05 R= 1e+03
+Depth= 117893 States= 2.31e+08 Transitions= 1.3e+11 Memory= 9103.830 t= 2.25e+05 R= 1e+03
+Depth= 117893 States= 2.32e+08 Transitions= 1.31e+11 Memory= 9128.830 t= 2.26e+05 R= 1e+03
+Depth= 117893 States= 2.33e+08 Transitions= 1.32e+11 Memory= 9150.315 t= 2.28e+05 R= 1e+03
+Depth= 117893 States= 2.34e+08 Transitions= 1.32e+11 Memory= 9175.705 t= 2.29e+05 R= 1e+03
+Depth= 117893 States= 2.35e+08 Transitions= 1.33e+11 Memory= 9201.096 t= 2.3e+05 R= 1e+03
+Depth= 117893 States= 2.36e+08 Transitions= 1.34e+11 Memory= 9226.682 t= 2.31e+05 R= 1e+03
+Depth= 117893 States= 2.37e+08 Transitions= 1.34e+11 Memory= 9253.049 t= 2.31e+05 R= 1e+03
+Depth= 117893 States= 2.38e+08 Transitions= 1.35e+11 Memory= 9276.291 t= 2.33e+05 R= 1e+03
+Depth= 117893 States= 2.39e+08 Transitions= 1.36e+11 Memory= 9300.608 t= 2.34e+05 R= 1e+03
+Depth= 117893 States= 2.4e+08 Transitions= 1.37e+11 Memory= 9324.240 t= 2.35e+05 R= 1e+03
+Depth= 117893 States= 2.41e+08 Transitions= 1.37e+11 Memory= 9348.361 t= 2.37e+05 R= 1e+03
+Depth= 117893 States= 2.42e+08 Transitions= 1.38e+11 Memory= 9372.873 t= 2.38e+05 R= 1e+03
+Depth= 117893 States= 2.43e+08 Transitions= 1.39e+11 Memory= 9396.604 t= 2.39e+05 R= 1e+03
+Depth= 117893 States= 2.44e+08 Transitions= 1.39e+11 Memory= 9421.994 t= 2.4e+05 R= 1e+03
+Depth= 117893 States= 2.45e+08 Transitions= 1.4e+11 Memory= 9450.998 t= 2.41e+05 R= 1e+03
+Depth= 117893 States= 2.46e+08 Transitions= 1.41e+11 Memory= 9475.217 t= 2.42e+05 R= 1e+03
+Depth= 117893 States= 2.47e+08 Transitions= 1.41e+11 Memory= 9498.264 t= 2.43e+05 R= 1e+03
+Depth= 117893 States= 2.48e+08 Transitions= 1.42e+11 Memory= 9522.580 t= 2.44e+05 R= 1e+03
+Depth= 117893 States= 2.49e+08 Transitions= 1.42e+11 Memory= 9549.924 t= 2.45e+05 R= 1e+03
+Depth= 117893 States= 2.5e+08 Transitions= 1.43e+11 Memory= 9579.807 t= 2.45e+05 R= 1e+03
+Depth= 117893 States= 2.51e+08 Transitions= 1.43e+11 Memory= 9609.104 t= 2.46e+05 R= 1e+03
+Depth= 117893 States= 2.52e+08 Transitions= 1.44e+11 Memory= 9631.858 t= 2.47e+05 R= 1e+03
+Depth= 117893 States= 2.53e+08 Transitions= 1.45e+11 Memory= 9652.756 t= 2.48e+05 R= 1e+03
+Depth= 117893 States= 2.54e+08 Transitions= 1.45e+11 Memory= 9678.733 t= 2.49e+05 R= 1e+03
+Depth= 117893 States= 2.55e+08 Transitions= 1.45e+11 Memory= 9703.733 t= 2.5e+05 R= 1e+03
+Depth= 117893 States= 2.56e+08 Transitions= 1.46e+11 Memory= 9728.440 t= 2.5e+05 R= 1e+03
+Depth= 117893 States= 2.57e+08 Transitions= 1.46e+11 Memory= 9757.834 t= 2.51e+05 R= 1e+03
+Depth= 117893 States= 2.58e+08 Transitions= 1.47e+11 Memory= 9784.006 t= 2.52e+05 R= 1e+03
+Depth= 117893 States= 2.59e+08 Transitions= 1.48e+11 Memory= 9810.959 t= 2.54e+05 R= 1e+03
+Depth= 117893 States= 2.6e+08 Transitions= 1.48e+11 Memory= 9839.475 t= 2.54e+05 R= 1e+03
+Depth= 117893 States= 2.61e+08 Transitions= 1.49e+11 Memory= 9862.717 t= 2.55e+05 R= 1e+03
+Depth= 117893 States= 2.62e+08 Transitions= 1.49e+11 Memory= 9891.428 t= 2.56e+05 R= 1e+03
+Depth= 117893 States= 2.63e+08 Transitions= 1.5e+11 Memory= 9916.623 t= 2.57e+05 R= 1e+03
+Depth= 117893 States= 2.64e+08 Transitions= 1.5e+11 Memory= 9944.162 t= 2.58e+05 R= 1e+03
+Depth= 117893 States= 2.65e+08 Transitions= 1.51e+11 Memory= 9969.358 t= 2.58e+05 R= 1e+03
+Depth= 117893 States= 2.66e+08 Transitions= 1.52e+11 Memory= 9995.432 t= 2.6e+05 R= 1e+03
+Depth= 117893 States= 2.67e+08 Transitions= 1.52e+11 Memory= 10023.654 t= 2.6e+05 R= 1e+03
+Depth= 117893 States= 2.68e+08 Transitions= 1.52e+11 Memory= 10047.580 t= 2.61e+05 R= 1e+03
+Depth= 117893 States= 2.69e+08 Transitions= 1.53e+11 Memory= 10075.022 t= 2.62e+05 R= 1e+03
+Depth= 117893 States= 2.7e+08 Transitions= 1.54e+11 Memory= 10101.779 t= 2.63e+05 R= 1e+03
+Depth= 117893 States= 2.71e+08 Transitions= 1.54e+11 Memory= 10129.221 t= 2.64e+05 R= 1e+03
+Depth= 117893 States= 2.72e+08 Transitions= 1.54e+11 Memory= 10154.416 t= 2.64e+05 R= 1e+03
+Depth= 117893 States= 2.73e+08 Transitions= 1.55e+11 Memory= 10180.393 t= 2.66e+05 R= 1e+03
+Depth= 117893 States= 2.74e+08 Transitions= 1.56e+11 Memory= 10209.104 t= 2.66e+05 R= 1e+03
+Depth= 117893 States= 2.75e+08 Transitions= 1.56e+11 Memory= 10232.541 t= 2.67e+05 R= 1e+03
+Depth= 117893 States= 2.76e+08 Transitions= 1.57e+11 Memory= 10259.690 t= 2.68e+05 R= 1e+03
+Depth= 117893 States= 2.77e+08 Transitions= 1.57e+11 Memory= 10285.080 t= 2.68e+05 R= 1e+03
+Depth= 117893 States= 2.78e+08 Transitions= 1.57e+11 Memory= 10311.154 t= 2.69e+05 R= 1e+03
+Depth= 117893 States= 2.79e+08 Transitions= 1.58e+11 Memory= 10337.033 t= 2.71e+05 R= 1e+03
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+depth 7: Claim reached state 9 (line 1367)
+depth 50: Claim reached state 9 (line 1366)
+Depth= 7605 States= 1e+06 Transitions= 3.21e+08 Memory= 493.010 t= 500 R= 2e+03
+Depth= 7605 States= 2e+06 Transitions= 6.35e+08 Memory= 518.401 t= 996 R= 2e+03
+Depth= 7605 States= 3e+06 Transitions= 9.46e+08 Memory= 549.455 t= 1.5e+03 R= 2e+03
+pan: resizing hashtable to -w22.. done
+Depth= 7605 States= 4e+06 Transitions= 1.25e+09 Memory= 609.776 t= 1.97e+03 R= 2e+03
+Depth= 9389 States= 5e+06 Transitions= 1.56e+09 Memory= 634.873 t= 2.46e+03 R= 2e+03
+Depth= 9389 States= 6e+06 Transitions= 1.88e+09 Memory= 662.315 t= 2.97e+03 R= 2e+03
+Depth= 9389 States= 7e+06 Transitions= 2.25e+09 Memory= 688.193 t= 3.58e+03 R= 2e+03
+Depth= 9389 States= 8e+06 Transitions= 2.61e+09 Memory= 716.611 t= 4.18e+03 R= 2e+03
+Depth= 9389 States= 9e+06 Transitions= 2.96e+09 Memory= 743.662 t= 4.75e+03 R= 2e+03
+pan: resizing hashtable to -w24.. done
+Depth= 9389 States= 1e+07 Transitions= 3.29e+09 Memory= 894.611 t= 5.26e+03 R= 2e+03
+Depth= 9389 States= 1.1e+07 Transitions= 3.62e+09 Memory= 921.076 t= 5.77e+03 R= 2e+03
+Depth= 9389 States= 1.2e+07 Transitions= 3.93e+09 Memory= 947.053 t= 6.27e+03 R= 2e+03
+Depth= 9389 States= 1.3e+07 Transitions= 4.25e+09 Memory= 974.299 t= 6.76e+03 R= 2e+03
+Depth= 9389 States= 1.4e+07 Transitions= 4.55e+09 Memory= 1004.963 t= 7.23e+03 R= 2e+03
+Depth= 9389 States= 1.5e+07 Transitions= 4.87e+09 Memory= 1029.963 t= 7.73e+03 R= 2e+03
+Depth= 9389 States= 1.6e+07 Transitions= 5.18e+09 Memory= 1058.088 t= 8.23e+03 R= 2e+03
+Depth= 9389 States= 1.7e+07 Transitions= 5.48e+09 Memory= 1087.580 t= 8.71e+03 R= 2e+03
+Depth= 9389 States= 1.8e+07 Transitions= 5.79e+09 Memory= 1113.166 t= 9.19e+03 R= 2e+03
+Depth= 9389 States= 1.9e+07 Transitions= 6.1e+09 Memory= 1139.143 t= 9.68e+03 R= 2e+03
+Depth= 9389 States= 2e+07 Transitions= 6.59e+09 Memory= 1164.436 t= 1.05e+04 R= 2e+03
+Depth= 9389 States= 2.1e+07 Transitions= 7.19e+09 Memory= 1188.557 t= 1.15e+04 R= 2e+03
+Depth= 9389 States= 2.2e+07 Transitions= 8.02e+09 Memory= 1210.236 t= 1.28e+04 R= 2e+03
+Depth= 9389 States= 2.3e+07 Transitions= 8.41e+09 Memory= 1237.385 t= 1.35e+04 R= 2e+03
+Depth= 9389 States= 2.4e+07 Transitions= 8.96e+09 Memory= 1261.604 t= 1.44e+04 R= 2e+03
+Depth= 9389 States= 2.5e+07 Transitions= 9.91e+09 Memory= 1287.287 t= 1.6e+04 R= 2e+03
+Depth= 9389 States= 2.6e+07 Transitions= 1.06e+10 Memory= 1312.971 t= 1.71e+04 R= 2e+03
+Depth= 9600 States= 2.7e+07 Transitions= 1.1e+10 Memory= 1340.510 t= 1.78e+04 R= 2e+03
+Depth= 9600 States= 2.8e+07 Transitions= 1.15e+10 Memory= 1367.756 t= 1.86e+04 R= 2e+03
+Depth= 9600 States= 2.9e+07 Transitions= 1.21e+10 Memory= 1395.100 t= 1.96e+04 R= 1e+03
+Depth= 9600 States= 3e+07 Transitions= 1.27e+10 Memory= 1422.639 t= 2.05e+04 R= 1e+03
+Depth= 9600 States= 3.1e+07 Transitions= 1.32e+10 Memory= 1448.908 t= 2.15e+04 R= 1e+03
+Depth= 9600 States= 3.2e+07 Transitions= 1.39e+10 Memory= 1474.494 t= 2.25e+04 R= 1e+03
+Depth= 9600 States= 3.3e+07 Transitions= 1.46e+10 Memory= 1494.807 t= 2.38e+04 R= 1e+03
+Depth= 9600 States= 3.4e+07 Transitions= 1.52e+10 Memory= 1519.709 t= 2.47e+04 R= 1e+03
+pan: resizing hashtable to -w26.. done
+Depth= 9600 States= 3.5e+07 Transitions= 1.58e+10 Memory= 2042.061 t= 2.57e+04 R= 1e+03
+Depth= 9600 States= 3.6e+07 Transitions= 1.63e+10 Memory= 2068.916 t= 2.66e+04 R= 1e+03
+Depth= 9600 States= 3.7e+07 Transitions= 1.7e+10 Memory= 2094.404 t= 2.75e+04 R= 1e+03
+Depth= 9600 States= 3.8e+07 Transitions= 1.76e+10 Memory= 2119.893 t= 2.86e+04 R= 1e+03
+Depth= 9600 States= 3.9e+07 Transitions= 1.82e+10 Memory= 2144.697 t= 2.96e+04 R= 1e+03
+Depth= 9600 States= 4e+07 Transitions= 1.87e+10 Memory= 2173.018 t= 3.03e+04 R= 1e+03
+Depth= 9600 States= 4.1e+07 Transitions= 1.93e+10 Memory= 2200.068 t= 3.13e+04 R= 1e+03
+Depth= 9600 States= 4.2e+07 Transitions= 1.98e+10 Memory= 2225.459 t= 3.22e+04 R= 1e+03
+Depth= 9600 States= 4.3e+07 Transitions= 2.05e+10 Memory= 2252.217 t= 3.32e+04 R= 1e+03
+Depth= 9600 States= 4.4e+07 Transitions= 2.13e+10 Memory= 2275.557 t= 3.45e+04 R= 1e+03
+Depth= 9600 States= 4.5e+07 Transitions= 2.18e+10 Memory= 2303.096 t= 3.53e+04 R= 1e+03
+Depth= 9600 States= 4.6e+07 Transitions= 2.22e+10 Memory= 2327.608 t= 3.59e+04 R= 1e+03
+Depth= 9600 States= 4.7e+07 Transitions= 2.25e+10 Memory= 2355.342 t= 3.65e+04 R= 1e+03
+Depth= 9600 States= 4.8e+07 Transitions= 2.28e+10 Memory= 2385.029 t= 3.7e+04 R= 1e+03
+Depth= 9600 States= 4.9e+07 Transitions= 2.32e+10 Memory= 2413.643 t= 3.75e+04 R= 1e+03
+Depth= 9600 States= 5e+07 Transitions= 2.35e+10 Memory= 2439.522 t= 3.81e+04 R= 1e+03
+Depth= 9600 States= 5.1e+07 Transitions= 2.42e+10 Memory= 2462.959 t= 3.91e+04 R= 1e+03
+Depth= 9600 States= 5.2e+07 Transitions= 2.46e+10 Memory= 2490.498 t= 3.97e+04 R= 1e+03
+Depth= 9600 States= 5.3e+07 Transitions= 2.49e+10 Memory= 2519.600 t= 4.03e+04 R= 1e+03
+Depth= 9600 States= 5.4e+07 Transitions= 2.53e+10 Memory= 2545.674 t= 4.09e+04 R= 1e+03
+Depth= 9600 States= 5.5e+07 Transitions= 2.56e+10 Memory= 2574.190 t= 4.13e+04 R= 1e+03
+Depth= 9600 States= 5.6e+07 Transitions= 2.6e+10 Memory= 2598.604 t= 4.2e+04 R= 1e+03
+Depth= 9600 States= 5.7e+07 Transitions= 2.66e+10 Memory= 2622.334 t= 4.3e+04 R= 1e+03
+Depth= 9600 States= 5.8e+07 Transitions= 2.73e+10 Memory= 2645.869 t= 4.41e+04 R= 1e+03
+Depth= 9600 States= 5.9e+07 Transitions= 2.81e+10 Memory= 2668.623 t= 4.54e+04 R= 1e+03
+Depth= 9600 States= 6e+07 Transitions= 2.91e+10 Memory= 2701.631 t= 4.72e+04 R= 1e+03
+Depth= 9600 States= 6.1e+07 Transitions= 3.02e+10 Memory= 2729.170 t= 4.9e+04 R= 1e+03
+Depth= 9600 States= 6.2e+07 Transitions= 3.14e+10 Memory= 2754.072 t= 5.09e+04 R= 1e+03
+Depth= 9600 States= 6.3e+07 Transitions= 3.25e+10 Memory= 2778.682 t= 5.29e+04 R= 1e+03
+Depth= 9600 States= 6.4e+07 Transitions= 3.35e+10 Memory= 2799.190 t= 5.46e+04 R= 1e+03
+Depth= 9600 States= 6.5e+07 Transitions= 3.45e+10 Memory= 2820.869 t= 5.61e+04 R= 1e+03
+Depth= 9600 States= 6.6e+07 Transitions= 3.56e+10 Memory= 2840.401 t= 5.81e+04 R= 1e+03
+Depth= 9600 States= 6.7e+07 Transitions= 3.66e+10 Memory= 2859.443 t= 5.98e+04 R= 1e+03
+Depth= 9600 States= 6.8e+07 Transitions= 3.74e+10 Memory= 2881.807 t= 6.1e+04 R= 1e+03
+Depth= 9600 States= 6.9e+07 Transitions= 3.78e+10 Memory= 2909.053 t= 6.17e+04 R= 1e+03
+Depth= 9600 States= 7e+07 Transitions= 3.84e+10 Memory= 2934.151 t= 6.27e+04 R= 1e+03
+Depth= 9600 States= 7.1e+07 Transitions= 3.94e+10 Memory= 2959.053 t= 6.43e+04 R= 1e+03
+Depth= 9600 States= 7.2e+07 Transitions= 4.05e+10 Memory= 2980.049 t= 6.62e+04 R= 1e+03
+Depth= 9600 States= 7.3e+07 Transitions= 4.11e+10 Memory= 3007.197 t= 6.72e+04 R= 1e+03
+Depth= 9600 States= 7.4e+07 Transitions= 4.14e+10 Memory= 3037.276 t= 6.78e+04 R= 1e+03
+Depth= 9600 States= 7.5e+07 Transitions= 4.18e+10 Memory= 3063.252 t= 6.83e+04 R= 1e+03
+Depth= 9600 States= 7.6e+07 Transitions= 4.21e+10 Memory= 3087.276 t= 6.89e+04 R= 1e+03
+Depth= 9600 States= 7.7e+07 Transitions= 4.26e+10 Memory= 3112.178 t= 6.95e+04 R= 1e+03
+Depth= 9600 States= 7.8e+07 Transitions= 4.3e+10 Memory= 3137.764 t= 7.03e+04 R= 1e+03
+Depth= 9600 States= 7.9e+07 Transitions= 4.4e+10 Memory= 3162.178 t= 7.2e+04 R= 1e+03
+Depth= 9600 States= 8e+07 Transitions= 4.48e+10 Memory= 3185.420 t= 7.32e+04 R= 1e+03
+Depth= 9600 States= 8.1e+07 Transitions= 4.53e+10 Memory= 3212.276 t= 7.4e+04 R= 1e+03
+Depth= 9600 States= 8.2e+07 Transitions= 4.6e+10 Memory= 3237.178 t= 7.52e+04 R= 1e+03
+Depth= 9600 States= 8.3e+07 Transitions= 4.7e+10 Memory= 3261.299 t= 7.69e+04 R= 1e+03
+Depth= 9600 States= 8.4e+07 Transitions= 4.75e+10 Memory= 3286.104 t= 7.76e+04 R= 1e+03
+Depth= 9600 States= 8.5e+07 Transitions= 4.84e+10 Memory= 3309.639 t= 7.91e+04 R= 1e+03
+Depth= 9600 States= 8.6e+07 Transitions= 4.91e+10 Memory= 3333.272 t= 8.04e+04 R= 1e+03
+Depth= 9600 States= 8.7e+07 Transitions= 4.98e+10 Memory= 3358.272 t= 8.15e+04 R= 1e+03
+Depth= 9600 States= 8.8e+07 Transitions= 5.04e+10 Memory= 3382.490 t= 8.25e+04 R= 1e+03
+Depth= 9600 States= 8.9e+07 Transitions= 5.09e+10 Memory= 3410.908 t= 8.32e+04 R= 1e+03
+Depth= 9600 States= 9e+07 Transitions= 5.14e+10 Memory= 3437.959 t= 8.41e+04 R= 1e+03
+Depth= 9600 States= 9.1e+07 Transitions= 5.23e+10 Memory= 3460.908 t= 8.56e+04 R= 1e+03
+Depth= 9600 States= 9.2e+07 Transitions= 5.32e+10 Memory= 3484.639 t= 8.71e+04 R= 1e+03
+Depth= 9600 States= 9.3e+07 Transitions= 5.37e+10 Memory= 3509.932 t= 8.79e+04 R= 1e+03
+Depth= 9600 States= 9.4e+07 Transitions= 5.44e+10 Memory= 3534.346 t= 8.91e+04 R= 1e+03
+Depth= 9600 States= 9.5e+07 Transitions= 5.49e+10 Memory= 3561.299 t= 8.98e+04 R= 1e+03
+Depth= 9600 States= 9.6e+07 Transitions= 5.53e+10 Memory= 3589.522 t= 9.06e+04 R= 1e+03
+Depth= 9600 States= 9.7e+07 Transitions= 5.58e+10 Memory= 3619.209 t= 9.14e+04 R= 1e+03
+Depth= 9600 States= 9.8e+07 Transitions= 5.62e+10 Memory= 3645.576 t= 9.2e+04 R= 1e+03
+Depth= 9600 States= 9.9e+07 Transitions= 5.68e+10 Memory= 3668.623 t= 9.31e+04 R= 1e+03
+Depth= 9600 States= 1e+08 Transitions= 5.75e+10 Memory= 3692.061 t= 9.41e+04 R= 1e+03
+Depth= 9600 States= 1.01e+08 Transitions= 5.79e+10 Memory= 3717.940 t= 9.48e+04 R= 1e+03
+Depth= 9600 States= 1.02e+08 Transitions= 5.85e+10 Memory= 3741.963 t= 9.57e+04 R= 1e+03
+Depth= 9600 States= 1.03e+08 Transitions= 5.89e+10 Memory= 3768.428 t= 9.64e+04 R= 1e+03
+Depth= 9600 States= 1.04e+08 Transitions= 5.95e+10 Memory= 3795.186 t= 9.75e+04 R= 1e+03
+Depth= 9600 States= 1.05e+08 Transitions= 6.01e+10 Memory= 3820.283 t= 9.84e+04 R= 1e+03
+Depth= 9600 States= 1.06e+08 Transitions= 6.09e+10 Memory= 3846.358 t= 9.98e+04 R= 1e+03
+Depth= 10157 States= 1.07e+08 Transitions= 6.17e+10 Memory= 3873.408 t= 1.01e+05 R= 1e+03
+Depth= 10157 States= 1.08e+08 Transitions= 6.21e+10 Memory= 3901.924 t= 1.02e+05 R= 1e+03
+Depth= 10157 States= 1.09e+08 Transitions= 6.24e+10 Memory= 3925.850 t= 1.02e+05 R= 1e+03
+Depth= 10157 States= 1.1e+08 Transitions= 6.29e+10 Memory= 3955.244 t= 1.03e+05 R= 1e+03
+Depth= 10193 States= 1.11e+08 Transitions= 6.38e+10 Memory= 3979.854 t= 1.05e+05 R= 1e+03
+Depth= 10193 States= 1.12e+08 Transitions= 6.42e+10 Memory= 4007.686 t= 1.05e+05 R= 1e+03
+Depth= 10193 States= 1.13e+08 Transitions= 6.45e+10 Memory= 4033.076 t= 1.06e+05 R= 1e+03
+Depth= 10193 States= 1.14e+08 Transitions= 6.55e+10 Memory= 4060.127 t= 1.07e+05 R= 1e+03
+Depth= 10193 States= 1.15e+08 Transitions= 6.59e+10 Memory= 4088.057 t= 1.08e+05 R= 1e+03
+Depth= 10193 States= 1.16e+08 Transitions= 6.63e+10 Memory= 4112.276 t= 1.09e+05 R= 1e+03
+Depth= 10193 States= 1.17e+08 Transitions= 6.66e+10 Memory= 4140.986 t= 1.09e+05 R= 1e+03
+Depth= 10193 States= 1.18e+08 Transitions= 6.73e+10 Memory= 4167.158 t= 1.1e+05 R= 1e+03
+Depth= 10193 States= 1.19e+08 Transitions= 6.78e+10 Memory= 4195.088 t= 1.11e+05 R= 1e+03
+Depth= 10193 States= 1.2e+08 Transitions= 6.82e+10 Memory= 4220.674 t= 1.12e+05 R= 1e+03
+Depth= 10193 States= 1.21e+08 Transitions= 6.9e+10 Memory= 4247.041 t= 1.13e+05 R= 1e+03
+Depth= 10193 States= 1.22e+08 Transitions= 6.94e+10 Memory= 4275.166 t= 1.14e+05 R= 1e+03
+Depth= 10193 States= 1.23e+08 Transitions= 6.98e+10 Memory= 4299.287 t= 1.14e+05 R= 1e+03
+Depth= 10193 States= 1.24e+08 Transitions= 7.03e+10 Memory= 4326.143 t= 1.15e+05 R= 1e+03
+Depth= 10193 States= 1.25e+08 Transitions= 7.08e+10 Memory= 4352.901 t= 1.16e+05 R= 1e+03
+Depth= 10193 States= 1.26e+08 Transitions= 7.11e+10 Memory= 4380.440 t= 1.17e+05 R= 1e+03
+Depth= 10193 States= 1.27e+08 Transitions= 7.17e+10 Memory= 4407.490 t= 1.18e+05 R= 1e+03
+Depth= 10193 States= 1.28e+08 Transitions= 7.26e+10 Memory= 4431.026 t= 1.19e+05 R= 1e+03
+Depth= 10193 States= 1.29e+08 Transitions= 7.3e+10 Memory= 4461.787 t= 1.2e+05 R= 1e+03
+Depth= 10193 States= 1.3e+08 Transitions= 7.34e+10 Memory= 4487.373 t= 1.2e+05 R= 1e+03
+Depth= 10193 States= 1.31e+08 Transitions= 7.37e+10 Memory= 4511.006 t= 1.21e+05 R= 1e+03
+Depth= 10193 States= 1.32e+08 Transitions= 7.43e+10 Memory= 4536.494 t= 1.22e+05 R= 1e+03
+Depth= 10193 States= 1.33e+08 Transitions= 7.47e+10 Memory= 4564.815 t= 1.23e+05 R= 1e+03
+Depth= 10193 States= 1.34e+08 Transitions= 7.56e+10 Memory= 4590.498 t= 1.24e+05 R= 1e+03
+Depth= 10193 States= 1.35e+08 Transitions= 7.6e+10 Memory= 4619.209 t= 1.25e+05 R= 1e+03
+pan: resizing hashtable to -w28.. done
+Depth= 10193 States= 1.36e+08 Transitions= 7.63e+10 Memory= 6667.209 t= 1.25e+05 R= 1e+03
+Depth= 10193 States= 1.37e+08 Transitions= 7.68e+10 Memory= 6667.209 t= 1.26e+05 R= 1e+03
+Depth= 10193 States= 1.38e+08 Transitions= 7.73e+10 Memory= 6680.490 t= 1.27e+05 R= 1e+03
+Depth= 10193 States= 1.39e+08 Transitions= 7.76e+10 Memory= 6710.178 t= 1.27e+05 R= 1e+03
+Depth= 10193 States= 1.4e+08 Transitions= 7.86e+10 Memory= 6736.252 t= 1.29e+05 R= 1e+03
+Depth= 10193 States= 1.41e+08 Transitions= 7.91e+10 Memory= 6765.647 t= 1.3e+05 R= 1e+03
+Depth= 10193 States= 1.42e+08 Transitions= 7.95e+10 Memory= 6792.697 t= 1.3e+05 R= 1e+03
+Depth= 10193 States= 1.43e+08 Transitions= 7.98e+10 Memory= 6816.818 t= 1.31e+05 R= 1e+03
+Depth= 10193 States= 1.44e+08 Transitions= 8.02e+10 Memory= 6842.893 t= 1.32e+05 R= 1e+03
+Depth= 10193 States= 1.45e+08 Transitions= 8.1e+10 Memory= 6870.236 t= 1.33e+05 R= 1e+03
+Depth= 10193 States= 1.46e+08 Transitions= 8.15e+10 Memory= 6898.361 t= 1.34e+05 R= 1e+03
+Depth= 10193 States= 1.47e+08 Transitions= 8.18e+10 Memory= 6922.092 t= 1.34e+05 R= 1e+03
+Depth= 10193 States= 1.48e+08 Transitions= 8.23e+10 Memory= 6948.557 t= 1.35e+05 R= 1e+03
+Depth= 10193 States= 1.49e+08 Transitions= 8.28e+10 Memory= 6974.533 t= 1.36e+05 R= 1e+03
+Depth= 10193 States= 1.5e+08 Transitions= 8.31e+10 Memory= 7004.221 t= 1.36e+05 R= 1e+03
+Depth= 10193 States= 1.51e+08 Transitions= 8.36e+10 Memory= 7029.416 t= 1.37e+05 R= 1e+03
+Depth= 10193 States= 1.52e+08 Transitions= 8.41e+10 Memory= 7055.588 t= 1.38e+05 R= 1e+03
+Depth= 10193 States= 1.53e+08 Transitions= 8.45e+10 Memory= 7081.760 t= 1.39e+05 R= 1e+03
+Depth= 10193 States= 1.54e+08 Transitions= 8.5e+10 Memory= 7107.834 t= 1.39e+05 R= 1e+03
+Depth= 10193 States= 1.55e+08 Transitions= 8.54e+10 Memory= 7134.201 t= 1.4e+05 R= 1e+03
+Depth= 10193 States= 1.56e+08 Transitions= 8.59e+10 Memory= 7158.713 t= 1.41e+05 R= 1e+03
+Depth= 10193 States= 1.57e+08 Transitions= 8.66e+10 Memory= 7181.662 t= 1.42e+05 R= 1e+03
+Depth= 10193 States= 1.58e+08 Transitions= 8.74e+10 Memory= 7204.221 t= 1.43e+05 R= 1e+03
+Depth= 10193 States= 1.59e+08 Transitions= 8.78e+10 Memory= 7230.295 t= 1.44e+05 R= 1e+03
+Depth= 10193 States= 1.6e+08 Transitions= 8.83e+10 Memory= 7256.662 t= 1.45e+05 R= 1e+03
+Depth= 10193 States= 1.61e+08 Transitions= 8.87e+10 Memory= 7283.127 t= 1.45e+05 R= 1e+03
+Depth= 10193 States= 1.62e+08 Transitions= 8.94e+10 Memory= 7306.760 t= 1.47e+05 R= 1e+03
+Depth= 10193 States= 1.63e+08 Transitions= 9.03e+10 Memory= 7331.565 t= 1.48e+05 R= 1e+03
+Depth= 10193 States= 1.64e+08 Transitions= 9.12e+10 Memory= 7356.955 t= 1.49e+05 R= 1e+03
+Depth= 10193 States= 1.65e+08 Transitions= 9.15e+10 Memory= 7384.983 t= 1.5e+05 R= 1e+03
+Depth= 10193 States= 1.66e+08 Transitions= 9.2e+10 Memory= 7412.033 t= 1.51e+05 R= 1e+03
+Depth= 10193 States= 1.67e+08 Transitions= 9.26e+10 Memory= 7439.377 t= 1.52e+05 R= 1e+03
+Depth= 10193 States= 1.68e+08 Transitions= 9.32e+10 Memory= 7465.256 t= 1.53e+05 R= 1e+03
+Depth= 10193 States= 1.69e+08 Transitions= 9.37e+10 Memory= 7493.479 t= 1.54e+05 R= 1e+03
+Depth= 10193 States= 1.7e+08 Transitions= 9.44e+10 Memory= 7520.041 t= 1.55e+05 R= 1e+03
+Depth= 10193 States= 1.71e+08 Transitions= 9.5e+10 Memory= 7544.065 t= 1.56e+05 R= 1e+03
+Depth= 10193 States= 1.72e+08 Transitions= 9.59e+10 Memory= 7564.377 t= 1.57e+05 R= 1e+03
+Depth= 10193 States= 1.73e+08 Transitions= 9.66e+10 Memory= 7588.693 t= 1.58e+05 R= 1e+03
+Depth= 10193 States= 1.74e+08 Transitions= 9.73e+10 Memory= 7614.865 t= 1.59e+05 R= 1e+03
+Depth= 10193 States= 1.75e+08 Transitions= 9.81e+10 Memory= 7640.354 t= 1.61e+05 R= 1e+03
+Depth= 10193 States= 1.76e+08 Transitions= 9.87e+10 Memory= 7665.744 t= 1.62e+05 R= 1e+03
+Depth= 10193 States= 1.77e+08 Transitions= 9.93e+10 Memory= 7691.135 t= 1.63e+05 R= 1e+03
+Depth= 10193 States= 1.78e+08 Transitions= 9.99e+10 Memory= 7718.479 t= 1.64e+05 R= 1e+03
+Depth= 10193 States= 1.79e+08 Transitions= 1.01e+11 Memory= 7743.772 t= 1.65e+05 R= 1e+03
+Depth= 10193 States= 1.8e+08 Transitions= 1.01e+11 Memory= 7769.651 t= 1.66e+05 R= 1e+03
+Depth= 10193 States= 1.81e+08 Transitions= 1.02e+11 Memory= 7795.920 t= 1.67e+05 R= 1e+03
+Depth= 10193 States= 1.82e+08 Transitions= 1.03e+11 Memory= 7819.651 t= 1.68e+05 R= 1e+03
+Depth= 10193 States= 1.83e+08 Transitions= 1.03e+11 Memory= 7846.897 t= 1.69e+05 R= 1e+03
+Depth= 10193 States= 1.84e+08 Transitions= 1.04e+11 Memory= 7874.631 t= 1.7e+05 R= 1e+03
+Depth= 10193 States= 1.85e+08 Transitions= 1.04e+11 Memory= 7900.510 t= 1.7e+05 R= 1e+03
+Depth= 10193 States= 1.86e+08 Transitions= 1.05e+11 Memory= 7925.803 t= 1.71e+05 R= 1e+03
+Depth= 10193 States= 1.87e+08 Transitions= 1.05e+11 Memory= 7955.295 t= 1.72e+05 R= 1e+03
+Depth= 10193 States= 1.88e+08 Transitions= 1.05e+11 Memory= 7983.420 t= 1.72e+05 R= 1e+03
+Depth= 10193 States= 1.89e+08 Transitions= 1.06e+11 Memory= 8010.373 t= 1.73e+05 R= 1e+03
+Depth= 10193 States= 1.9e+08 Transitions= 1.06e+11 Memory= 8037.424 t= 1.73e+05 R= 1e+03
+Depth= 10193 States= 1.91e+08 Transitions= 1.07e+11 Memory= 8061.838 t= 1.74e+05 R= 1e+03
+Depth= 10193 States= 1.92e+08 Transitions= 1.07e+11 Memory= 8087.326 t= 1.75e+05 R= 1e+03
+Depth= 10193 States= 1.93e+08 Transitions= 1.08e+11 Memory= 8115.256 t= 1.76e+05 R= 1e+03
+Depth= 10193 States= 1.94e+08 Transitions= 1.08e+11 Memory= 8142.307 t= 1.76e+05 R= 1e+03
+Depth= 10193 States= 1.95e+08 Transitions= 1.08e+11 Memory= 8168.479 t= 1.77e+05 R= 1e+03
+Depth= 10193 States= 1.96e+08 Transitions= 1.09e+11 Memory= 8194.846 t= 1.78e+05 R= 1e+03
+Depth= 10193 States= 1.97e+08 Transitions= 1.09e+11 Memory= 8221.311 t= 1.79e+05 R= 1e+03
+Depth= 10193 States= 1.98e+08 Transitions= 1.1e+11 Memory= 8249.240 t= 1.79e+05 R= 1e+03
+Depth= 10193 States= 1.99e+08 Transitions= 1.1e+11 Memory= 8273.264 t= 1.8e+05 R= 1e+03
+Depth= 10193 States= 2e+08 Transitions= 1.11e+11 Memory= 8295.920 t= 1.81e+05 R= 1e+03
+Depth= 10193 States= 2.01e+08 Transitions= 1.11e+11 Memory= 8320.529 t= 1.82e+05 R= 1e+03
+Depth= 10193 States= 2.02e+08 Transitions= 1.12e+11 Memory= 8345.236 t= 1.84e+05 R= 1e+03
+Depth= 10193 States= 2.03e+08 Transitions= 1.13e+11 Memory= 8379.026 t= 1.86e+05 R= 1e+03
+Depth= 10193 States= 2.04e+08 Transitions= 1.15e+11 Memory= 8403.635 t= 1.87e+05 R= 1e+03
+Depth= 10193 States= 2.05e+08 Transitions= 1.16e+11 Memory= 8427.951 t= 1.89e+05 R= 1e+03
+Depth= 10193 States= 2.06e+08 Transitions= 1.17e+11 Memory= 8452.463 t= 1.91e+05 R= 1e+03
+Depth= 10193 States= 2.07e+08 Transitions= 1.18e+11 Memory= 8472.483 t= 1.93e+05 R= 1e+03
+Depth= 10193 States= 2.08e+08 Transitions= 1.19e+11 Memory= 8493.283 t= 1.94e+05 R= 1e+03
+Depth= 10193 States= 2.09e+08 Transitions= 1.2e+11 Memory= 8513.205 t= 1.96e+05 R= 1e+03
+Depth= 10193 States= 2.1e+08 Transitions= 1.21e+11 Memory= 8532.053 t= 1.98e+05 R= 1e+03
+Depth= 10193 States= 2.11e+08 Transitions= 1.22e+11 Memory= 8555.588 t= 1.99e+05 R= 1e+03
+Depth= 10193 States= 2.12e+08 Transitions= 1.22e+11 Memory= 8582.932 t= 2e+05 R= 1e+03
+Depth= 10193 States= 2.13e+08 Transitions= 1.23e+11 Memory= 8607.834 t= 2.01e+05 R= 1e+03
+Depth= 10193 States= 2.14e+08 Transitions= 1.23e+11 Memory= 8633.029 t= 2.02e+05 R= 1e+03
+Depth= 10193 States= 2.15e+08 Transitions= 1.24e+11 Memory= 8656.858 t= 2.04e+05 R= 1e+03
+Depth= 10193 States= 2.16e+08 Transitions= 1.25e+11 Memory= 8679.904 t= 2.05e+05 R= 1e+03
+Depth= 10193 States= 2.17e+08 Transitions= 1.26e+11 Memory= 8707.932 t= 2.06e+05 R= 1e+03
+Depth= 10193 States= 2.18e+08 Transitions= 1.26e+11 Memory= 8736.740 t= 2.07e+05 R= 1e+03
+Depth= 10193 States= 2.19e+08 Transitions= 1.26e+11 Memory= 8762.229 t= 2.07e+05 R= 1e+03
+Depth= 10193 States= 2.2e+08 Transitions= 1.27e+11 Memory= 8785.764 t= 2.08e+05 R= 1e+03
+Depth= 10193 States= 2.21e+08 Transitions= 1.27e+11 Memory= 8812.619 t= 2.08e+05 R= 1e+03
+Depth= 10193 States= 2.22e+08 Transitions= 1.28e+11 Memory= 8837.326 t= 2.09e+05 R= 1e+03
+Depth= 10193 States= 2.23e+08 Transitions= 1.29e+11 Memory= 8859.006 t= 2.11e+05 R= 1e+03
+Depth= 10193 States= 2.24e+08 Transitions= 1.3e+11 Memory= 8884.104 t= 2.12e+05 R= 1e+03
+Depth= 10193 States= 2.25e+08 Transitions= 1.3e+11 Memory= 8909.006 t= 2.13e+05 R= 1e+03
+Depth= 10193 States= 2.26e+08 Transitions= 1.31e+11 Memory= 8934.787 t= 2.14e+05 R= 1e+03
+Depth= 10193 States= 2.27e+08 Transitions= 1.31e+11 Memory= 8961.057 t= 2.15e+05 R= 1e+03
+Depth= 10193 States= 2.28e+08 Transitions= 1.32e+11 Memory= 8985.666 t= 2.16e+05 R= 1e+03
+Depth= 10193 States= 2.29e+08 Transitions= 1.33e+11 Memory= 9010.080 t= 2.18e+05 R= 1e+03
+Depth= 10193 States= 2.3e+08 Transitions= 1.34e+11 Memory= 9034.885 t= 2.19e+05 R= 1e+03
+Depth= 10193 States= 2.31e+08 Transitions= 1.35e+11 Memory= 9058.127 t= 2.2e+05 R= 1e+03
+Depth= 10193 States= 2.32e+08 Transitions= 1.35e+11 Memory= 9081.760 t= 2.22e+05 R= 1e+03
+Depth= 10193 States= 2.33e+08 Transitions= 1.36e+11 Memory= 9106.467 t= 2.23e+05 R= 1e+03
+Depth= 10193 States= 2.34e+08 Transitions= 1.37e+11 Memory= 9130.295 t= 2.24e+05 R= 1e+03
+Depth= 10193 States= 2.35e+08 Transitions= 1.37e+11 Memory= 9159.690 t= 2.24e+05 R= 1e+03
+Depth= 10193 States= 2.36e+08 Transitions= 1.38e+11 Memory= 9185.471 t= 2.25e+05 R= 1e+03
+Depth= 10193 States= 2.37e+08 Transitions= 1.38e+11 Memory= 9207.639 t= 2.27e+05 R= 1e+03
+Depth= 10193 States= 2.38e+08 Transitions= 1.39e+11 Memory= 9232.443 t= 2.28e+05 R= 1e+03
+Depth= 10193 States= 2.39e+08 Transitions= 1.4e+11 Memory= 9258.811 t= 2.29e+05 R= 1e+03
+Depth= 10193 States= 2.4e+08 Transitions= 1.4e+11 Memory= 9287.619 t= 2.29e+05 R= 1e+03
+Depth= 10193 States= 2.41e+08 Transitions= 1.4e+11 Memory= 9317.209 t= 2.3e+05 R= 1e+03
+Depth= 10193 States= 2.42e+08 Transitions= 1.41e+11 Memory= 9343.088 t= 2.31e+05 R= 1e+03
+Depth= 10193 States= 2.43e+08 Transitions= 1.42e+11 Memory= 9365.354 t= 2.32e+05 R= 1e+03
+Depth= 10193 States= 2.44e+08 Transitions= 1.42e+11 Memory= 9389.182 t= 2.33e+05 R= 1e+03
+Depth= 10193 States= 2.45e+08 Transitions= 1.43e+11 Memory= 9415.256 t= 2.33e+05 R= 1e+03
+Depth= 10193 States= 2.46e+08 Transitions= 1.43e+11 Memory= 9438.596 t= 2.34e+05 R= 1e+03
+Depth= 10193 States= 2.47e+08 Transitions= 1.44e+11 Memory= 9466.623 t= 2.35e+05 R= 1e+03
+Depth= 10193 States= 2.48e+08 Transitions= 1.44e+11 Memory= 9495.041 t= 2.36e+05 R= 1e+03
+Depth= 10193 States= 2.49e+08 Transitions= 1.45e+11 Memory= 9519.651 t= 2.37e+05 R= 1e+03
+Depth= 10193 States= 2.5e+08 Transitions= 1.46e+11 Memory= 9549.436 t= 2.38e+05 R= 1e+03
+Depth= 10193 States= 2.51e+08 Transitions= 1.46e+11 Memory= 9575.022 t= 2.39e+05 R= 1e+03
+Depth= 10193 States= 2.52e+08 Transitions= 1.46e+11 Memory= 9598.752 t= 2.39e+05 R= 1e+03
+Depth= 10193 States= 2.53e+08 Transitions= 1.47e+11 Memory= 9626.584 t= 2.41e+05 R= 1e+03
+Depth= 10193 States= 2.54e+08 Transitions= 1.48e+11 Memory= 9655.588 t= 2.42e+05 R= 1e+03
+Depth= 10193 States= 2.55e+08 Transitions= 1.48e+11 Memory= 9679.904 t= 2.42e+05 R= 1e+03
+Depth= 10193 States= 2.56e+08 Transitions= 1.49e+11 Memory= 9707.834 t= 2.43e+05 R= 1e+03
+Depth= 10193 States= 2.57e+08 Transitions= 1.49e+11 Memory= 9735.568 t= 2.45e+05 R= 1e+03
+Depth= 10193 States= 2.58e+08 Transitions= 1.5e+11 Memory= 9760.861 t= 2.45e+05 R= 1e+03
+Depth= 10193 States= 2.59e+08 Transitions= 1.5e+11 Memory= 9785.959 t= 2.46e+05 R= 1e+03
+Depth= 10193 States= 2.6e+08 Transitions= 1.5e+11 Memory= 9814.182 t= 2.46e+05 R= 1e+03
+Depth= 10193 States= 2.61e+08 Transitions= 1.51e+11 Memory= 9841.428 t= 2.48e+05 R= 1e+03
+Depth= 10193 States= 2.62e+08 Transitions= 1.52e+11 Memory= 9867.014 t= 2.48e+05 R= 1e+03
+Depth= 10193 States= 2.63e+08 Transitions= 1.52e+11 Memory= 9894.846 t= 2.49e+05 R= 1e+03
+Depth= 10193 States= 2.64e+08 Transitions= 1.53e+11 Memory= 9921.604 t= 2.5e+05 R= 1e+03
+Depth= 10193 States= 2.65e+08 Transitions= 1.53e+11 Memory= 9947.287 t= 2.51e+05 R= 1e+03
+Depth= 10193 States= 2.66e+08 Transitions= 1.54e+11 Memory= 9973.361 t= 2.51e+05 R= 1e+03
+Depth= 10193 States= 2.67e+08 Transitions= 1.54e+11 Memory= 9999.240 t= 2.52e+05 R= 1e+03
+Depth= 10193 States= 2.68e+08 Transitions= 1.55e+11 Memory= 10026.584 t= 2.53e+05 R= 1e+03
+Depth= 10193 States= 2.69e+08 Transitions= 1.55e+11 Memory= 10054.416 t= 2.54e+05 R= 1e+03
+Depth= 10193 States= 2.7e+08 Transitions= 1.56e+11 Memory= 10077.658 t= 2.56e+05 R= 1e+03
+Depth= 10193 States= 2.71e+08 Transitions= 1.56e+11 Memory= 10108.615 t= 2.56e+05 R= 1e+03
+Depth= 10193 States= 2.72e+08 Transitions= 1.57e+11 Memory= 10134.494 t= 2.57e+05 R= 1e+03
+Depth= 10193 States= 2.73e+08 Transitions= 1.57e+11 Memory= 10157.639 t= 2.57e+05 R= 1e+03
+Depth= 10193 States= 2.74e+08 Transitions= 1.58e+11 Memory= 10183.127 t= 2.58e+05 R= 1e+03
+Depth= 10193 States= 2.75e+08 Transitions= 1.58e+11 Memory= 10212.522 t= 2.59e+05 R= 1e+03
+Depth= 10193 States= 2.76e+08 Transitions= 1.59e+11 Memory= 10238.596 t= 2.6e+05 R= 1e+03
+Depth= 10193 States= 2.77e+08 Transitions= 1.59e+11 Memory= 10265.647 t= 2.61e+05 R= 1e+03
+Depth= 10193 States= 2.78e+08 Transitions= 1.6e+11 Memory= 10289.963 t= 2.62e+05 R= 1e+03
+Depth= 10193 States= 2.79e+08 Transitions= 1.6e+11 Memory= 10316.233 t= 2.62e+05 R= 1e+03
+Depth= 10193 States= 2.8e+08 Transitions= 1.61e+11 Memory= 10344.651 t= 2.63e+05 R= 1e+03
+Depth= 10193 States= 2.81e+08 Transitions= 1.61e+11 Memory= 10375.315 t= 2.64e+05 R= 1e+03
+Depth= 10193 States= 2.82e+08 Transitions= 1.62e+11 Memory= 10398.654 t= 2.65e+05 R= 1e+03
+Depth= 10193 States= 2.83e+08 Transitions= 1.62e+11 Memory= 10429.611 t= 2.66e+05 R= 1e+03
+Depth= 10193 States= 2.84e+08 Transitions= 1.63e+11 Memory= 10455.588 t= 2.67e+05 R= 1e+03
+Depth= 10193 States= 2.85e+08 Transitions= 1.63e+11 Memory= 10478.830 t= 2.67e+05 R= 1e+03
+Depth= 10193 States= 2.86e+08 Transitions= 1.64e+11 Memory= 10506.760 t= 2.68e+05 R= 1e+03
+Depth= 10193 States= 2.87e+08 Transitions= 1.64e+11 Memory= 10532.443 t= 2.69e+05 R= 1e+03
+Depth= 10193 States= 2.88e+08 Transitions= 1.65e+11 Memory= 10561.252 t= 2.7e+05 R= 1e+03
+Depth= 10193 States= 2.89e+08 Transitions= 1.65e+11 Memory= 10584.983 t= 2.71e+05 R= 1e+03
+Depth= 10193 States= 2.9e+08 Transitions= 1.66e+11 Memory= 10611.252 t= 2.71e+05 R= 1e+03
+Depth= 10193 States= 2.91e+08 Transitions= 1.66e+11 Memory= 10637.033 t= 2.72e+05 R= 1e+03
+Depth= 10193 States= 2.92e+08 Transitions= 1.66e+11 Memory= 10668.674 t= 2.73e+05 R= 1e+03
+Depth= 10193 States= 2.93e+08 Transitions= 1.67e+11 Memory= 10692.111 t= 2.73e+05 R= 1e+03
+Depth= 10193 States= 2.94e+08 Transitions= 1.67e+11 Memory= 10718.283 t= 2.74e+05 R= 1e+03
+Depth= 10193 States= 2.95e+08 Transitions= 1.68e+11 Memory= 10744.748 t= 2.75e+05 R= 1e+03
+Depth= 10193 States= 2.96e+08 Transitions= 1.68e+11 Memory= 10770.920 t= 2.76e+05 R= 1e+03
+Depth= 10193 States= 2.97e+08 Transitions= 1.69e+11 Memory= 10795.139 t= 2.76e+05 R= 1e+03
+Depth= 10193 States= 2.98e+08 Transitions= 1.69e+11 Memory= 10819.358 t= 2.77e+05 R= 1e+03
+Depth= 10193 States= 2.99e+08 Transitions= 1.7e+11 Memory= 10841.721 t= 2.79e+05 R= 1e+03
+Depth= 10193 States= 3e+08 Transitions= 1.71e+11 Memory= 10867.209 t= 2.79e+05 R= 1e+03
+Depth= 10193 States= 3.01e+08 Transitions= 1.71e+11 Memory= 10893.283 t= 2.8e+05 R= 1e+03
+Depth= 10193 States= 3.02e+08 Transitions= 1.72e+11 Memory= 10916.233 t= 2.81e+05 R= 1e+03
+Depth= 10193 States= 3.03e+08 Transitions= 1.73e+11 Memory= 10940.549 t= 2.83e+05 R= 1e+03
+Depth= 10193 States= 3.04e+08 Transitions= 1.73e+11 Memory= 10971.408 t= 2.84e+05 R= 1e+03
+Depth= 10193 States= 3.05e+08 Transitions= 1.74e+11 Memory= 10996.897 t= 2.84e+05 R= 1e+03
+Depth= 10193 States= 3.06e+08 Transitions= 1.74e+11 Memory= 11023.850 t= 2.85e+05 R= 1e+03
+Depth= 10193 States= 3.07e+08 Transitions= 1.75e+11 Memory= 11049.436 t= 2.86e+05 R= 1e+03
+Depth= 10193 States= 3.08e+08 Transitions= 1.75e+11 Memory= 11077.854 t= 2.87e+05 R= 1e+03
+Depth= 10193 States= 3.09e+08 Transitions= 1.76e+11 Memory= 11104.514 t= 2.88e+05 R= 1e+03
+Depth= 10193 States= 3.1e+08 Transitions= 1.77e+11 Memory= 11125.119 t= 2.89e+05 R= 1e+03
+Depth= 10193 States= 3.11e+08 Transitions= 1.77e+11 Memory= 11146.897 t= 2.91e+05 R= 1e+03
+Depth= 10193 States= 3.12e+08 Transitions= 1.78e+11 Memory= 11173.264 t= 2.92e+05 R= 1e+03
+Depth= 10193 States= 3.13e+08 Transitions= 1.79e+11 Memory= 11198.654 t= 2.93e+05 R= 1e+03
+Depth= 10193 States= 3.14e+08 Transitions= 1.8e+11 Memory= 11224.045 t= 2.94e+05 R= 1e+03
+Depth= 10193 States= 3.15e+08 Transitions= 1.8e+11 Memory= 11248.850 t= 2.95e+05 R= 1e+03
+Depth= 10193 States= 3.16e+08 Transitions= 1.81e+11 Memory= 11274.729 t= 2.96e+05 R= 1e+03
+Depth= 10193 States= 3.17e+08 Transitions= 1.82e+11 Memory= 11300.315 t= 2.97e+05 R= 1e+03
+Depth= 10193 States= 3.18e+08 Transitions= 1.82e+11 Memory= 11326.193 t= 2.98e+05 R= 1e+03
+Depth= 10193 States= 3.19e+08 Transitions= 1.83e+11 Memory= 11351.584 t= 2.99e+05 R= 1e+03
+Depth= 10193 States= 3.2e+08 Transitions= 1.83e+11 Memory= 11377.561 t= 3e+05 R= 1e+03
+Depth= 10193 States= 3.21e+08 Transitions= 1.84e+11 Memory= 11400.510 t= 3.01e+05 R= 1e+03
+Depth= 10193 States= 3.22e+08 Transitions= 1.85e+11 Memory= 11425.803 t= 3.02e+05 R= 1e+03
+Depth= 10193 States= 3.23e+08 Transitions= 1.85e+11 Memory= 11453.928 t= 3.03e+05 R= 1e+03
+Depth= 10193 States= 3.24e+08 Transitions= 1.86e+11 Memory= 11478.635 t= 3.04e+05 R= 1e+03
+Depth= 10193 States= 3.25e+08 Transitions= 1.87e+11 Memory= 11503.830 t= 3.05e+05 R= 1e+03
+Depth= 10193 States= 3.26e+08 Transitions= 1.87e+11 Memory= 11528.830 t= 3.06e+05 R= 1e+03
+Depth= 10193 States= 3.27e+08 Transitions= 1.88e+11 Memory= 11554.416 t= 3.07e+05 R= 1e+03
+Depth= 10193 States= 3.28e+08 Transitions= 1.89e+11 Memory= 11580.686 t= 3.08e+05 R= 1e+03
+Depth= 10193 States= 3.29e+08 Transitions= 1.89e+11 Memory= 11606.467 t= 3.09e+05 R= 1e+03
+Depth= 10193 States= 3.3e+08 Transitions= 1.9e+11 Memory= 11632.346 t= 3.1e+05 R= 1e+03
+Depth= 10193 States= 3.31e+08 Transitions= 1.9e+11 Memory= 11658.420 t= 3.11e+05 R= 1e+03
+Depth= 10193 States= 3.32e+08 Transitions= 1.91e+11 Memory= 11681.662 t= 3.13e+05 R= 1e+03
+Depth= 10193 States= 3.33e+08 Transitions= 1.92e+11 Memory= 11708.713 t= 3.13e+05 R= 1e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 10193, errors: 0
+1.8778602e+08 states, stored (3.33973e+08 visited)
+1.9159243e+11 states, matched
+1.919264e+11 transitions (= visited+matched)
+1.0808296e+12 atomic steps
+hash conflicts: 3.7119584e+10 (resolved)
+
+Stats on memory usage (in Megabytes):
+20774.057 equivalent memory usage for states (stored*(State-vector + overhead))
+ 9228.353 actual memory usage for states (compression: 44.42%)
+ state-vector as stored = 16 byte + 36 byte overhead
+ 2048.000 memory used for hash table (-w28)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1.576 memory lost to fragmentation
+11732.541 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 618104 5194 3828 2 2 ]
+unreached in proctype urcu_reader
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 223, "(1)"
+ line 434, "pan.___", state 253, "(1)"
+ line 438, "pan.___", state 266, "(1)"
+ line 687, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 359, "(1)"
+ line 434, "pan.___", state 389, "(1)"
+ line 438, "pan.___", state 402, "(1)"
+ line 407, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 488, "(1)"
+ line 434, "pan.___", state 518, "(1)"
+ line 438, "pan.___", state 531, "(1)"
+ line 407, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 556, "(1)"
+ line 407, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 557, "else"
+ line 407, "pan.___", state 560, "(1)"
+ line 411, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 570, "(1)"
+ line 411, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 571, "else"
+ line 411, "pan.___", state 574, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 409, "pan.___", state 580, "((i<1))"
+ line 409, "pan.___", state 580, "((i>=1))"
+ line 416, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 588, "(1)"
+ line 416, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 589, "else"
+ line 416, "pan.___", state 592, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 420, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 602, "(1)"
+ line 420, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 603, "else"
+ line 420, "pan.___", state 606, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 418, "pan.___", state 612, "((i<2))"
+ line 418, "pan.___", state 612, "((i>=2))"
+ line 425, "pan.___", state 619, "(1)"
+ line 425, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 620, "else"
+ line 425, "pan.___", state 623, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 429, "pan.___", state 632, "(1)"
+ line 429, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 633, "else"
+ line 429, "pan.___", state 636, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 427, "pan.___", state 642, "((i<1))"
+ line 427, "pan.___", state 642, "((i>=1))"
+ line 434, "pan.___", state 649, "(1)"
+ line 434, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 650, "else"
+ line 434, "pan.___", state 653, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 438, "pan.___", state 662, "(1)"
+ line 438, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 663, "else"
+ line 438, "pan.___", state 666, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 436, "pan.___", state 672, "((i<2))"
+ line 436, "pan.___", state 672, "((i>=2))"
+ line 446, "pan.___", state 676, "(1)"
+ line 446, "pan.___", state 676, "(1)"
+ line 687, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 681, "(1)"
+ line 407, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 753, "(1)"
+ line 434, "pan.___", state 783, "(1)"
+ line 438, "pan.___", state 796, "(1)"
+ line 407, "pan.___", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 856, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 889, "(1)"
+ line 434, "pan.___", state 919, "(1)"
+ line 438, "pan.___", state 932, "(1)"
+ line 407, "pan.___", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 955, "(1)"
+ line 407, "pan.___", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 956, "else"
+ line 407, "pan.___", state 959, "(1)"
+ line 411, "pan.___", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 969, "(1)"
+ line 411, "pan.___", state 970, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 970, "else"
+ line 411, "pan.___", state 973, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 409, "pan.___", state 979, "((i<1))"
+ line 409, "pan.___", state 979, "((i>=1))"
+ line 416, "pan.___", state 985, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 987, "(1)"
+ line 416, "pan.___", state 988, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 988, "else"
+ line 416, "pan.___", state 991, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 420, "pan.___", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 1001, "(1)"
+ line 420, "pan.___", state 1002, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 1002, "else"
+ line 420, "pan.___", state 1005, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 418, "pan.___", state 1011, "((i<2))"
+ line 418, "pan.___", state 1011, "((i>=2))"
+ line 425, "pan.___", state 1018, "(1)"
+ line 425, "pan.___", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 1019, "else"
+ line 425, "pan.___", state 1022, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 429, "pan.___", state 1031, "(1)"
+ line 429, "pan.___", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 1032, "else"
+ line 429, "pan.___", state 1035, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 427, "pan.___", state 1041, "((i<1))"
+ line 427, "pan.___", state 1041, "((i>=1))"
+ line 434, "pan.___", state 1048, "(1)"
+ line 434, "pan.___", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 1049, "else"
+ line 434, "pan.___", state 1052, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 438, "pan.___", state 1061, "(1)"
+ line 438, "pan.___", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 1062, "else"
+ line 438, "pan.___", state 1065, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 436, "pan.___", state 1071, "((i<2))"
+ line 436, "pan.___", state 1071, "((i>=2))"
+ line 446, "pan.___", state 1075, "(1)"
+ line 446, "pan.___", state 1075, "(1)"
+ line 695, "pan.___", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1149, "(1)"
+ line 434, "pan.___", state 1179, "(1)"
+ line 438, "pan.___", state 1192, "(1)"
+ line 407, "pan.___", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1281, "(1)"
+ line 434, "pan.___", state 1311, "(1)"
+ line 438, "pan.___", state 1324, "(1)"
+ line 407, "pan.___", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1414, "(1)"
+ line 434, "pan.___", state 1444, "(1)"
+ line 438, "pan.___", state 1457, "(1)"
+ line 407, "pan.___", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1543, "(1)"
+ line 434, "pan.___", state 1573, "(1)"
+ line 438, "pan.___", state 1586, "(1)"
+ line 407, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1677, "(1)"
+ line 434, "pan.___", state 1707, "(1)"
+ line 438, "pan.___", state 1720, "(1)"
+ line 407, "pan.___", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1806, "(1)"
+ line 434, "pan.___", state 1836, "(1)"
+ line 438, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1938, "(1)"
+ line 434, "pan.___", state 1968, "(1)"
+ line 438, "pan.___", state 1981, "(1)"
+ line 734, "pan.___", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2074, "(1)"
+ line 434, "pan.___", state 2104, "(1)"
+ line 438, "pan.___", state 2117, "(1)"
+ line 407, "pan.___", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2203, "(1)"
+ line 434, "pan.___", state 2233, "(1)"
+ line 438, "pan.___", state 2246, "(1)"
+ line 407, "pan.___", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 2271, "(1)"
+ line 407, "pan.___", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 2272, "else"
+ line 407, "pan.___", state 2275, "(1)"
+ line 411, "pan.___", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 2286, "else"
+ line 411, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 409, "pan.___", state 2295, "((i<1))"
+ line 409, "pan.___", state 2295, "((i>=1))"
+ line 416, "pan.___", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2303, "(1)"
+ line 416, "pan.___", state 2304, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2304, "else"
+ line 416, "pan.___", state 2307, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 420, "pan.___", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2317, "(1)"
+ line 420, "pan.___", state 2318, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2318, "else"
+ line 420, "pan.___", state 2321, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 418, "pan.___", state 2327, "((i<2))"
+ line 418, "pan.___", state 2327, "((i>=2))"
+ line 425, "pan.___", state 2334, "(1)"
+ line 425, "pan.___", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 2335, "else"
+ line 425, "pan.___", state 2338, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 429, "pan.___", state 2347, "(1)"
+ line 429, "pan.___", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 2348, "else"
+ line 429, "pan.___", state 2351, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 427, "pan.___", state 2357, "((i<1))"
+ line 427, "pan.___", state 2357, "((i>=1))"
+ line 434, "pan.___", state 2364, "(1)"
+ line 434, "pan.___", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 2365, "else"
+ line 434, "pan.___", state 2368, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 438, "pan.___", state 2377, "(1)"
+ line 438, "pan.___", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 2378, "else"
+ line 438, "pan.___", state 2381, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 436, "pan.___", state 2387, "((i<2))"
+ line 436, "pan.___", state 2387, "((i>=2))"
+ line 446, "pan.___", state 2391, "(1)"
+ line 446, "pan.___", state 2391, "(1)"
+ line 734, "pan.___", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2396, "(1)"
+ line 407, "pan.___", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2468, "(1)"
+ line 434, "pan.___", state 2498, "(1)"
+ line 438, "pan.___", state 2511, "(1)"
+ line 407, "pan.___", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2603, "(1)"
+ line 434, "pan.___", state 2633, "(1)"
+ line 438, "pan.___", state 2646, "(1)"
+ line 407, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2732, "(1)"
+ line 434, "pan.___", state 2762, "(1)"
+ line 438, "pan.___", state 2775, "(1)"
+ line 245, "pan.___", state 2808, "(1)"
+ line 253, "pan.___", state 2828, "(1)"
+ line 257, "pan.___", state 2836, "(1)"
+ line 245, "pan.___", state 2851, "(1)"
+ line 253, "pan.___", state 2871, "(1)"
+ line 257, "pan.___", state 2879, "(1)"
+ line 929, "pan.___", state 2896, "-end-"
+ (245 of 2896 states)
+unreached in proctype urcu_writer
+ line 407, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 425, "pan.___", state 110, "(1)"
+ line 429, "pan.___", state 123, "(1)"
+ line 434, "pan.___", state 140, "(1)"
+ line 268, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 407, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 303, "(1)"
+ line 429, "pan.___", state 316, "(1)"
+ line 434, "pan.___", state 333, "(1)"
+ line 438, "pan.___", state 346, "(1)"
+ line 411, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 447, "(1)"
+ line 434, "pan.___", state 464, "(1)"
+ line 438, "pan.___", state 477, "(1)"
+ line 411, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 586, "(1)"
+ line 434, "pan.___", state 603, "(1)"
+ line 438, "pan.___", state 616, "(1)"
+ line 411, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 715, "(1)"
+ line 434, "pan.___", state 732, "(1)"
+ line 438, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 846, "(1)"
+ line 434, "pan.___", state 863, "(1)"
+ line 438, "pan.___", state 876, "(1)"
+ line 268, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 955, "(1)"
+ line 280, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 978, "(1)"
+ line 249, "pan.___", state 986, "(1)"
+ line 253, "pan.___", state 998, "(1)"
+ line 257, "pan.___", state 1006, "(1)"
+ line 268, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1084, "(1)"
+ line 249, "pan.___", state 1092, "(1)"
+ line 253, "pan.___", state 1104, "(1)"
+ line 257, "pan.___", state 1112, "(1)"
+ line 272, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1176, "(1)"
+ line 249, "pan.___", state 1184, "(1)"
+ line 253, "pan.___", state 1196, "(1)"
+ line 257, "pan.___", state 1204, "(1)"
+ line 268, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1282, "(1)"
+ line 249, "pan.___", state 1290, "(1)"
+ line 253, "pan.___", state 1302, "(1)"
+ line 257, "pan.___", state 1310, "(1)"
+ line 272, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1374, "(1)"
+ line 249, "pan.___", state 1382, "(1)"
+ line 253, "pan.___", state 1394, "(1)"
+ line 257, "pan.___", state 1402, "(1)"
+ line 268, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1480, "(1)"
+ line 249, "pan.___", state 1488, "(1)"
+ line 253, "pan.___", state 1500, "(1)"
+ line 257, "pan.___", state 1508, "(1)"
+ line 272, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1572, "(1)"
+ line 249, "pan.___", state 1580, "(1)"
+ line 253, "pan.___", state 1592, "(1)"
+ line 257, "pan.___", state 1600, "(1)"
+ line 268, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1678, "(1)"
+ line 249, "pan.___", state 1686, "(1)"
+ line 253, "pan.___", state 1698, "(1)"
+ line 257, "pan.___", state 1706, "(1)"
+ line 1304, "pan.___", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 28 states)
+unreached in proctype :never:
+ line 1369, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 3.14e+05 seconds
+pan: rate 1063.7031 states/second
+pan: avg transition delay 1.6359e-06 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi-compress'
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64 -DCOLLAPSE
+#CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ make urcu_free | tee urcu_free.log
+ make urcu_free_no_mb | tee urcu_free_no_mb.log
+ make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth= 3250 States= 1e+06 Transitions= 2.74e+08 Memory= 500.529 t= 357 R= 3e+03
+Depth= 3250 States= 2e+06 Transitions= 5.69e+08 Memory= 537.248 t= 774 R= 3e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim - (none specified)
+ assertion violations +
+ cycle checks - (disabled by -DSAFETY)
+ invalid end states +
+
+State-vector 72 byte, depth reached 3250, errors: 0
+ 2668047 states, stored
+7.3166567e+08 states, matched
+7.3433372e+08 transitions (= stored+matched)
+4.2954757e+09 atomic steps
+hash conflicts: 4.8630608e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 254.445 equivalent memory usage for states (stored*(State-vector + overhead))
+ 94.790 actual memory usage for states (compression: 37.25%)
+ state-vector as stored = 9 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 560.490 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 25912 2128 1970 2 ]
+unreached in proctype urcu_reader
+ line 267, ".input.spin", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 275, ".input.spin", state 77, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 102, "(1)"
+ line 248, ".input.spin", state 110, "(1)"
+ line 252, ".input.spin", state 122, "(1)"
+ line 256, ".input.spin", state 130, "(1)"
+ line 403, ".input.spin", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 188, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 221, "(1)"
+ line 430, ".input.spin", state 251, "(1)"
+ line 434, ".input.spin", state 264, "(1)"
+ line 613, ".input.spin", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 403, ".input.spin", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 324, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 357, "(1)"
+ line 430, ".input.spin", state 387, "(1)"
+ line 434, ".input.spin", state 400, "(1)"
+ line 403, ".input.spin", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 453, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 486, "(1)"
+ line 430, ".input.spin", state 516, "(1)"
+ line 434, ".input.spin", state 529, "(1)"
+ line 403, ".input.spin", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 403, ".input.spin", state 554, "(1)"
+ line 403, ".input.spin", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 403, ".input.spin", state 555, "else"
+ line 403, ".input.spin", state 558, "(1)"
+ line 407, ".input.spin", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 407, ".input.spin", state 568, "(1)"
+ line 407, ".input.spin", state 569, "(cache_dirty_urcu_active_readers)"
+ line 407, ".input.spin", state 569, "else"
+ line 407, ".input.spin", state 572, "(1)"
+ line 407, ".input.spin", state 573, "(1)"
+ line 407, ".input.spin", state 573, "(1)"
+ line 405, ".input.spin", state 578, "((i<1))"
+ line 405, ".input.spin", state 578, "((i>=1))"
+ line 412, ".input.spin", state 584, "cache_dirty_rcu_ptr = 0"
+ line 412, ".input.spin", state 586, "(1)"
+ line 412, ".input.spin", state 587, "(cache_dirty_rcu_ptr)"
+ line 412, ".input.spin", state 587, "else"
+ line 412, ".input.spin", state 590, "(1)"
+ line 412, ".input.spin", state 591, "(1)"
+ line 412, ".input.spin", state 591, "(1)"
+ line 416, ".input.spin", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 416, ".input.spin", state 600, "(1)"
+ line 416, ".input.spin", state 601, "(cache_dirty_rcu_data[i])"
+ line 416, ".input.spin", state 601, "else"
+ line 416, ".input.spin", state 604, "(1)"
+ line 416, ".input.spin", state 605, "(1)"
+ line 416, ".input.spin", state 605, "(1)"
+ line 414, ".input.spin", state 610, "((i<2))"
+ line 414, ".input.spin", state 610, "((i>=2))"
+ line 421, ".input.spin", state 617, "(1)"
+ line 421, ".input.spin", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 421, ".input.spin", state 618, "else"
+ line 421, ".input.spin", state 621, "(1)"
+ line 421, ".input.spin", state 622, "(1)"
+ line 421, ".input.spin", state 622, "(1)"
+ line 425, ".input.spin", state 630, "(1)"
+ line 425, ".input.spin", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 425, ".input.spin", state 631, "else"
+ line 425, ".input.spin", state 634, "(1)"
+ line 425, ".input.spin", state 635, "(1)"
+ line 425, ".input.spin", state 635, "(1)"
+ line 423, ".input.spin", state 640, "((i<1))"
+ line 423, ".input.spin", state 640, "((i>=1))"
+ line 430, ".input.spin", state 647, "(1)"
+ line 430, ".input.spin", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 430, ".input.spin", state 648, "else"
+ line 430, ".input.spin", state 651, "(1)"
+ line 430, ".input.spin", state 652, "(1)"
+ line 430, ".input.spin", state 652, "(1)"
+ line 434, ".input.spin", state 660, "(1)"
+ line 434, ".input.spin", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 434, ".input.spin", state 661, "else"
+ line 434, ".input.spin", state 664, "(1)"
+ line 434, ".input.spin", state 665, "(1)"
+ line 434, ".input.spin", state 665, "(1)"
+ line 432, ".input.spin", state 670, "((i<2))"
+ line 432, ".input.spin", state 670, "((i>=2))"
+ line 442, ".input.spin", state 674, "(1)"
+ line 442, ".input.spin", state 674, "(1)"
+ line 613, ".input.spin", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 613, ".input.spin", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 613, ".input.spin", state 679, "(1)"
+ line 403, ".input.spin", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 718, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 751, "(1)"
+ line 430, ".input.spin", state 781, "(1)"
+ line 434, ".input.spin", state 794, "(1)"
+ line 403, ".input.spin", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 853, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 886, "(1)"
+ line 430, ".input.spin", state 916, "(1)"
+ line 434, ".input.spin", state 929, "(1)"
+ line 403, ".input.spin", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, ".input.spin", state 982, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 1015, "(1)"
+ line 430, ".input.spin", state 1045, "(1)"
+ line 434, ".input.spin", state 1058, "(1)"
+ line 244, ".input.spin", state 1091, "(1)"
+ line 252, ".input.spin", state 1111, "(1)"
+ line 256, ".input.spin", state 1119, "(1)"
+ line 747, ".input.spin", state 1136, "-end-"
+ (91 of 1136 states)
+unreached in proctype urcu_writer
+ line 403, ".input.spin", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, ".input.spin", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 77, "cache_dirty_rcu_ptr = 0"
+ line 421, ".input.spin", state 110, "(1)"
+ line 425, ".input.spin", state 123, "(1)"
+ line 430, ".input.spin", state 140, "(1)"
+ line 267, ".input.spin", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 198, "cache_dirty_rcu_ptr = 0"
+ line 403, ".input.spin", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, ".input.spin", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 270, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 421, ".input.spin", state 303, "(1)"
+ line 425, ".input.spin", state 316, "(1)"
+ line 430, ".input.spin", state 333, "(1)"
+ line 434, ".input.spin", state 346, "(1)"
+ line 407, ".input.spin", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 401, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 425, ".input.spin", state 447, "(1)"
+ line 430, ".input.spin", state 464, "(1)"
+ line 434, ".input.spin", state 477, "(1)"
+ line 407, ".input.spin", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 540, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 425, ".input.spin", state 586, "(1)"
+ line 430, ".input.spin", state 603, "(1)"
+ line 434, ".input.spin", state 616, "(1)"
+ line 407, ".input.spin", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 669, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 425, ".input.spin", state 715, "(1)"
+ line 430, ".input.spin", state 732, "(1)"
+ line 434, ".input.spin", state 745, "(1)"
+ line 407, ".input.spin", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 412, ".input.spin", state 800, "cache_dirty_rcu_ptr = 0"
+ line 416, ".input.spin", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 425, ".input.spin", state 846, "(1)"
+ line 430, ".input.spin", state 863, "(1)"
+ line 434, ".input.spin", state 876, "(1)"
+ line 267, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 955, "(1)"
+ line 279, ".input.spin", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 978, "(1)"
+ line 248, ".input.spin", state 986, "(1)"
+ line 252, ".input.spin", state 998, "(1)"
+ line 256, ".input.spin", state 1006, "(1)"
+ line 267, ".input.spin", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1084, "(1)"
+ line 248, ".input.spin", state 1092, "(1)"
+ line 252, ".input.spin", state 1104, "(1)"
+ line 256, ".input.spin", state 1112, "(1)"
+ line 271, ".input.spin", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1176, "(1)"
+ line 248, ".input.spin", state 1184, "(1)"
+ line 252, ".input.spin", state 1196, "(1)"
+ line 256, ".input.spin", state 1204, "(1)"
+ line 267, ".input.spin", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1282, "(1)"
+ line 248, ".input.spin", state 1290, "(1)"
+ line 252, ".input.spin", state 1302, "(1)"
+ line 256, ".input.spin", state 1310, "(1)"
+ line 271, ".input.spin", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1374, "(1)"
+ line 248, ".input.spin", state 1382, "(1)"
+ line 252, ".input.spin", state 1394, "(1)"
+ line 256, ".input.spin", state 1402, "(1)"
+ line 267, ".input.spin", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1480, "(1)"
+ line 248, ".input.spin", state 1488, "(1)"
+ line 252, ".input.spin", state 1500, "(1)"
+ line 256, ".input.spin", state 1508, "(1)"
+ line 271, ".input.spin", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1572, "(1)"
+ line 248, ".input.spin", state 1580, "(1)"
+ line 252, ".input.spin", state 1592, "(1)"
+ line 256, ".input.spin", state 1600, "(1)"
+ line 267, ".input.spin", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1678, "(1)"
+ line 248, ".input.spin", state 1686, "(1)"
+ line 252, ".input.spin", state 1698, "(1)"
+ line 256, ".input.spin", state 1706, "(1)"
+ line 1122, ".input.spin", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 26 states)
+
+pan: elapsed time 1.01e+03 seconds
+pan: rate 2639.775 states/second
+pan: avg transition delay 1.3764e-06 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1178)
+Depth= 3880 States= 1e+06 Transitions= 2.74e+08 Memory= 512.932 t= 435 R= 2e+03
+Depth= 3880 States= 2e+06 Transitions= 5.69e+08 Memory= 559.318 t= 929 R= 2e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3880, errors: 0
+ 2668047 states, stored
+7.3167024e+08 states, matched
+7.3433829e+08 transitions (= stored+matched)
+4.2954757e+09 atomic steps
+hash conflicts: 4.8818996e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 295.156 equivalent memory usage for states (stored*(State-vector + overhead))
+ 124.292 actual memory usage for states (compression: 42.11%)
+ state-vector as stored = 13 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 589.983 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 25912 2128 1970 2 1 ]
+unreached in proctype urcu_reader
+ line 267, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 275, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 102, "(1)"
+ line 248, "pan.___", state 110, "(1)"
+ line 252, "pan.___", state 122, "(1)"
+ line 256, "pan.___", state 130, "(1)"
+ line 403, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 221, "(1)"
+ line 430, "pan.___", state 251, "(1)"
+ line 434, "pan.___", state 264, "(1)"
+ line 613, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 403, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 357, "(1)"
+ line 430, "pan.___", state 387, "(1)"
+ line 434, "pan.___", state 400, "(1)"
+ line 403, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 486, "(1)"
+ line 430, "pan.___", state 516, "(1)"
+ line 434, "pan.___", state 529, "(1)"
+ line 403, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 403, "pan.___", state 554, "(1)"
+ line 403, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 403, "pan.___", state 555, "else"
+ line 403, "pan.___", state 558, "(1)"
+ line 407, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 407, "pan.___", state 568, "(1)"
+ line 407, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 407, "pan.___", state 569, "else"
+ line 407, "pan.___", state 572, "(1)"
+ line 407, "pan.___", state 573, "(1)"
+ line 407, "pan.___", state 573, "(1)"
+ line 405, "pan.___", state 578, "((i<1))"
+ line 405, "pan.___", state 578, "((i>=1))"
+ line 412, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 412, "pan.___", state 586, "(1)"
+ line 412, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 412, "pan.___", state 587, "else"
+ line 412, "pan.___", state 590, "(1)"
+ line 412, "pan.___", state 591, "(1)"
+ line 412, "pan.___", state 591, "(1)"
+ line 416, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 416, "pan.___", state 600, "(1)"
+ line 416, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 416, "pan.___", state 601, "else"
+ line 416, "pan.___", state 604, "(1)"
+ line 416, "pan.___", state 605, "(1)"
+ line 416, "pan.___", state 605, "(1)"
+ line 414, "pan.___", state 610, "((i<2))"
+ line 414, "pan.___", state 610, "((i>=2))"
+ line 421, "pan.___", state 617, "(1)"
+ line 421, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 421, "pan.___", state 618, "else"
+ line 421, "pan.___", state 621, "(1)"
+ line 421, "pan.___", state 622, "(1)"
+ line 421, "pan.___", state 622, "(1)"
+ line 425, "pan.___", state 630, "(1)"
+ line 425, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 425, "pan.___", state 631, "else"
+ line 425, "pan.___", state 634, "(1)"
+ line 425, "pan.___", state 635, "(1)"
+ line 425, "pan.___", state 635, "(1)"
+ line 423, "pan.___", state 640, "((i<1))"
+ line 423, "pan.___", state 640, "((i>=1))"
+ line 430, "pan.___", state 647, "(1)"
+ line 430, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 430, "pan.___", state 648, "else"
+ line 430, "pan.___", state 651, "(1)"
+ line 430, "pan.___", state 652, "(1)"
+ line 430, "pan.___", state 652, "(1)"
+ line 434, "pan.___", state 660, "(1)"
+ line 434, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 434, "pan.___", state 661, "else"
+ line 434, "pan.___", state 664, "(1)"
+ line 434, "pan.___", state 665, "(1)"
+ line 434, "pan.___", state 665, "(1)"
+ line 432, "pan.___", state 670, "((i<2))"
+ line 432, "pan.___", state 670, "((i>=2))"
+ line 442, "pan.___", state 674, "(1)"
+ line 442, "pan.___", state 674, "(1)"
+ line 613, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 613, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 613, "pan.___", state 679, "(1)"
+ line 403, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 751, "(1)"
+ line 430, "pan.___", state 781, "(1)"
+ line 434, "pan.___", state 794, "(1)"
+ line 403, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 886, "(1)"
+ line 430, "pan.___", state 916, "(1)"
+ line 434, "pan.___", state 929, "(1)"
+ line 403, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 1015, "(1)"
+ line 430, "pan.___", state 1045, "(1)"
+ line 434, "pan.___", state 1058, "(1)"
+ line 244, "pan.___", state 1091, "(1)"
+ line 252, "pan.___", state 1111, "(1)"
+ line 256, "pan.___", state 1119, "(1)"
+ line 747, "pan.___", state 1136, "-end-"
+ (91 of 1136 states)
+unreached in proctype urcu_writer
+ line 403, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 110, "(1)"
+ line 425, "pan.___", state 123, "(1)"
+ line 430, "pan.___", state 140, "(1)"
+ line 267, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 403, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 303, "(1)"
+ line 425, "pan.___", state 316, "(1)"
+ line 430, "pan.___", state 333, "(1)"
+ line 434, "pan.___", state 346, "(1)"
+ line 407, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 447, "(1)"
+ line 430, "pan.___", state 464, "(1)"
+ line 434, "pan.___", state 477, "(1)"
+ line 407, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 586, "(1)"
+ line 430, "pan.___", state 603, "(1)"
+ line 434, "pan.___", state 616, "(1)"
+ line 407, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 715, "(1)"
+ line 430, "pan.___", state 732, "(1)"
+ line 434, "pan.___", state 745, "(1)"
+ line 407, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 846, "(1)"
+ line 430, "pan.___", state 863, "(1)"
+ line 434, "pan.___", state 876, "(1)"
+ line 267, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 955, "(1)"
+ line 279, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 978, "(1)"
+ line 248, "pan.___", state 986, "(1)"
+ line 252, "pan.___", state 998, "(1)"
+ line 256, "pan.___", state 1006, "(1)"
+ line 267, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1084, "(1)"
+ line 248, "pan.___", state 1092, "(1)"
+ line 252, "pan.___", state 1104, "(1)"
+ line 256, "pan.___", state 1112, "(1)"
+ line 271, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1176, "(1)"
+ line 248, "pan.___", state 1184, "(1)"
+ line 252, "pan.___", state 1196, "(1)"
+ line 256, "pan.___", state 1204, "(1)"
+ line 267, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1282, "(1)"
+ line 248, "pan.___", state 1290, "(1)"
+ line 252, "pan.___", state 1302, "(1)"
+ line 256, "pan.___", state 1310, "(1)"
+ line 271, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1374, "(1)"
+ line 248, "pan.___", state 1382, "(1)"
+ line 252, "pan.___", state 1394, "(1)"
+ line 256, "pan.___", state 1402, "(1)"
+ line 267, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1480, "(1)"
+ line 248, "pan.___", state 1488, "(1)"
+ line 252, "pan.___", state 1500, "(1)"
+ line 256, "pan.___", state 1508, "(1)"
+ line 271, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1572, "(1)"
+ line 248, "pan.___", state 1580, "(1)"
+ line 252, "pan.___", state 1592, "(1)"
+ line 256, "pan.___", state 1600, "(1)"
+ line 267, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1678, "(1)"
+ line 248, "pan.___", state 1686, "(1)"
+ line 252, "pan.___", state 1698, "(1)"
+ line 256, "pan.___", state 1706, "(1)"
+ line 1122, "pan.___", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 26 states)
+unreached in proctype :never:
+ line 1183, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 1.21e+03 seconds
+pan: rate 2200.5963 states/second
+pan: avg transition delay 1.651e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+[] (!read_poison)
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+pan: claim violated! (at depth 1246)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3190, errors: 1
+ 124498 states, stored
+ 15198533 states, matched
+ 15323031 transitions (= stored+matched)
+ 86866126 atomic steps
+hash conflicts: 473423 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 13.773 equivalent memory usage for states (stored*(State-vector + overhead))
+ 6.400 actual memory usage for states (compression: 46.47%)
+ state-vector as stored = 18 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 472.111 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 2572 1245 179 2 2 ]
+unreached in proctype urcu_reader
+ line 713, "pan.___", state 12, "((i<1))"
+ line 713, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 404, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 223, "(1)"
+ line 431, "pan.___", state 253, "(1)"
+ line 435, "pan.___", state 266, "(1)"
+ line 614, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 359, "(1)"
+ line 431, "pan.___", state 389, "(1)"
+ line 435, "pan.___", state 402, "(1)"
+ line 404, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 488, "(1)"
+ line 431, "pan.___", state 518, "(1)"
+ line 435, "pan.___", state 531, "(1)"
+ line 404, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 556, "(1)"
+ line 404, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 557, "else"
+ line 404, "pan.___", state 560, "(1)"
+ line 408, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 570, "(1)"
+ line 408, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 571, "else"
+ line 408, "pan.___", state 574, "(1)"
+ line 408, "pan.___", state 575, "(1)"
+ line 408, "pan.___", state 575, "(1)"
+ line 406, "pan.___", state 580, "((i<1))"
+ line 406, "pan.___", state 580, "((i>=1))"
+ line 413, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 588, "(1)"
+ line 413, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 589, "else"
+ line 413, "pan.___", state 592, "(1)"
+ line 413, "pan.___", state 593, "(1)"
+ line 413, "pan.___", state 593, "(1)"
+ line 417, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 602, "(1)"
+ line 417, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 603, "else"
+ line 417, "pan.___", state 606, "(1)"
+ line 417, "pan.___", state 607, "(1)"
+ line 417, "pan.___", state 607, "(1)"
+ line 415, "pan.___", state 612, "((i<2))"
+ line 415, "pan.___", state 612, "((i>=2))"
+ line 422, "pan.___", state 619, "(1)"
+ line 422, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 620, "else"
+ line 422, "pan.___", state 623, "(1)"
+ line 422, "pan.___", state 624, "(1)"
+ line 422, "pan.___", state 624, "(1)"
+ line 426, "pan.___", state 632, "(1)"
+ line 426, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 633, "else"
+ line 426, "pan.___", state 636, "(1)"
+ line 426, "pan.___", state 637, "(1)"
+ line 426, "pan.___", state 637, "(1)"
+ line 424, "pan.___", state 642, "((i<1))"
+ line 424, "pan.___", state 642, "((i>=1))"
+ line 431, "pan.___", state 649, "(1)"
+ line 431, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 650, "else"
+ line 431, "pan.___", state 653, "(1)"
+ line 431, "pan.___", state 654, "(1)"
+ line 431, "pan.___", state 654, "(1)"
+ line 435, "pan.___", state 662, "(1)"
+ line 435, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 663, "else"
+ line 435, "pan.___", state 666, "(1)"
+ line 435, "pan.___", state 667, "(1)"
+ line 435, "pan.___", state 667, "(1)"
+ line 433, "pan.___", state 672, "((i<2))"
+ line 433, "pan.___", state 672, "((i>=2))"
+ line 443, "pan.___", state 676, "(1)"
+ line 443, "pan.___", state 676, "(1)"
+ line 614, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 681, "(1)"
+ line 404, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 753, "(1)"
+ line 431, "pan.___", state 783, "(1)"
+ line 435, "pan.___", state 796, "(1)"
+ line 404, "pan.___", state 823, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 855, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 869, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 888, "(1)"
+ line 431, "pan.___", state 918, "(1)"
+ line 435, "pan.___", state 931, "(1)"
+ line 404, "pan.___", state 952, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 984, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 998, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1017, "(1)"
+ line 431, "pan.___", state 1047, "(1)"
+ line 435, "pan.___", state 1060, "(1)"
+ line 245, "pan.___", state 1093, "(1)"
+ line 253, "pan.___", state 1113, "(1)"
+ line 257, "pan.___", state 1121, "(1)"
+ line 748, "pan.___", state 1138, "-end-"
+ (92 of 1138 states)
+unreached in proctype urcu_writer
+ line 837, "pan.___", state 12, "((i<1))"
+ line 837, "pan.___", state 12, "((i>=1))"
+ line 404, "pan.___", state 47, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 53, "(1)"
+ line 408, "pan.___", state 61, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 67, "(1)"
+ line 408, "pan.___", state 68, "(1)"
+ line 408, "pan.___", state 68, "(1)"
+ line 406, "pan.___", state 73, "((i<1))"
+ line 406, "pan.___", state 73, "((i>=1))"
+ line 413, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 85, "(1)"
+ line 413, "pan.___", state 86, "(1)"
+ line 413, "pan.___", state 86, "(1)"
+ line 417, "pan.___", state 99, "(1)"
+ line 417, "pan.___", state 100, "(1)"
+ line 417, "pan.___", state 100, "(1)"
+ line 415, "pan.___", state 105, "((i<2))"
+ line 415, "pan.___", state 105, "((i>=2))"
+ line 422, "pan.___", state 112, "(1)"
+ line 422, "pan.___", state 113, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 113, "else"
+ line 422, "pan.___", state 116, "(1)"
+ line 422, "pan.___", state 117, "(1)"
+ line 422, "pan.___", state 117, "(1)"
+ line 426, "pan.___", state 125, "(1)"
+ line 426, "pan.___", state 126, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 126, "else"
+ line 426, "pan.___", state 129, "(1)"
+ line 426, "pan.___", state 130, "(1)"
+ line 426, "pan.___", state 130, "(1)"
+ line 424, "pan.___", state 135, "((i<1))"
+ line 424, "pan.___", state 135, "((i>=1))"
+ line 431, "pan.___", state 142, "(1)"
+ line 431, "pan.___", state 143, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 143, "else"
+ line 431, "pan.___", state 146, "(1)"
+ line 431, "pan.___", state 147, "(1)"
+ line 431, "pan.___", state 147, "(1)"
+ line 435, "pan.___", state 155, "(1)"
+ line 435, "pan.___", state 156, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 156, "else"
+ line 435, "pan.___", state 159, "(1)"
+ line 435, "pan.___", state 160, "(1)"
+ line 435, "pan.___", state 160, "(1)"
+ line 433, "pan.___", state 165, "((i<2))"
+ line 433, "pan.___", state 165, "((i>=2))"
+ line 443, "pan.___", state 169, "(1)"
+ line 443, "pan.___", state 169, "(1)"
+ line 268, "pan.___", state 178, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 187, "cache_dirty_urcu_active_readers = 0"
+ line 270, "pan.___", state 195, "((i<1))"
+ line 270, "pan.___", state 195, "((i>=1))"
+ line 276, "pan.___", state 200, "cache_dirty_rcu_ptr = 0"
+ line 907, "pan.___", state 228, "old_data = cached_rcu_ptr"
+ line 918, "pan.___", state 232, "_proc_urcu_writer = (_proc_urcu_writer|(1<<4))"
+ line 404, "pan.___", state 240, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 246, "(1)"
+ line 408, "pan.___", state 254, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 260, "(1)"
+ line 408, "pan.___", state 261, "(1)"
+ line 408, "pan.___", state 261, "(1)"
+ line 406, "pan.___", state 266, "((i<1))"
+ line 406, "pan.___", state 266, "((i>=1))"
+ line 413, "pan.___", state 274, "(1)"
+ line 413, "pan.___", state 275, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 275, "else"
+ line 413, "pan.___", state 278, "(1)"
+ line 413, "pan.___", state 279, "(1)"
+ line 413, "pan.___", state 279, "(1)"
+ line 417, "pan.___", state 286, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 292, "(1)"
+ line 417, "pan.___", state 293, "(1)"
+ line 417, "pan.___", state 293, "(1)"
+ line 415, "pan.___", state 298, "((i<2))"
+ line 415, "pan.___", state 298, "((i>=2))"
+ line 422, "pan.___", state 305, "(1)"
+ line 422, "pan.___", state 306, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 306, "else"
+ line 422, "pan.___", state 309, "(1)"
+ line 422, "pan.___", state 310, "(1)"
+ line 422, "pan.___", state 310, "(1)"
+ line 426, "pan.___", state 318, "(1)"
+ line 426, "pan.___", state 319, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 319, "else"
+ line 426, "pan.___", state 322, "(1)"
+ line 426, "pan.___", state 323, "(1)"
+ line 426, "pan.___", state 323, "(1)"
+ line 424, "pan.___", state 328, "((i<1))"
+ line 424, "pan.___", state 328, "((i>=1))"
+ line 431, "pan.___", state 335, "(1)"
+ line 431, "pan.___", state 336, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 336, "else"
+ line 431, "pan.___", state 339, "(1)"
+ line 431, "pan.___", state 340, "(1)"
+ line 431, "pan.___", state 340, "(1)"
+ line 435, "pan.___", state 348, "(1)"
+ line 435, "pan.___", state 349, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 349, "else"
+ line 435, "pan.___", state 352, "(1)"
+ line 435, "pan.___", state 353, "(1)"
+ line 435, "pan.___", state 353, "(1)"
+ line 433, "pan.___", state 358, "((i<2))"
+ line 433, "pan.___", state 358, "((i>=2))"
+ line 443, "pan.___", state 362, "(1)"
+ line 443, "pan.___", state 362, "(1)"
+ line 404, "pan.___", state 373, "(1)"
+ line 404, "pan.___", state 374, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 374, "else"
+ line 404, "pan.___", state 377, "(1)"
+ line 408, "pan.___", state 385, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 391, "(1)"
+ line 408, "pan.___", state 392, "(1)"
+ line 408, "pan.___", state 392, "(1)"
+ line 406, "pan.___", state 397, "((i<1))"
+ line 406, "pan.___", state 397, "((i>=1))"
+ line 413, "pan.___", state 403, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 409, "(1)"
+ line 413, "pan.___", state 410, "(1)"
+ line 413, "pan.___", state 410, "(1)"
+ line 417, "pan.___", state 417, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 423, "(1)"
+ line 417, "pan.___", state 424, "(1)"
+ line 417, "pan.___", state 424, "(1)"
+ line 415, "pan.___", state 429, "((i<2))"
+ line 415, "pan.___", state 429, "((i>=2))"
+ line 422, "pan.___", state 436, "(1)"
+ line 422, "pan.___", state 437, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 437, "else"
+ line 422, "pan.___", state 440, "(1)"
+ line 422, "pan.___", state 441, "(1)"
+ line 422, "pan.___", state 441, "(1)"
+ line 426, "pan.___", state 449, "(1)"
+ line 426, "pan.___", state 450, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 450, "else"
+ line 426, "pan.___", state 453, "(1)"
+ line 426, "pan.___", state 454, "(1)"
+ line 426, "pan.___", state 454, "(1)"
+ line 424, "pan.___", state 459, "((i<1))"
+ line 424, "pan.___", state 459, "((i>=1))"
+ line 431, "pan.___", state 466, "(1)"
+ line 431, "pan.___", state 467, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 467, "else"
+ line 431, "pan.___", state 470, "(1)"
+ line 431, "pan.___", state 471, "(1)"
+ line 431, "pan.___", state 471, "(1)"
+ line 435, "pan.___", state 479, "(1)"
+ line 435, "pan.___", state 480, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 480, "else"
+ line 435, "pan.___", state 483, "(1)"
+ line 435, "pan.___", state 484, "(1)"
+ line 435, "pan.___", state 484, "(1)"
+ line 433, "pan.___", state 489, "((i<2))"
+ line 433, "pan.___", state 489, "((i>=2))"
+ line 443, "pan.___", state 493, "(1)"
+ line 443, "pan.___", state 493, "(1)"
+ line 972, "pan.___", state 504, "_proc_urcu_writer = (_proc_urcu_writer&~((1<<9)))"
+ line 977, "pan.___", state 505, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<8)|(1<<7))))"
+ line 404, "pan.___", state 510, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 516, "(1)"
+ line 408, "pan.___", state 524, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 530, "(1)"
+ line 408, "pan.___", state 531, "(1)"
+ line 408, "pan.___", state 531, "(1)"
+ line 406, "pan.___", state 536, "((i<1))"
+ line 406, "pan.___", state 536, "((i>=1))"
+ line 413, "pan.___", state 542, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 548, "(1)"
+ line 413, "pan.___", state 549, "(1)"
+ line 413, "pan.___", state 549, "(1)"
+ line 417, "pan.___", state 556, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 562, "(1)"
+ line 417, "pan.___", state 563, "(1)"
+ line 417, "pan.___", state 563, "(1)"
+ line 415, "pan.___", state 568, "((i<2))"
+ line 415, "pan.___", state 568, "((i>=2))"
+ line 422, "pan.___", state 575, "(1)"
+ line 422, "pan.___", state 576, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 576, "else"
+ line 422, "pan.___", state 579, "(1)"
+ line 422, "pan.___", state 580, "(1)"
+ line 422, "pan.___", state 580, "(1)"
+ line 426, "pan.___", state 588, "(1)"
+ line 426, "pan.___", state 589, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 589, "else"
+ line 426, "pan.___", state 592, "(1)"
+ line 426, "pan.___", state 593, "(1)"
+ line 426, "pan.___", state 593, "(1)"
+ line 424, "pan.___", state 598, "((i<1))"
+ line 424, "pan.___", state 598, "((i>=1))"
+ line 431, "pan.___", state 605, "(1)"
+ line 431, "pan.___", state 606, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 606, "else"
+ line 431, "pan.___", state 609, "(1)"
+ line 431, "pan.___", state 610, "(1)"
+ line 431, "pan.___", state 610, "(1)"
+ line 435, "pan.___", state 618, "(1)"
+ line 435, "pan.___", state 619, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 619, "else"
+ line 435, "pan.___", state 622, "(1)"
+ line 435, "pan.___", state 623, "(1)"
+ line 435, "pan.___", state 623, "(1)"
+ line 443, "pan.___", state 632, "(1)"
+ line 443, "pan.___", state 632, "(1)"
+ line 404, "pan.___", state 639, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 653, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 671, "cache_dirty_rcu_ptr = 0"
+ line 422, "pan.___", state 704, "(1)"
+ line 426, "pan.___", state 717, "(1)"
+ line 431, "pan.___", state 734, "(1)"
+ line 435, "pan.___", state 747, "(1)"
+ line 408, "pan.___", state 784, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 802, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 816, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 848, "(1)"
+ line 431, "pan.___", state 865, "(1)"
+ line 435, "pan.___", state 878, "(1)"
+ line 1054, "pan.___", state 905, "_proc_urcu_writer = (_proc_urcu_writer|(1<<13))"
+ line 268, "pan.___", state 933, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 935, "(1)"
+ line 272, "pan.___", state 942, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 944, "(1)"
+ line 272, "pan.___", state 945, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 945, "else"
+ line 270, "pan.___", state 950, "((i<1))"
+ line 270, "pan.___", state 950, "((i>=1))"
+ line 276, "pan.___", state 955, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 957, "(1)"
+ line 276, "pan.___", state 958, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 958, "else"
+ line 280, "pan.___", state 964, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 966, "(1)"
+ line 280, "pan.___", state 967, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 967, "else"
+ line 278, "pan.___", state 972, "((i<2))"
+ line 278, "pan.___", state 972, "((i>=2))"
+ line 245, "pan.___", state 980, "(1)"
+ line 249, "pan.___", state 988, "(1)"
+ line 249, "pan.___", state 989, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 989, "else"
+ line 247, "pan.___", state 994, "((i<1))"
+ line 247, "pan.___", state 994, "((i>=1))"
+ line 253, "pan.___", state 1000, "(1)"
+ line 253, "pan.___", state 1001, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1001, "else"
+ line 257, "pan.___", state 1008, "(1)"
+ line 257, "pan.___", state 1009, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1009, "else"
+ line 262, "pan.___", state 1018, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1018, "else"
+ line 1108, "pan.___", state 1034, "((i<1))"
+ line 1108, "pan.___", state 1034, "((i>=1))"
+ line 268, "pan.___", state 1039, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1041, "(1)"
+ line 272, "pan.___", state 1048, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1050, "(1)"
+ line 272, "pan.___", state 1051, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1051, "else"
+ line 270, "pan.___", state 1056, "((i<1))"
+ line 270, "pan.___", state 1056, "((i>=1))"
+ line 276, "pan.___", state 1061, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1063, "(1)"
+ line 276, "pan.___", state 1064, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1064, "else"
+ line 280, "pan.___", state 1070, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1072, "(1)"
+ line 280, "pan.___", state 1073, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1073, "else"
+ line 278, "pan.___", state 1078, "((i<2))"
+ line 278, "pan.___", state 1078, "((i>=2))"
+ line 245, "pan.___", state 1086, "(1)"
+ line 249, "pan.___", state 1094, "(1)"
+ line 249, "pan.___", state 1095, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1095, "else"
+ line 247, "pan.___", state 1100, "((i<1))"
+ line 247, "pan.___", state 1100, "((i>=1))"
+ line 253, "pan.___", state 1106, "(1)"
+ line 253, "pan.___", state 1107, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1107, "else"
+ line 257, "pan.___", state 1114, "(1)"
+ line 257, "pan.___", state 1115, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1115, "else"
+ line 262, "pan.___", state 1124, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1124, "else"
+ line 295, "pan.___", state 1126, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1126, "else"
+ line 1108, "pan.___", state 1127, "(cache_dirty_urcu_gp_ctr)"
+ line 1108, "pan.___", state 1127, "else"
+ line 268, "pan.___", state 1131, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1133, "(1)"
+ line 272, "pan.___", state 1140, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1142, "(1)"
+ line 272, "pan.___", state 1143, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1143, "else"
+ line 270, "pan.___", state 1148, "((i<1))"
+ line 270, "pan.___", state 1148, "((i>=1))"
+ line 276, "pan.___", state 1153, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1155, "(1)"
+ line 276, "pan.___", state 1156, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1156, "else"
+ line 280, "pan.___", state 1162, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1164, "(1)"
+ line 280, "pan.___", state 1165, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1165, "else"
+ line 278, "pan.___", state 1170, "((i<2))"
+ line 278, "pan.___", state 1170, "((i>=2))"
+ line 245, "pan.___", state 1178, "(1)"
+ line 249, "pan.___", state 1186, "(1)"
+ line 249, "pan.___", state 1187, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1187, "else"
+ line 247, "pan.___", state 1192, "((i<1))"
+ line 247, "pan.___", state 1192, "((i>=1))"
+ line 253, "pan.___", state 1198, "(1)"
+ line 253, "pan.___", state 1199, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1199, "else"
+ line 257, "pan.___", state 1206, "(1)"
+ line 257, "pan.___", state 1207, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1207, "else"
+ line 262, "pan.___", state 1216, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1216, "else"
+ line 1112, "pan.___", state 1219, "i = 0"
+ line 1112, "pan.___", state 1221, "reader_barrier = 1"
+ line 1112, "pan.___", state 1232, "((i<1))"
+ line 1112, "pan.___", state 1232, "((i>=1))"
+ line 268, "pan.___", state 1237, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1239, "(1)"
+ line 272, "pan.___", state 1246, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1248, "(1)"
+ line 272, "pan.___", state 1249, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1249, "else"
+ line 270, "pan.___", state 1254, "((i<1))"
+ line 270, "pan.___", state 1254, "((i>=1))"
+ line 276, "pan.___", state 1259, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1261, "(1)"
+ line 276, "pan.___", state 1262, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1262, "else"
+ line 280, "pan.___", state 1268, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1270, "(1)"
+ line 280, "pan.___", state 1271, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1271, "else"
+ line 278, "pan.___", state 1276, "((i<2))"
+ line 278, "pan.___", state 1276, "((i>=2))"
+ line 245, "pan.___", state 1284, "(1)"
+ line 249, "pan.___", state 1292, "(1)"
+ line 249, "pan.___", state 1293, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1293, "else"
+ line 247, "pan.___", state 1298, "((i<1))"
+ line 247, "pan.___", state 1298, "((i>=1))"
+ line 253, "pan.___", state 1304, "(1)"
+ line 253, "pan.___", state 1305, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1305, "else"
+ line 257, "pan.___", state 1312, "(1)"
+ line 257, "pan.___", state 1313, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1313, "else"
+ line 262, "pan.___", state 1322, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1322, "else"
+ line 295, "pan.___", state 1324, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1324, "else"
+ line 1112, "pan.___", state 1325, "(cache_dirty_urcu_gp_ctr)"
+ line 1112, "pan.___", state 1325, "else"
+ line 272, "pan.___", state 1338, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1351, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1360, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1376, "(1)"
+ line 249, "pan.___", state 1384, "(1)"
+ line 253, "pan.___", state 1396, "(1)"
+ line 257, "pan.___", state 1404, "(1)"
+ line 268, "pan.___", state 1435, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1444, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1457, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1466, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1482, "(1)"
+ line 249, "pan.___", state 1490, "(1)"
+ line 253, "pan.___", state 1502, "(1)"
+ line 257, "pan.___", state 1510, "(1)"
+ line 268, "pan.___", state 1527, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1529, "(1)"
+ line 272, "pan.___", state 1536, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1538, "(1)"
+ line 272, "pan.___", state 1539, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1539, "else"
+ line 270, "pan.___", state 1544, "((i<1))"
+ line 270, "pan.___", state 1544, "((i>=1))"
+ line 276, "pan.___", state 1549, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1551, "(1)"
+ line 276, "pan.___", state 1552, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1552, "else"
+ line 280, "pan.___", state 1558, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1560, "(1)"
+ line 280, "pan.___", state 1561, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1561, "else"
+ line 278, "pan.___", state 1566, "((i<2))"
+ line 278, "pan.___", state 1566, "((i>=2))"
+ line 245, "pan.___", state 1574, "(1)"
+ line 249, "pan.___", state 1582, "(1)"
+ line 249, "pan.___", state 1583, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1583, "else"
+ line 247, "pan.___", state 1588, "((i<1))"
+ line 247, "pan.___", state 1588, "((i>=1))"
+ line 253, "pan.___", state 1594, "(1)"
+ line 253, "pan.___", state 1595, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1595, "else"
+ line 257, "pan.___", state 1602, "(1)"
+ line 257, "pan.___", state 1603, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1603, "else"
+ line 262, "pan.___", state 1612, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1612, "else"
+ line 1119, "pan.___", state 1615, "i = 0"
+ line 1119, "pan.___", state 1617, "reader_barrier = 1"
+ line 1119, "pan.___", state 1628, "((i<1))"
+ line 1119, "pan.___", state 1628, "((i>=1))"
+ line 268, "pan.___", state 1633, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1635, "(1)"
+ line 272, "pan.___", state 1642, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1644, "(1)"
+ line 272, "pan.___", state 1645, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1645, "else"
+ line 270, "pan.___", state 1650, "((i<1))"
+ line 270, "pan.___", state 1650, "((i>=1))"
+ line 276, "pan.___", state 1655, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1657, "(1)"
+ line 276, "pan.___", state 1658, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1658, "else"
+ line 280, "pan.___", state 1664, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1666, "(1)"
+ line 280, "pan.___", state 1667, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1667, "else"
+ line 278, "pan.___", state 1672, "((i<2))"
+ line 278, "pan.___", state 1672, "((i>=2))"
+ line 245, "pan.___", state 1680, "(1)"
+ line 249, "pan.___", state 1688, "(1)"
+ line 249, "pan.___", state 1689, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1689, "else"
+ line 247, "pan.___", state 1694, "((i<1))"
+ line 247, "pan.___", state 1694, "((i>=1))"
+ line 253, "pan.___", state 1700, "(1)"
+ line 253, "pan.___", state 1701, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1701, "else"
+ line 257, "pan.___", state 1708, "(1)"
+ line 257, "pan.___", state 1709, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1709, "else"
+ line 262, "pan.___", state 1718, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1718, "else"
+ line 295, "pan.___", state 1720, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1720, "else"
+ line 1119, "pan.___", state 1721, "(cache_dirty_urcu_gp_ctr)"
+ line 1119, "pan.___", state 1721, "else"
+ line 1123, "pan.___", state 1724, "-end-"
+ (312 of 1724 states)
+unreached in proctype :init:
+ line 1138, "pan.___", state 11, "((i<1))"
+ line 1138, "pan.___", state 11, "((i>=1))"
+ (1 of 26 states)
+unreached in proctype :never:
+ line 1184, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 23.7 seconds
+pan: rate 5259.7381 states/second
+pan: avg transition delay 1.5447e-06 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define NO_MB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_RMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+pan: claim violated! (at depth 1476)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3979, errors: 1
+ 430584 states, stored
+ 99483765 states, matched
+ 99914349 transitions (= stored+matched)
+5.7035561e+08 atomic steps
+hash conflicts: 13587432 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 47.634 equivalent memory usage for states (stored*(State-vector + overhead))
+ 20.652 actual memory usage for states (compression: 43.36%)
+ state-vector as stored = 14 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 486.369 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 7914 682 569 2 2 ]
+unreached in proctype urcu_reader
+ line 713, "pan.___", state 12, "((i<1))"
+ line 713, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 102, "(1)"
+ line 249, "pan.___", state 110, "(1)"
+ line 253, "pan.___", state 122, "(1)"
+ line 257, "pan.___", state 130, "(1)"
+ line 404, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 221, "(1)"
+ line 431, "pan.___", state 251, "(1)"
+ line 435, "pan.___", state 264, "(1)"
+ line 614, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 357, "(1)"
+ line 431, "pan.___", state 387, "(1)"
+ line 435, "pan.___", state 400, "(1)"
+ line 404, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 486, "(1)"
+ line 431, "pan.___", state 516, "(1)"
+ line 435, "pan.___", state 529, "(1)"
+ line 404, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 554, "(1)"
+ line 404, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 555, "else"
+ line 404, "pan.___", state 558, "(1)"
+ line 408, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 568, "(1)"
+ line 408, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 569, "else"
+ line 408, "pan.___", state 572, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 406, "pan.___", state 578, "((i<1))"
+ line 406, "pan.___", state 578, "((i>=1))"
+ line 413, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 586, "(1)"
+ line 413, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 587, "else"
+ line 413, "pan.___", state 590, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 417, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 600, "(1)"
+ line 417, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 601, "else"
+ line 417, "pan.___", state 604, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 415, "pan.___", state 610, "((i<2))"
+ line 415, "pan.___", state 610, "((i>=2))"
+ line 422, "pan.___", state 617, "(1)"
+ line 422, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 618, "else"
+ line 422, "pan.___", state 621, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 426, "pan.___", state 630, "(1)"
+ line 426, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 631, "else"
+ line 426, "pan.___", state 634, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 424, "pan.___", state 640, "((i<1))"
+ line 424, "pan.___", state 640, "((i>=1))"
+ line 431, "pan.___", state 647, "(1)"
+ line 431, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 648, "else"
+ line 431, "pan.___", state 651, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 435, "pan.___", state 660, "(1)"
+ line 435, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 661, "else"
+ line 435, "pan.___", state 664, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 433, "pan.___", state 670, "((i<2))"
+ line 433, "pan.___", state 670, "((i>=2))"
+ line 443, "pan.___", state 674, "(1)"
+ line 443, "pan.___", state 674, "(1)"
+ line 614, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 679, "(1)"
+ line 404, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 751, "(1)"
+ line 431, "pan.___", state 781, "(1)"
+ line 435, "pan.___", state 794, "(1)"
+ line 404, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 886, "(1)"
+ line 431, "pan.___", state 916, "(1)"
+ line 435, "pan.___", state 929, "(1)"
+ line 404, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1015, "(1)"
+ line 431, "pan.___", state 1045, "(1)"
+ line 435, "pan.___", state 1058, "(1)"
+ line 404, "pan.___", state 1091, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 1123, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 1137, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1156, "(1)"
+ line 431, "pan.___", state 1186, "(1)"
+ line 435, "pan.___", state 1199, "(1)"
+ line 748, "pan.___", state 1220, "-end-"
+ (95 of 1220 states)
+unreached in proctype urcu_writer
+ line 837, "pan.___", state 12, "((i<1))"
+ line 837, "pan.___", state 12, "((i>=1))"
+ line 404, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 51, "(1)"
+ line 408, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 65, "(1)"
+ line 408, "pan.___", state 66, "(1)"
+ line 408, "pan.___", state 66, "(1)"
+ line 406, "pan.___", state 71, "((i<1))"
+ line 406, "pan.___", state 71, "((i>=1))"
+ line 413, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 83, "(1)"
+ line 413, "pan.___", state 84, "(1)"
+ line 413, "pan.___", state 84, "(1)"
+ line 417, "pan.___", state 97, "(1)"
+ line 417, "pan.___", state 98, "(1)"
+ line 417, "pan.___", state 98, "(1)"
+ line 415, "pan.___", state 103, "((i<2))"
+ line 415, "pan.___", state 103, "((i>=2))"
+ line 422, "pan.___", state 110, "(1)"
+ line 422, "pan.___", state 111, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 111, "else"
+ line 422, "pan.___", state 114, "(1)"
+ line 422, "pan.___", state 115, "(1)"
+ line 422, "pan.___", state 115, "(1)"
+ line 426, "pan.___", state 123, "(1)"
+ line 426, "pan.___", state 124, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 124, "else"
+ line 426, "pan.___", state 127, "(1)"
+ line 426, "pan.___", state 128, "(1)"
+ line 426, "pan.___", state 128, "(1)"
+ line 424, "pan.___", state 133, "((i<1))"
+ line 424, "pan.___", state 133, "((i>=1))"
+ line 431, "pan.___", state 140, "(1)"
+ line 431, "pan.___", state 141, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 141, "else"
+ line 431, "pan.___", state 144, "(1)"
+ line 431, "pan.___", state 145, "(1)"
+ line 431, "pan.___", state 145, "(1)"
+ line 435, "pan.___", state 153, "(1)"
+ line 435, "pan.___", state 154, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 154, "else"
+ line 435, "pan.___", state 157, "(1)"
+ line 435, "pan.___", state 158, "(1)"
+ line 435, "pan.___", state 158, "(1)"
+ line 433, "pan.___", state 163, "((i<2))"
+ line 433, "pan.___", state 163, "((i>=2))"
+ line 443, "pan.___", state 167, "(1)"
+ line 443, "pan.___", state 167, "(1)"
+ line 268, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 404, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 303, "(1)"
+ line 426, "pan.___", state 316, "(1)"
+ line 431, "pan.___", state 333, "(1)"
+ line 435, "pan.___", state 346, "(1)"
+ line 408, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 447, "(1)"
+ line 431, "pan.___", state 464, "(1)"
+ line 435, "pan.___", state 477, "(1)"
+ line 408, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 586, "(1)"
+ line 431, "pan.___", state 603, "(1)"
+ line 435, "pan.___", state 616, "(1)"
+ line 408, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 715, "(1)"
+ line 431, "pan.___", state 732, "(1)"
+ line 435, "pan.___", state 745, "(1)"
+ line 408, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 846, "(1)"
+ line 431, "pan.___", state 863, "(1)"
+ line 435, "pan.___", state 876, "(1)"
+ line 268, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 955, "(1)"
+ line 280, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 978, "(1)"
+ line 249, "pan.___", state 986, "(1)"
+ line 253, "pan.___", state 998, "(1)"
+ line 257, "pan.___", state 1006, "(1)"
+ line 268, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1084, "(1)"
+ line 249, "pan.___", state 1092, "(1)"
+ line 253, "pan.___", state 1104, "(1)"
+ line 257, "pan.___", state 1112, "(1)"
+ line 272, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1176, "(1)"
+ line 249, "pan.___", state 1184, "(1)"
+ line 253, "pan.___", state 1196, "(1)"
+ line 257, "pan.___", state 1204, "(1)"
+ line 268, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1282, "(1)"
+ line 249, "pan.___", state 1290, "(1)"
+ line 253, "pan.___", state 1302, "(1)"
+ line 257, "pan.___", state 1310, "(1)"
+ line 272, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1374, "(1)"
+ line 249, "pan.___", state 1382, "(1)"
+ line 253, "pan.___", state 1394, "(1)"
+ line 257, "pan.___", state 1402, "(1)"
+ line 268, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1480, "(1)"
+ line 249, "pan.___", state 1488, "(1)"
+ line 253, "pan.___", state 1500, "(1)"
+ line 257, "pan.___", state 1508, "(1)"
+ line 272, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1572, "(1)"
+ line 249, "pan.___", state 1580, "(1)"
+ line 253, "pan.___", state 1592, "(1)"
+ line 257, "pan.___", state 1600, "(1)"
+ line 268, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1678, "(1)"
+ line 249, "pan.___", state 1686, "(1)"
+ line 253, "pan.___", state 1698, "(1)"
+ line 257, "pan.___", state 1706, "(1)"
+ line 1123, "pan.___", state 1722, "-end-"
+ (129 of 1722 states)
+unreached in proctype :init:
+ line 1138, "pan.___", state 11, "((i<1))"
+ line 1138, "pan.___", state 11, "((i>=1))"
+ (1 of 26 states)
+unreached in proctype :never:
+ line 1184, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 155 seconds
+pan: rate 2784.0683 states/second
+pan: avg transition delay 1.5479e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define NO_RMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_WMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+Depth= 3829 States= 1e+06 Transitions= 2.15e+08 Memory= 512.834 t= 341 R= 3e+03
+Depth= 3829 States= 2e+06 Transitions= 5.61e+08 Memory= 559.026 t= 920 R= 2e+03
+pan: claim violated! (at depth 1358)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3829, errors: 1
+ 2932262 states, stored
+7.8211443e+08 states, matched
+7.850467e+08 transitions (= stored+matched)
+4.5802467e+09 atomic steps
+hash conflicts: 5.9075827e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 324.385 equivalent memory usage for states (stored*(State-vector + overhead))
+ 136.208 actual memory usage for states (compression: 41.99%)
+ state-vector as stored = 13 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 601.897 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 22861 1831 2500 2 2 ]
+unreached in proctype urcu_reader
+ line 713, "pan.___", state 12, "((i<1))"
+ line 713, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 102, "(1)"
+ line 249, "pan.___", state 110, "(1)"
+ line 253, "pan.___", state 122, "(1)"
+ line 257, "pan.___", state 130, "(1)"
+ line 404, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 221, "(1)"
+ line 431, "pan.___", state 251, "(1)"
+ line 435, "pan.___", state 264, "(1)"
+ line 614, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 357, "(1)"
+ line 431, "pan.___", state 387, "(1)"
+ line 435, "pan.___", state 400, "(1)"
+ line 404, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 486, "(1)"
+ line 431, "pan.___", state 516, "(1)"
+ line 435, "pan.___", state 529, "(1)"
+ line 404, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 554, "(1)"
+ line 404, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 555, "else"
+ line 404, "pan.___", state 558, "(1)"
+ line 408, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 568, "(1)"
+ line 408, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 569, "else"
+ line 408, "pan.___", state 572, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 406, "pan.___", state 578, "((i<1))"
+ line 406, "pan.___", state 578, "((i>=1))"
+ line 413, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 586, "(1)"
+ line 413, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 587, "else"
+ line 413, "pan.___", state 590, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 417, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 600, "(1)"
+ line 417, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 601, "else"
+ line 417, "pan.___", state 604, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 415, "pan.___", state 610, "((i<2))"
+ line 415, "pan.___", state 610, "((i>=2))"
+ line 422, "pan.___", state 617, "(1)"
+ line 422, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 618, "else"
+ line 422, "pan.___", state 621, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 426, "pan.___", state 630, "(1)"
+ line 426, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 631, "else"
+ line 426, "pan.___", state 634, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 424, "pan.___", state 640, "((i<1))"
+ line 424, "pan.___", state 640, "((i>=1))"
+ line 431, "pan.___", state 647, "(1)"
+ line 431, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 648, "else"
+ line 431, "pan.___", state 651, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 435, "pan.___", state 660, "(1)"
+ line 435, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 661, "else"
+ line 435, "pan.___", state 664, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 433, "pan.___", state 670, "((i<2))"
+ line 433, "pan.___", state 670, "((i>=2))"
+ line 443, "pan.___", state 674, "(1)"
+ line 443, "pan.___", state 674, "(1)"
+ line 614, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 679, "(1)"
+ line 404, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 751, "(1)"
+ line 431, "pan.___", state 781, "(1)"
+ line 435, "pan.___", state 794, "(1)"
+ line 404, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 886, "(1)"
+ line 431, "pan.___", state 916, "(1)"
+ line 435, "pan.___", state 929, "(1)"
+ line 404, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1015, "(1)"
+ line 431, "pan.___", state 1045, "(1)"
+ line 435, "pan.___", state 1058, "(1)"
+ line 245, "pan.___", state 1091, "(1)"
+ line 253, "pan.___", state 1111, "(1)"
+ line 257, "pan.___", state 1119, "(1)"
+ line 748, "pan.___", state 1136, "-end-"
+ (92 of 1136 states)
+unreached in proctype urcu_writer
+ line 837, "pan.___", state 12, "((i<1))"
+ line 837, "pan.___", state 12, "((i>=1))"
+ line 404, "pan.___", state 46, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 60, "cache_dirty_urcu_active_readers = 0"
+ line 422, "pan.___", state 111, "(1)"
+ line 426, "pan.___", state 124, "(1)"
+ line 268, "pan.___", state 177, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 179, "(1)"
+ line 272, "pan.___", state 186, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 188, "(1)"
+ line 272, "pan.___", state 189, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 189, "else"
+ line 270, "pan.___", state 194, "((i<1))"
+ line 270, "pan.___", state 194, "((i>=1))"
+ line 276, "pan.___", state 199, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 201, "(1)"
+ line 276, "pan.___", state 202, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 202, "else"
+ line 280, "pan.___", state 208, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 210, "(1)"
+ line 280, "pan.___", state 211, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 211, "else"
+ line 285, "pan.___", state 220, "(cache_dirty_urcu_gp_ctr)"
+ line 285, "pan.___", state 220, "else"
+ line 404, "pan.___", state 239, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 253, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 271, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 285, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 304, "(1)"
+ line 426, "pan.___", state 317, "(1)"
+ line 431, "pan.___", state 334, "(1)"
+ line 435, "pan.___", state 347, "(1)"
+ line 408, "pan.___", state 384, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 402, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 416, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 448, "(1)"
+ line 431, "pan.___", state 465, "(1)"
+ line 435, "pan.___", state 478, "(1)"
+ line 408, "pan.___", state 523, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 541, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 555, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 587, "(1)"
+ line 431, "pan.___", state 604, "(1)"
+ line 435, "pan.___", state 617, "(1)"
+ line 408, "pan.___", state 652, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 670, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 684, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 716, "(1)"
+ line 431, "pan.___", state 733, "(1)"
+ line 435, "pan.___", state 746, "(1)"
+ line 408, "pan.___", state 783, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 801, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 815, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 847, "(1)"
+ line 431, "pan.___", state 864, "(1)"
+ line 435, "pan.___", state 877, "(1)"
+ line 268, "pan.___", state 932, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 941, "cache_dirty_urcu_active_readers = 0"
+ line 245, "pan.___", state 979, "(1)"
+ line 249, "pan.___", state 987, "(1)"
+ line 253, "pan.___", state 999, "(1)"
+ line 257, "pan.___", state 1007, "(1)"
+ line 268, "pan.___", state 1038, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1047, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1060, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1069, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1085, "(1)"
+ line 249, "pan.___", state 1093, "(1)"
+ line 253, "pan.___", state 1105, "(1)"
+ line 257, "pan.___", state 1113, "(1)"
+ line 272, "pan.___", state 1139, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1152, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1161, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1177, "(1)"
+ line 249, "pan.___", state 1185, "(1)"
+ line 253, "pan.___", state 1197, "(1)"
+ line 257, "pan.___", state 1205, "(1)"
+ line 268, "pan.___", state 1236, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1245, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1258, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1267, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1283, "(1)"
+ line 249, "pan.___", state 1291, "(1)"
+ line 253, "pan.___", state 1303, "(1)"
+ line 257, "pan.___", state 1311, "(1)"
+ line 272, "pan.___", state 1337, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1350, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1359, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1375, "(1)"
+ line 249, "pan.___", state 1383, "(1)"
+ line 253, "pan.___", state 1395, "(1)"
+ line 257, "pan.___", state 1403, "(1)"
+ line 268, "pan.___", state 1434, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1443, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1456, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1465, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1481, "(1)"
+ line 249, "pan.___", state 1489, "(1)"
+ line 253, "pan.___", state 1501, "(1)"
+ line 257, "pan.___", state 1509, "(1)"
+ line 272, "pan.___", state 1535, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1548, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1557, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1573, "(1)"
+ line 249, "pan.___", state 1581, "(1)"
+ line 253, "pan.___", state 1593, "(1)"
+ line 257, "pan.___", state 1601, "(1)"
+ line 268, "pan.___", state 1632, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1641, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1654, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1663, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1679, "(1)"
+ line 249, "pan.___", state 1687, "(1)"
+ line 253, "pan.___", state 1699, "(1)"
+ line 257, "pan.___", state 1707, "(1)"
+ line 1123, "pan.___", state 1723, "-end-"
+ (110 of 1723 states)
+unreached in proctype :init:
+ line 1138, "pan.___", state 11, "((i<1))"
+ line 1138, "pan.___", state 11, "((i>=1))"
+ (1 of 26 states)
+unreached in proctype :never:
+ line 1184, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 1.31e+03 seconds
+pan: rate 2245.8255 states/second
+pan: avg transition delay 1.6631e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define NO_WMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+Depth= 4014 States= 1e+06 Transitions= 1.62e+08 Memory= 512.736 t= 256 R= 4e+03
+pan: claim violated! (at depth 1235)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 4014, errors: 1
+ 1411681 states, stored
+2.3165948e+08 states, matched
+2.3307116e+08 transitions (= stored+matched)
+1.3076596e+09 atomic steps
+hash conflicts: 78416855 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 156.169 equivalent memory usage for states (stored*(State-vector + overhead))
+ 66.078 actual memory usage for states (compression: 42.31%)
+ state-vector as stored = 13 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 531.779 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 14645 1835 1567 2 2 ]
+unreached in proctype urcu_reader
+ line 713, "pan.___", state 12, "((i<1))"
+ line 713, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 102, "(1)"
+ line 249, "pan.___", state 110, "(1)"
+ line 253, "pan.___", state 122, "(1)"
+ line 257, "pan.___", state 130, "(1)"
+ line 404, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 221, "(1)"
+ line 431, "pan.___", state 251, "(1)"
+ line 435, "pan.___", state 264, "(1)"
+ line 614, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 357, "(1)"
+ line 431, "pan.___", state 387, "(1)"
+ line 435, "pan.___", state 400, "(1)"
+ line 404, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 486, "(1)"
+ line 431, "pan.___", state 516, "(1)"
+ line 435, "pan.___", state 529, "(1)"
+ line 404, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 554, "(1)"
+ line 404, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 555, "else"
+ line 404, "pan.___", state 558, "(1)"
+ line 408, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 568, "(1)"
+ line 408, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 569, "else"
+ line 408, "pan.___", state 572, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 406, "pan.___", state 578, "((i<1))"
+ line 406, "pan.___", state 578, "((i>=1))"
+ line 413, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 586, "(1)"
+ line 413, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 587, "else"
+ line 413, "pan.___", state 590, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 417, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 600, "(1)"
+ line 417, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 601, "else"
+ line 417, "pan.___", state 604, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 415, "pan.___", state 610, "((i<2))"
+ line 415, "pan.___", state 610, "((i>=2))"
+ line 422, "pan.___", state 617, "(1)"
+ line 422, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 618, "else"
+ line 422, "pan.___", state 621, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 426, "pan.___", state 630, "(1)"
+ line 426, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 631, "else"
+ line 426, "pan.___", state 634, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 424, "pan.___", state 640, "((i<1))"
+ line 424, "pan.___", state 640, "((i>=1))"
+ line 431, "pan.___", state 647, "(1)"
+ line 431, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 648, "else"
+ line 431, "pan.___", state 651, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 435, "pan.___", state 660, "(1)"
+ line 435, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 661, "else"
+ line 435, "pan.___", state 664, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 433, "pan.___", state 670, "((i<2))"
+ line 433, "pan.___", state 670, "((i>=2))"
+ line 443, "pan.___", state 674, "(1)"
+ line 443, "pan.___", state 674, "(1)"
+ line 614, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 679, "(1)"
+ line 404, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 751, "(1)"
+ line 431, "pan.___", state 781, "(1)"
+ line 435, "pan.___", state 794, "(1)"
+ line 404, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 886, "(1)"
+ line 431, "pan.___", state 916, "(1)"
+ line 435, "pan.___", state 929, "(1)"
+ line 404, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1015, "(1)"
+ line 431, "pan.___", state 1045, "(1)"
+ line 435, "pan.___", state 1058, "(1)"
+ line 245, "pan.___", state 1091, "(1)"
+ line 253, "pan.___", state 1111, "(1)"
+ line 257, "pan.___", state 1119, "(1)"
+ line 748, "pan.___", state 1136, "-end-"
+ (92 of 1136 states)
+unreached in proctype urcu_writer
+ line 837, "pan.___", state 12, "((i<1))"
+ line 837, "pan.___", state 12, "((i>=1))"
+ line 404, "pan.___", state 49, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 63, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 81, "cache_dirty_rcu_ptr = 0"
+ line 422, "pan.___", state 114, "(1)"
+ line 426, "pan.___", state 127, "(1)"
+ line 431, "pan.___", state 144, "(1)"
+ line 268, "pan.___", state 180, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 189, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 202, "cache_dirty_rcu_ptr = 0"
+ line 404, "pan.___", state 242, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 256, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 274, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 288, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 307, "(1)"
+ line 426, "pan.___", state 320, "(1)"
+ line 431, "pan.___", state 337, "(1)"
+ line 435, "pan.___", state 350, "(1)"
+ line 408, "pan.___", state 387, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 405, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 419, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 451, "(1)"
+ line 431, "pan.___", state 468, "(1)"
+ line 435, "pan.___", state 481, "(1)"
+ line 404, "pan.___", state 511, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 525, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 543, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 557, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 576, "(1)"
+ line 426, "pan.___", state 589, "(1)"
+ line 431, "pan.___", state 606, "(1)"
+ line 435, "pan.___", state 619, "(1)"
+ line 404, "pan.___", state 640, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 642, "(1)"
+ line 404, "pan.___", state 643, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 643, "else"
+ line 404, "pan.___", state 646, "(1)"
+ line 408, "pan.___", state 654, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 656, "(1)"
+ line 408, "pan.___", state 657, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 657, "else"
+ line 408, "pan.___", state 660, "(1)"
+ line 408, "pan.___", state 661, "(1)"
+ line 408, "pan.___", state 661, "(1)"
+ line 406, "pan.___", state 666, "((i<1))"
+ line 406, "pan.___", state 666, "((i>=1))"
+ line 413, "pan.___", state 672, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 674, "(1)"
+ line 413, "pan.___", state 675, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 675, "else"
+ line 413, "pan.___", state 678, "(1)"
+ line 413, "pan.___", state 679, "(1)"
+ line 413, "pan.___", state 679, "(1)"
+ line 417, "pan.___", state 686, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 688, "(1)"
+ line 417, "pan.___", state 689, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 689, "else"
+ line 417, "pan.___", state 692, "(1)"
+ line 417, "pan.___", state 693, "(1)"
+ line 417, "pan.___", state 693, "(1)"
+ line 415, "pan.___", state 698, "((i<2))"
+ line 415, "pan.___", state 698, "((i>=2))"
+ line 422, "pan.___", state 705, "(1)"
+ line 422, "pan.___", state 706, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 706, "else"
+ line 422, "pan.___", state 709, "(1)"
+ line 422, "pan.___", state 710, "(1)"
+ line 422, "pan.___", state 710, "(1)"
+ line 426, "pan.___", state 718, "(1)"
+ line 426, "pan.___", state 719, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 719, "else"
+ line 426, "pan.___", state 722, "(1)"
+ line 426, "pan.___", state 723, "(1)"
+ line 426, "pan.___", state 723, "(1)"
+ line 424, "pan.___", state 728, "((i<1))"
+ line 424, "pan.___", state 728, "((i>=1))"
+ line 431, "pan.___", state 735, "(1)"
+ line 431, "pan.___", state 736, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 736, "else"
+ line 431, "pan.___", state 739, "(1)"
+ line 431, "pan.___", state 740, "(1)"
+ line 431, "pan.___", state 740, "(1)"
+ line 435, "pan.___", state 748, "(1)"
+ line 435, "pan.___", state 749, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 749, "else"
+ line 435, "pan.___", state 752, "(1)"
+ line 435, "pan.___", state 753, "(1)"
+ line 435, "pan.___", state 753, "(1)"
+ line 433, "pan.___", state 758, "((i<2))"
+ line 433, "pan.___", state 758, "((i>=2))"
+ line 443, "pan.___", state 762, "(1)"
+ line 443, "pan.___", state 762, "(1)"
+ line 1003, "pan.___", state 766, "_proc_urcu_writer = (_proc_urcu_writer|(1<<10))"
+ line 404, "pan.___", state 771, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 773, "(1)"
+ line 404, "pan.___", state 774, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 774, "else"
+ line 404, "pan.___", state 777, "(1)"
+ line 408, "pan.___", state 785, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 787, "(1)"
+ line 408, "pan.___", state 788, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 788, "else"
+ line 408, "pan.___", state 791, "(1)"
+ line 408, "pan.___", state 792, "(1)"
+ line 408, "pan.___", state 792, "(1)"
+ line 406, "pan.___", state 797, "((i<1))"
+ line 406, "pan.___", state 797, "((i>=1))"
+ line 413, "pan.___", state 803, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 805, "(1)"
+ line 413, "pan.___", state 806, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 806, "else"
+ line 413, "pan.___", state 809, "(1)"
+ line 413, "pan.___", state 810, "(1)"
+ line 413, "pan.___", state 810, "(1)"
+ line 417, "pan.___", state 817, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 819, "(1)"
+ line 417, "pan.___", state 820, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 820, "else"
+ line 417, "pan.___", state 823, "(1)"
+ line 417, "pan.___", state 824, "(1)"
+ line 417, "pan.___", state 824, "(1)"
+ line 415, "pan.___", state 829, "((i<2))"
+ line 415, "pan.___", state 829, "((i>=2))"
+ line 422, "pan.___", state 836, "(1)"
+ line 422, "pan.___", state 837, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 837, "else"
+ line 422, "pan.___", state 840, "(1)"
+ line 422, "pan.___", state 841, "(1)"
+ line 422, "pan.___", state 841, "(1)"
+ line 426, "pan.___", state 849, "(1)"
+ line 426, "pan.___", state 850, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 850, "else"
+ line 426, "pan.___", state 853, "(1)"
+ line 426, "pan.___", state 854, "(1)"
+ line 426, "pan.___", state 854, "(1)"
+ line 424, "pan.___", state 859, "((i<1))"
+ line 424, "pan.___", state 859, "((i>=1))"
+ line 431, "pan.___", state 866, "(1)"
+ line 431, "pan.___", state 867, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 867, "else"
+ line 431, "pan.___", state 870, "(1)"
+ line 431, "pan.___", state 871, "(1)"
+ line 431, "pan.___", state 871, "(1)"
+ line 435, "pan.___", state 879, "(1)"
+ line 435, "pan.___", state 880, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 880, "else"
+ line 435, "pan.___", state 883, "(1)"
+ line 435, "pan.___", state 884, "(1)"
+ line 435, "pan.___", state 884, "(1)"
+ line 433, "pan.___", state 889, "((i<2))"
+ line 433, "pan.___", state 889, "((i>=2))"
+ line 443, "pan.___", state 893, "(1)"
+ line 443, "pan.___", state 893, "(1)"
+ line 1019, "pan.___", state 898, "_proc_urcu_writer = (_proc_urcu_writer|(1<<11))"
+ line 1014, "pan.___", state 899, "(((tmp2&((1<<7)-1))&&((tmp2^0)&(1<<7))))"
+ line 1014, "pan.___", state 899, "else"
+ line 1039, "pan.___", state 903, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<12)|(1<<11))))"
+ line 268, "pan.___", state 934, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 943, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 958, "(1)"
+ line 280, "pan.___", state 965, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 981, "(1)"
+ line 249, "pan.___", state 989, "(1)"
+ line 253, "pan.___", state 1001, "(1)"
+ line 257, "pan.___", state 1009, "(1)"
+ line 268, "pan.___", state 1040, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1049, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1062, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1071, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1087, "(1)"
+ line 249, "pan.___", state 1095, "(1)"
+ line 253, "pan.___", state 1107, "(1)"
+ line 257, "pan.___", state 1115, "(1)"
+ line 272, "pan.___", state 1141, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1154, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1163, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1179, "(1)"
+ line 249, "pan.___", state 1187, "(1)"
+ line 253, "pan.___", state 1199, "(1)"
+ line 257, "pan.___", state 1207, "(1)"
+ line 268, "pan.___", state 1238, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1247, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1260, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1269, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1285, "(1)"
+ line 249, "pan.___", state 1293, "(1)"
+ line 253, "pan.___", state 1305, "(1)"
+ line 257, "pan.___", state 1313, "(1)"
+ line 268, "pan.___", state 1330, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1332, "(1)"
+ line 272, "pan.___", state 1339, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1341, "(1)"
+ line 272, "pan.___", state 1342, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1342, "else"
+ line 270, "pan.___", state 1347, "((i<1))"
+ line 270, "pan.___", state 1347, "((i>=1))"
+ line 276, "pan.___", state 1352, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1354, "(1)"
+ line 276, "pan.___", state 1355, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1355, "else"
+ line 280, "pan.___", state 1361, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1363, "(1)"
+ line 280, "pan.___", state 1364, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1364, "else"
+ line 278, "pan.___", state 1369, "((i<2))"
+ line 278, "pan.___", state 1369, "((i>=2))"
+ line 245, "pan.___", state 1377, "(1)"
+ line 249, "pan.___", state 1385, "(1)"
+ line 249, "pan.___", state 1386, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1386, "else"
+ line 247, "pan.___", state 1391, "((i<1))"
+ line 247, "pan.___", state 1391, "((i>=1))"
+ line 253, "pan.___", state 1397, "(1)"
+ line 253, "pan.___", state 1398, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1398, "else"
+ line 257, "pan.___", state 1405, "(1)"
+ line 257, "pan.___", state 1406, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1406, "else"
+ line 262, "pan.___", state 1415, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1415, "else"
+ line 1115, "pan.___", state 1418, "i = 0"
+ line 1115, "pan.___", state 1420, "reader_barrier = 1"
+ line 1115, "pan.___", state 1431, "((i<1))"
+ line 1115, "pan.___", state 1431, "((i>=1))"
+ line 268, "pan.___", state 1436, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1438, "(1)"
+ line 272, "pan.___", state 1445, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1447, "(1)"
+ line 272, "pan.___", state 1448, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1448, "else"
+ line 270, "pan.___", state 1453, "((i<1))"
+ line 270, "pan.___", state 1453, "((i>=1))"
+ line 276, "pan.___", state 1458, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1460, "(1)"
+ line 276, "pan.___", state 1461, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1461, "else"
+ line 280, "pan.___", state 1467, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1469, "(1)"
+ line 280, "pan.___", state 1470, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1470, "else"
+ line 278, "pan.___", state 1475, "((i<2))"
+ line 278, "pan.___", state 1475, "((i>=2))"
+ line 245, "pan.___", state 1483, "(1)"
+ line 249, "pan.___", state 1491, "(1)"
+ line 249, "pan.___", state 1492, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1492, "else"
+ line 247, "pan.___", state 1497, "((i<1))"
+ line 247, "pan.___", state 1497, "((i>=1))"
+ line 253, "pan.___", state 1503, "(1)"
+ line 253, "pan.___", state 1504, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1504, "else"
+ line 257, "pan.___", state 1511, "(1)"
+ line 257, "pan.___", state 1512, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1512, "else"
+ line 262, "pan.___", state 1521, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1521, "else"
+ line 295, "pan.___", state 1523, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1523, "else"
+ line 1115, "pan.___", state 1524, "(cache_dirty_urcu_gp_ctr)"
+ line 1115, "pan.___", state 1524, "else"
+ line 272, "pan.___", state 1537, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1550, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1559, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1575, "(1)"
+ line 249, "pan.___", state 1583, "(1)"
+ line 253, "pan.___", state 1595, "(1)"
+ line 257, "pan.___", state 1603, "(1)"
+ line 268, "pan.___", state 1634, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1643, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1656, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1665, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1681, "(1)"
+ line 249, "pan.___", state 1689, "(1)"
+ line 253, "pan.___", state 1701, "(1)"
+ line 257, "pan.___", state 1709, "(1)"
+ line 1123, "pan.___", state 1725, "-end-"
+ (212 of 1725 states)
+unreached in proctype :init:
+ line 1138, "pan.___", state 11, "((i<1))"
+ line 1138, "pan.___", state 11, "((i>=1))"
+ (1 of 26 states)
+unreached in proctype :never:
+ line 1184, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 372 seconds
+pan: rate 3796.6785 states/second
+pan: avg transition delay 1.5953e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define SINGLE_FLIP
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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+1212:2:2120
+1213:2:2121
+1214:2:2128
+1215:2:2133
+1216:2:2140
+1217:2:2141
+1218:2:2140
+1219:2:2141
+1220:2:2148
+1221:2:2152
+1222:0:2889
+1223:2:2157
+1224:0:2889
+1225:2:2158
+1226:0:2889
+1227:2:2159
+1228:0:2889
+1229:2:2160
+1230:0:2889
+1231:1:812
+1232:1:813
+1233:0:2887
+1234:2:2161
+1235:0:2893
+1236:1:1005
--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+depth 7: Claim reached state 9 (line 1184)
+depth 136: Claim reached state 9 (line 1183)
+Depth= 12986 States= 1e+06 Transitions= 1.85e+08 Memory= 494.963 t= 294 R= 3e+03
+Depth= 12986 States= 2e+06 Transitions= 6.44e+08 Memory= 520.744 t= 1.06e+03 R= 2e+03
+Depth= 12986 States= 3e+06 Transitions= 1.24e+09 Memory= 545.842 t= 2.08e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 12986 States= 4e+06 Transitions= 1.65e+09 Memory= 602.940 t= 2.76e+03 R= 1e+03
+Depth= 12986 States= 5e+06 Transitions= 2e+09 Memory= 629.111 t= 3.34e+03 R= 1e+03
+Depth= 12986 States= 6e+06 Transitions= 2.47e+09 Memory= 655.283 t= 4.12e+03 R= 1e+03
+Depth= 12986 States= 7e+06 Transitions= 2.94e+09 Memory= 681.260 t= 4.93e+03 R= 1e+03
+Depth= 12986 States= 8e+06 Transitions= 3.45e+09 Memory= 705.967 t= 5.79e+03 R= 1e+03
+Depth= 12986 States= 9e+06 Transitions= 3.84e+09 Memory= 732.529 t= 6.46e+03 R= 1e+03
+pan: resizing hashtable to -w24.. done
+Depth= 12986 States= 1e+07 Transitions= 4.23e+09 Memory= 882.404 t= 7.1e+03 R= 1e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 12986, errors: 0
+ 5822478 states, stored (1.02932e+07 visited)
+4.3658924e+09 states, matched
+4.3761856e+09 transitions (= visited+matched)
+2.5547511e+10 atomic steps
+hash conflicts: 1.1937107e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 644.119 equivalent memory usage for states (stored*(State-vector + overhead))
+ 303.976 actual memory usage for states (compression: 47.19%)
+ state-vector as stored = 19 byte + 36 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 889.631 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 28603 2179 2102 2 2 ]
+unreached in proctype urcu_reader
+ line 268, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 102, "(1)"
+ line 249, "pan.___", state 110, "(1)"
+ line 253, "pan.___", state 122, "(1)"
+ line 257, "pan.___", state 130, "(1)"
+ line 404, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 221, "(1)"
+ line 431, "pan.___", state 251, "(1)"
+ line 435, "pan.___", state 264, "(1)"
+ line 614, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 357, "(1)"
+ line 431, "pan.___", state 387, "(1)"
+ line 435, "pan.___", state 400, "(1)"
+ line 404, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 486, "(1)"
+ line 431, "pan.___", state 516, "(1)"
+ line 435, "pan.___", state 529, "(1)"
+ line 404, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 554, "(1)"
+ line 404, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 555, "else"
+ line 404, "pan.___", state 558, "(1)"
+ line 408, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 568, "(1)"
+ line 408, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 569, "else"
+ line 408, "pan.___", state 572, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 406, "pan.___", state 578, "((i<1))"
+ line 406, "pan.___", state 578, "((i>=1))"
+ line 413, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 586, "(1)"
+ line 413, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 587, "else"
+ line 413, "pan.___", state 590, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 417, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 600, "(1)"
+ line 417, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 601, "else"
+ line 417, "pan.___", state 604, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 415, "pan.___", state 610, "((i<2))"
+ line 415, "pan.___", state 610, "((i>=2))"
+ line 422, "pan.___", state 617, "(1)"
+ line 422, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 618, "else"
+ line 422, "pan.___", state 621, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 426, "pan.___", state 630, "(1)"
+ line 426, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 631, "else"
+ line 426, "pan.___", state 634, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 424, "pan.___", state 640, "((i<1))"
+ line 424, "pan.___", state 640, "((i>=1))"
+ line 431, "pan.___", state 647, "(1)"
+ line 431, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 648, "else"
+ line 431, "pan.___", state 651, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 435, "pan.___", state 660, "(1)"
+ line 435, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 661, "else"
+ line 435, "pan.___", state 664, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 433, "pan.___", state 670, "((i<2))"
+ line 433, "pan.___", state 670, "((i>=2))"
+ line 443, "pan.___", state 674, "(1)"
+ line 443, "pan.___", state 674, "(1)"
+ line 614, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 679, "(1)"
+ line 404, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 751, "(1)"
+ line 431, "pan.___", state 781, "(1)"
+ line 435, "pan.___", state 794, "(1)"
+ line 404, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 886, "(1)"
+ line 431, "pan.___", state 916, "(1)"
+ line 435, "pan.___", state 929, "(1)"
+ line 404, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1015, "(1)"
+ line 431, "pan.___", state 1045, "(1)"
+ line 435, "pan.___", state 1058, "(1)"
+ line 245, "pan.___", state 1091, "(1)"
+ line 253, "pan.___", state 1111, "(1)"
+ line 257, "pan.___", state 1119, "(1)"
+ line 748, "pan.___", state 1136, "-end-"
+ (91 of 1136 states)
+unreached in proctype urcu_writer
+ line 404, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 422, "pan.___", state 110, "(1)"
+ line 426, "pan.___", state 123, "(1)"
+ line 431, "pan.___", state 140, "(1)"
+ line 268, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 404, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 303, "(1)"
+ line 426, "pan.___", state 316, "(1)"
+ line 431, "pan.___", state 333, "(1)"
+ line 435, "pan.___", state 346, "(1)"
+ line 408, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 447, "(1)"
+ line 431, "pan.___", state 464, "(1)"
+ line 435, "pan.___", state 477, "(1)"
+ line 408, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 586, "(1)"
+ line 431, "pan.___", state 603, "(1)"
+ line 435, "pan.___", state 616, "(1)"
+ line 408, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 715, "(1)"
+ line 431, "pan.___", state 732, "(1)"
+ line 435, "pan.___", state 745, "(1)"
+ line 408, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 846, "(1)"
+ line 431, "pan.___", state 863, "(1)"
+ line 435, "pan.___", state 876, "(1)"
+ line 268, "pan.___", state 926, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 935, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 948, "cache_dirty_rcu_ptr = 0"
+ line 245, "pan.___", state 973, "(1)"
+ line 249, "pan.___", state 981, "(1)"
+ line 253, "pan.___", state 993, "(1)"
+ line 257, "pan.___", state 1001, "(1)"
+ line 268, "pan.___", state 1032, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1041, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1054, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1063, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1079, "(1)"
+ line 249, "pan.___", state 1087, "(1)"
+ line 253, "pan.___", state 1099, "(1)"
+ line 257, "pan.___", state 1107, "(1)"
+ line 268, "pan.___", state 1128, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1137, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1152, "(1)"
+ line 280, "pan.___", state 1159, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1175, "(1)"
+ line 249, "pan.___", state 1183, "(1)"
+ line 253, "pan.___", state 1195, "(1)"
+ line 257, "pan.___", state 1203, "(1)"
+ line 268, "pan.___", state 1234, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1243, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1256, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1265, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1281, "(1)"
+ line 249, "pan.___", state 1289, "(1)"
+ line 253, "pan.___", state 1301, "(1)"
+ line 257, "pan.___", state 1309, "(1)"
+ line 272, "pan.___", state 1335, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1348, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1357, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1373, "(1)"
+ line 249, "pan.___", state 1381, "(1)"
+ line 253, "pan.___", state 1393, "(1)"
+ line 257, "pan.___", state 1401, "(1)"
+ line 268, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1441, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1454, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1463, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1479, "(1)"
+ line 249, "pan.___", state 1487, "(1)"
+ line 253, "pan.___", state 1499, "(1)"
+ line 257, "pan.___", state 1507, "(1)"
+ line 272, "pan.___", state 1533, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1546, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1555, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1571, "(1)"
+ line 249, "pan.___", state 1579, "(1)"
+ line 253, "pan.___", state 1591, "(1)"
+ line 257, "pan.___", state 1599, "(1)"
+ line 268, "pan.___", state 1630, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1639, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1652, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1661, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1677, "(1)"
+ line 249, "pan.___", state 1685, "(1)"
+ line 253, "pan.___", state 1697, "(1)"
+ line 257, "pan.___", state 1705, "(1)"
+ line 272, "pan.___", state 1731, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1744, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1753, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1769, "(1)"
+ line 249, "pan.___", state 1777, "(1)"
+ line 253, "pan.___", state 1789, "(1)"
+ line 257, "pan.___", state 1797, "(1)"
+ line 268, "pan.___", state 1828, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1837, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1850, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1859, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1875, "(1)"
+ line 249, "pan.___", state 1883, "(1)"
+ line 253, "pan.___", state 1895, "(1)"
+ line 257, "pan.___", state 1903, "(1)"
+ line 1123, "pan.___", state 1919, "-end-"
+ (118 of 1919 states)
+unreached in proctype :init:
+ (0 of 26 states)
+unreached in proctype :never:
+ line 1186, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 7.33e+03 seconds
+pan: rate 1403.7352 states/second
+pan: avg transition delay 1.6756e-06 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define READER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1179)
+depth 7: Claim reached state 9 (line 1184)
+depth 46: Claim reached state 9 (line 1183)
+Depth= 3817 States= 1e+06 Transitions= 2.94e+08 Memory= 492.912 t= 480 R= 2e+03
+Depth= 3900 States= 2e+06 Transitions= 6.63e+08 Memory= 519.572 t= 1.09e+03 R= 2e+03
+Depth= 3900 States= 3e+06 Transitions= 1.33e+09 Memory= 543.986 t= 2.23e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 3900 States= 4e+06 Transitions= 1.71e+09 Memory= 601.279 t= 2.86e+03 R= 1e+03
+Depth= 3900 States= 5e+06 Transitions= 2.06e+09 Memory= 627.647 t= 3.45e+03 R= 1e+03
+Depth= 3900 States= 6e+06 Transitions= 2.49e+09 Memory= 653.818 t= 4.18e+03 R= 1e+03
+Depth= 3900 States= 7e+06 Transitions= 3.14e+09 Memory= 678.135 t= 5.28e+03 R= 1e+03
+Depth= 3900 States= 8e+06 Transitions= 3.52e+09 Memory= 704.404 t= 5.93e+03 R= 1e+03
+Depth= 3900 States= 9e+06 Transitions= 3.88e+09 Memory= 730.869 t= 6.53e+03 R= 1e+03
+pan: resizing hashtable to -w24.. done
+Depth= 3900 States= 1e+07 Transitions= 4.34e+09 Memory= 880.451 t= 7.29e+03 R= 1e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3900, errors: 0
+ 5638524 states, stored (1.00251e+07 visited)
+4.3347674e+09 states, matched
+4.3447924e+09 transitions (= visited+matched)
+2.5387604e+10 atomic steps
+hash conflicts: 1.1627355e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 623.769 equivalent memory usage for states (stored*(State-vector + overhead))
+ 295.411 actual memory usage for states (compression: 47.36%)
+ state-vector as stored = 19 byte + 36 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 881.037 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 26786 2128 1995 2 2 ]
+unreached in proctype urcu_reader
+ line 268, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 102, "(1)"
+ line 249, "pan.___", state 110, "(1)"
+ line 253, "pan.___", state 122, "(1)"
+ line 257, "pan.___", state 130, "(1)"
+ line 404, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 221, "(1)"
+ line 431, "pan.___", state 251, "(1)"
+ line 435, "pan.___", state 264, "(1)"
+ line 614, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 404, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 357, "(1)"
+ line 431, "pan.___", state 387, "(1)"
+ line 435, "pan.___", state 400, "(1)"
+ line 404, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 486, "(1)"
+ line 431, "pan.___", state 516, "(1)"
+ line 435, "pan.___", state 529, "(1)"
+ line 404, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 404, "pan.___", state 554, "(1)"
+ line 404, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 404, "pan.___", state 555, "else"
+ line 404, "pan.___", state 558, "(1)"
+ line 408, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 408, "pan.___", state 568, "(1)"
+ line 408, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 408, "pan.___", state 569, "else"
+ line 408, "pan.___", state 572, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 408, "pan.___", state 573, "(1)"
+ line 406, "pan.___", state 578, "((i<1))"
+ line 406, "pan.___", state 578, "((i>=1))"
+ line 413, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 413, "pan.___", state 586, "(1)"
+ line 413, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 413, "pan.___", state 587, "else"
+ line 413, "pan.___", state 590, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 413, "pan.___", state 591, "(1)"
+ line 417, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 417, "pan.___", state 600, "(1)"
+ line 417, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 417, "pan.___", state 601, "else"
+ line 417, "pan.___", state 604, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 417, "pan.___", state 605, "(1)"
+ line 415, "pan.___", state 610, "((i<2))"
+ line 415, "pan.___", state 610, "((i>=2))"
+ line 422, "pan.___", state 617, "(1)"
+ line 422, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 422, "pan.___", state 618, "else"
+ line 422, "pan.___", state 621, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 422, "pan.___", state 622, "(1)"
+ line 426, "pan.___", state 630, "(1)"
+ line 426, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 426, "pan.___", state 631, "else"
+ line 426, "pan.___", state 634, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 426, "pan.___", state 635, "(1)"
+ line 424, "pan.___", state 640, "((i<1))"
+ line 424, "pan.___", state 640, "((i>=1))"
+ line 431, "pan.___", state 647, "(1)"
+ line 431, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 431, "pan.___", state 648, "else"
+ line 431, "pan.___", state 651, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 431, "pan.___", state 652, "(1)"
+ line 435, "pan.___", state 660, "(1)"
+ line 435, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 435, "pan.___", state 661, "else"
+ line 435, "pan.___", state 664, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 435, "pan.___", state 665, "(1)"
+ line 433, "pan.___", state 670, "((i<2))"
+ line 433, "pan.___", state 670, "((i>=2))"
+ line 443, "pan.___", state 674, "(1)"
+ line 443, "pan.___", state 674, "(1)"
+ line 614, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 614, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 614, "pan.___", state 679, "(1)"
+ line 404, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 751, "(1)"
+ line 431, "pan.___", state 781, "(1)"
+ line 435, "pan.___", state 794, "(1)"
+ line 404, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 886, "(1)"
+ line 431, "pan.___", state 916, "(1)"
+ line 435, "pan.___", state 929, "(1)"
+ line 404, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 413, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 1015, "(1)"
+ line 431, "pan.___", state 1045, "(1)"
+ line 435, "pan.___", state 1058, "(1)"
+ line 245, "pan.___", state 1091, "(1)"
+ line 253, "pan.___", state 1111, "(1)"
+ line 257, "pan.___", state 1119, "(1)"
+ line 748, "pan.___", state 1136, "-end-"
+ (91 of 1136 states)
+unreached in proctype urcu_writer
+ line 404, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 422, "pan.___", state 110, "(1)"
+ line 426, "pan.___", state 123, "(1)"
+ line 431, "pan.___", state 140, "(1)"
+ line 268, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 404, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 422, "pan.___", state 303, "(1)"
+ line 426, "pan.___", state 316, "(1)"
+ line 431, "pan.___", state 333, "(1)"
+ line 435, "pan.___", state 346, "(1)"
+ line 408, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 447, "(1)"
+ line 431, "pan.___", state 464, "(1)"
+ line 435, "pan.___", state 477, "(1)"
+ line 408, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 586, "(1)"
+ line 431, "pan.___", state 603, "(1)"
+ line 435, "pan.___", state 616, "(1)"
+ line 408, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 715, "(1)"
+ line 431, "pan.___", state 732, "(1)"
+ line 435, "pan.___", state 745, "(1)"
+ line 408, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 413, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 426, "pan.___", state 846, "(1)"
+ line 431, "pan.___", state 863, "(1)"
+ line 435, "pan.___", state 876, "(1)"
+ line 268, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 955, "(1)"
+ line 280, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 978, "(1)"
+ line 249, "pan.___", state 986, "(1)"
+ line 253, "pan.___", state 998, "(1)"
+ line 257, "pan.___", state 1006, "(1)"
+ line 268, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1084, "(1)"
+ line 249, "pan.___", state 1092, "(1)"
+ line 253, "pan.___", state 1104, "(1)"
+ line 257, "pan.___", state 1112, "(1)"
+ line 272, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1176, "(1)"
+ line 249, "pan.___", state 1184, "(1)"
+ line 253, "pan.___", state 1196, "(1)"
+ line 257, "pan.___", state 1204, "(1)"
+ line 268, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1282, "(1)"
+ line 249, "pan.___", state 1290, "(1)"
+ line 253, "pan.___", state 1302, "(1)"
+ line 257, "pan.___", state 1310, "(1)"
+ line 272, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1374, "(1)"
+ line 249, "pan.___", state 1382, "(1)"
+ line 253, "pan.___", state 1394, "(1)"
+ line 257, "pan.___", state 1402, "(1)"
+ line 268, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1480, "(1)"
+ line 249, "pan.___", state 1488, "(1)"
+ line 253, "pan.___", state 1500, "(1)"
+ line 257, "pan.___", state 1508, "(1)"
+ line 272, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1572, "(1)"
+ line 249, "pan.___", state 1580, "(1)"
+ line 253, "pan.___", state 1592, "(1)"
+ line 257, "pan.___", state 1600, "(1)"
+ line 268, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1678, "(1)"
+ line 249, "pan.___", state 1686, "(1)"
+ line 253, "pan.___", state 1698, "(1)"
+ line 257, "pan.___", state 1706, "(1)"
+ line 1123, "pan.___", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 26 states)
+unreached in proctype :never:
+ line 1186, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 7.3e+03 seconds
+pan: rate 1373.8126 states/second
+pan: avg transition delay 1.6795e-06 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1180)
+depth 7: Claim reached state 9 (line 1185)
+depth 46: Claim reached state 9 (line 1184)
+pan: acceptance cycle (at depth 3798)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 3956, errors: 1
+ 139740 states, stored (233412 visited)
+ 43234612 states, matched
+ 43468024 transitions (= visited+matched)
+2.3201732e+08 atomic steps
+hash conflicts: 937081 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 15.459 equivalent memory usage for states (stored*(State-vector + overhead))
+ 7.007 actual memory usage for states (compression: 45.33%)
+ state-vector as stored = 17 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 472.697 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 1001 532 228 2 2 ]
+unreached in proctype urcu_reader
+ line 269, "pan.___", state 55, "cache_dirty_urcu_gp_ctr = 0"
+ line 277, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 86, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 102, "(1)"
+ line 250, "pan.___", state 110, "(1)"
+ line 254, "pan.___", state 122, "(1)"
+ line 258, "pan.___", state 130, "(1)"
+ line 405, "pan.___", state 156, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 188, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 202, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 221, "(1)"
+ line 432, "pan.___", state 251, "(1)"
+ line 436, "pan.___", state 264, "(1)"
+ line 615, "pan.___", state 285, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 405, "pan.___", state 292, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 324, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 338, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 357, "(1)"
+ line 432, "pan.___", state 387, "(1)"
+ line 436, "pan.___", state 400, "(1)"
+ line 405, "pan.___", state 421, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 453, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 467, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 486, "(1)"
+ line 432, "pan.___", state 516, "(1)"
+ line 436, "pan.___", state 529, "(1)"
+ line 405, "pan.___", state 552, "cache_dirty_urcu_gp_ctr = 0"
+ line 405, "pan.___", state 554, "(1)"
+ line 405, "pan.___", state 555, "(cache_dirty_urcu_gp_ctr)"
+ line 405, "pan.___", state 555, "else"
+ line 405, "pan.___", state 558, "(1)"
+ line 409, "pan.___", state 566, "cache_dirty_urcu_active_readers = 0"
+ line 409, "pan.___", state 568, "(1)"
+ line 409, "pan.___", state 569, "(cache_dirty_urcu_active_readers)"
+ line 409, "pan.___", state 569, "else"
+ line 409, "pan.___", state 572, "(1)"
+ line 409, "pan.___", state 573, "(1)"
+ line 409, "pan.___", state 573, "(1)"
+ line 407, "pan.___", state 578, "((i<1))"
+ line 407, "pan.___", state 578, "((i>=1))"
+ line 414, "pan.___", state 584, "cache_dirty_rcu_ptr = 0"
+ line 414, "pan.___", state 586, "(1)"
+ line 414, "pan.___", state 587, "(cache_dirty_rcu_ptr)"
+ line 414, "pan.___", state 587, "else"
+ line 414, "pan.___", state 590, "(1)"
+ line 414, "pan.___", state 591, "(1)"
+ line 414, "pan.___", state 591, "(1)"
+ line 418, "pan.___", state 598, "cache_dirty_rcu_data[i] = 0"
+ line 418, "pan.___", state 600, "(1)"
+ line 418, "pan.___", state 601, "(cache_dirty_rcu_data[i])"
+ line 418, "pan.___", state 601, "else"
+ line 418, "pan.___", state 604, "(1)"
+ line 418, "pan.___", state 605, "(1)"
+ line 418, "pan.___", state 605, "(1)"
+ line 416, "pan.___", state 610, "((i<2))"
+ line 416, "pan.___", state 610, "((i>=2))"
+ line 423, "pan.___", state 617, "(1)"
+ line 423, "pan.___", state 618, "(!(cache_dirty_urcu_gp_ctr))"
+ line 423, "pan.___", state 618, "else"
+ line 423, "pan.___", state 621, "(1)"
+ line 423, "pan.___", state 622, "(1)"
+ line 423, "pan.___", state 622, "(1)"
+ line 427, "pan.___", state 630, "(1)"
+ line 427, "pan.___", state 631, "(!(cache_dirty_urcu_active_readers))"
+ line 427, "pan.___", state 631, "else"
+ line 427, "pan.___", state 634, "(1)"
+ line 427, "pan.___", state 635, "(1)"
+ line 427, "pan.___", state 635, "(1)"
+ line 425, "pan.___", state 640, "((i<1))"
+ line 425, "pan.___", state 640, "((i>=1))"
+ line 432, "pan.___", state 647, "(1)"
+ line 432, "pan.___", state 648, "(!(cache_dirty_rcu_ptr))"
+ line 432, "pan.___", state 648, "else"
+ line 432, "pan.___", state 651, "(1)"
+ line 432, "pan.___", state 652, "(1)"
+ line 432, "pan.___", state 652, "(1)"
+ line 436, "pan.___", state 660, "(1)"
+ line 436, "pan.___", state 661, "(!(cache_dirty_rcu_data[i]))"
+ line 436, "pan.___", state 661, "else"
+ line 436, "pan.___", state 664, "(1)"
+ line 436, "pan.___", state 665, "(1)"
+ line 436, "pan.___", state 665, "(1)"
+ line 434, "pan.___", state 670, "((i<2))"
+ line 434, "pan.___", state 670, "((i>=2))"
+ line 444, "pan.___", state 674, "(1)"
+ line 444, "pan.___", state 674, "(1)"
+ line 615, "pan.___", state 677, "cached_urcu_active_readers = (tmp+1)"
+ line 615, "pan.___", state 678, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 615, "pan.___", state 679, "(1)"
+ line 405, "pan.___", state 686, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 718, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 732, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 751, "(1)"
+ line 432, "pan.___", state 781, "(1)"
+ line 436, "pan.___", state 794, "(1)"
+ line 405, "pan.___", state 821, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 853, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 867, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 886, "(1)"
+ line 432, "pan.___", state 916, "(1)"
+ line 436, "pan.___", state 929, "(1)"
+ line 405, "pan.___", state 950, "cache_dirty_urcu_gp_ctr = 0"
+ line 414, "pan.___", state 982, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 996, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 1015, "(1)"
+ line 432, "pan.___", state 1045, "(1)"
+ line 436, "pan.___", state 1058, "(1)"
+ line 246, "pan.___", state 1091, "(1)"
+ line 254, "pan.___", state 1111, "(1)"
+ line 258, "pan.___", state 1119, "(1)"
+ line 749, "pan.___", state 1136, "-end-"
+ (91 of 1136 states)
+unreached in proctype urcu_writer
+ line 405, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 409, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 423, "pan.___", state 110, "(1)"
+ line 427, "pan.___", state 123, "(1)"
+ line 432, "pan.___", state 140, "(1)"
+ line 269, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 405, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 409, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 423, "pan.___", state 303, "(1)"
+ line 427, "pan.___", state 316, "(1)"
+ line 432, "pan.___", state 333, "(1)"
+ line 436, "pan.___", state 346, "(1)"
+ line 409, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 427, "pan.___", state 447, "(1)"
+ line 432, "pan.___", state 464, "(1)"
+ line 436, "pan.___", state 477, "(1)"
+ line 405, "pan.___", state 504, "cache_dirty_urcu_gp_ctr = 0"
+ line 405, "pan.___", state 506, "(1)"
+ line 405, "pan.___", state 507, "(cache_dirty_urcu_gp_ctr)"
+ line 405, "pan.___", state 507, "else"
+ line 405, "pan.___", state 510, "(1)"
+ line 409, "pan.___", state 518, "cache_dirty_urcu_active_readers = 0"
+ line 409, "pan.___", state 520, "(1)"
+ line 409, "pan.___", state 521, "(cache_dirty_urcu_active_readers)"
+ line 409, "pan.___", state 521, "else"
+ line 409, "pan.___", state 524, "(1)"
+ line 409, "pan.___", state 525, "(1)"
+ line 409, "pan.___", state 525, "(1)"
+ line 407, "pan.___", state 530, "((i<1))"
+ line 407, "pan.___", state 530, "((i>=1))"
+ line 414, "pan.___", state 536, "cache_dirty_rcu_ptr = 0"
+ line 414, "pan.___", state 538, "(1)"
+ line 414, "pan.___", state 539, "(cache_dirty_rcu_ptr)"
+ line 414, "pan.___", state 539, "else"
+ line 414, "pan.___", state 542, "(1)"
+ line 414, "pan.___", state 543, "(1)"
+ line 414, "pan.___", state 543, "(1)"
+ line 418, "pan.___", state 550, "cache_dirty_rcu_data[i] = 0"
+ line 418, "pan.___", state 552, "(1)"
+ line 418, "pan.___", state 553, "(cache_dirty_rcu_data[i])"
+ line 418, "pan.___", state 553, "else"
+ line 418, "pan.___", state 556, "(1)"
+ line 418, "pan.___", state 557, "(1)"
+ line 418, "pan.___", state 557, "(1)"
+ line 416, "pan.___", state 562, "((i<2))"
+ line 416, "pan.___", state 562, "((i>=2))"
+ line 423, "pan.___", state 569, "(1)"
+ line 423, "pan.___", state 570, "(!(cache_dirty_urcu_gp_ctr))"
+ line 423, "pan.___", state 570, "else"
+ line 423, "pan.___", state 573, "(1)"
+ line 423, "pan.___", state 574, "(1)"
+ line 423, "pan.___", state 574, "(1)"
+ line 427, "pan.___", state 582, "(1)"
+ line 427, "pan.___", state 583, "(!(cache_dirty_urcu_active_readers))"
+ line 427, "pan.___", state 583, "else"
+ line 427, "pan.___", state 586, "(1)"
+ line 427, "pan.___", state 587, "(1)"
+ line 427, "pan.___", state 587, "(1)"
+ line 425, "pan.___", state 592, "((i<1))"
+ line 425, "pan.___", state 592, "((i>=1))"
+ line 432, "pan.___", state 599, "(1)"
+ line 432, "pan.___", state 600, "(!(cache_dirty_rcu_ptr))"
+ line 432, "pan.___", state 600, "else"
+ line 432, "pan.___", state 603, "(1)"
+ line 432, "pan.___", state 604, "(1)"
+ line 432, "pan.___", state 604, "(1)"
+ line 436, "pan.___", state 612, "(1)"
+ line 436, "pan.___", state 613, "(!(cache_dirty_rcu_data[i]))"
+ line 436, "pan.___", state 613, "else"
+ line 436, "pan.___", state 616, "(1)"
+ line 436, "pan.___", state 617, "(1)"
+ line 436, "pan.___", state 617, "(1)"
+ line 444, "pan.___", state 626, "(1)"
+ line 444, "pan.___", state 626, "(1)"
+ line 409, "pan.___", state 646, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 664, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 678, "cache_dirty_rcu_data[i] = 0"
+ line 427, "pan.___", state 710, "(1)"
+ line 432, "pan.___", state 727, "(1)"
+ line 436, "pan.___", state 740, "(1)"
+ line 409, "pan.___", state 775, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 793, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 807, "cache_dirty_rcu_data[i] = 0"
+ line 427, "pan.___", state 839, "(1)"
+ line 432, "pan.___", state 856, "(1)"
+ line 436, "pan.___", state 869, "(1)"
+ line 409, "pan.___", state 906, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 924, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 938, "cache_dirty_rcu_data[i] = 0"
+ line 427, "pan.___", state 970, "(1)"
+ line 432, "pan.___", state 987, "(1)"
+ line 436, "pan.___", state 1000, "(1)"
+ line 409, "pan.___", state 1040, "cache_dirty_urcu_active_readers = 0"
+ line 414, "pan.___", state 1058, "cache_dirty_rcu_ptr = 0"
+ line 418, "pan.___", state 1072, "cache_dirty_rcu_data[i] = 0"
+ line 427, "pan.___", state 1104, "(1)"
+ line 432, "pan.___", state 1121, "(1)"
+ line 436, "pan.___", state 1134, "(1)"
+ line 269, "pan.___", state 1180, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1189, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1204, "(1)"
+ line 281, "pan.___", state 1211, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1227, "(1)"
+ line 250, "pan.___", state 1235, "(1)"
+ line 254, "pan.___", state 1247, "(1)"
+ line 258, "pan.___", state 1255, "(1)"
+ line 269, "pan.___", state 1286, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1295, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1308, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1317, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1333, "(1)"
+ line 250, "pan.___", state 1341, "(1)"
+ line 254, "pan.___", state 1353, "(1)"
+ line 258, "pan.___", state 1361, "(1)"
+ line 273, "pan.___", state 1387, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1400, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1409, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1425, "(1)"
+ line 250, "pan.___", state 1433, "(1)"
+ line 254, "pan.___", state 1445, "(1)"
+ line 258, "pan.___", state 1453, "(1)"
+ line 269, "pan.___", state 1484, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1493, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1506, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1515, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1531, "(1)"
+ line 250, "pan.___", state 1539, "(1)"
+ line 254, "pan.___", state 1551, "(1)"
+ line 258, "pan.___", state 1559, "(1)"
+ line 1124, "pan.___", state 1575, "-end-"
+ (118 of 1575 states)
+unreached in proctype :init:
+ (0 of 26 states)
+unreached in proctype :never:
+ line 1187, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 67.7 seconds
+pan: rate 3447.2308 states/second
+pan: avg transition delay 1.5577e-06 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-min-progress'
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN, READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_OUT)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE
+ | READ_LOCK_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN
+ | READ_UNLOCK_OUT, 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ data_read_first[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64 -DCOLLAPSE
+#CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ make urcu_free | tee urcu_free.log
+ make urcu_free_no_mb | tee urcu_free_no_mb.log
+ make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ make urcu_free_single_flip | tee urcu_free_single_flip.log
+ #state-space over 14gb..
+ #make urcu_progress_writer | tee urcu_progress_writer.log
+ #make urcu_progress_reader | tee urcu_progress_reader.log
+ #make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth= 6176 States= 1e+06 Transitions= 1.77e+08 Memory= 497.600 t= 218 R= 5e+03
+Depth= 7720 States= 2e+06 Transitions= 3.71e+08 Memory= 528.654 t= 474 R= 4e+03
+Depth= 7720 States= 3e+06 Transitions= 5.8e+08 Memory= 561.955 t= 768 R= 4e+03
+pan: resizing hashtable to -w22.. done
+Depth= 7720 States= 4e+06 Transitions= 7.6e+08 Memory= 627.549 t= 999 R= 4e+03
+Depth= 7720 States= 5e+06 Transitions= 9.44e+08 Memory= 662.217 t= 1.24e+03 R= 4e+03
+Depth= 7720 States= 6e+06 Transitions= 1.35e+09 Memory= 699.619 t= 1.79e+03 R= 3e+03
+Depth= 7720 States= 7e+06 Transitions= 1.79e+09 Memory= 735.361 t= 2.39e+03 R= 3e+03
+Depth= 7720 States= 8e+06 Transitions= 2.11e+09 Memory= 773.545 t= 2.83e+03 R= 3e+03
+Depth= 7720 States= 9e+06 Transitions= 2.49e+09 Memory= 811.143 t= 3.37e+03 R= 3e+03
+pan: resizing hashtable to -w24.. done
+Depth= 7720 States= 1e+07 Transitions= 2.83e+09 Memory= 973.518 t= 3.8e+03 R= 3e+03
+Depth= 7720 States= 1.1e+07 Transitions= 3.2e+09 Memory= 1011.506 t= 4.27e+03 R= 3e+03
+Depth= 7720 States= 1.2e+07 Transitions= 3.59e+09 Memory= 1049.885 t= 4.78e+03 R= 3e+03
+Depth= 7720 States= 1.3e+07 Transitions= 3.81e+09 Memory= 1087.678 t= 5.06e+03 R= 3e+03
+Depth= 7720 States= 1.4e+07 Transitions= 4.12e+09 Memory= 1122.834 t= 5.46e+03 R= 3e+03
+Depth= 7720 States= 1.5e+07 Transitions= 4.35e+09 Memory= 1159.358 t= 5.75e+03 R= 3e+03
+Depth= 7720 States= 1.6e+07 Transitions= 4.88e+09 Memory= 1195.783 t= 6.46e+03 R= 2e+03
+Depth= 7720 States= 1.7e+07 Transitions= 5.67e+09 Memory= 1231.721 t= 7.51e+03 R= 2e+03
+Depth= 7720 States= 1.8e+07 Transitions= 6.31e+09 Memory= 1268.537 t= 8.37e+03 R= 2e+03
+Depth= 7720 States= 1.9e+07 Transitions= 6.77e+09 Memory= 1306.526 t= 8.98e+03 R= 2e+03
+Depth= 7720 States= 2e+07 Transitions= 7.09e+09 Memory= 1345.393 t= 9.41e+03 R= 2e+03
+Depth= 7720 States= 2.1e+07 Transitions= 7.48e+09 Memory= 1383.576 t= 9.93e+03 R= 2e+03
+Depth= 7720 States= 2.2e+07 Transitions= 7.94e+09 Memory= 1421.955 t= 1.06e+04 R= 2e+03
+Depth= 7720 States= 2.3e+07 Transitions= 8.37e+09 Memory= 1459.846 t= 1.11e+04 R= 2e+03
+Depth= 7720 States= 2.4e+07 Transitions= 8.77e+09 Memory= 1497.346 t= 1.17e+04 R= 2e+03
+Depth= 7720 States= 2.5e+07 Transitions= 9.22e+09 Memory= 1535.529 t= 1.23e+04 R= 2e+03
+Depth= 7720 States= 2.6e+07 Transitions= 9.48e+09 Memory= 1574.006 t= 1.26e+04 R= 2e+03
+Depth= 7720 States= 2.7e+07 Transitions= 9.85e+09 Memory= 1612.385 t= 1.31e+04 R= 2e+03
+Depth= 7720 States= 2.8e+07 Transitions= 1.02e+10 Memory= 1650.666 t= 1.37e+04 R= 2e+03
+Depth= 7940 States= 2.9e+07 Transitions= 1.06e+10 Memory= 1688.752 t= 1.41e+04 R= 2e+03
+Depth= 7998 States= 3e+07 Transitions= 1.09e+10 Memory= 1726.936 t= 1.46e+04 R= 2e+03
+Depth= 7998 States= 3.1e+07 Transitions= 1.13e+10 Memory= 1765.315 t= 1.51e+04 R= 2e+03
+Depth= 7998 States= 3.2e+07 Transitions= 1.16e+10 Memory= 1803.498 t= 1.55e+04 R= 2e+03
+Depth= 7998 States= 3.3e+07 Transitions= 1.19e+10 Memory= 1841.682 t= 1.6e+04 R= 2e+03
+Depth= 7998 States= 3.4e+07 Transitions= 1.23e+10 Memory= 1879.963 t= 1.65e+04 R= 2e+03
+pan: resizing hashtable to -w26.. done
+Depth= 7998 States= 3.5e+07 Transitions= 1.26e+10 Memory= 2414.131 t= 1.69e+04 R= 2e+03
+Depth= 7998 States= 3.6e+07 Transitions= 1.29e+10 Memory= 2452.315 t= 1.73e+04 R= 2e+03
+Depth= 7998 States= 3.7e+07 Transitions= 1.32e+10 Memory= 2490.498 t= 1.77e+04 R= 2e+03
+Depth= 7998 States= 3.8e+07 Transitions= 1.35e+10 Memory= 2528.584 t= 1.82e+04 R= 2e+03
+Depth= 7998 States= 3.9e+07 Transitions= 1.39e+10 Memory= 2566.768 t= 1.86e+04 R= 2e+03
+Depth= 7998 States= 4e+07 Transitions= 1.41e+10 Memory= 2604.951 t= 1.89e+04 R= 2e+03
+Depth= 7998 States= 4.1e+07 Transitions= 1.44e+10 Memory= 2643.135 t= 1.93e+04 R= 2e+03
+Depth= 7998 States= 4.2e+07 Transitions= 1.48e+10 Memory= 2682.002 t= 1.98e+04 R= 2e+03
+Depth= 7998 States= 4.3e+07 Transitions= 1.51e+10 Memory= 2720.283 t= 2.03e+04 R= 2e+03
+Depth= 7998 States= 4.4e+07 Transitions= 1.56e+10 Memory= 2759.053 t= 2.09e+04 R= 2e+03
+Depth= 7998 States= 4.5e+07 Transitions= 1.59e+10 Memory= 2797.432 t= 2.13e+04 R= 2e+03
+Depth= 7998 States= 4.6e+07 Transitions= 1.64e+10 Memory= 2836.201 t= 2.19e+04 R= 2e+03
+Depth= 7998 States= 4.7e+07 Transitions= 1.68e+10 Memory= 2875.068 t= 2.24e+04 R= 2e+03
+Depth= 7998 States= 4.8e+07 Transitions= 1.72e+10 Memory= 2913.643 t= 2.29e+04 R= 2e+03
+Depth= 7998 States= 4.9e+07 Transitions= 1.76e+10 Memory= 2952.412 t= 2.34e+04 R= 2e+03
+Depth= 7998 States= 5e+07 Transitions= 1.78e+10 Memory= 2989.619 t= 2.38e+04 R= 2e+03
+Depth= 7998 States= 5.1e+07 Transitions= 1.81e+10 Memory= 3027.901 t= 2.42e+04 R= 2e+03
+Depth= 7998 States= 5.2e+07 Transitions= 1.84e+10 Memory= 3066.279 t= 2.46e+04 R= 2e+03
+Depth= 7998 States= 5.3e+07 Transitions= 1.87e+10 Memory= 3104.463 t= 2.49e+04 R= 2e+03
+Depth= 7998 States= 5.4e+07 Transitions= 1.93e+10 Memory= 3142.842 t= 2.57e+04 R= 2e+03
+Depth= 7998 States= 5.5e+07 Transitions= 2.01e+10 Memory= 3181.026 t= 2.68e+04 R= 2e+03
+Depth= 7998 States= 5.6e+07 Transitions= 2.07e+10 Memory= 3219.990 t= 2.76e+04 R= 2e+03
+Depth= 7998 States= 5.7e+07 Transitions= 2.11e+10 Memory= 3258.467 t= 2.82e+04 R= 2e+03
+Depth= 7998 States= 5.8e+07 Transitions= 2.15e+10 Memory= 3297.236 t= 2.87e+04 R= 2e+03
+Depth= 7998 States= 5.9e+07 Transitions= 2.18e+10 Memory= 3334.151 t= 2.91e+04 R= 2e+03
+Depth= 7998 States= 6e+07 Transitions= 2.22e+10 Memory= 3372.432 t= 2.97e+04 R= 2e+03
+Depth= 7998 States= 6.1e+07 Transitions= 2.27e+10 Memory= 3410.713 t= 3.03e+04 R= 2e+03
+Depth= 7998 States= 6.2e+07 Transitions= 2.32e+10 Memory= 3448.701 t= 3.09e+04 R= 2e+03
+Depth= 7998 States= 6.3e+07 Transitions= 2.35e+10 Memory= 3485.615 t= 3.15e+04 R= 2e+03
+Depth= 7998 States= 6.4e+07 Transitions= 2.38e+10 Memory= 3523.604 t= 3.19e+04 R= 2e+03
+Depth= 7998 States= 6.5e+07 Transitions= 2.42e+10 Memory= 3561.690 t= 3.23e+04 R= 2e+03
+Depth= 7998 States= 6.6e+07 Transitions= 2.46e+10 Memory= 3598.799 t= 3.28e+04 R= 2e+03
+Depth= 7998 States= 6.7e+07 Transitions= 2.49e+10 Memory= 3635.225 t= 3.33e+04 R= 2e+03
+Depth= 7998 States= 6.8e+07 Transitions= 2.53e+10 Memory= 3672.139 t= 3.38e+04 R= 2e+03
+Depth= 7998 States= 6.9e+07 Transitions= 2.56e+10 Memory= 3706.807 t= 3.42e+04 R= 2e+03
+Depth= 7998 States= 7e+07 Transitions= 2.59e+10 Memory= 3743.916 t= 3.47e+04 R= 2e+03
+Depth= 7998 States= 7.1e+07 Transitions= 2.62e+10 Memory= 3781.026 t= 3.51e+04 R= 2e+03
+Depth= 7998 States= 7.2e+07 Transitions= 2.66e+10 Memory= 3818.721 t= 3.56e+04 R= 2e+03
+Depth= 7998 States= 7.3e+07 Transitions= 2.68e+10 Memory= 3855.244 t= 3.59e+04 R= 2e+03
+Depth= 7998 States= 7.4e+07 Transitions= 2.72e+10 Memory= 3892.647 t= 3.64e+04 R= 2e+03
+Depth= 7998 States= 7.5e+07 Transitions= 2.76e+10 Memory= 3930.049 t= 3.69e+04 R= 2e+03
+Depth= 7998 States= 7.6e+07 Transitions= 2.78e+10 Memory= 3966.963 t= 3.72e+04 R= 2e+03
+Depth= 7998 States= 7.7e+07 Transitions= 2.81e+10 Memory= 4003.975 t= 3.77e+04 R= 2e+03
+Depth= 7998 States= 7.8e+07 Transitions= 2.84e+10 Memory= 4041.084 t= 3.8e+04 R= 2e+03
+Depth= 7998 States= 7.9e+07 Transitions= 2.87e+10 Memory= 4078.584 t= 3.84e+04 R= 2e+03
+Depth= 7998 States= 8e+07 Transitions= 2.91e+10 Memory= 4114.815 t= 3.9e+04 R= 2e+03
+Depth= 7998 States= 8.1e+07 Transitions= 2.95e+10 Memory= 4151.240 t= 3.95e+04 R= 2e+03
+Depth= 7998 States= 8.2e+07 Transitions= 2.99e+10 Memory= 4189.131 t= 4e+04 R= 2e+03
+Depth= 7998 States= 8.3e+07 Transitions= 3.03e+10 Memory= 4226.533 t= 4.06e+04 R= 2e+03
+Depth= 7998 States= 8.4e+07 Transitions= 3.07e+10 Memory= 4264.912 t= 4.11e+04 R= 2e+03
+Depth= 7998 States= 8.5e+07 Transitions= 3.11e+10 Memory= 4302.998 t= 4.16e+04 R= 2e+03
+Depth= 7998 States= 8.6e+07 Transitions= 3.15e+10 Memory= 4340.693 t= 4.21e+04 R= 2e+03
+Depth= 7998 States= 8.7e+07 Transitions= 3.19e+10 Memory= 4378.877 t= 4.27e+04 R= 2e+03
+Depth= 7998 States= 8.8e+07 Transitions= 3.23e+10 Memory= 4417.061 t= 4.32e+04 R= 2e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim - (none specified)
+ assertion violations +
+ cycle checks - (disabled by -DSAFETY)
+ invalid end states +
+
+State-vector 72 byte, depth reached 7998, errors: 0
+ 88716525 states, stored
+3.2432758e+10 states, matched
+3.2521475e+10 transitions (= stored+matched)
+1.8325967e+11 atomic steps
+hash conflicts: 1.7127982e+10 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 8460.667 equivalent memory usage for states (stored*(State-vector + overhead))
+ 3474.757 actual memory usage for states (compression: 41.07%)
+ state-vector as stored = 13 byte + 28 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 4444.111 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 606546 5194 3779 2 ]
+unreached in proctype urcu_reader
+ line 267, ".input.spin", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 275, ".input.spin", state 79, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 104, "(1)"
+ line 248, ".input.spin", state 112, "(1)"
+ line 252, ".input.spin", state 124, "(1)"
+ line 256, ".input.spin", state 132, "(1)"
+ line 406, ".input.spin", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 190, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 223, "(1)"
+ line 433, ".input.spin", state 253, "(1)"
+ line 437, ".input.spin", state 266, "(1)"
+ line 686, ".input.spin", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 406, ".input.spin", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 326, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 359, "(1)"
+ line 433, ".input.spin", state 389, "(1)"
+ line 437, ".input.spin", state 402, "(1)"
+ line 406, ".input.spin", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 455, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 488, "(1)"
+ line 433, ".input.spin", state 518, "(1)"
+ line 437, ".input.spin", state 531, "(1)"
+ line 406, ".input.spin", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, ".input.spin", state 556, "(1)"
+ line 406, ".input.spin", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 406, ".input.spin", state 557, "else"
+ line 406, ".input.spin", state 560, "(1)"
+ line 410, ".input.spin", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 410, ".input.spin", state 570, "(1)"
+ line 410, ".input.spin", state 571, "(cache_dirty_urcu_active_readers)"
+ line 410, ".input.spin", state 571, "else"
+ line 410, ".input.spin", state 574, "(1)"
+ line 410, ".input.spin", state 575, "(1)"
+ line 410, ".input.spin", state 575, "(1)"
+ line 408, ".input.spin", state 580, "((i<1))"
+ line 408, ".input.spin", state 580, "((i>=1))"
+ line 415, ".input.spin", state 586, "cache_dirty_rcu_ptr = 0"
+ line 415, ".input.spin", state 588, "(1)"
+ line 415, ".input.spin", state 589, "(cache_dirty_rcu_ptr)"
+ line 415, ".input.spin", state 589, "else"
+ line 415, ".input.spin", state 592, "(1)"
+ line 415, ".input.spin", state 593, "(1)"
+ line 415, ".input.spin", state 593, "(1)"
+ line 419, ".input.spin", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 419, ".input.spin", state 602, "(1)"
+ line 419, ".input.spin", state 603, "(cache_dirty_rcu_data[i])"
+ line 419, ".input.spin", state 603, "else"
+ line 419, ".input.spin", state 606, "(1)"
+ line 419, ".input.spin", state 607, "(1)"
+ line 419, ".input.spin", state 607, "(1)"
+ line 417, ".input.spin", state 612, "((i<2))"
+ line 417, ".input.spin", state 612, "((i>=2))"
+ line 424, ".input.spin", state 619, "(1)"
+ line 424, ".input.spin", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, ".input.spin", state 620, "else"
+ line 424, ".input.spin", state 623, "(1)"
+ line 424, ".input.spin", state 624, "(1)"
+ line 424, ".input.spin", state 624, "(1)"
+ line 428, ".input.spin", state 632, "(1)"
+ line 428, ".input.spin", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 428, ".input.spin", state 633, "else"
+ line 428, ".input.spin", state 636, "(1)"
+ line 428, ".input.spin", state 637, "(1)"
+ line 428, ".input.spin", state 637, "(1)"
+ line 426, ".input.spin", state 642, "((i<1))"
+ line 426, ".input.spin", state 642, "((i>=1))"
+ line 433, ".input.spin", state 649, "(1)"
+ line 433, ".input.spin", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 433, ".input.spin", state 650, "else"
+ line 433, ".input.spin", state 653, "(1)"
+ line 433, ".input.spin", state 654, "(1)"
+ line 433, ".input.spin", state 654, "(1)"
+ line 437, ".input.spin", state 662, "(1)"
+ line 437, ".input.spin", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 437, ".input.spin", state 663, "else"
+ line 437, ".input.spin", state 666, "(1)"
+ line 437, ".input.spin", state 667, "(1)"
+ line 437, ".input.spin", state 667, "(1)"
+ line 435, ".input.spin", state 672, "((i<2))"
+ line 435, ".input.spin", state 672, "((i>=2))"
+ line 445, ".input.spin", state 676, "(1)"
+ line 445, ".input.spin", state 676, "(1)"
+ line 686, ".input.spin", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 686, ".input.spin", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 686, ".input.spin", state 681, "(1)"
+ line 406, ".input.spin", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 720, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 753, "(1)"
+ line 433, ".input.spin", state 783, "(1)"
+ line 437, ".input.spin", state 796, "(1)"
+ line 406, ".input.spin", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 856, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 889, "(1)"
+ line 433, ".input.spin", state 919, "(1)"
+ line 437, ".input.spin", state 932, "(1)"
+ line 406, ".input.spin", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, ".input.spin", state 955, "(1)"
+ line 406, ".input.spin", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 406, ".input.spin", state 956, "else"
+ line 406, ".input.spin", state 959, "(1)"
+ line 410, ".input.spin", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 410, ".input.spin", state 969, "(1)"
+ line 410, ".input.spin", state 970, "(cache_dirty_urcu_active_readers)"
+ line 410, ".input.spin", state 970, "else"
+ line 410, ".input.spin", state 973, "(1)"
+ line 410, ".input.spin", state 974, "(1)"
+ line 410, ".input.spin", state 974, "(1)"
+ line 408, ".input.spin", state 979, "((i<1))"
+ line 408, ".input.spin", state 979, "((i>=1))"
+ line 415, ".input.spin", state 985, "cache_dirty_rcu_ptr = 0"
+ line 415, ".input.spin", state 987, "(1)"
+ line 415, ".input.spin", state 988, "(cache_dirty_rcu_ptr)"
+ line 415, ".input.spin", state 988, "else"
+ line 415, ".input.spin", state 991, "(1)"
+ line 415, ".input.spin", state 992, "(1)"
+ line 415, ".input.spin", state 992, "(1)"
+ line 419, ".input.spin", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 419, ".input.spin", state 1001, "(1)"
+ line 419, ".input.spin", state 1002, "(cache_dirty_rcu_data[i])"
+ line 419, ".input.spin", state 1002, "else"
+ line 419, ".input.spin", state 1005, "(1)"
+ line 419, ".input.spin", state 1006, "(1)"
+ line 419, ".input.spin", state 1006, "(1)"
+ line 417, ".input.spin", state 1011, "((i<2))"
+ line 417, ".input.spin", state 1011, "((i>=2))"
+ line 424, ".input.spin", state 1018, "(1)"
+ line 424, ".input.spin", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, ".input.spin", state 1019, "else"
+ line 424, ".input.spin", state 1022, "(1)"
+ line 424, ".input.spin", state 1023, "(1)"
+ line 424, ".input.spin", state 1023, "(1)"
+ line 428, ".input.spin", state 1031, "(1)"
+ line 428, ".input.spin", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 428, ".input.spin", state 1032, "else"
+ line 428, ".input.spin", state 1035, "(1)"
+ line 428, ".input.spin", state 1036, "(1)"
+ line 428, ".input.spin", state 1036, "(1)"
+ line 426, ".input.spin", state 1041, "((i<1))"
+ line 426, ".input.spin", state 1041, "((i>=1))"
+ line 433, ".input.spin", state 1048, "(1)"
+ line 433, ".input.spin", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 433, ".input.spin", state 1049, "else"
+ line 433, ".input.spin", state 1052, "(1)"
+ line 433, ".input.spin", state 1053, "(1)"
+ line 433, ".input.spin", state 1053, "(1)"
+ line 437, ".input.spin", state 1061, "(1)"
+ line 437, ".input.spin", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 437, ".input.spin", state 1062, "else"
+ line 437, ".input.spin", state 1065, "(1)"
+ line 437, ".input.spin", state 1066, "(1)"
+ line 437, ".input.spin", state 1066, "(1)"
+ line 435, ".input.spin", state 1071, "((i<2))"
+ line 435, ".input.spin", state 1071, "((i>=2))"
+ line 445, ".input.spin", state 1075, "(1)"
+ line 445, ".input.spin", state 1075, "(1)"
+ line 694, ".input.spin", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 406, ".input.spin", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1149, "(1)"
+ line 433, ".input.spin", state 1179, "(1)"
+ line 437, ".input.spin", state 1192, "(1)"
+ line 406, ".input.spin", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1281, "(1)"
+ line 433, ".input.spin", state 1311, "(1)"
+ line 437, ".input.spin", state 1324, "(1)"
+ line 406, ".input.spin", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1414, "(1)"
+ line 433, ".input.spin", state 1444, "(1)"
+ line 437, ".input.spin", state 1457, "(1)"
+ line 406, ".input.spin", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1543, "(1)"
+ line 433, ".input.spin", state 1573, "(1)"
+ line 437, ".input.spin", state 1586, "(1)"
+ line 406, ".input.spin", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1677, "(1)"
+ line 433, ".input.spin", state 1707, "(1)"
+ line 437, ".input.spin", state 1720, "(1)"
+ line 406, ".input.spin", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1806, "(1)"
+ line 433, ".input.spin", state 1836, "(1)"
+ line 437, ".input.spin", state 1849, "(1)"
+ line 406, ".input.spin", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 1938, "(1)"
+ line 433, ".input.spin", state 1968, "(1)"
+ line 437, ".input.spin", state 1981, "(1)"
+ line 733, ".input.spin", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 406, ".input.spin", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 2074, "(1)"
+ line 433, ".input.spin", state 2104, "(1)"
+ line 437, ".input.spin", state 2117, "(1)"
+ line 406, ".input.spin", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 2203, "(1)"
+ line 433, ".input.spin", state 2233, "(1)"
+ line 437, ".input.spin", state 2246, "(1)"
+ line 406, ".input.spin", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, ".input.spin", state 2271, "(1)"
+ line 406, ".input.spin", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 406, ".input.spin", state 2272, "else"
+ line 406, ".input.spin", state 2275, "(1)"
+ line 410, ".input.spin", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 410, ".input.spin", state 2285, "(1)"
+ line 410, ".input.spin", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 410, ".input.spin", state 2286, "else"
+ line 410, ".input.spin", state 2289, "(1)"
+ line 410, ".input.spin", state 2290, "(1)"
+ line 410, ".input.spin", state 2290, "(1)"
+ line 408, ".input.spin", state 2295, "((i<1))"
+ line 408, ".input.spin", state 2295, "((i>=1))"
+ line 415, ".input.spin", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 415, ".input.spin", state 2303, "(1)"
+ line 415, ".input.spin", state 2304, "(cache_dirty_rcu_ptr)"
+ line 415, ".input.spin", state 2304, "else"
+ line 415, ".input.spin", state 2307, "(1)"
+ line 415, ".input.spin", state 2308, "(1)"
+ line 415, ".input.spin", state 2308, "(1)"
+ line 419, ".input.spin", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 419, ".input.spin", state 2317, "(1)"
+ line 419, ".input.spin", state 2318, "(cache_dirty_rcu_data[i])"
+ line 419, ".input.spin", state 2318, "else"
+ line 419, ".input.spin", state 2321, "(1)"
+ line 419, ".input.spin", state 2322, "(1)"
+ line 419, ".input.spin", state 2322, "(1)"
+ line 417, ".input.spin", state 2327, "((i<2))"
+ line 417, ".input.spin", state 2327, "((i>=2))"
+ line 424, ".input.spin", state 2334, "(1)"
+ line 424, ".input.spin", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, ".input.spin", state 2335, "else"
+ line 424, ".input.spin", state 2338, "(1)"
+ line 424, ".input.spin", state 2339, "(1)"
+ line 424, ".input.spin", state 2339, "(1)"
+ line 428, ".input.spin", state 2347, "(1)"
+ line 428, ".input.spin", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 428, ".input.spin", state 2348, "else"
+ line 428, ".input.spin", state 2351, "(1)"
+ line 428, ".input.spin", state 2352, "(1)"
+ line 428, ".input.spin", state 2352, "(1)"
+ line 426, ".input.spin", state 2357, "((i<1))"
+ line 426, ".input.spin", state 2357, "((i>=1))"
+ line 433, ".input.spin", state 2364, "(1)"
+ line 433, ".input.spin", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 433, ".input.spin", state 2365, "else"
+ line 433, ".input.spin", state 2368, "(1)"
+ line 433, ".input.spin", state 2369, "(1)"
+ line 433, ".input.spin", state 2369, "(1)"
+ line 437, ".input.spin", state 2377, "(1)"
+ line 437, ".input.spin", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 437, ".input.spin", state 2378, "else"
+ line 437, ".input.spin", state 2381, "(1)"
+ line 437, ".input.spin", state 2382, "(1)"
+ line 437, ".input.spin", state 2382, "(1)"
+ line 435, ".input.spin", state 2387, "((i<2))"
+ line 435, ".input.spin", state 2387, "((i>=2))"
+ line 445, ".input.spin", state 2391, "(1)"
+ line 445, ".input.spin", state 2391, "(1)"
+ line 733, ".input.spin", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 733, ".input.spin", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 733, ".input.spin", state 2396, "(1)"
+ line 406, ".input.spin", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 2468, "(1)"
+ line 433, ".input.spin", state 2498, "(1)"
+ line 437, ".input.spin", state 2511, "(1)"
+ line 406, ".input.spin", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 2603, "(1)"
+ line 433, ".input.spin", state 2633, "(1)"
+ line 437, ".input.spin", state 2646, "(1)"
+ line 406, ".input.spin", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, ".input.spin", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 2732, "(1)"
+ line 433, ".input.spin", state 2762, "(1)"
+ line 437, ".input.spin", state 2775, "(1)"
+ line 244, ".input.spin", state 2808, "(1)"
+ line 252, ".input.spin", state 2828, "(1)"
+ line 256, ".input.spin", state 2836, "(1)"
+ line 244, ".input.spin", state 2851, "(1)"
+ line 252, ".input.spin", state 2871, "(1)"
+ line 256, ".input.spin", state 2879, "(1)"
+ line 928, ".input.spin", state 2896, "-end-"
+ (245 of 2896 states)
+unreached in proctype urcu_writer
+ line 406, ".input.spin", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 410, ".input.spin", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 77, "cache_dirty_rcu_ptr = 0"
+ line 424, ".input.spin", state 110, "(1)"
+ line 428, ".input.spin", state 123, "(1)"
+ line 433, ".input.spin", state 140, "(1)"
+ line 267, ".input.spin", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 198, "cache_dirty_rcu_ptr = 0"
+ line 406, ".input.spin", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 410, ".input.spin", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 270, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 424, ".input.spin", state 303, "(1)"
+ line 428, ".input.spin", state 316, "(1)"
+ line 433, ".input.spin", state 333, "(1)"
+ line 437, ".input.spin", state 346, "(1)"
+ line 410, ".input.spin", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 401, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 428, ".input.spin", state 447, "(1)"
+ line 433, ".input.spin", state 464, "(1)"
+ line 437, ".input.spin", state 477, "(1)"
+ line 410, ".input.spin", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 540, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 428, ".input.spin", state 586, "(1)"
+ line 433, ".input.spin", state 603, "(1)"
+ line 437, ".input.spin", state 616, "(1)"
+ line 410, ".input.spin", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 669, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 428, ".input.spin", state 715, "(1)"
+ line 433, ".input.spin", state 732, "(1)"
+ line 437, ".input.spin", state 745, "(1)"
+ line 410, ".input.spin", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 415, ".input.spin", state 800, "cache_dirty_rcu_ptr = 0"
+ line 419, ".input.spin", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 428, ".input.spin", state 846, "(1)"
+ line 433, ".input.spin", state 863, "(1)"
+ line 437, ".input.spin", state 876, "(1)"
+ line 267, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 955, "(1)"
+ line 279, ".input.spin", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 978, "(1)"
+ line 248, ".input.spin", state 986, "(1)"
+ line 252, ".input.spin", state 998, "(1)"
+ line 256, ".input.spin", state 1006, "(1)"
+ line 267, ".input.spin", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1084, "(1)"
+ line 248, ".input.spin", state 1092, "(1)"
+ line 252, ".input.spin", state 1104, "(1)"
+ line 256, ".input.spin", state 1112, "(1)"
+ line 271, ".input.spin", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1176, "(1)"
+ line 248, ".input.spin", state 1184, "(1)"
+ line 252, ".input.spin", state 1196, "(1)"
+ line 256, ".input.spin", state 1204, "(1)"
+ line 267, ".input.spin", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1282, "(1)"
+ line 248, ".input.spin", state 1290, "(1)"
+ line 252, ".input.spin", state 1302, "(1)"
+ line 256, ".input.spin", state 1310, "(1)"
+ line 271, ".input.spin", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1374, "(1)"
+ line 248, ".input.spin", state 1382, "(1)"
+ line 252, ".input.spin", state 1394, "(1)"
+ line 256, ".input.spin", state 1402, "(1)"
+ line 267, ".input.spin", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1480, "(1)"
+ line 248, ".input.spin", state 1488, "(1)"
+ line 252, ".input.spin", state 1500, "(1)"
+ line 256, ".input.spin", state 1508, "(1)"
+ line 271, ".input.spin", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1572, "(1)"
+ line 248, ".input.spin", state 1580, "(1)"
+ line 252, ".input.spin", state 1592, "(1)"
+ line 256, ".input.spin", state 1600, "(1)"
+ line 267, ".input.spin", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, ".input.spin", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 275, ".input.spin", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 279, ".input.spin", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 244, ".input.spin", state 1678, "(1)"
+ line 248, ".input.spin", state 1686, "(1)"
+ line 252, ".input.spin", state 1698, "(1)"
+ line 256, ".input.spin", state 1706, "(1)"
+ line 1303, ".input.spin", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 28 states)
+
+pan: elapsed time 4.35e+04 seconds
+pan: rate 2039.1355 states/second
+pan: avg transition delay 1.3378e-06 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1361)
+Depth= 8053 States= 1e+06 Transitions= 1.77e+08 Memory= 513.029 t= 265 R= 4e+03
+Depth= 9797 States= 2e+06 Transitions= 3.71e+08 Memory= 559.416 t= 575 R= 3e+03
+Depth= 9797 States= 3e+06 Transitions= 5.8e+08 Memory= 605.901 t= 922 R= 3e+03
+pan: resizing hashtable to -w22.. done
+Depth= 9797 States= 4e+06 Transitions= 7.6e+08 Memory= 682.920 t= 1.2e+03 R= 3e+03
+Depth= 9797 States= 5e+06 Transitions= 9.44e+08 Memory= 728.721 t= 1.48e+03 R= 3e+03
+Depth= 9797 States= 6e+06 Transitions= 1.35e+09 Memory= 775.303 t= 2.13e+03 R= 3e+03
+Depth= 9797 States= 7e+06 Transitions= 1.79e+09 Memory= 821.885 t= 2.85e+03 R= 2e+03
+Depth= 9797 States= 8e+06 Transitions= 2.11e+09 Memory= 868.076 t= 3.36e+03 R= 2e+03
+Depth= 9797 States= 9e+06 Transitions= 2.49e+09 Memory= 914.658 t= 4.01e+03 R= 2e+03
+pan: resizing hashtable to -w24.. done
+Depth= 9797 States= 1e+07 Transitions= 2.83e+09 Memory= 1085.529 t= 4.52e+03 R= 2e+03
+Depth= 9797 States= 1.1e+07 Transitions= 3.2e+09 Memory= 1132.697 t= 5.08e+03 R= 2e+03
+Depth= 9797 States= 1.2e+07 Transitions= 3.59e+09 Memory= 1179.670 t= 5.69e+03 R= 2e+03
+Depth= 9797 States= 1.3e+07 Transitions= 3.81e+09 Memory= 1226.838 t= 6.03e+03 R= 2e+03
+Depth= 9797 States= 1.4e+07 Transitions= 4.12e+09 Memory= 1273.029 t= 6.5e+03 R= 2e+03
+Depth= 9797 States= 1.5e+07 Transitions= 4.35e+09 Memory= 1319.123 t= 6.85e+03 R= 2e+03
+Depth= 9797 States= 1.6e+07 Transitions= 4.88e+09 Memory= 1365.608 t= 7.7e+03 R= 2e+03
+Depth= 9797 States= 1.7e+07 Transitions= 5.67e+09 Memory= 1411.506 t= 8.95e+03 R= 2e+03
+Depth= 9797 States= 1.8e+07 Transitions= 6.31e+09 Memory= 1458.479 t= 9.98e+03 R= 2e+03
+Depth= 9797 States= 1.9e+07 Transitions= 6.77e+09 Memory= 1504.963 t= 1.07e+04 R= 2e+03
+Depth= 9797 States= 2e+07 Transitions= 7.09e+09 Memory= 1552.131 t= 1.12e+04 R= 2e+03
+Depth= 9797 States= 2.1e+07 Transitions= 7.48e+09 Memory= 1598.615 t= 1.18e+04 R= 2e+03
+Depth= 9797 States= 2.2e+07 Transitions= 7.94e+09 Memory= 1645.295 t= 1.26e+04 R= 2e+03
+Depth= 9797 States= 2.3e+07 Transitions= 8.37e+09 Memory= 1691.486 t= 1.33e+04 R= 2e+03
+Depth= 9797 States= 2.4e+07 Transitions= 8.77e+09 Memory= 1737.678 t= 1.39e+04 R= 2e+03
+Depth= 9797 States= 2.5e+07 Transitions= 9.22e+09 Memory= 1783.967 t= 1.46e+04 R= 2e+03
+Depth= 9797 States= 2.6e+07 Transitions= 9.48e+09 Memory= 1830.061 t= 1.5e+04 R= 2e+03
+Depth= 9797 States= 2.7e+07 Transitions= 9.85e+09 Memory= 1876.350 t= 1.56e+04 R= 2e+03
+Depth= 9797 States= 2.8e+07 Transitions= 1.02e+10 Memory= 1922.639 t= 1.62e+04 R= 2e+03
+Depth= 9919 States= 2.9e+07 Transitions= 1.06e+10 Memory= 1968.537 t= 1.68e+04 R= 2e+03
+Depth= 9963 States= 3e+07 Transitions= 1.09e+10 Memory= 2014.338 t= 1.74e+04 R= 2e+03
+Depth= 9963 States= 3.1e+07 Transitions= 1.13e+10 Memory= 2060.334 t= 1.79e+04 R= 2e+03
+Depth= 9963 States= 3.2e+07 Transitions= 1.16e+10 Memory= 2106.233 t= 1.85e+04 R= 2e+03
+Depth= 9963 States= 3.3e+07 Transitions= 1.19e+10 Memory= 2152.033 t= 1.9e+04 R= 2e+03
+Depth= 9963 States= 3.4e+07 Transitions= 1.23e+10 Memory= 2198.029 t= 1.96e+04 R= 2e+03
+pan: resizing hashtable to -w26.. done
+Depth= 9963 States= 3.5e+07 Transitions= 1.26e+10 Memory= 2739.912 t= 2e+04 R= 2e+03
+Depth= 9963 States= 3.6e+07 Transitions= 1.29e+10 Memory= 2785.713 t= 2.06e+04 R= 2e+03
+Depth= 9963 States= 3.7e+07 Transitions= 1.32e+10 Memory= 2831.416 t= 2.1e+04 R= 2e+03
+Depth= 9963 States= 3.8e+07 Transitions= 1.35e+10 Memory= 2877.217 t= 2.15e+04 R= 2e+03
+Depth= 9963 States= 3.9e+07 Transitions= 1.39e+10 Memory= 2923.018 t= 2.2e+04 R= 2e+03
+Depth= 9963 States= 4e+07 Transitions= 1.41e+10 Memory= 2968.818 t= 2.24e+04 R= 2e+03
+Depth= 9963 States= 4.1e+07 Transitions= 1.44e+10 Memory= 3014.717 t= 2.29e+04 R= 2e+03
+Depth= 9963 States= 4.2e+07 Transitions= 1.48e+10 Memory= 3061.299 t= 2.35e+04 R= 2e+03
+Depth= 9963 States= 4.3e+07 Transitions= 1.51e+10 Memory= 3107.295 t= 2.4e+04 R= 2e+03
+Depth= 9963 States= 4.4e+07 Transitions= 1.56e+10 Memory= 3153.779 t= 2.48e+04 R= 2e+03
+Depth= 9963 States= 4.5e+07 Transitions= 1.59e+10 Memory= 3199.873 t= 2.53e+04 R= 2e+03
+Depth= 9963 States= 4.6e+07 Transitions= 1.64e+10 Memory= 3246.553 t= 2.59e+04 R= 2e+03
+Depth= 9963 States= 4.7e+07 Transitions= 1.68e+10 Memory= 3293.623 t= 2.66e+04 R= 2e+03
+Depth= 9963 States= 4.8e+07 Transitions= 1.72e+10 Memory= 3339.912 t= 2.72e+04 R= 2e+03
+Depth= 9963 States= 4.9e+07 Transitions= 1.76e+10 Memory= 3386.494 t= 2.78e+04 R= 2e+03
+Depth= 9963 States= 5e+07 Transitions= 1.78e+10 Memory= 3433.076 t= 2.82e+04 R= 2e+03
+Depth= 9963 States= 5.1e+07 Transitions= 1.81e+10 Memory= 3479.072 t= 2.87e+04 R= 2e+03
+Depth= 9963 States= 5.2e+07 Transitions= 1.84e+10 Memory= 3525.068 t= 2.91e+04 R= 2e+03
+Depth= 9963 States= 5.3e+07 Transitions= 1.87e+10 Memory= 3570.869 t= 2.95e+04 R= 2e+03
+Depth= 9963 States= 5.4e+07 Transitions= 1.93e+10 Memory= 3616.865 t= 3.05e+04 R= 2e+03
+Depth= 9963 States= 5.5e+07 Transitions= 2.01e+10 Memory= 3662.764 t= 3.17e+04 R= 2e+03
+Depth= 9963 States= 5.6e+07 Transitions= 2.07e+10 Memory= 3709.541 t= 3.27e+04 R= 2e+03
+Depth= 9963 States= 5.7e+07 Transitions= 2.11e+10 Memory= 3755.635 t= 3.34e+04 R= 2e+03
+Depth= 9963 States= 5.8e+07 Transitions= 2.15e+10 Memory= 3802.315 t= 3.4e+04 R= 2e+03
+Depth= 9963 States= 5.9e+07 Transitions= 2.18e+10 Memory= 3848.408 t= 3.45e+04 R= 2e+03
+Depth= 9963 States= 6e+07 Transitions= 2.22e+10 Memory= 3894.404 t= 3.52e+04 R= 2e+03
+Depth= 9963 States= 6.1e+07 Transitions= 2.27e+10 Memory= 3940.596 t= 3.59e+04 R= 2e+03
+Depth= 9963 States= 6.2e+07 Transitions= 2.32e+10 Memory= 3986.494 t= 3.66e+04 R= 2e+03
+Depth= 9963 States= 6.3e+07 Transitions= 2.35e+10 Memory= 4032.295 t= 3.73e+04 R= 2e+03
+Depth= 9963 States= 6.4e+07 Transitions= 2.38e+10 Memory= 4078.193 t= 3.77e+04 R= 2e+03
+Depth= 9963 States= 6.5e+07 Transitions= 2.42e+10 Memory= 4124.092 t= 3.83e+04 R= 2e+03
+Depth= 9963 States= 6.6e+07 Transitions= 2.46e+10 Memory= 4169.990 t= 3.89e+04 R= 2e+03
+Depth= 9963 States= 6.7e+07 Transitions= 2.49e+10 Memory= 4215.791 t= 3.94e+04 R= 2e+03
+Depth= 9963 States= 6.8e+07 Transitions= 2.53e+10 Memory= 4261.494 t= 4e+04 R= 2e+03
+Depth= 9963 States= 6.9e+07 Transitions= 2.56e+10 Memory= 4307.295 t= 4.04e+04 R= 2e+03
+Depth= 9963 States= 7e+07 Transitions= 2.59e+10 Memory= 4353.096 t= 4.11e+04 R= 2e+03
+Depth= 9963 States= 7.1e+07 Transitions= 2.62e+10 Memory= 4398.897 t= 4.15e+04 R= 2e+03
+Depth= 9963 States= 7.2e+07 Transitions= 2.66e+10 Memory= 4444.697 t= 4.21e+04 R= 2e+03
+Depth= 9963 States= 7.3e+07 Transitions= 2.68e+10 Memory= 4490.498 t= 4.25e+04 R= 2e+03
+Depth= 9963 States= 7.4e+07 Transitions= 2.72e+10 Memory= 4536.299 t= 4.31e+04 R= 2e+03
+Depth= 9963 States= 7.5e+07 Transitions= 2.76e+10 Memory= 4582.002 t= 4.37e+04 R= 2e+03
+Depth= 9963 States= 7.6e+07 Transitions= 2.78e+10 Memory= 4627.803 t= 4.41e+04 R= 2e+03
+Depth= 9963 States= 7.7e+07 Transitions= 2.81e+10 Memory= 4673.604 t= 4.46e+04 R= 2e+03
+Depth= 9963 States= 7.8e+07 Transitions= 2.84e+10 Memory= 4719.404 t= 4.5e+04 R= 2e+03
+Depth= 9963 States= 7.9e+07 Transitions= 2.87e+10 Memory= 4765.205 t= 4.55e+04 R= 2e+03
+Depth= 9963 States= 8e+07 Transitions= 2.91e+10 Memory= 4811.006 t= 4.61e+04 R= 2e+03
+Depth= 9963 States= 8.1e+07 Transitions= 2.95e+10 Memory= 4856.807 t= 4.68e+04 R= 2e+03
+Depth= 9963 States= 8.2e+07 Transitions= 2.99e+10 Memory= 4902.608 t= 4.74e+04 R= 2e+03
+Depth= 9963 States= 8.3e+07 Transitions= 3.03e+10 Memory= 4948.701 t= 4.8e+04 R= 2e+03
+Depth= 9963 States= 8.4e+07 Transitions= 3.07e+10 Memory= 4995.283 t= 4.87e+04 R= 2e+03
+Depth= 9963 States= 8.5e+07 Transitions= 3.11e+10 Memory= 5041.084 t= 4.93e+04 R= 2e+03
+Depth= 9963 States= 8.6e+07 Transitions= 3.15e+10 Memory= 5087.276 t= 4.98e+04 R= 2e+03
+Depth= 9963 States= 8.7e+07 Transitions= 3.19e+10 Memory= 5133.369 t= 5.06e+04 R= 2e+03
+Depth= 9963 States= 8.8e+07 Transitions= 3.23e+10 Memory= 5179.170 t= 5.11e+04 R= 2e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 9963, errors: 0
+ 88716525 states, stored
+3.243293e+10 states, matched
+3.2521646e+10 transitions (= stored+matched)
+1.8325967e+11 atomic steps
+hash conflicts: 1.7134961e+10 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 9814.374 equivalent memory usage for states (stored*(State-vector + overhead))
+ 4243.430 actual memory usage for states (compression: 43.24%)
+ state-vector as stored = 14 byte + 36 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 5212.276 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 606546 5194 3779 2 1 ]
+unreached in proctype urcu_reader
+ line 267, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 275, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 104, "(1)"
+ line 248, "pan.___", state 112, "(1)"
+ line 252, "pan.___", state 124, "(1)"
+ line 256, "pan.___", state 132, "(1)"
+ line 406, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 223, "(1)"
+ line 433, "pan.___", state 253, "(1)"
+ line 437, "pan.___", state 266, "(1)"
+ line 686, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 406, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 359, "(1)"
+ line 433, "pan.___", state 389, "(1)"
+ line 437, "pan.___", state 402, "(1)"
+ line 406, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 488, "(1)"
+ line 433, "pan.___", state 518, "(1)"
+ line 437, "pan.___", state 531, "(1)"
+ line 406, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, "pan.___", state 556, "(1)"
+ line 406, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 406, "pan.___", state 557, "else"
+ line 406, "pan.___", state 560, "(1)"
+ line 410, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 410, "pan.___", state 570, "(1)"
+ line 410, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 410, "pan.___", state 571, "else"
+ line 410, "pan.___", state 574, "(1)"
+ line 410, "pan.___", state 575, "(1)"
+ line 410, "pan.___", state 575, "(1)"
+ line 408, "pan.___", state 580, "((i<1))"
+ line 408, "pan.___", state 580, "((i>=1))"
+ line 415, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 415, "pan.___", state 588, "(1)"
+ line 415, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 415, "pan.___", state 589, "else"
+ line 415, "pan.___", state 592, "(1)"
+ line 415, "pan.___", state 593, "(1)"
+ line 415, "pan.___", state 593, "(1)"
+ line 419, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 419, "pan.___", state 602, "(1)"
+ line 419, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 419, "pan.___", state 603, "else"
+ line 419, "pan.___", state 606, "(1)"
+ line 419, "pan.___", state 607, "(1)"
+ line 419, "pan.___", state 607, "(1)"
+ line 417, "pan.___", state 612, "((i<2))"
+ line 417, "pan.___", state 612, "((i>=2))"
+ line 424, "pan.___", state 619, "(1)"
+ line 424, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, "pan.___", state 620, "else"
+ line 424, "pan.___", state 623, "(1)"
+ line 424, "pan.___", state 624, "(1)"
+ line 424, "pan.___", state 624, "(1)"
+ line 428, "pan.___", state 632, "(1)"
+ line 428, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 428, "pan.___", state 633, "else"
+ line 428, "pan.___", state 636, "(1)"
+ line 428, "pan.___", state 637, "(1)"
+ line 428, "pan.___", state 637, "(1)"
+ line 426, "pan.___", state 642, "((i<1))"
+ line 426, "pan.___", state 642, "((i>=1))"
+ line 433, "pan.___", state 649, "(1)"
+ line 433, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 433, "pan.___", state 650, "else"
+ line 433, "pan.___", state 653, "(1)"
+ line 433, "pan.___", state 654, "(1)"
+ line 433, "pan.___", state 654, "(1)"
+ line 437, "pan.___", state 662, "(1)"
+ line 437, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 437, "pan.___", state 663, "else"
+ line 437, "pan.___", state 666, "(1)"
+ line 437, "pan.___", state 667, "(1)"
+ line 437, "pan.___", state 667, "(1)"
+ line 435, "pan.___", state 672, "((i<2))"
+ line 435, "pan.___", state 672, "((i>=2))"
+ line 445, "pan.___", state 676, "(1)"
+ line 445, "pan.___", state 676, "(1)"
+ line 686, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 686, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 686, "pan.___", state 681, "(1)"
+ line 406, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 753, "(1)"
+ line 433, "pan.___", state 783, "(1)"
+ line 437, "pan.___", state 796, "(1)"
+ line 406, "pan.___", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 856, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 889, "(1)"
+ line 433, "pan.___", state 919, "(1)"
+ line 437, "pan.___", state 932, "(1)"
+ line 406, "pan.___", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, "pan.___", state 955, "(1)"
+ line 406, "pan.___", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 406, "pan.___", state 956, "else"
+ line 406, "pan.___", state 959, "(1)"
+ line 410, "pan.___", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 410, "pan.___", state 969, "(1)"
+ line 410, "pan.___", state 970, "(cache_dirty_urcu_active_readers)"
+ line 410, "pan.___", state 970, "else"
+ line 410, "pan.___", state 973, "(1)"
+ line 410, "pan.___", state 974, "(1)"
+ line 410, "pan.___", state 974, "(1)"
+ line 408, "pan.___", state 979, "((i<1))"
+ line 408, "pan.___", state 979, "((i>=1))"
+ line 415, "pan.___", state 985, "cache_dirty_rcu_ptr = 0"
+ line 415, "pan.___", state 987, "(1)"
+ line 415, "pan.___", state 988, "(cache_dirty_rcu_ptr)"
+ line 415, "pan.___", state 988, "else"
+ line 415, "pan.___", state 991, "(1)"
+ line 415, "pan.___", state 992, "(1)"
+ line 415, "pan.___", state 992, "(1)"
+ line 419, "pan.___", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 419, "pan.___", state 1001, "(1)"
+ line 419, "pan.___", state 1002, "(cache_dirty_rcu_data[i])"
+ line 419, "pan.___", state 1002, "else"
+ line 419, "pan.___", state 1005, "(1)"
+ line 419, "pan.___", state 1006, "(1)"
+ line 419, "pan.___", state 1006, "(1)"
+ line 417, "pan.___", state 1011, "((i<2))"
+ line 417, "pan.___", state 1011, "((i>=2))"
+ line 424, "pan.___", state 1018, "(1)"
+ line 424, "pan.___", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, "pan.___", state 1019, "else"
+ line 424, "pan.___", state 1022, "(1)"
+ line 424, "pan.___", state 1023, "(1)"
+ line 424, "pan.___", state 1023, "(1)"
+ line 428, "pan.___", state 1031, "(1)"
+ line 428, "pan.___", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 428, "pan.___", state 1032, "else"
+ line 428, "pan.___", state 1035, "(1)"
+ line 428, "pan.___", state 1036, "(1)"
+ line 428, "pan.___", state 1036, "(1)"
+ line 426, "pan.___", state 1041, "((i<1))"
+ line 426, "pan.___", state 1041, "((i>=1))"
+ line 433, "pan.___", state 1048, "(1)"
+ line 433, "pan.___", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 433, "pan.___", state 1049, "else"
+ line 433, "pan.___", state 1052, "(1)"
+ line 433, "pan.___", state 1053, "(1)"
+ line 433, "pan.___", state 1053, "(1)"
+ line 437, "pan.___", state 1061, "(1)"
+ line 437, "pan.___", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 437, "pan.___", state 1062, "else"
+ line 437, "pan.___", state 1065, "(1)"
+ line 437, "pan.___", state 1066, "(1)"
+ line 437, "pan.___", state 1066, "(1)"
+ line 435, "pan.___", state 1071, "((i<2))"
+ line 435, "pan.___", state 1071, "((i>=2))"
+ line 445, "pan.___", state 1075, "(1)"
+ line 445, "pan.___", state 1075, "(1)"
+ line 694, "pan.___", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 406, "pan.___", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1149, "(1)"
+ line 433, "pan.___", state 1179, "(1)"
+ line 437, "pan.___", state 1192, "(1)"
+ line 406, "pan.___", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1281, "(1)"
+ line 433, "pan.___", state 1311, "(1)"
+ line 437, "pan.___", state 1324, "(1)"
+ line 406, "pan.___", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1414, "(1)"
+ line 433, "pan.___", state 1444, "(1)"
+ line 437, "pan.___", state 1457, "(1)"
+ line 406, "pan.___", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1543, "(1)"
+ line 433, "pan.___", state 1573, "(1)"
+ line 437, "pan.___", state 1586, "(1)"
+ line 406, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1677, "(1)"
+ line 433, "pan.___", state 1707, "(1)"
+ line 437, "pan.___", state 1720, "(1)"
+ line 406, "pan.___", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1806, "(1)"
+ line 433, "pan.___", state 1836, "(1)"
+ line 437, "pan.___", state 1849, "(1)"
+ line 406, "pan.___", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 1938, "(1)"
+ line 433, "pan.___", state 1968, "(1)"
+ line 437, "pan.___", state 1981, "(1)"
+ line 733, "pan.___", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 406, "pan.___", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 2074, "(1)"
+ line 433, "pan.___", state 2104, "(1)"
+ line 437, "pan.___", state 2117, "(1)"
+ line 406, "pan.___", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 2203, "(1)"
+ line 433, "pan.___", state 2233, "(1)"
+ line 437, "pan.___", state 2246, "(1)"
+ line 406, "pan.___", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 406, "pan.___", state 2271, "(1)"
+ line 406, "pan.___", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 406, "pan.___", state 2272, "else"
+ line 406, "pan.___", state 2275, "(1)"
+ line 410, "pan.___", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 410, "pan.___", state 2285, "(1)"
+ line 410, "pan.___", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 410, "pan.___", state 2286, "else"
+ line 410, "pan.___", state 2289, "(1)"
+ line 410, "pan.___", state 2290, "(1)"
+ line 410, "pan.___", state 2290, "(1)"
+ line 408, "pan.___", state 2295, "((i<1))"
+ line 408, "pan.___", state 2295, "((i>=1))"
+ line 415, "pan.___", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 415, "pan.___", state 2303, "(1)"
+ line 415, "pan.___", state 2304, "(cache_dirty_rcu_ptr)"
+ line 415, "pan.___", state 2304, "else"
+ line 415, "pan.___", state 2307, "(1)"
+ line 415, "pan.___", state 2308, "(1)"
+ line 415, "pan.___", state 2308, "(1)"
+ line 419, "pan.___", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 419, "pan.___", state 2317, "(1)"
+ line 419, "pan.___", state 2318, "(cache_dirty_rcu_data[i])"
+ line 419, "pan.___", state 2318, "else"
+ line 419, "pan.___", state 2321, "(1)"
+ line 419, "pan.___", state 2322, "(1)"
+ line 419, "pan.___", state 2322, "(1)"
+ line 417, "pan.___", state 2327, "((i<2))"
+ line 417, "pan.___", state 2327, "((i>=2))"
+ line 424, "pan.___", state 2334, "(1)"
+ line 424, "pan.___", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 424, "pan.___", state 2335, "else"
+ line 424, "pan.___", state 2338, "(1)"
+ line 424, "pan.___", state 2339, "(1)"
+ line 424, "pan.___", state 2339, "(1)"
+ line 428, "pan.___", state 2347, "(1)"
+ line 428, "pan.___", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 428, "pan.___", state 2348, "else"
+ line 428, "pan.___", state 2351, "(1)"
+ line 428, "pan.___", state 2352, "(1)"
+ line 428, "pan.___", state 2352, "(1)"
+ line 426, "pan.___", state 2357, "((i<1))"
+ line 426, "pan.___", state 2357, "((i>=1))"
+ line 433, "pan.___", state 2364, "(1)"
+ line 433, "pan.___", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 433, "pan.___", state 2365, "else"
+ line 433, "pan.___", state 2368, "(1)"
+ line 433, "pan.___", state 2369, "(1)"
+ line 433, "pan.___", state 2369, "(1)"
+ line 437, "pan.___", state 2377, "(1)"
+ line 437, "pan.___", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 437, "pan.___", state 2378, "else"
+ line 437, "pan.___", state 2381, "(1)"
+ line 437, "pan.___", state 2382, "(1)"
+ line 437, "pan.___", state 2382, "(1)"
+ line 435, "pan.___", state 2387, "((i<2))"
+ line 435, "pan.___", state 2387, "((i>=2))"
+ line 445, "pan.___", state 2391, "(1)"
+ line 445, "pan.___", state 2391, "(1)"
+ line 733, "pan.___", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 733, "pan.___", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 733, "pan.___", state 2396, "(1)"
+ line 406, "pan.___", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 2468, "(1)"
+ line 433, "pan.___", state 2498, "(1)"
+ line 437, "pan.___", state 2511, "(1)"
+ line 406, "pan.___", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 2603, "(1)"
+ line 433, "pan.___", state 2633, "(1)"
+ line 437, "pan.___", state 2646, "(1)"
+ line 406, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 415, "pan.___", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 2732, "(1)"
+ line 433, "pan.___", state 2762, "(1)"
+ line 437, "pan.___", state 2775, "(1)"
+ line 244, "pan.___", state 2808, "(1)"
+ line 252, "pan.___", state 2828, "(1)"
+ line 256, "pan.___", state 2836, "(1)"
+ line 244, "pan.___", state 2851, "(1)"
+ line 252, "pan.___", state 2871, "(1)"
+ line 256, "pan.___", state 2879, "(1)"
+ line 928, "pan.___", state 2896, "-end-"
+ (245 of 2896 states)
+unreached in proctype urcu_writer
+ line 406, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 410, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 424, "pan.___", state 110, "(1)"
+ line 428, "pan.___", state 123, "(1)"
+ line 433, "pan.___", state 140, "(1)"
+ line 267, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 406, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 410, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 424, "pan.___", state 303, "(1)"
+ line 428, "pan.___", state 316, "(1)"
+ line 433, "pan.___", state 333, "(1)"
+ line 437, "pan.___", state 346, "(1)"
+ line 410, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 428, "pan.___", state 447, "(1)"
+ line 433, "pan.___", state 464, "(1)"
+ line 437, "pan.___", state 477, "(1)"
+ line 410, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 428, "pan.___", state 586, "(1)"
+ line 433, "pan.___", state 603, "(1)"
+ line 437, "pan.___", state 616, "(1)"
+ line 410, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 428, "pan.___", state 715, "(1)"
+ line 433, "pan.___", state 732, "(1)"
+ line 437, "pan.___", state 745, "(1)"
+ line 410, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 415, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 419, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 428, "pan.___", state 846, "(1)"
+ line 433, "pan.___", state 863, "(1)"
+ line 437, "pan.___", state 876, "(1)"
+ line 267, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 955, "(1)"
+ line 279, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 978, "(1)"
+ line 248, "pan.___", state 986, "(1)"
+ line 252, "pan.___", state 998, "(1)"
+ line 256, "pan.___", state 1006, "(1)"
+ line 267, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1084, "(1)"
+ line 248, "pan.___", state 1092, "(1)"
+ line 252, "pan.___", state 1104, "(1)"
+ line 256, "pan.___", state 1112, "(1)"
+ line 271, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1176, "(1)"
+ line 248, "pan.___", state 1184, "(1)"
+ line 252, "pan.___", state 1196, "(1)"
+ line 256, "pan.___", state 1204, "(1)"
+ line 267, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1282, "(1)"
+ line 248, "pan.___", state 1290, "(1)"
+ line 252, "pan.___", state 1302, "(1)"
+ line 256, "pan.___", state 1310, "(1)"
+ line 271, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1374, "(1)"
+ line 248, "pan.___", state 1382, "(1)"
+ line 252, "pan.___", state 1394, "(1)"
+ line 256, "pan.___", state 1402, "(1)"
+ line 267, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1480, "(1)"
+ line 248, "pan.___", state 1488, "(1)"
+ line 252, "pan.___", state 1500, "(1)"
+ line 256, "pan.___", state 1508, "(1)"
+ line 271, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1572, "(1)"
+ line 248, "pan.___", state 1580, "(1)"
+ line 252, "pan.___", state 1592, "(1)"
+ line 256, "pan.___", state 1600, "(1)"
+ line 267, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 271, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 275, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 279, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 244, "pan.___", state 1678, "(1)"
+ line 248, "pan.___", state 1686, "(1)"
+ line 252, "pan.___", state 1698, "(1)"
+ line 256, "pan.___", state 1706, "(1)"
+ line 1303, "pan.___", state 1722, "-end-"
+ (103 of 1722 states)
+unreached in proctype :init:
+ (0 of 28 states)
+unreached in proctype :never:
+ line 1366, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 5.15e+04 seconds
+pan: rate 1721.7944 states/second
+pan: avg transition delay 1.5843e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+[] (!read_poison)
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+Depth= 9193 States= 1e+06 Transitions= 2.02e+08 Memory= 513.615 t= 308 R= 3e+03
+Depth= 9193 States= 2e+06 Transitions= 4.02e+08 Memory= 560.100 t= 617 R= 3e+03
+pan: claim violated! (at depth 1482)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 9193, errors: 1
+ 2638623 states, stored
+5.0906949e+08 states, matched
+5.1170812e+08 transitions (= stored+matched)
+2.7495835e+09 atomic steps
+hash conflicts: 3.3187407e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 291.901 equivalent memory usage for states (stored*(State-vector + overhead))
+ 123.793 actual memory usage for states (compression: 42.41%)
+ state-vector as stored = 13 byte + 36 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 589.494 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 39337 2870 221 2 2 ]
+unreached in proctype urcu_reader
+ line 894, "pan.___", state 12, "((i<1))"
+ line 894, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 61, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 83, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 92, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 108, "(1)"
+ line 249, "pan.___", state 116, "(1)"
+ line 253, "pan.___", state 128, "(1)"
+ line 257, "pan.___", state 136, "(1)"
+ line 407, "pan.___", state 162, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 194, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 208, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 227, "(1)"
+ line 434, "pan.___", state 257, "(1)"
+ line 438, "pan.___", state 270, "(1)"
+ line 696, "pan.___", state 291, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 298, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 330, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 344, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 363, "(1)"
+ line 434, "pan.___", state 393, "(1)"
+ line 438, "pan.___", state 406, "(1)"
+ line 407, "pan.___", state 427, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 459, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 473, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 492, "(1)"
+ line 434, "pan.___", state 522, "(1)"
+ line 438, "pan.___", state 535, "(1)"
+ line 407, "pan.___", state 558, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 560, "(1)"
+ line 407, "pan.___", state 561, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 561, "else"
+ line 407, "pan.___", state 564, "(1)"
+ line 411, "pan.___", state 572, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 574, "(1)"
+ line 411, "pan.___", state 575, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 575, "else"
+ line 411, "pan.___", state 578, "(1)"
+ line 411, "pan.___", state 579, "(1)"
+ line 411, "pan.___", state 579, "(1)"
+ line 409, "pan.___", state 584, "((i<1))"
+ line 409, "pan.___", state 584, "((i>=1))"
+ line 416, "pan.___", state 590, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 592, "(1)"
+ line 416, "pan.___", state 593, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 593, "else"
+ line 416, "pan.___", state 596, "(1)"
+ line 416, "pan.___", state 597, "(1)"
+ line 416, "pan.___", state 597, "(1)"
+ line 420, "pan.___", state 604, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 606, "(1)"
+ line 420, "pan.___", state 607, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 607, "else"
+ line 420, "pan.___", state 610, "(1)"
+ line 420, "pan.___", state 611, "(1)"
+ line 420, "pan.___", state 611, "(1)"
+ line 418, "pan.___", state 616, "((i<2))"
+ line 418, "pan.___", state 616, "((i>=2))"
+ line 425, "pan.___", state 623, "(1)"
+ line 425, "pan.___", state 624, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 624, "else"
+ line 425, "pan.___", state 627, "(1)"
+ line 425, "pan.___", state 628, "(1)"
+ line 425, "pan.___", state 628, "(1)"
+ line 429, "pan.___", state 636, "(1)"
+ line 429, "pan.___", state 637, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 637, "else"
+ line 429, "pan.___", state 640, "(1)"
+ line 429, "pan.___", state 641, "(1)"
+ line 429, "pan.___", state 641, "(1)"
+ line 427, "pan.___", state 646, "((i<1))"
+ line 427, "pan.___", state 646, "((i>=1))"
+ line 434, "pan.___", state 653, "(1)"
+ line 434, "pan.___", state 654, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 654, "else"
+ line 434, "pan.___", state 657, "(1)"
+ line 434, "pan.___", state 658, "(1)"
+ line 434, "pan.___", state 658, "(1)"
+ line 438, "pan.___", state 666, "(1)"
+ line 438, "pan.___", state 667, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 667, "else"
+ line 438, "pan.___", state 670, "(1)"
+ line 438, "pan.___", state 671, "(1)"
+ line 438, "pan.___", state 671, "(1)"
+ line 436, "pan.___", state 676, "((i<2))"
+ line 436, "pan.___", state 676, "((i>=2))"
+ line 446, "pan.___", state 680, "(1)"
+ line 446, "pan.___", state 680, "(1)"
+ line 696, "pan.___", state 683, "cached_urcu_active_readers = (tmp+1)"
+ line 696, "pan.___", state 684, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 696, "pan.___", state 685, "(1)"
+ line 407, "pan.___", state 692, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 724, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 738, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 757, "(1)"
+ line 434, "pan.___", state 787, "(1)"
+ line 438, "pan.___", state 800, "(1)"
+ line 407, "pan.___", state 828, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 860, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 874, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 893, "(1)"
+ line 434, "pan.___", state 923, "(1)"
+ line 438, "pan.___", state 936, "(1)"
+ line 407, "pan.___", state 957, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 959, "(1)"
+ line 407, "pan.___", state 960, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 960, "else"
+ line 407, "pan.___", state 963, "(1)"
+ line 411, "pan.___", state 971, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 973, "(1)"
+ line 411, "pan.___", state 974, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 974, "else"
+ line 411, "pan.___", state 977, "(1)"
+ line 411, "pan.___", state 978, "(1)"
+ line 411, "pan.___", state 978, "(1)"
+ line 409, "pan.___", state 983, "((i<1))"
+ line 409, "pan.___", state 983, "((i>=1))"
+ line 416, "pan.___", state 989, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 991, "(1)"
+ line 416, "pan.___", state 992, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 992, "else"
+ line 416, "pan.___", state 995, "(1)"
+ line 416, "pan.___", state 996, "(1)"
+ line 416, "pan.___", state 996, "(1)"
+ line 420, "pan.___", state 1003, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 1005, "(1)"
+ line 420, "pan.___", state 1006, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 1006, "else"
+ line 420, "pan.___", state 1009, "(1)"
+ line 420, "pan.___", state 1010, "(1)"
+ line 420, "pan.___", state 1010, "(1)"
+ line 418, "pan.___", state 1015, "((i<2))"
+ line 418, "pan.___", state 1015, "((i>=2))"
+ line 425, "pan.___", state 1022, "(1)"
+ line 425, "pan.___", state 1023, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 1023, "else"
+ line 425, "pan.___", state 1026, "(1)"
+ line 425, "pan.___", state 1027, "(1)"
+ line 425, "pan.___", state 1027, "(1)"
+ line 429, "pan.___", state 1035, "(1)"
+ line 429, "pan.___", state 1036, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 1036, "else"
+ line 429, "pan.___", state 1039, "(1)"
+ line 429, "pan.___", state 1040, "(1)"
+ line 429, "pan.___", state 1040, "(1)"
+ line 427, "pan.___", state 1045, "((i<1))"
+ line 427, "pan.___", state 1045, "((i>=1))"
+ line 434, "pan.___", state 1052, "(1)"
+ line 434, "pan.___", state 1053, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 1053, "else"
+ line 434, "pan.___", state 1056, "(1)"
+ line 434, "pan.___", state 1057, "(1)"
+ line 434, "pan.___", state 1057, "(1)"
+ line 438, "pan.___", state 1065, "(1)"
+ line 438, "pan.___", state 1066, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 1066, "else"
+ line 438, "pan.___", state 1069, "(1)"
+ line 438, "pan.___", state 1070, "(1)"
+ line 438, "pan.___", state 1070, "(1)"
+ line 436, "pan.___", state 1075, "((i<2))"
+ line 436, "pan.___", state 1075, "((i>=2))"
+ line 446, "pan.___", state 1079, "(1)"
+ line 446, "pan.___", state 1079, "(1)"
+ line 704, "pan.___", state 1083, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 1088, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1120, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1134, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1153, "(1)"
+ line 434, "pan.___", state 1183, "(1)"
+ line 438, "pan.___", state 1196, "(1)"
+ line 407, "pan.___", state 1220, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1252, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1285, "(1)"
+ line 434, "pan.___", state 1315, "(1)"
+ line 438, "pan.___", state 1328, "(1)"
+ line 407, "pan.___", state 1353, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1385, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1399, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1418, "(1)"
+ line 434, "pan.___", state 1448, "(1)"
+ line 438, "pan.___", state 1461, "(1)"
+ line 407, "pan.___", state 1482, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1514, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1528, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1547, "(1)"
+ line 434, "pan.___", state 1577, "(1)"
+ line 438, "pan.___", state 1590, "(1)"
+ line 407, "pan.___", state 1616, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1648, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1681, "(1)"
+ line 434, "pan.___", state 1711, "(1)"
+ line 438, "pan.___", state 1724, "(1)"
+ line 407, "pan.___", state 1745, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1777, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1791, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1810, "(1)"
+ line 434, "pan.___", state 1840, "(1)"
+ line 438, "pan.___", state 1853, "(1)"
+ line 407, "pan.___", state 1877, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1909, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1923, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1942, "(1)"
+ line 434, "pan.___", state 1972, "(1)"
+ line 438, "pan.___", state 1985, "(1)"
+ line 743, "pan.___", state 2006, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 2013, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2045, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2059, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2078, "(1)"
+ line 434, "pan.___", state 2108, "(1)"
+ line 438, "pan.___", state 2121, "(1)"
+ line 407, "pan.___", state 2142, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2174, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2188, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2207, "(1)"
+ line 434, "pan.___", state 2237, "(1)"
+ line 438, "pan.___", state 2250, "(1)"
+ line 407, "pan.___", state 2273, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 2275, "(1)"
+ line 407, "pan.___", state 2276, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 2276, "else"
+ line 407, "pan.___", state 2279, "(1)"
+ line 411, "pan.___", state 2287, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2290, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 2290, "else"
+ line 411, "pan.___", state 2293, "(1)"
+ line 411, "pan.___", state 2294, "(1)"
+ line 411, "pan.___", state 2294, "(1)"
+ line 409, "pan.___", state 2299, "((i<1))"
+ line 409, "pan.___", state 2299, "((i>=1))"
+ line 416, "pan.___", state 2305, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2307, "(1)"
+ line 416, "pan.___", state 2308, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2308, "else"
+ line 416, "pan.___", state 2311, "(1)"
+ line 416, "pan.___", state 2312, "(1)"
+ line 416, "pan.___", state 2312, "(1)"
+ line 420, "pan.___", state 2319, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2321, "(1)"
+ line 420, "pan.___", state 2322, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2322, "else"
+ line 420, "pan.___", state 2325, "(1)"
+ line 420, "pan.___", state 2326, "(1)"
+ line 420, "pan.___", state 2326, "(1)"
+ line 418, "pan.___", state 2331, "((i<2))"
+ line 418, "pan.___", state 2331, "((i>=2))"
+ line 425, "pan.___", state 2338, "(1)"
+ line 425, "pan.___", state 2339, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 2339, "else"
+ line 425, "pan.___", state 2342, "(1)"
+ line 425, "pan.___", state 2343, "(1)"
+ line 425, "pan.___", state 2343, "(1)"
+ line 429, "pan.___", state 2351, "(1)"
+ line 429, "pan.___", state 2352, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 2352, "else"
+ line 429, "pan.___", state 2355, "(1)"
+ line 429, "pan.___", state 2356, "(1)"
+ line 429, "pan.___", state 2356, "(1)"
+ line 427, "pan.___", state 2361, "((i<1))"
+ line 427, "pan.___", state 2361, "((i>=1))"
+ line 434, "pan.___", state 2368, "(1)"
+ line 434, "pan.___", state 2369, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 2369, "else"
+ line 434, "pan.___", state 2372, "(1)"
+ line 434, "pan.___", state 2373, "(1)"
+ line 434, "pan.___", state 2373, "(1)"
+ line 438, "pan.___", state 2381, "(1)"
+ line 438, "pan.___", state 2382, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 2382, "else"
+ line 438, "pan.___", state 2385, "(1)"
+ line 438, "pan.___", state 2386, "(1)"
+ line 438, "pan.___", state 2386, "(1)"
+ line 436, "pan.___", state 2391, "((i<2))"
+ line 436, "pan.___", state 2391, "((i>=2))"
+ line 446, "pan.___", state 2395, "(1)"
+ line 446, "pan.___", state 2395, "(1)"
+ line 743, "pan.___", state 2398, "cached_urcu_active_readers = (tmp+1)"
+ line 743, "pan.___", state 2399, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 743, "pan.___", state 2400, "(1)"
+ line 407, "pan.___", state 2407, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2439, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2453, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2472, "(1)"
+ line 434, "pan.___", state 2502, "(1)"
+ line 438, "pan.___", state 2515, "(1)"
+ line 407, "pan.___", state 2542, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2574, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2588, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2607, "(1)"
+ line 434, "pan.___", state 2637, "(1)"
+ line 438, "pan.___", state 2650, "(1)"
+ line 407, "pan.___", state 2671, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2703, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2717, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2736, "(1)"
+ line 434, "pan.___", state 2766, "(1)"
+ line 438, "pan.___", state 2779, "(1)"
+ line 245, "pan.___", state 2812, "(1)"
+ line 253, "pan.___", state 2832, "(1)"
+ line 257, "pan.___", state 2840, "(1)"
+ line 245, "pan.___", state 2855, "(1)"
+ line 253, "pan.___", state 2875, "(1)"
+ line 257, "pan.___", state 2883, "(1)"
+ line 929, "pan.___", state 2900, "-end-"
+ (246 of 2900 states)
+unreached in proctype urcu_writer
+ line 1018, "pan.___", state 12, "((i<1))"
+ line 1018, "pan.___", state 12, "((i>=1))"
+ line 407, "pan.___", state 47, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 53, "(1)"
+ line 411, "pan.___", state 61, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 67, "(1)"
+ line 411, "pan.___", state 68, "(1)"
+ line 411, "pan.___", state 68, "(1)"
+ line 409, "pan.___", state 73, "((i<1))"
+ line 409, "pan.___", state 73, "((i>=1))"
+ line 416, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 85, "(1)"
+ line 416, "pan.___", state 86, "(1)"
+ line 416, "pan.___", state 86, "(1)"
+ line 420, "pan.___", state 99, "(1)"
+ line 420, "pan.___", state 100, "(1)"
+ line 420, "pan.___", state 100, "(1)"
+ line 418, "pan.___", state 105, "((i<2))"
+ line 418, "pan.___", state 105, "((i>=2))"
+ line 425, "pan.___", state 112, "(1)"
+ line 425, "pan.___", state 113, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 113, "else"
+ line 425, "pan.___", state 116, "(1)"
+ line 425, "pan.___", state 117, "(1)"
+ line 425, "pan.___", state 117, "(1)"
+ line 429, "pan.___", state 125, "(1)"
+ line 429, "pan.___", state 126, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 126, "else"
+ line 429, "pan.___", state 129, "(1)"
+ line 429, "pan.___", state 130, "(1)"
+ line 429, "pan.___", state 130, "(1)"
+ line 427, "pan.___", state 135, "((i<1))"
+ line 427, "pan.___", state 135, "((i>=1))"
+ line 434, "pan.___", state 142, "(1)"
+ line 434, "pan.___", state 143, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 143, "else"
+ line 434, "pan.___", state 146, "(1)"
+ line 434, "pan.___", state 147, "(1)"
+ line 434, "pan.___", state 147, "(1)"
+ line 438, "pan.___", state 155, "(1)"
+ line 438, "pan.___", state 156, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 156, "else"
+ line 438, "pan.___", state 159, "(1)"
+ line 438, "pan.___", state 160, "(1)"
+ line 438, "pan.___", state 160, "(1)"
+ line 436, "pan.___", state 165, "((i<2))"
+ line 436, "pan.___", state 165, "((i>=2))"
+ line 446, "pan.___", state 169, "(1)"
+ line 446, "pan.___", state 169, "(1)"
+ line 268, "pan.___", state 178, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 187, "cache_dirty_urcu_active_readers = 0"
+ line 270, "pan.___", state 195, "((i<1))"
+ line 270, "pan.___", state 195, "((i>=1))"
+ line 276, "pan.___", state 200, "cache_dirty_rcu_ptr = 0"
+ line 1088, "pan.___", state 228, "old_data = cached_rcu_ptr"
+ line 1099, "pan.___", state 232, "_proc_urcu_writer = (_proc_urcu_writer|(1<<4))"
+ line 407, "pan.___", state 240, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 246, "(1)"
+ line 411, "pan.___", state 254, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 260, "(1)"
+ line 411, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 261, "(1)"
+ line 409, "pan.___", state 266, "((i<1))"
+ line 409, "pan.___", state 266, "((i>=1))"
+ line 416, "pan.___", state 274, "(1)"
+ line 416, "pan.___", state 275, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 275, "else"
+ line 416, "pan.___", state 278, "(1)"
+ line 416, "pan.___", state 279, "(1)"
+ line 416, "pan.___", state 279, "(1)"
+ line 420, "pan.___", state 286, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 292, "(1)"
+ line 420, "pan.___", state 293, "(1)"
+ line 420, "pan.___", state 293, "(1)"
+ line 418, "pan.___", state 298, "((i<2))"
+ line 418, "pan.___", state 298, "((i>=2))"
+ line 425, "pan.___", state 305, "(1)"
+ line 425, "pan.___", state 306, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 306, "else"
+ line 425, "pan.___", state 309, "(1)"
+ line 425, "pan.___", state 310, "(1)"
+ line 425, "pan.___", state 310, "(1)"
+ line 429, "pan.___", state 318, "(1)"
+ line 429, "pan.___", state 319, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 319, "else"
+ line 429, "pan.___", state 322, "(1)"
+ line 429, "pan.___", state 323, "(1)"
+ line 429, "pan.___", state 323, "(1)"
+ line 427, "pan.___", state 328, "((i<1))"
+ line 427, "pan.___", state 328, "((i>=1))"
+ line 434, "pan.___", state 335, "(1)"
+ line 434, "pan.___", state 336, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 336, "else"
+ line 434, "pan.___", state 339, "(1)"
+ line 434, "pan.___", state 340, "(1)"
+ line 434, "pan.___", state 340, "(1)"
+ line 438, "pan.___", state 348, "(1)"
+ line 438, "pan.___", state 349, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 349, "else"
+ line 438, "pan.___", state 352, "(1)"
+ line 438, "pan.___", state 353, "(1)"
+ line 438, "pan.___", state 353, "(1)"
+ line 436, "pan.___", state 358, "((i<2))"
+ line 436, "pan.___", state 358, "((i>=2))"
+ line 446, "pan.___", state 362, "(1)"
+ line 446, "pan.___", state 362, "(1)"
+ line 407, "pan.___", state 373, "(1)"
+ line 407, "pan.___", state 374, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 374, "else"
+ line 407, "pan.___", state 377, "(1)"
+ line 411, "pan.___", state 385, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 391, "(1)"
+ line 411, "pan.___", state 392, "(1)"
+ line 411, "pan.___", state 392, "(1)"
+ line 409, "pan.___", state 397, "((i<1))"
+ line 409, "pan.___", state 397, "((i>=1))"
+ line 416, "pan.___", state 403, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 409, "(1)"
+ line 416, "pan.___", state 410, "(1)"
+ line 416, "pan.___", state 410, "(1)"
+ line 420, "pan.___", state 417, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 423, "(1)"
+ line 420, "pan.___", state 424, "(1)"
+ line 420, "pan.___", state 424, "(1)"
+ line 418, "pan.___", state 429, "((i<2))"
+ line 418, "pan.___", state 429, "((i>=2))"
+ line 425, "pan.___", state 436, "(1)"
+ line 425, "pan.___", state 437, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 437, "else"
+ line 425, "pan.___", state 440, "(1)"
+ line 425, "pan.___", state 441, "(1)"
+ line 425, "pan.___", state 441, "(1)"
+ line 429, "pan.___", state 449, "(1)"
+ line 429, "pan.___", state 450, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 450, "else"
+ line 429, "pan.___", state 453, "(1)"
+ line 429, "pan.___", state 454, "(1)"
+ line 429, "pan.___", state 454, "(1)"
+ line 427, "pan.___", state 459, "((i<1))"
+ line 427, "pan.___", state 459, "((i>=1))"
+ line 434, "pan.___", state 466, "(1)"
+ line 434, "pan.___", state 467, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 467, "else"
+ line 434, "pan.___", state 470, "(1)"
+ line 434, "pan.___", state 471, "(1)"
+ line 434, "pan.___", state 471, "(1)"
+ line 438, "pan.___", state 479, "(1)"
+ line 438, "pan.___", state 480, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 480, "else"
+ line 438, "pan.___", state 483, "(1)"
+ line 438, "pan.___", state 484, "(1)"
+ line 438, "pan.___", state 484, "(1)"
+ line 436, "pan.___", state 489, "((i<2))"
+ line 436, "pan.___", state 489, "((i>=2))"
+ line 446, "pan.___", state 493, "(1)"
+ line 446, "pan.___", state 493, "(1)"
+ line 1153, "pan.___", state 504, "_proc_urcu_writer = (_proc_urcu_writer&~((1<<9)))"
+ line 1158, "pan.___", state 505, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<8)|(1<<7))))"
+ line 407, "pan.___", state 510, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 516, "(1)"
+ line 411, "pan.___", state 524, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 530, "(1)"
+ line 411, "pan.___", state 531, "(1)"
+ line 411, "pan.___", state 531, "(1)"
+ line 409, "pan.___", state 536, "((i<1))"
+ line 409, "pan.___", state 536, "((i>=1))"
+ line 416, "pan.___", state 542, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 548, "(1)"
+ line 416, "pan.___", state 549, "(1)"
+ line 416, "pan.___", state 549, "(1)"
+ line 420, "pan.___", state 556, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 562, "(1)"
+ line 420, "pan.___", state 563, "(1)"
+ line 420, "pan.___", state 563, "(1)"
+ line 418, "pan.___", state 568, "((i<2))"
+ line 418, "pan.___", state 568, "((i>=2))"
+ line 425, "pan.___", state 575, "(1)"
+ line 425, "pan.___", state 576, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 576, "else"
+ line 425, "pan.___", state 579, "(1)"
+ line 425, "pan.___", state 580, "(1)"
+ line 425, "pan.___", state 580, "(1)"
+ line 429, "pan.___", state 588, "(1)"
+ line 429, "pan.___", state 589, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 589, "else"
+ line 429, "pan.___", state 592, "(1)"
+ line 429, "pan.___", state 593, "(1)"
+ line 429, "pan.___", state 593, "(1)"
+ line 427, "pan.___", state 598, "((i<1))"
+ line 427, "pan.___", state 598, "((i>=1))"
+ line 434, "pan.___", state 605, "(1)"
+ line 434, "pan.___", state 606, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 606, "else"
+ line 434, "pan.___", state 609, "(1)"
+ line 434, "pan.___", state 610, "(1)"
+ line 434, "pan.___", state 610, "(1)"
+ line 438, "pan.___", state 618, "(1)"
+ line 438, "pan.___", state 619, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 619, "else"
+ line 438, "pan.___", state 622, "(1)"
+ line 438, "pan.___", state 623, "(1)"
+ line 438, "pan.___", state 623, "(1)"
+ line 446, "pan.___", state 632, "(1)"
+ line 446, "pan.___", state 632, "(1)"
+ line 407, "pan.___", state 639, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 653, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 671, "cache_dirty_rcu_ptr = 0"
+ line 425, "pan.___", state 704, "(1)"
+ line 429, "pan.___", state 717, "(1)"
+ line 434, "pan.___", state 734, "(1)"
+ line 438, "pan.___", state 747, "(1)"
+ line 411, "pan.___", state 784, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 802, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 816, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 848, "(1)"
+ line 434, "pan.___", state 865, "(1)"
+ line 438, "pan.___", state 878, "(1)"
+ line 1235, "pan.___", state 905, "_proc_urcu_writer = (_proc_urcu_writer|(1<<13))"
+ line 268, "pan.___", state 933, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 935, "(1)"
+ line 272, "pan.___", state 942, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 944, "(1)"
+ line 272, "pan.___", state 945, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 945, "else"
+ line 270, "pan.___", state 950, "((i<1))"
+ line 270, "pan.___", state 950, "((i>=1))"
+ line 276, "pan.___", state 955, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 957, "(1)"
+ line 276, "pan.___", state 958, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 958, "else"
+ line 280, "pan.___", state 964, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 966, "(1)"
+ line 280, "pan.___", state 967, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 967, "else"
+ line 278, "pan.___", state 972, "((i<2))"
+ line 278, "pan.___", state 972, "((i>=2))"
+ line 245, "pan.___", state 980, "(1)"
+ line 249, "pan.___", state 988, "(1)"
+ line 249, "pan.___", state 989, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 989, "else"
+ line 247, "pan.___", state 994, "((i<1))"
+ line 247, "pan.___", state 994, "((i>=1))"
+ line 253, "pan.___", state 1000, "(1)"
+ line 253, "pan.___", state 1001, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1001, "else"
+ line 257, "pan.___", state 1008, "(1)"
+ line 257, "pan.___", state 1009, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1009, "else"
+ line 262, "pan.___", state 1018, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1018, "else"
+ line 1289, "pan.___", state 1034, "((i<1))"
+ line 1289, "pan.___", state 1034, "((i>=1))"
+ line 268, "pan.___", state 1039, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1041, "(1)"
+ line 272, "pan.___", state 1048, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1050, "(1)"
+ line 272, "pan.___", state 1051, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1051, "else"
+ line 270, "pan.___", state 1056, "((i<1))"
+ line 270, "pan.___", state 1056, "((i>=1))"
+ line 276, "pan.___", state 1061, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1063, "(1)"
+ line 276, "pan.___", state 1064, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1064, "else"
+ line 280, "pan.___", state 1070, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1072, "(1)"
+ line 280, "pan.___", state 1073, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1073, "else"
+ line 278, "pan.___", state 1078, "((i<2))"
+ line 278, "pan.___", state 1078, "((i>=2))"
+ line 245, "pan.___", state 1086, "(1)"
+ line 249, "pan.___", state 1094, "(1)"
+ line 249, "pan.___", state 1095, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1095, "else"
+ line 247, "pan.___", state 1100, "((i<1))"
+ line 247, "pan.___", state 1100, "((i>=1))"
+ line 253, "pan.___", state 1106, "(1)"
+ line 253, "pan.___", state 1107, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1107, "else"
+ line 257, "pan.___", state 1114, "(1)"
+ line 257, "pan.___", state 1115, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1115, "else"
+ line 262, "pan.___", state 1124, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1124, "else"
+ line 295, "pan.___", state 1126, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1126, "else"
+ line 1289, "pan.___", state 1127, "(cache_dirty_urcu_gp_ctr)"
+ line 1289, "pan.___", state 1127, "else"
+ line 268, "pan.___", state 1131, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1133, "(1)"
+ line 272, "pan.___", state 1140, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1142, "(1)"
+ line 272, "pan.___", state 1143, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1143, "else"
+ line 270, "pan.___", state 1148, "((i<1))"
+ line 270, "pan.___", state 1148, "((i>=1))"
+ line 276, "pan.___", state 1153, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1155, "(1)"
+ line 276, "pan.___", state 1156, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1156, "else"
+ line 280, "pan.___", state 1162, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1164, "(1)"
+ line 280, "pan.___", state 1165, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1165, "else"
+ line 278, "pan.___", state 1170, "((i<2))"
+ line 278, "pan.___", state 1170, "((i>=2))"
+ line 245, "pan.___", state 1178, "(1)"
+ line 249, "pan.___", state 1186, "(1)"
+ line 249, "pan.___", state 1187, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1187, "else"
+ line 247, "pan.___", state 1192, "((i<1))"
+ line 247, "pan.___", state 1192, "((i>=1))"
+ line 253, "pan.___", state 1198, "(1)"
+ line 253, "pan.___", state 1199, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1199, "else"
+ line 257, "pan.___", state 1206, "(1)"
+ line 257, "pan.___", state 1207, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1207, "else"
+ line 262, "pan.___", state 1216, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1216, "else"
+ line 1293, "pan.___", state 1219, "i = 0"
+ line 1293, "pan.___", state 1221, "reader_barrier = 1"
+ line 1293, "pan.___", state 1232, "((i<1))"
+ line 1293, "pan.___", state 1232, "((i>=1))"
+ line 268, "pan.___", state 1237, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1239, "(1)"
+ line 272, "pan.___", state 1246, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1248, "(1)"
+ line 272, "pan.___", state 1249, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1249, "else"
+ line 270, "pan.___", state 1254, "((i<1))"
+ line 270, "pan.___", state 1254, "((i>=1))"
+ line 276, "pan.___", state 1259, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1261, "(1)"
+ line 276, "pan.___", state 1262, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1262, "else"
+ line 280, "pan.___", state 1268, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1270, "(1)"
+ line 280, "pan.___", state 1271, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1271, "else"
+ line 278, "pan.___", state 1276, "((i<2))"
+ line 278, "pan.___", state 1276, "((i>=2))"
+ line 245, "pan.___", state 1284, "(1)"
+ line 249, "pan.___", state 1292, "(1)"
+ line 249, "pan.___", state 1293, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1293, "else"
+ line 247, "pan.___", state 1298, "((i<1))"
+ line 247, "pan.___", state 1298, "((i>=1))"
+ line 253, "pan.___", state 1304, "(1)"
+ line 253, "pan.___", state 1305, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1305, "else"
+ line 257, "pan.___", state 1312, "(1)"
+ line 257, "pan.___", state 1313, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1313, "else"
+ line 262, "pan.___", state 1322, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1322, "else"
+ line 295, "pan.___", state 1324, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1324, "else"
+ line 1293, "pan.___", state 1325, "(cache_dirty_urcu_gp_ctr)"
+ line 1293, "pan.___", state 1325, "else"
+ line 272, "pan.___", state 1338, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1351, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1360, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1376, "(1)"
+ line 249, "pan.___", state 1384, "(1)"
+ line 253, "pan.___", state 1396, "(1)"
+ line 257, "pan.___", state 1404, "(1)"
+ line 268, "pan.___", state 1435, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1444, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1457, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1466, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1482, "(1)"
+ line 249, "pan.___", state 1490, "(1)"
+ line 253, "pan.___", state 1502, "(1)"
+ line 257, "pan.___", state 1510, "(1)"
+ line 268, "pan.___", state 1527, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1529, "(1)"
+ line 272, "pan.___", state 1536, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1538, "(1)"
+ line 272, "pan.___", state 1539, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1539, "else"
+ line 270, "pan.___", state 1544, "((i<1))"
+ line 270, "pan.___", state 1544, "((i>=1))"
+ line 276, "pan.___", state 1549, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1551, "(1)"
+ line 276, "pan.___", state 1552, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1552, "else"
+ line 280, "pan.___", state 1558, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1560, "(1)"
+ line 280, "pan.___", state 1561, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1561, "else"
+ line 278, "pan.___", state 1566, "((i<2))"
+ line 278, "pan.___", state 1566, "((i>=2))"
+ line 245, "pan.___", state 1574, "(1)"
+ line 249, "pan.___", state 1582, "(1)"
+ line 249, "pan.___", state 1583, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1583, "else"
+ line 247, "pan.___", state 1588, "((i<1))"
+ line 247, "pan.___", state 1588, "((i>=1))"
+ line 253, "pan.___", state 1594, "(1)"
+ line 253, "pan.___", state 1595, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1595, "else"
+ line 257, "pan.___", state 1602, "(1)"
+ line 257, "pan.___", state 1603, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1603, "else"
+ line 262, "pan.___", state 1612, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1612, "else"
+ line 1300, "pan.___", state 1615, "i = 0"
+ line 1300, "pan.___", state 1617, "reader_barrier = 1"
+ line 1300, "pan.___", state 1628, "((i<1))"
+ line 1300, "pan.___", state 1628, "((i>=1))"
+ line 268, "pan.___", state 1633, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1635, "(1)"
+ line 272, "pan.___", state 1642, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1644, "(1)"
+ line 272, "pan.___", state 1645, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1645, "else"
+ line 270, "pan.___", state 1650, "((i<1))"
+ line 270, "pan.___", state 1650, "((i>=1))"
+ line 276, "pan.___", state 1655, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1657, "(1)"
+ line 276, "pan.___", state 1658, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1658, "else"
+ line 280, "pan.___", state 1664, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1666, "(1)"
+ line 280, "pan.___", state 1667, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1667, "else"
+ line 278, "pan.___", state 1672, "((i<2))"
+ line 278, "pan.___", state 1672, "((i>=2))"
+ line 245, "pan.___", state 1680, "(1)"
+ line 249, "pan.___", state 1688, "(1)"
+ line 249, "pan.___", state 1689, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1689, "else"
+ line 247, "pan.___", state 1694, "((i<1))"
+ line 247, "pan.___", state 1694, "((i>=1))"
+ line 253, "pan.___", state 1700, "(1)"
+ line 253, "pan.___", state 1701, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1701, "else"
+ line 257, "pan.___", state 1708, "(1)"
+ line 257, "pan.___", state 1709, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1709, "else"
+ line 262, "pan.___", state 1718, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1718, "else"
+ line 295, "pan.___", state 1720, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1720, "else"
+ line 1300, "pan.___", state 1721, "(cache_dirty_urcu_gp_ctr)"
+ line 1300, "pan.___", state 1721, "else"
+ line 1304, "pan.___", state 1724, "-end-"
+ (312 of 1724 states)
+unreached in proctype :init:
+ line 1319, "pan.___", state 13, "((i<1))"
+ line 1319, "pan.___", state 13, "((i>=1))"
+ (1 of 28 states)
+unreached in proctype :never:
+ line 1367, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 792 seconds
+pan: rate 3330.8797 states/second
+pan: avg transition delay 1.5481e-06 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+#define NO_MB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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+1478:1:1346
+1479:1:1347
+1480:0:4652
+1481:2:3824
+1482:0:4658
+1483:1:2492
--- /dev/null
+#define NO_RMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+Depth= 8300 States= 1e+06 Transitions= 1.86e+08 Memory= 513.029 t= 280 R= 4e+03
+Depth= 10044 States= 2e+06 Transitions= 3.84e+08 Memory= 559.221 t= 594 R= 3e+03
+Depth= 10044 States= 3e+06 Transitions= 6.04e+08 Memory= 605.803 t= 964 R= 3e+03
+pan: resizing hashtable to -w22.. done
+Depth= 10044 States= 4e+06 Transitions= 8.01e+08 Memory= 682.920 t= 1.27e+03 R= 3e+03
+Depth= 10044 States= 5e+06 Transitions= 9.95e+08 Memory= 728.721 t= 1.57e+03 R= 3e+03
+Depth= 10044 States= 6e+06 Transitions= 1.26e+09 Memory= 775.010 t= 1.99e+03 R= 3e+03
+Depth= 10044 States= 7e+06 Transitions= 1.79e+09 Memory= 821.592 t= 2.89e+03 R= 2e+03
+Depth= 10044 States= 8e+06 Transitions= 2.16e+09 Memory= 867.979 t= 3.5e+03 R= 2e+03
+Depth= 10044 States= 9e+06 Transitions= 2.51e+09 Memory= 914.072 t= 4.1e+03 R= 2e+03
+pan: resizing hashtable to -w24.. done
+Depth= 10044 States= 1e+07 Transitions= 2.87e+09 Memory= 1085.334 t= 4.67e+03 R= 2e+03
+Depth= 10044 States= 1.1e+07 Transitions= 3.27e+09 Memory= 1132.404 t= 5.29e+03 R= 2e+03
+Depth= 10044 States= 1.2e+07 Transitions= 3.66e+09 Memory= 1179.377 t= 5.91e+03 R= 2e+03
+pan: claim violated! (at depth 1680)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 10044, errors: 1
+ 12387044 states, stored
+3.7683983e+09 states, matched
+3.7807853e+09 transitions (= stored+matched)
+2.0718621e+10 atomic steps
+hash conflicts: 2.2091218e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1370.332 equivalent memory usage for states (stored*(State-vector + overhead))
+ 612.258 actual memory usage for states (compression: 44.68%)
+ state-vector as stored = 16 byte + 36 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1197.736 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 166228 1420 961 2 2 ]
+unreached in proctype urcu_reader
+ line 894, "pan.___", state 12, "((i<1))"
+ line 894, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 223, "(1)"
+ line 434, "pan.___", state 253, "(1)"
+ line 438, "pan.___", state 266, "(1)"
+ line 687, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 359, "(1)"
+ line 434, "pan.___", state 389, "(1)"
+ line 438, "pan.___", state 402, "(1)"
+ line 407, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 488, "(1)"
+ line 434, "pan.___", state 518, "(1)"
+ line 438, "pan.___", state 531, "(1)"
+ line 407, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 556, "(1)"
+ line 407, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 557, "else"
+ line 407, "pan.___", state 560, "(1)"
+ line 411, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 570, "(1)"
+ line 411, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 571, "else"
+ line 411, "pan.___", state 574, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 409, "pan.___", state 580, "((i<1))"
+ line 409, "pan.___", state 580, "((i>=1))"
+ line 416, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 588, "(1)"
+ line 416, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 589, "else"
+ line 416, "pan.___", state 592, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 420, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 602, "(1)"
+ line 420, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 603, "else"
+ line 420, "pan.___", state 606, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 418, "pan.___", state 612, "((i<2))"
+ line 418, "pan.___", state 612, "((i>=2))"
+ line 425, "pan.___", state 619, "(1)"
+ line 425, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 620, "else"
+ line 425, "pan.___", state 623, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 429, "pan.___", state 632, "(1)"
+ line 429, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 633, "else"
+ line 429, "pan.___", state 636, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 427, "pan.___", state 642, "((i<1))"
+ line 427, "pan.___", state 642, "((i>=1))"
+ line 434, "pan.___", state 649, "(1)"
+ line 434, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 650, "else"
+ line 434, "pan.___", state 653, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 438, "pan.___", state 662, "(1)"
+ line 438, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 663, "else"
+ line 438, "pan.___", state 666, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 436, "pan.___", state 672, "((i<2))"
+ line 436, "pan.___", state 672, "((i>=2))"
+ line 446, "pan.___", state 676, "(1)"
+ line 446, "pan.___", state 676, "(1)"
+ line 687, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 681, "(1)"
+ line 407, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 753, "(1)"
+ line 434, "pan.___", state 783, "(1)"
+ line 438, "pan.___", state 796, "(1)"
+ line 407, "pan.___", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 856, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 889, "(1)"
+ line 434, "pan.___", state 919, "(1)"
+ line 438, "pan.___", state 932, "(1)"
+ line 407, "pan.___", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 955, "(1)"
+ line 407, "pan.___", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 956, "else"
+ line 407, "pan.___", state 959, "(1)"
+ line 411, "pan.___", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 969, "(1)"
+ line 411, "pan.___", state 970, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 970, "else"
+ line 411, "pan.___", state 973, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 409, "pan.___", state 979, "((i<1))"
+ line 409, "pan.___", state 979, "((i>=1))"
+ line 416, "pan.___", state 985, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 987, "(1)"
+ line 416, "pan.___", state 988, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 988, "else"
+ line 416, "pan.___", state 991, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 420, "pan.___", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 1001, "(1)"
+ line 420, "pan.___", state 1002, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 1002, "else"
+ line 420, "pan.___", state 1005, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 418, "pan.___", state 1011, "((i<2))"
+ line 418, "pan.___", state 1011, "((i>=2))"
+ line 425, "pan.___", state 1018, "(1)"
+ line 425, "pan.___", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 1019, "else"
+ line 425, "pan.___", state 1022, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 429, "pan.___", state 1031, "(1)"
+ line 429, "pan.___", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 1032, "else"
+ line 429, "pan.___", state 1035, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 427, "pan.___", state 1041, "((i<1))"
+ line 427, "pan.___", state 1041, "((i>=1))"
+ line 434, "pan.___", state 1048, "(1)"
+ line 434, "pan.___", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 1049, "else"
+ line 434, "pan.___", state 1052, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 438, "pan.___", state 1061, "(1)"
+ line 438, "pan.___", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 1062, "else"
+ line 438, "pan.___", state 1065, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 436, "pan.___", state 1071, "((i<2))"
+ line 436, "pan.___", state 1071, "((i>=2))"
+ line 446, "pan.___", state 1075, "(1)"
+ line 446, "pan.___", state 1075, "(1)"
+ line 695, "pan.___", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1149, "(1)"
+ line 434, "pan.___", state 1179, "(1)"
+ line 438, "pan.___", state 1192, "(1)"
+ line 407, "pan.___", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1281, "(1)"
+ line 434, "pan.___", state 1311, "(1)"
+ line 438, "pan.___", state 1324, "(1)"
+ line 407, "pan.___", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1414, "(1)"
+ line 434, "pan.___", state 1444, "(1)"
+ line 438, "pan.___", state 1457, "(1)"
+ line 407, "pan.___", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1543, "(1)"
+ line 434, "pan.___", state 1573, "(1)"
+ line 438, "pan.___", state 1586, "(1)"
+ line 407, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1677, "(1)"
+ line 434, "pan.___", state 1707, "(1)"
+ line 438, "pan.___", state 1720, "(1)"
+ line 407, "pan.___", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1806, "(1)"
+ line 434, "pan.___", state 1836, "(1)"
+ line 438, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1938, "(1)"
+ line 434, "pan.___", state 1968, "(1)"
+ line 438, "pan.___", state 1981, "(1)"
+ line 734, "pan.___", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2074, "(1)"
+ line 434, "pan.___", state 2104, "(1)"
+ line 438, "pan.___", state 2117, "(1)"
+ line 407, "pan.___", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2203, "(1)"
+ line 434, "pan.___", state 2233, "(1)"
+ line 438, "pan.___", state 2246, "(1)"
+ line 407, "pan.___", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 2271, "(1)"
+ line 407, "pan.___", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 2272, "else"
+ line 407, "pan.___", state 2275, "(1)"
+ line 411, "pan.___", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 2286, "else"
+ line 411, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 409, "pan.___", state 2295, "((i<1))"
+ line 409, "pan.___", state 2295, "((i>=1))"
+ line 416, "pan.___", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2303, "(1)"
+ line 416, "pan.___", state 2304, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2304, "else"
+ line 416, "pan.___", state 2307, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 420, "pan.___", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2317, "(1)"
+ line 420, "pan.___", state 2318, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2318, "else"
+ line 420, "pan.___", state 2321, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 418, "pan.___", state 2327, "((i<2))"
+ line 418, "pan.___", state 2327, "((i>=2))"
+ line 425, "pan.___", state 2334, "(1)"
+ line 425, "pan.___", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 2335, "else"
+ line 425, "pan.___", state 2338, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 429, "pan.___", state 2347, "(1)"
+ line 429, "pan.___", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 2348, "else"
+ line 429, "pan.___", state 2351, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 427, "pan.___", state 2357, "((i<1))"
+ line 427, "pan.___", state 2357, "((i>=1))"
+ line 434, "pan.___", state 2364, "(1)"
+ line 434, "pan.___", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 2365, "else"
+ line 434, "pan.___", state 2368, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 438, "pan.___", state 2377, "(1)"
+ line 438, "pan.___", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 2378, "else"
+ line 438, "pan.___", state 2381, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 436, "pan.___", state 2387, "((i<2))"
+ line 436, "pan.___", state 2387, "((i>=2))"
+ line 446, "pan.___", state 2391, "(1)"
+ line 446, "pan.___", state 2391, "(1)"
+ line 734, "pan.___", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2396, "(1)"
+ line 407, "pan.___", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2468, "(1)"
+ line 434, "pan.___", state 2498, "(1)"
+ line 438, "pan.___", state 2511, "(1)"
+ line 407, "pan.___", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2603, "(1)"
+ line 434, "pan.___", state 2633, "(1)"
+ line 438, "pan.___", state 2646, "(1)"
+ line 407, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2732, "(1)"
+ line 434, "pan.___", state 2762, "(1)"
+ line 438, "pan.___", state 2775, "(1)"
+ line 407, "pan.___", state 2808, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2840, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2854, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2873, "(1)"
+ line 434, "pan.___", state 2903, "(1)"
+ line 438, "pan.___", state 2916, "(1)"
+ line 407, "pan.___", state 2935, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2967, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2981, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 3000, "(1)"
+ line 434, "pan.___", state 3030, "(1)"
+ line 438, "pan.___", state 3043, "(1)"
+ line 929, "pan.___", state 3064, "-end-"
+ (252 of 3064 states)
+unreached in proctype urcu_writer
+ line 1018, "pan.___", state 12, "((i<1))"
+ line 1018, "pan.___", state 12, "((i>=1))"
+ line 407, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 51, "(1)"
+ line 411, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 65, "(1)"
+ line 411, "pan.___", state 66, "(1)"
+ line 411, "pan.___", state 66, "(1)"
+ line 409, "pan.___", state 71, "((i<1))"
+ line 409, "pan.___", state 71, "((i>=1))"
+ line 416, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 83, "(1)"
+ line 416, "pan.___", state 84, "(1)"
+ line 416, "pan.___", state 84, "(1)"
+ line 420, "pan.___", state 97, "(1)"
+ line 420, "pan.___", state 98, "(1)"
+ line 420, "pan.___", state 98, "(1)"
+ line 418, "pan.___", state 103, "((i<2))"
+ line 418, "pan.___", state 103, "((i>=2))"
+ line 425, "pan.___", state 110, "(1)"
+ line 425, "pan.___", state 111, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 111, "else"
+ line 425, "pan.___", state 114, "(1)"
+ line 425, "pan.___", state 115, "(1)"
+ line 425, "pan.___", state 115, "(1)"
+ line 429, "pan.___", state 123, "(1)"
+ line 429, "pan.___", state 124, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 124, "else"
+ line 429, "pan.___", state 127, "(1)"
+ line 429, "pan.___", state 128, "(1)"
+ line 429, "pan.___", state 128, "(1)"
+ line 427, "pan.___", state 133, "((i<1))"
+ line 427, "pan.___", state 133, "((i>=1))"
+ line 434, "pan.___", state 140, "(1)"
+ line 434, "pan.___", state 141, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 141, "else"
+ line 434, "pan.___", state 144, "(1)"
+ line 434, "pan.___", state 145, "(1)"
+ line 434, "pan.___", state 145, "(1)"
+ line 438, "pan.___", state 153, "(1)"
+ line 438, "pan.___", state 154, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 154, "else"
+ line 438, "pan.___", state 157, "(1)"
+ line 438, "pan.___", state 158, "(1)"
+ line 438, "pan.___", state 158, "(1)"
+ line 436, "pan.___", state 163, "((i<2))"
+ line 436, "pan.___", state 163, "((i>=2))"
+ line 446, "pan.___", state 167, "(1)"
+ line 446, "pan.___", state 167, "(1)"
+ line 268, "pan.___", state 176, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 185, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 198, "cache_dirty_rcu_ptr = 0"
+ line 407, "pan.___", state 238, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 252, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 270, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 284, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 303, "(1)"
+ line 429, "pan.___", state 316, "(1)"
+ line 434, "pan.___", state 333, "(1)"
+ line 438, "pan.___", state 346, "(1)"
+ line 411, "pan.___", state 383, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 401, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 415, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 447, "(1)"
+ line 434, "pan.___", state 464, "(1)"
+ line 438, "pan.___", state 477, "(1)"
+ line 411, "pan.___", state 522, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 540, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 554, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 586, "(1)"
+ line 434, "pan.___", state 603, "(1)"
+ line 438, "pan.___", state 616, "(1)"
+ line 411, "pan.___", state 651, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 669, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 715, "(1)"
+ line 434, "pan.___", state 732, "(1)"
+ line 438, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 782, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 800, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 814, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 846, "(1)"
+ line 434, "pan.___", state 863, "(1)"
+ line 438, "pan.___", state 876, "(1)"
+ line 268, "pan.___", state 931, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 940, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 955, "(1)"
+ line 280, "pan.___", state 962, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 978, "(1)"
+ line 249, "pan.___", state 986, "(1)"
+ line 253, "pan.___", state 998, "(1)"
+ line 257, "pan.___", state 1006, "(1)"
+ line 268, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1046, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1059, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1068, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1084, "(1)"
+ line 249, "pan.___", state 1092, "(1)"
+ line 253, "pan.___", state 1104, "(1)"
+ line 257, "pan.___", state 1112, "(1)"
+ line 272, "pan.___", state 1138, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1151, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1160, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1176, "(1)"
+ line 249, "pan.___", state 1184, "(1)"
+ line 253, "pan.___", state 1196, "(1)"
+ line 257, "pan.___", state 1204, "(1)"
+ line 268, "pan.___", state 1235, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1244, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1257, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1282, "(1)"
+ line 249, "pan.___", state 1290, "(1)"
+ line 253, "pan.___", state 1302, "(1)"
+ line 257, "pan.___", state 1310, "(1)"
+ line 272, "pan.___", state 1336, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1349, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1358, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1374, "(1)"
+ line 249, "pan.___", state 1382, "(1)"
+ line 253, "pan.___", state 1394, "(1)"
+ line 257, "pan.___", state 1402, "(1)"
+ line 268, "pan.___", state 1433, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1442, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1455, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1464, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1480, "(1)"
+ line 249, "pan.___", state 1488, "(1)"
+ line 253, "pan.___", state 1500, "(1)"
+ line 257, "pan.___", state 1508, "(1)"
+ line 272, "pan.___", state 1534, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1547, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1556, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1572, "(1)"
+ line 249, "pan.___", state 1580, "(1)"
+ line 253, "pan.___", state 1592, "(1)"
+ line 257, "pan.___", state 1600, "(1)"
+ line 268, "pan.___", state 1631, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1640, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1653, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1678, "(1)"
+ line 249, "pan.___", state 1686, "(1)"
+ line 253, "pan.___", state 1698, "(1)"
+ line 257, "pan.___", state 1706, "(1)"
+ line 1304, "pan.___", state 1722, "-end-"
+ (129 of 1722 states)
+unreached in proctype :init:
+ line 1319, "pan.___", state 13, "((i<1))"
+ line 1319, "pan.___", state 13, "((i>=1))"
+ (1 of 28 states)
+unreached in proctype :never:
+ line 1367, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 6.09e+03 seconds
+pan: rate 2033.9606 states/second
+pan: avg transition delay 1.6108e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+#define NO_RMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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--- /dev/null
+#define NO_WMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+Depth= 8002 States= 1e+06 Transitions= 1.77e+08 Memory= 513.029 t= 264 R= 4e+03
+Depth= 9746 States= 2e+06 Transitions= 3.71e+08 Memory= 559.318 t= 570 R= 4e+03
+Depth= 9746 States= 3e+06 Transitions= 5.8e+08 Memory= 605.901 t= 916 R= 3e+03
+pan: resizing hashtable to -w22.. done
+Depth= 9746 States= 4e+06 Transitions= 7.6e+08 Memory= 682.920 t= 1.19e+03 R= 3e+03
+Depth= 9746 States= 5e+06 Transitions= 9.44e+08 Memory= 728.721 t= 1.47e+03 R= 3e+03
+Depth= 9746 States= 6e+06 Transitions= 1.35e+09 Memory= 775.303 t= 2.12e+03 R= 3e+03
+Depth= 9746 States= 7e+06 Transitions= 1.79e+09 Memory= 821.885 t= 2.84e+03 R= 2e+03
+Depth= 9746 States= 8e+06 Transitions= 2.11e+09 Memory= 868.076 t= 3.35e+03 R= 2e+03
+Depth= 9746 States= 9e+06 Transitions= 2.49e+09 Memory= 914.658 t= 3.99e+03 R= 2e+03
+pan: resizing hashtable to -w24.. done
+Depth= 9746 States= 1e+07 Transitions= 2.83e+09 Memory= 1085.529 t= 4.5e+03 R= 2e+03
+Depth= 9746 States= 1.1e+07 Transitions= 3.2e+09 Memory= 1132.795 t= 5.06e+03 R= 2e+03
+Depth= 9746 States= 1.2e+07 Transitions= 3.59e+09 Memory= 1179.670 t= 5.66e+03 R= 2e+03
+Depth= 9746 States= 1.3e+07 Transitions= 3.78e+09 Memory= 1226.447 t= 5.95e+03 R= 2e+03
+Depth= 9746 States= 1.4e+07 Transitions= 3.96e+09 Memory= 1272.346 t= 6.23e+03 R= 2e+03
+Depth= 9746 States= 1.5e+07 Transitions= 4.17e+09 Memory= 1318.440 t= 6.56e+03 R= 2e+03
+Depth= 9746 States= 1.6e+07 Transitions= 4.37e+09 Memory= 1364.338 t= 6.86e+03 R= 2e+03
+Depth= 9746 States= 1.7e+07 Transitions= 4.55e+09 Memory= 1410.139 t= 7.14e+03 R= 2e+03
+Depth= 9746 States= 1.8e+07 Transitions= 4.8e+09 Memory= 1456.135 t= 7.53e+03 R= 2e+03
+Depth= 9746 States= 1.9e+07 Transitions= 5.2e+09 Memory= 1502.326 t= 8.17e+03 R= 2e+03
+Depth= 9746 States= 2e+07 Transitions= 5.67e+09 Memory= 1548.615 t= 8.94e+03 R= 2e+03
+Depth= 9746 States= 2.1e+07 Transitions= 6.01e+09 Memory= 1594.611 t= 9.49e+03 R= 2e+03
+Depth= 9746 States= 2.2e+07 Transitions= 6.42e+09 Memory= 1640.998 t= 1.01e+04 R= 2e+03
+Depth= 9746 States= 2.3e+07 Transitions= 6.67e+09 Memory= 1687.580 t= 1.05e+04 R= 2e+03
+Depth= 9746 States= 2.4e+07 Transitions= 6.96e+09 Memory= 1733.674 t= 1.1e+04 R= 2e+03
+Depth= 9746 States= 2.5e+07 Transitions= 7.2e+09 Memory= 1779.865 t= 1.14e+04 R= 2e+03
+Depth= 9746 States= 2.6e+07 Transitions= 7.61e+09 Memory= 1826.154 t= 1.2e+04 R= 2e+03
+Depth= 9746 States= 2.7e+07 Transitions= 8.36e+09 Memory= 1872.248 t= 1.32e+04 R= 2e+03
+Depth= 9746 States= 2.8e+07 Transitions= 9.08e+09 Memory= 1918.733 t= 1.44e+04 R= 2e+03
+Depth= 9746 States= 2.9e+07 Transitions= 9.48e+09 Memory= 1965.608 t= 1.51e+04 R= 2e+03
+Depth= 9746 States= 3e+07 Transitions= 9.94e+09 Memory= 2012.483 t= 1.58e+04 R= 2e+03
+Depth= 9746 States= 3.1e+07 Transitions= 1.02e+10 Memory= 2058.576 t= 1.62e+04 R= 2e+03
+Depth= 9746 States= 3.2e+07 Transitions= 1.05e+10 Memory= 2104.475 t= 1.67e+04 R= 2e+03
+Depth= 9746 States= 3.3e+07 Transitions= 1.08e+10 Memory= 2150.373 t= 1.72e+04 R= 2e+03
+Depth= 9746 States= 3.4e+07 Transitions= 1.15e+10 Memory= 2196.369 t= 1.84e+04 R= 2e+03
+pan: resizing hashtable to -w26.. done
+Depth= 9746 States= 3.5e+07 Transitions= 1.22e+10 Memory= 2738.350 t= 1.96e+04 R= 2e+03
+Depth= 9746 States= 3.6e+07 Transitions= 1.27e+10 Memory= 2784.639 t= 2.03e+04 R= 2e+03
+Depth= 9746 States= 3.7e+07 Transitions= 1.29e+10 Memory= 2831.026 t= 2.07e+04 R= 2e+03
+Depth= 9746 States= 3.8e+07 Transitions= 1.34e+10 Memory= 2877.510 t= 2.14e+04 R= 2e+03
+Depth= 9746 States= 3.9e+07 Transitions= 1.39e+10 Memory= 2923.701 t= 2.21e+04 R= 2e+03
+Depth= 9746 States= 4e+07 Transitions= 1.44e+10 Memory= 2969.697 t= 2.29e+04 R= 2e+03
+Depth= 9746 States= 4.1e+07 Transitions= 1.48e+10 Memory= 3015.889 t= 2.36e+04 R= 2e+03
+Depth= 9746 States= 4.2e+07 Transitions= 1.52e+10 Memory= 3061.787 t= 2.42e+04 R= 2e+03
+Depth= 9746 States= 4.3e+07 Transitions= 1.57e+10 Memory= 3107.979 t= 2.5e+04 R= 2e+03
+Depth= 9746 States= 4.4e+07 Transitions= 1.61e+10 Memory= 3153.779 t= 2.56e+04 R= 2e+03
+Depth= 9746 States= 4.5e+07 Transitions= 1.64e+10 Memory= 3199.873 t= 2.6e+04 R= 2e+03
+Depth= 9746 States= 4.6e+07 Transitions= 1.68e+10 Memory= 3245.967 t= 2.66e+04 R= 2e+03
+Depth= 9746 States= 4.7e+07 Transitions= 1.7e+10 Memory= 3291.865 t= 2.7e+04 R= 2e+03
+Depth= 9746 States= 4.8e+07 Transitions= 1.74e+10 Memory= 3338.057 t= 2.75e+04 R= 2e+03
+Depth= 9746 States= 4.9e+07 Transitions= 1.79e+10 Memory= 3384.151 t= 2.83e+04 R= 2e+03
+Depth= 9868 States= 5e+07 Transitions= 1.82e+10 Memory= 3429.951 t= 2.88e+04 R= 2e+03
+Depth= 9912 States= 5.1e+07 Transitions= 1.86e+10 Memory= 3475.752 t= 2.94e+04 R= 2e+03
+Depth= 9912 States= 5.2e+07 Transitions= 1.89e+10 Memory= 3521.553 t= 2.99e+04 R= 2e+03
+Depth= 9912 States= 5.3e+07 Transitions= 1.93e+10 Memory= 3567.256 t= 3.05e+04 R= 2e+03
+Depth= 9912 States= 5.4e+07 Transitions= 1.96e+10 Memory= 3613.154 t= 3.1e+04 R= 2e+03
+Depth= 9912 States= 5.5e+07 Transitions= 2e+10 Memory= 3659.053 t= 3.16e+04 R= 2e+03
+Depth= 9912 States= 5.6e+07 Transitions= 2.03e+10 Memory= 3704.756 t= 3.2e+04 R= 2e+03
+Depth= 9912 States= 5.7e+07 Transitions= 2.06e+10 Memory= 3750.557 t= 3.25e+04 R= 2e+03
+Depth= 9912 States= 5.8e+07 Transitions= 2.1e+10 Memory= 3796.455 t= 3.31e+04 R= 2e+03
+Depth= 9912 States= 5.9e+07 Transitions= 2.13e+10 Memory= 3842.256 t= 3.37e+04 R= 2e+03
+Depth= 9912 States= 6e+07 Transitions= 2.16e+10 Memory= 3888.057 t= 3.42e+04 R= 2e+03
+Depth= 9912 States= 6.1e+07 Transitions= 2.2e+10 Memory= 3933.858 t= 3.47e+04 R= 2e+03
+Depth= 9912 States= 6.2e+07 Transitions= 2.23e+10 Memory= 3979.658 t= 3.52e+04 R= 2e+03
+Depth= 9912 States= 6.3e+07 Transitions= 2.27e+10 Memory= 4025.459 t= 3.58e+04 R= 2e+03
+Depth= 9912 States= 6.4e+07 Transitions= 2.3e+10 Memory= 4071.260 t= 3.63e+04 R= 2e+03
+Depth= 9912 States= 6.5e+07 Transitions= 2.33e+10 Memory= 4116.963 t= 3.69e+04 R= 2e+03
+Depth= 9912 States= 6.6e+07 Transitions= 2.36e+10 Memory= 4162.764 t= 3.73e+04 R= 2e+03
+Depth= 9912 States= 6.7e+07 Transitions= 2.39e+10 Memory= 4208.565 t= 3.78e+04 R= 2e+03
+Depth= 9912 States= 6.8e+07 Transitions= 2.42e+10 Memory= 4254.463 t= 3.83e+04 R= 2e+03
+Depth= 9912 States= 6.9e+07 Transitions= 2.46e+10 Memory= 4300.361 t= 3.88e+04 R= 2e+03
+Depth= 9912 States= 7e+07 Transitions= 2.5e+10 Memory= 4346.553 t= 3.94e+04 R= 2e+03
+Depth= 9912 States= 7.1e+07 Transitions= 2.53e+10 Memory= 4392.354 t= 4e+04 R= 2e+03
+Depth= 9912 States= 7.2e+07 Transitions= 2.58e+10 Memory= 4438.252 t= 4.07e+04 R= 2e+03
+Depth= 9912 States= 7.3e+07 Transitions= 2.61e+10 Memory= 4484.151 t= 4.12e+04 R= 2e+03
+Depth= 9912 States= 7.4e+07 Transitions= 2.66e+10 Memory= 4530.635 t= 4.19e+04 R= 2e+03
+Depth= 9912 States= 7.5e+07 Transitions= 2.69e+10 Memory= 4577.315 t= 4.25e+04 R= 2e+03
+Depth= 9912 States= 7.6e+07 Transitions= 2.74e+10 Memory= 4623.897 t= 4.32e+04 R= 2e+03
+Depth= 9912 States= 7.7e+07 Transitions= 2.78e+10 Memory= 4669.893 t= 4.39e+04 R= 2e+03
+Depth= 9912 States= 7.8e+07 Transitions= 2.82e+10 Memory= 4716.084 t= 4.45e+04 R= 2e+03
+Depth= 9912 States= 7.9e+07 Transitions= 2.85e+10 Memory= 4762.568 t= 4.5e+04 R= 2e+03
+Depth= 9912 States= 8e+07 Transitions= 2.87e+10 Memory= 4808.369 t= 4.52e+04 R= 2e+03
+Depth= 9912 States= 8.1e+07 Transitions= 2.89e+10 Memory= 4854.170 t= 4.56e+04 R= 2e+03
+Depth= 9912 States= 8.2e+07 Transitions= 2.91e+10 Memory= 4899.971 t= 4.59e+04 R= 2e+03
+Depth= 9912 States= 8.3e+07 Transitions= 2.93e+10 Memory= 4945.772 t= 4.61e+04 R= 2e+03
+Depth= 9912 States= 8.4e+07 Transitions= 2.95e+10 Memory= 4991.475 t= 4.64e+04 R= 2e+03
+Depth= 9912 States= 8.5e+07 Transitions= 2.99e+10 Memory= 5037.276 t= 4.71e+04 R= 2e+03
+Depth= 9912 States= 8.6e+07 Transitions= 3.03e+10 Memory= 5083.076 t= 4.78e+04 R= 2e+03
+Depth= 9912 States= 8.7e+07 Transitions= 3.07e+10 Memory= 5128.877 t= 4.83e+04 R= 2e+03
+pan: claim violated! (at depth 1530)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 9912, errors: 1
+ 87915830 states, stored
+3.0918075e+10 states, matched
+3.100599e+10 transitions (= stored+matched)
+1.742054e+11 atomic steps
+hash conflicts: 1.5948958e+10 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 9725.796 equivalent memory usage for states (stored*(State-vector + overhead))
+ 4202.002 actual memory usage for states (compression: 43.20%)
+ state-vector as stored = 14 byte + 36 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 5170.869 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 517357 4332 4682 2 2 ]
+unreached in proctype urcu_reader
+ line 894, "pan.___", state 12, "((i<1))"
+ line 894, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 223, "(1)"
+ line 434, "pan.___", state 253, "(1)"
+ line 438, "pan.___", state 266, "(1)"
+ line 687, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 359, "(1)"
+ line 434, "pan.___", state 389, "(1)"
+ line 438, "pan.___", state 402, "(1)"
+ line 407, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 488, "(1)"
+ line 434, "pan.___", state 518, "(1)"
+ line 438, "pan.___", state 531, "(1)"
+ line 407, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 556, "(1)"
+ line 407, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 557, "else"
+ line 407, "pan.___", state 560, "(1)"
+ line 411, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 570, "(1)"
+ line 411, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 571, "else"
+ line 411, "pan.___", state 574, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 409, "pan.___", state 580, "((i<1))"
+ line 409, "pan.___", state 580, "((i>=1))"
+ line 416, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 588, "(1)"
+ line 416, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 589, "else"
+ line 416, "pan.___", state 592, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 420, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 602, "(1)"
+ line 420, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 603, "else"
+ line 420, "pan.___", state 606, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 418, "pan.___", state 612, "((i<2))"
+ line 418, "pan.___", state 612, "((i>=2))"
+ line 425, "pan.___", state 619, "(1)"
+ line 425, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 620, "else"
+ line 425, "pan.___", state 623, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 429, "pan.___", state 632, "(1)"
+ line 429, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 633, "else"
+ line 429, "pan.___", state 636, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 427, "pan.___", state 642, "((i<1))"
+ line 427, "pan.___", state 642, "((i>=1))"
+ line 434, "pan.___", state 649, "(1)"
+ line 434, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 650, "else"
+ line 434, "pan.___", state 653, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 438, "pan.___", state 662, "(1)"
+ line 438, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 663, "else"
+ line 438, "pan.___", state 666, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 436, "pan.___", state 672, "((i<2))"
+ line 436, "pan.___", state 672, "((i>=2))"
+ line 446, "pan.___", state 676, "(1)"
+ line 446, "pan.___", state 676, "(1)"
+ line 687, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 681, "(1)"
+ line 407, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 753, "(1)"
+ line 434, "pan.___", state 783, "(1)"
+ line 438, "pan.___", state 796, "(1)"
+ line 407, "pan.___", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 856, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 889, "(1)"
+ line 434, "pan.___", state 919, "(1)"
+ line 438, "pan.___", state 932, "(1)"
+ line 407, "pan.___", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 955, "(1)"
+ line 407, "pan.___", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 956, "else"
+ line 407, "pan.___", state 959, "(1)"
+ line 411, "pan.___", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 969, "(1)"
+ line 411, "pan.___", state 970, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 970, "else"
+ line 411, "pan.___", state 973, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 409, "pan.___", state 979, "((i<1))"
+ line 409, "pan.___", state 979, "((i>=1))"
+ line 416, "pan.___", state 985, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 987, "(1)"
+ line 416, "pan.___", state 988, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 988, "else"
+ line 416, "pan.___", state 991, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 420, "pan.___", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 1001, "(1)"
+ line 420, "pan.___", state 1002, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 1002, "else"
+ line 420, "pan.___", state 1005, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 418, "pan.___", state 1011, "((i<2))"
+ line 418, "pan.___", state 1011, "((i>=2))"
+ line 425, "pan.___", state 1018, "(1)"
+ line 425, "pan.___", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 1019, "else"
+ line 425, "pan.___", state 1022, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 429, "pan.___", state 1031, "(1)"
+ line 429, "pan.___", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 1032, "else"
+ line 429, "pan.___", state 1035, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 427, "pan.___", state 1041, "((i<1))"
+ line 427, "pan.___", state 1041, "((i>=1))"
+ line 434, "pan.___", state 1048, "(1)"
+ line 434, "pan.___", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 1049, "else"
+ line 434, "pan.___", state 1052, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 438, "pan.___", state 1061, "(1)"
+ line 438, "pan.___", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 1062, "else"
+ line 438, "pan.___", state 1065, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 436, "pan.___", state 1071, "((i<2))"
+ line 436, "pan.___", state 1071, "((i>=2))"
+ line 446, "pan.___", state 1075, "(1)"
+ line 446, "pan.___", state 1075, "(1)"
+ line 695, "pan.___", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1149, "(1)"
+ line 434, "pan.___", state 1179, "(1)"
+ line 438, "pan.___", state 1192, "(1)"
+ line 407, "pan.___", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1281, "(1)"
+ line 434, "pan.___", state 1311, "(1)"
+ line 438, "pan.___", state 1324, "(1)"
+ line 407, "pan.___", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1414, "(1)"
+ line 434, "pan.___", state 1444, "(1)"
+ line 438, "pan.___", state 1457, "(1)"
+ line 407, "pan.___", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1543, "(1)"
+ line 434, "pan.___", state 1573, "(1)"
+ line 438, "pan.___", state 1586, "(1)"
+ line 407, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1677, "(1)"
+ line 434, "pan.___", state 1707, "(1)"
+ line 438, "pan.___", state 1720, "(1)"
+ line 407, "pan.___", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1806, "(1)"
+ line 434, "pan.___", state 1836, "(1)"
+ line 438, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1938, "(1)"
+ line 434, "pan.___", state 1968, "(1)"
+ line 438, "pan.___", state 1981, "(1)"
+ line 734, "pan.___", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2074, "(1)"
+ line 434, "pan.___", state 2104, "(1)"
+ line 438, "pan.___", state 2117, "(1)"
+ line 407, "pan.___", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2203, "(1)"
+ line 434, "pan.___", state 2233, "(1)"
+ line 438, "pan.___", state 2246, "(1)"
+ line 407, "pan.___", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 2271, "(1)"
+ line 407, "pan.___", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 2272, "else"
+ line 407, "pan.___", state 2275, "(1)"
+ line 411, "pan.___", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 2286, "else"
+ line 411, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 409, "pan.___", state 2295, "((i<1))"
+ line 409, "pan.___", state 2295, "((i>=1))"
+ line 416, "pan.___", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2303, "(1)"
+ line 416, "pan.___", state 2304, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2304, "else"
+ line 416, "pan.___", state 2307, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 420, "pan.___", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2317, "(1)"
+ line 420, "pan.___", state 2318, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2318, "else"
+ line 420, "pan.___", state 2321, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 418, "pan.___", state 2327, "((i<2))"
+ line 418, "pan.___", state 2327, "((i>=2))"
+ line 425, "pan.___", state 2334, "(1)"
+ line 425, "pan.___", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 2335, "else"
+ line 425, "pan.___", state 2338, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 429, "pan.___", state 2347, "(1)"
+ line 429, "pan.___", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 2348, "else"
+ line 429, "pan.___", state 2351, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 427, "pan.___", state 2357, "((i<1))"
+ line 427, "pan.___", state 2357, "((i>=1))"
+ line 434, "pan.___", state 2364, "(1)"
+ line 434, "pan.___", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 2365, "else"
+ line 434, "pan.___", state 2368, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 438, "pan.___", state 2377, "(1)"
+ line 438, "pan.___", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 2378, "else"
+ line 438, "pan.___", state 2381, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 436, "pan.___", state 2387, "((i<2))"
+ line 436, "pan.___", state 2387, "((i>=2))"
+ line 446, "pan.___", state 2391, "(1)"
+ line 446, "pan.___", state 2391, "(1)"
+ line 734, "pan.___", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2396, "(1)"
+ line 407, "pan.___", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2468, "(1)"
+ line 434, "pan.___", state 2498, "(1)"
+ line 438, "pan.___", state 2511, "(1)"
+ line 407, "pan.___", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2603, "(1)"
+ line 434, "pan.___", state 2633, "(1)"
+ line 438, "pan.___", state 2646, "(1)"
+ line 407, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2732, "(1)"
+ line 434, "pan.___", state 2762, "(1)"
+ line 438, "pan.___", state 2775, "(1)"
+ line 245, "pan.___", state 2808, "(1)"
+ line 253, "pan.___", state 2828, "(1)"
+ line 257, "pan.___", state 2836, "(1)"
+ line 245, "pan.___", state 2851, "(1)"
+ line 253, "pan.___", state 2871, "(1)"
+ line 257, "pan.___", state 2879, "(1)"
+ line 929, "pan.___", state 2896, "-end-"
+ (246 of 2896 states)
+unreached in proctype urcu_writer
+ line 1018, "pan.___", state 12, "((i<1))"
+ line 1018, "pan.___", state 12, "((i>=1))"
+ line 407, "pan.___", state 46, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 60, "cache_dirty_urcu_active_readers = 0"
+ line 425, "pan.___", state 111, "(1)"
+ line 429, "pan.___", state 124, "(1)"
+ line 268, "pan.___", state 177, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 179, "(1)"
+ line 272, "pan.___", state 186, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 188, "(1)"
+ line 272, "pan.___", state 189, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 189, "else"
+ line 270, "pan.___", state 194, "((i<1))"
+ line 270, "pan.___", state 194, "((i>=1))"
+ line 276, "pan.___", state 199, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 201, "(1)"
+ line 276, "pan.___", state 202, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 202, "else"
+ line 280, "pan.___", state 208, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 210, "(1)"
+ line 280, "pan.___", state 211, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 211, "else"
+ line 285, "pan.___", state 220, "(cache_dirty_urcu_gp_ctr)"
+ line 285, "pan.___", state 220, "else"
+ line 407, "pan.___", state 239, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 253, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 271, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 285, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 304, "(1)"
+ line 429, "pan.___", state 317, "(1)"
+ line 434, "pan.___", state 334, "(1)"
+ line 438, "pan.___", state 347, "(1)"
+ line 411, "pan.___", state 384, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 402, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 416, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 448, "(1)"
+ line 434, "pan.___", state 465, "(1)"
+ line 438, "pan.___", state 478, "(1)"
+ line 411, "pan.___", state 523, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 541, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 555, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 587, "(1)"
+ line 434, "pan.___", state 604, "(1)"
+ line 438, "pan.___", state 617, "(1)"
+ line 411, "pan.___", state 652, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 670, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 684, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 716, "(1)"
+ line 434, "pan.___", state 733, "(1)"
+ line 438, "pan.___", state 746, "(1)"
+ line 411, "pan.___", state 783, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 801, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 815, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 847, "(1)"
+ line 434, "pan.___", state 864, "(1)"
+ line 438, "pan.___", state 877, "(1)"
+ line 268, "pan.___", state 932, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 941, "cache_dirty_urcu_active_readers = 0"
+ line 245, "pan.___", state 979, "(1)"
+ line 249, "pan.___", state 987, "(1)"
+ line 253, "pan.___", state 999, "(1)"
+ line 257, "pan.___", state 1007, "(1)"
+ line 268, "pan.___", state 1038, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1047, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1060, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1069, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1085, "(1)"
+ line 249, "pan.___", state 1093, "(1)"
+ line 253, "pan.___", state 1105, "(1)"
+ line 257, "pan.___", state 1113, "(1)"
+ line 272, "pan.___", state 1139, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1152, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1161, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1177, "(1)"
+ line 249, "pan.___", state 1185, "(1)"
+ line 253, "pan.___", state 1197, "(1)"
+ line 257, "pan.___", state 1205, "(1)"
+ line 268, "pan.___", state 1236, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1245, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1258, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1267, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1283, "(1)"
+ line 249, "pan.___", state 1291, "(1)"
+ line 253, "pan.___", state 1303, "(1)"
+ line 257, "pan.___", state 1311, "(1)"
+ line 272, "pan.___", state 1337, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1350, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1359, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1375, "(1)"
+ line 249, "pan.___", state 1383, "(1)"
+ line 253, "pan.___", state 1395, "(1)"
+ line 257, "pan.___", state 1403, "(1)"
+ line 268, "pan.___", state 1434, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1443, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1456, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1465, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1481, "(1)"
+ line 249, "pan.___", state 1489, "(1)"
+ line 253, "pan.___", state 1501, "(1)"
+ line 257, "pan.___", state 1509, "(1)"
+ line 272, "pan.___", state 1535, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1548, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1557, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1573, "(1)"
+ line 249, "pan.___", state 1581, "(1)"
+ line 253, "pan.___", state 1593, "(1)"
+ line 257, "pan.___", state 1601, "(1)"
+ line 268, "pan.___", state 1632, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1641, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1654, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1663, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1679, "(1)"
+ line 249, "pan.___", state 1687, "(1)"
+ line 253, "pan.___", state 1699, "(1)"
+ line 257, "pan.___", state 1707, "(1)"
+ line 1304, "pan.___", state 1723, "-end-"
+ (110 of 1723 states)
+unreached in proctype :init:
+ line 1319, "pan.___", state 13, "((i<1))"
+ line 1319, "pan.___", state 13, "((i>=1))"
+ (1 of 28 states)
+unreached in proctype :never:
+ line 1367, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 4.88e+04 seconds
+pan: rate 1799.8673 states/second
+pan: avg transition delay 1.5754e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+#define NO_WMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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+1531:1:2501
--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+Depth= 9651 States= 1e+06 Transitions= 1.79e+08 Memory= 513.029 t= 267 R= 4e+03
+Depth= 9651 States= 2e+06 Transitions= 4.37e+08 Memory= 559.416 t= 679 R= 3e+03
+Depth= 9651 States= 3e+06 Transitions= 7.08e+08 Memory= 605.901 t= 1.13e+03 R= 3e+03
+pan: resizing hashtable to -w22.. done
+Depth= 9651 States= 4e+06 Transitions= 9.4e+08 Memory= 683.213 t= 1.48e+03 R= 3e+03
+Depth= 9651 States= 5e+06 Transitions= 1.26e+09 Memory= 730.479 t= 1.98e+03 R= 3e+03
+Depth= 9651 States= 6e+06 Transitions= 1.55e+09 Memory= 777.451 t= 2.43e+03 R= 2e+03
+Depth= 9651 States= 7e+06 Transitions= 1.82e+09 Memory= 824.522 t= 2.87e+03 R= 2e+03
+Depth= 9651 States= 8e+06 Transitions= 2.01e+09 Memory= 871.494 t= 3.16e+03 R= 3e+03
+Depth= 9651 States= 9e+06 Transitions= 2.19e+09 Memory= 917.295 t= 3.45e+03 R= 3e+03
+pan: resizing hashtable to -w24.. done
+Depth= 9651 States= 1e+07 Transitions= 2.37e+09 Memory= 1087.092 t= 3.73e+03 R= 3e+03
+Depth= 9651 States= 1.1e+07 Transitions= 2.59e+09 Memory= 1133.088 t= 4.06e+03 R= 3e+03
+Depth= 9651 States= 1.2e+07 Transitions= 2.88e+09 Memory= 1179.572 t= 4.5e+03 R= 3e+03
+Depth= 9651 States= 1.3e+07 Transitions= 3.1e+09 Memory= 1226.545 t= 4.84e+03 R= 3e+03
+Depth= 9651 States= 1.4e+07 Transitions= 3.33e+09 Memory= 1272.834 t= 5.18e+03 R= 3e+03
+Depth= 9651 States= 1.5e+07 Transitions= 3.58e+09 Memory= 1318.733 t= 5.57e+03 R= 3e+03
+Depth= 9651 States= 1.6e+07 Transitions= 3.79e+09 Memory= 1364.729 t= 5.9e+03 R= 3e+03
+Depth= 9651 States= 1.7e+07 Transitions= 4.09e+09 Memory= 1410.725 t= 6.36e+03 R= 3e+03
+Depth= 9892 States= 1.8e+07 Transitions= 4.34e+09 Memory= 1456.526 t= 6.76e+03 R= 3e+03
+Depth= 9897 States= 1.9e+07 Transitions= 4.61e+09 Memory= 1502.326 t= 7.17e+03 R= 3e+03
+Depth= 9897 States= 2e+07 Transitions= 4.88e+09 Memory= 1548.127 t= 7.6e+03 R= 3e+03
+Depth= 9897 States= 2.1e+07 Transitions= 5.16e+09 Memory= 1594.318 t= 8.03e+03 R= 3e+03
+Depth= 9897 States= 2.2e+07 Transitions= 5.46e+09 Memory= 1640.315 t= 8.52e+03 R= 3e+03
+Depth= 9897 States= 2.3e+07 Transitions= 5.74e+09 Memory= 1686.115 t= 8.95e+03 R= 3e+03
+Depth= 9897 States= 2.4e+07 Transitions= 6e+09 Memory= 1731.916 t= 9.36e+03 R= 3e+03
+Depth= 9897 States= 2.5e+07 Transitions= 6.24e+09 Memory= 1777.717 t= 9.75e+03 R= 3e+03
+Depth= 9897 States= 2.6e+07 Transitions= 6.48e+09 Memory= 1823.518 t= 1.01e+04 R= 3e+03
+Depth= 9897 States= 2.7e+07 Transitions= 6.7e+09 Memory= 1869.318 t= 1.05e+04 R= 3e+03
+Depth= 9897 States= 2.8e+07 Transitions= 7.03e+09 Memory= 1916.486 t= 1.1e+04 R= 3e+03
+Depth= 9897 States= 2.9e+07 Transitions= 7.36e+09 Memory= 1962.678 t= 1.15e+04 R= 3e+03
+Depth= 9897 States= 3e+07 Transitions= 7.63e+09 Memory= 2008.967 t= 1.2e+04 R= 3e+03
+Depth= 9897 States= 3.1e+07 Transitions= 7.94e+09 Memory= 2054.963 t= 1.25e+04 R= 2e+03
+Depth= 9897 States= 3.2e+07 Transitions= 8.2e+09 Memory= 2102.033 t= 1.29e+04 R= 2e+03
+Depth= 9897 States= 3.3e+07 Transitions= 8.41e+09 Memory= 2148.029 t= 1.32e+04 R= 2e+03
+Depth= 9897 States= 3.4e+07 Transitions= 8.68e+09 Memory= 2194.123 t= 1.36e+04 R= 2e+03
+pan: resizing hashtable to -w26.. done
+Depth= 9897 States= 3.5e+07 Transitions= 8.91e+09 Memory= 2736.006 t= 1.4e+04 R= 2e+03
+Depth= 9897 States= 3.6e+07 Transitions= 9.2e+09 Memory= 2781.807 t= 1.44e+04 R= 2e+03
+Depth= 9897 States= 3.7e+07 Transitions= 9.48e+09 Memory= 2827.608 t= 1.49e+04 R= 2e+03
+Depth= 9897 States= 3.8e+07 Transitions= 9.72e+09 Memory= 2873.408 t= 1.52e+04 R= 2e+03
+Depth= 9897 States= 3.9e+07 Transitions= 9.98e+09 Memory= 2919.209 t= 1.56e+04 R= 2e+03
+Depth= 9897 States= 4e+07 Transitions= 1.02e+10 Memory= 2965.010 t= 1.6e+04 R= 2e+03
+Depth= 9897 States= 4.1e+07 Transitions= 1.05e+10 Memory= 3010.713 t= 1.64e+04 R= 2e+03
+Depth= 9897 States= 4.2e+07 Transitions= 1.07e+10 Memory= 3056.611 t= 1.68e+04 R= 3e+03
+pan: claim violated! (at depth 1439)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 9897, errors: 1
+ 42642410 states, stored
+1.0909582e+10 states, matched
+1.0952224e+10 transitions (= stored+matched)
+5.922913e+10 atomic steps
+hash conflicts: 6.3170511e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 4717.369 equivalent memory usage for states (stored*(State-vector + overhead))
+ 2117.231 actual memory usage for states (compression: 44.88%)
+ state-vector as stored = 16 byte + 36 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 3086.494 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 304368 3993 2946 2 2 ]
+unreached in proctype urcu_reader
+ line 894, "pan.___", state 12, "((i<1))"
+ line 894, "pan.___", state 12, "((i>=1))"
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 223, "(1)"
+ line 434, "pan.___", state 253, "(1)"
+ line 438, "pan.___", state 266, "(1)"
+ line 687, "pan.___", state 287, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 294, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 326, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 340, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 359, "(1)"
+ line 434, "pan.___", state 389, "(1)"
+ line 438, "pan.___", state 402, "(1)"
+ line 407, "pan.___", state 423, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 455, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 469, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 488, "(1)"
+ line 434, "pan.___", state 518, "(1)"
+ line 438, "pan.___", state 531, "(1)"
+ line 407, "pan.___", state 554, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 556, "(1)"
+ line 407, "pan.___", state 557, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 557, "else"
+ line 407, "pan.___", state 560, "(1)"
+ line 411, "pan.___", state 568, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 570, "(1)"
+ line 411, "pan.___", state 571, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 571, "else"
+ line 411, "pan.___", state 574, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 411, "pan.___", state 575, "(1)"
+ line 409, "pan.___", state 580, "((i<1))"
+ line 409, "pan.___", state 580, "((i>=1))"
+ line 416, "pan.___", state 586, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 588, "(1)"
+ line 416, "pan.___", state 589, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 589, "else"
+ line 416, "pan.___", state 592, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 416, "pan.___", state 593, "(1)"
+ line 420, "pan.___", state 600, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 602, "(1)"
+ line 420, "pan.___", state 603, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 603, "else"
+ line 420, "pan.___", state 606, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 420, "pan.___", state 607, "(1)"
+ line 418, "pan.___", state 612, "((i<2))"
+ line 418, "pan.___", state 612, "((i>=2))"
+ line 425, "pan.___", state 619, "(1)"
+ line 425, "pan.___", state 620, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 620, "else"
+ line 425, "pan.___", state 623, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 425, "pan.___", state 624, "(1)"
+ line 429, "pan.___", state 632, "(1)"
+ line 429, "pan.___", state 633, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 633, "else"
+ line 429, "pan.___", state 636, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 429, "pan.___", state 637, "(1)"
+ line 427, "pan.___", state 642, "((i<1))"
+ line 427, "pan.___", state 642, "((i>=1))"
+ line 434, "pan.___", state 649, "(1)"
+ line 434, "pan.___", state 650, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 650, "else"
+ line 434, "pan.___", state 653, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 434, "pan.___", state 654, "(1)"
+ line 438, "pan.___", state 662, "(1)"
+ line 438, "pan.___", state 663, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 663, "else"
+ line 438, "pan.___", state 666, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 438, "pan.___", state 667, "(1)"
+ line 436, "pan.___", state 672, "((i<2))"
+ line 436, "pan.___", state 672, "((i>=2))"
+ line 446, "pan.___", state 676, "(1)"
+ line 446, "pan.___", state 676, "(1)"
+ line 687, "pan.___", state 679, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 680, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 681, "(1)"
+ line 407, "pan.___", state 688, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 720, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 734, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 753, "(1)"
+ line 434, "pan.___", state 783, "(1)"
+ line 438, "pan.___", state 796, "(1)"
+ line 407, "pan.___", state 824, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 856, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 870, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 889, "(1)"
+ line 434, "pan.___", state 919, "(1)"
+ line 438, "pan.___", state 932, "(1)"
+ line 407, "pan.___", state 953, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 955, "(1)"
+ line 407, "pan.___", state 956, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 956, "else"
+ line 407, "pan.___", state 959, "(1)"
+ line 411, "pan.___", state 967, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 969, "(1)"
+ line 411, "pan.___", state 970, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 970, "else"
+ line 411, "pan.___", state 973, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 411, "pan.___", state 974, "(1)"
+ line 409, "pan.___", state 979, "((i<1))"
+ line 409, "pan.___", state 979, "((i>=1))"
+ line 416, "pan.___", state 985, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 987, "(1)"
+ line 416, "pan.___", state 988, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 988, "else"
+ line 416, "pan.___", state 991, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 416, "pan.___", state 992, "(1)"
+ line 420, "pan.___", state 999, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 1001, "(1)"
+ line 420, "pan.___", state 1002, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 1002, "else"
+ line 420, "pan.___", state 1005, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 420, "pan.___", state 1006, "(1)"
+ line 418, "pan.___", state 1011, "((i<2))"
+ line 418, "pan.___", state 1011, "((i>=2))"
+ line 425, "pan.___", state 1018, "(1)"
+ line 425, "pan.___", state 1019, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 1019, "else"
+ line 425, "pan.___", state 1022, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 425, "pan.___", state 1023, "(1)"
+ line 429, "pan.___", state 1031, "(1)"
+ line 429, "pan.___", state 1032, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 1032, "else"
+ line 429, "pan.___", state 1035, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 429, "pan.___", state 1036, "(1)"
+ line 427, "pan.___", state 1041, "((i<1))"
+ line 427, "pan.___", state 1041, "((i>=1))"
+ line 434, "pan.___", state 1048, "(1)"
+ line 434, "pan.___", state 1049, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 1049, "else"
+ line 434, "pan.___", state 1052, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 434, "pan.___", state 1053, "(1)"
+ line 438, "pan.___", state 1061, "(1)"
+ line 438, "pan.___", state 1062, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 1062, "else"
+ line 438, "pan.___", state 1065, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 438, "pan.___", state 1066, "(1)"
+ line 436, "pan.___", state 1071, "((i<2))"
+ line 436, "pan.___", state 1071, "((i>=2))"
+ line 446, "pan.___", state 1075, "(1)"
+ line 446, "pan.___", state 1075, "(1)"
+ line 695, "pan.___", state 1079, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 1084, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1116, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1130, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1149, "(1)"
+ line 434, "pan.___", state 1179, "(1)"
+ line 438, "pan.___", state 1192, "(1)"
+ line 407, "pan.___", state 1216, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1248, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1262, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1281, "(1)"
+ line 434, "pan.___", state 1311, "(1)"
+ line 438, "pan.___", state 1324, "(1)"
+ line 407, "pan.___", state 1349, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1381, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1395, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1414, "(1)"
+ line 434, "pan.___", state 1444, "(1)"
+ line 438, "pan.___", state 1457, "(1)"
+ line 407, "pan.___", state 1478, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1510, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1524, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1543, "(1)"
+ line 434, "pan.___", state 1573, "(1)"
+ line 438, "pan.___", state 1586, "(1)"
+ line 407, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1644, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1658, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1677, "(1)"
+ line 434, "pan.___", state 1707, "(1)"
+ line 438, "pan.___", state 1720, "(1)"
+ line 407, "pan.___", state 1741, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1773, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1787, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1806, "(1)"
+ line 434, "pan.___", state 1836, "(1)"
+ line 438, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1873, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1905, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1919, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 1938, "(1)"
+ line 434, "pan.___", state 1968, "(1)"
+ line 438, "pan.___", state 1981, "(1)"
+ line 734, "pan.___", state 2002, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 2009, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2041, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2055, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2074, "(1)"
+ line 434, "pan.___", state 2104, "(1)"
+ line 438, "pan.___", state 2117, "(1)"
+ line 407, "pan.___", state 2138, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2170, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2184, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2203, "(1)"
+ line 434, "pan.___", state 2233, "(1)"
+ line 438, "pan.___", state 2246, "(1)"
+ line 407, "pan.___", state 2269, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 2271, "(1)"
+ line 407, "pan.___", state 2272, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 2272, "else"
+ line 407, "pan.___", state 2275, "(1)"
+ line 411, "pan.___", state 2283, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2286, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 2286, "else"
+ line 411, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 411, "pan.___", state 2290, "(1)"
+ line 409, "pan.___", state 2295, "((i<1))"
+ line 409, "pan.___", state 2295, "((i>=1))"
+ line 416, "pan.___", state 2301, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2303, "(1)"
+ line 416, "pan.___", state 2304, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2304, "else"
+ line 416, "pan.___", state 2307, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 416, "pan.___", state 2308, "(1)"
+ line 420, "pan.___", state 2315, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2317, "(1)"
+ line 420, "pan.___", state 2318, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2318, "else"
+ line 420, "pan.___", state 2321, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 420, "pan.___", state 2322, "(1)"
+ line 418, "pan.___", state 2327, "((i<2))"
+ line 418, "pan.___", state 2327, "((i>=2))"
+ line 425, "pan.___", state 2334, "(1)"
+ line 425, "pan.___", state 2335, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 2335, "else"
+ line 425, "pan.___", state 2338, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 425, "pan.___", state 2339, "(1)"
+ line 429, "pan.___", state 2347, "(1)"
+ line 429, "pan.___", state 2348, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 2348, "else"
+ line 429, "pan.___", state 2351, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 429, "pan.___", state 2352, "(1)"
+ line 427, "pan.___", state 2357, "((i<1))"
+ line 427, "pan.___", state 2357, "((i>=1))"
+ line 434, "pan.___", state 2364, "(1)"
+ line 434, "pan.___", state 2365, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 2365, "else"
+ line 434, "pan.___", state 2368, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 434, "pan.___", state 2369, "(1)"
+ line 438, "pan.___", state 2377, "(1)"
+ line 438, "pan.___", state 2378, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 2378, "else"
+ line 438, "pan.___", state 2381, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 438, "pan.___", state 2382, "(1)"
+ line 436, "pan.___", state 2387, "((i<2))"
+ line 436, "pan.___", state 2387, "((i>=2))"
+ line 446, "pan.___", state 2391, "(1)"
+ line 446, "pan.___", state 2391, "(1)"
+ line 734, "pan.___", state 2394, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2395, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2396, "(1)"
+ line 407, "pan.___", state 2403, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2435, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2449, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2468, "(1)"
+ line 434, "pan.___", state 2498, "(1)"
+ line 438, "pan.___", state 2511, "(1)"
+ line 407, "pan.___", state 2538, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2570, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2584, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2603, "(1)"
+ line 434, "pan.___", state 2633, "(1)"
+ line 438, "pan.___", state 2646, "(1)"
+ line 407, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2699, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2713, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 2732, "(1)"
+ line 434, "pan.___", state 2762, "(1)"
+ line 438, "pan.___", state 2775, "(1)"
+ line 245, "pan.___", state 2808, "(1)"
+ line 253, "pan.___", state 2828, "(1)"
+ line 257, "pan.___", state 2836, "(1)"
+ line 245, "pan.___", state 2851, "(1)"
+ line 253, "pan.___", state 2871, "(1)"
+ line 257, "pan.___", state 2879, "(1)"
+ line 929, "pan.___", state 2896, "-end-"
+ (246 of 2896 states)
+unreached in proctype urcu_writer
+ line 1018, "pan.___", state 12, "((i<1))"
+ line 1018, "pan.___", state 12, "((i>=1))"
+ line 407, "pan.___", state 49, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 63, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 81, "cache_dirty_rcu_ptr = 0"
+ line 425, "pan.___", state 114, "(1)"
+ line 429, "pan.___", state 127, "(1)"
+ line 434, "pan.___", state 144, "(1)"
+ line 268, "pan.___", state 180, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 189, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 202, "cache_dirty_rcu_ptr = 0"
+ line 407, "pan.___", state 242, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 256, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 274, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 288, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 307, "(1)"
+ line 429, "pan.___", state 320, "(1)"
+ line 434, "pan.___", state 337, "(1)"
+ line 438, "pan.___", state 350, "(1)"
+ line 411, "pan.___", state 387, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 405, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 419, "cache_dirty_rcu_data[i] = 0"
+ line 429, "pan.___", state 451, "(1)"
+ line 434, "pan.___", state 468, "(1)"
+ line 438, "pan.___", state 481, "(1)"
+ line 407, "pan.___", state 511, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 525, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 543, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 557, "cache_dirty_rcu_data[i] = 0"
+ line 425, "pan.___", state 576, "(1)"
+ line 429, "pan.___", state 589, "(1)"
+ line 434, "pan.___", state 606, "(1)"
+ line 438, "pan.___", state 619, "(1)"
+ line 407, "pan.___", state 640, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 642, "(1)"
+ line 407, "pan.___", state 643, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 643, "else"
+ line 407, "pan.___", state 646, "(1)"
+ line 411, "pan.___", state 654, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 656, "(1)"
+ line 411, "pan.___", state 657, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 657, "else"
+ line 411, "pan.___", state 660, "(1)"
+ line 411, "pan.___", state 661, "(1)"
+ line 411, "pan.___", state 661, "(1)"
+ line 409, "pan.___", state 666, "((i<1))"
+ line 409, "pan.___", state 666, "((i>=1))"
+ line 416, "pan.___", state 672, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 674, "(1)"
+ line 416, "pan.___", state 675, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 675, "else"
+ line 416, "pan.___", state 678, "(1)"
+ line 416, "pan.___", state 679, "(1)"
+ line 416, "pan.___", state 679, "(1)"
+ line 420, "pan.___", state 686, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 688, "(1)"
+ line 420, "pan.___", state 689, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 689, "else"
+ line 420, "pan.___", state 692, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 418, "pan.___", state 698, "((i<2))"
+ line 418, "pan.___", state 698, "((i>=2))"
+ line 425, "pan.___", state 705, "(1)"
+ line 425, "pan.___", state 706, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 706, "else"
+ line 425, "pan.___", state 709, "(1)"
+ line 425, "pan.___", state 710, "(1)"
+ line 425, "pan.___", state 710, "(1)"
+ line 429, "pan.___", state 718, "(1)"
+ line 429, "pan.___", state 719, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 719, "else"
+ line 429, "pan.___", state 722, "(1)"
+ line 429, "pan.___", state 723, "(1)"
+ line 429, "pan.___", state 723, "(1)"
+ line 427, "pan.___", state 728, "((i<1))"
+ line 427, "pan.___", state 728, "((i>=1))"
+ line 434, "pan.___", state 735, "(1)"
+ line 434, "pan.___", state 736, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 736, "else"
+ line 434, "pan.___", state 739, "(1)"
+ line 434, "pan.___", state 740, "(1)"
+ line 434, "pan.___", state 740, "(1)"
+ line 438, "pan.___", state 748, "(1)"
+ line 438, "pan.___", state 749, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 749, "else"
+ line 438, "pan.___", state 752, "(1)"
+ line 438, "pan.___", state 753, "(1)"
+ line 438, "pan.___", state 753, "(1)"
+ line 436, "pan.___", state 758, "((i<2))"
+ line 436, "pan.___", state 758, "((i>=2))"
+ line 446, "pan.___", state 762, "(1)"
+ line 446, "pan.___", state 762, "(1)"
+ line 1184, "pan.___", state 766, "_proc_urcu_writer = (_proc_urcu_writer|(1<<10))"
+ line 407, "pan.___", state 771, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 773, "(1)"
+ line 407, "pan.___", state 774, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 774, "else"
+ line 407, "pan.___", state 777, "(1)"
+ line 411, "pan.___", state 785, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 787, "(1)"
+ line 411, "pan.___", state 788, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 788, "else"
+ line 411, "pan.___", state 791, "(1)"
+ line 411, "pan.___", state 792, "(1)"
+ line 411, "pan.___", state 792, "(1)"
+ line 409, "pan.___", state 797, "((i<1))"
+ line 409, "pan.___", state 797, "((i>=1))"
+ line 416, "pan.___", state 803, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 805, "(1)"
+ line 416, "pan.___", state 806, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 806, "else"
+ line 416, "pan.___", state 809, "(1)"
+ line 416, "pan.___", state 810, "(1)"
+ line 416, "pan.___", state 810, "(1)"
+ line 420, "pan.___", state 817, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 819, "(1)"
+ line 420, "pan.___", state 820, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 820, "else"
+ line 420, "pan.___", state 823, "(1)"
+ line 420, "pan.___", state 824, "(1)"
+ line 420, "pan.___", state 824, "(1)"
+ line 418, "pan.___", state 829, "((i<2))"
+ line 418, "pan.___", state 829, "((i>=2))"
+ line 425, "pan.___", state 836, "(1)"
+ line 425, "pan.___", state 837, "(!(cache_dirty_urcu_gp_ctr))"
+ line 425, "pan.___", state 837, "else"
+ line 425, "pan.___", state 840, "(1)"
+ line 425, "pan.___", state 841, "(1)"
+ line 425, "pan.___", state 841, "(1)"
+ line 429, "pan.___", state 849, "(1)"
+ line 429, "pan.___", state 850, "(!(cache_dirty_urcu_active_readers))"
+ line 429, "pan.___", state 850, "else"
+ line 429, "pan.___", state 853, "(1)"
+ line 429, "pan.___", state 854, "(1)"
+ line 429, "pan.___", state 854, "(1)"
+ line 427, "pan.___", state 859, "((i<1))"
+ line 427, "pan.___", state 859, "((i>=1))"
+ line 434, "pan.___", state 866, "(1)"
+ line 434, "pan.___", state 867, "(!(cache_dirty_rcu_ptr))"
+ line 434, "pan.___", state 867, "else"
+ line 434, "pan.___", state 870, "(1)"
+ line 434, "pan.___", state 871, "(1)"
+ line 434, "pan.___", state 871, "(1)"
+ line 438, "pan.___", state 879, "(1)"
+ line 438, "pan.___", state 880, "(!(cache_dirty_rcu_data[i]))"
+ line 438, "pan.___", state 880, "else"
+ line 438, "pan.___", state 883, "(1)"
+ line 438, "pan.___", state 884, "(1)"
+ line 438, "pan.___", state 884, "(1)"
+ line 436, "pan.___", state 889, "((i<2))"
+ line 436, "pan.___", state 889, "((i>=2))"
+ line 446, "pan.___", state 893, "(1)"
+ line 446, "pan.___", state 893, "(1)"
+ line 1200, "pan.___", state 898, "_proc_urcu_writer = (_proc_urcu_writer|(1<<11))"
+ line 1195, "pan.___", state 899, "(((tmp2&((1<<7)-1))&&((tmp2^0)&(1<<7))))"
+ line 1195, "pan.___", state 899, "else"
+ line 1220, "pan.___", state 903, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<12)|(1<<11))))"
+ line 268, "pan.___", state 934, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 943, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 958, "(1)"
+ line 280, "pan.___", state 965, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 981, "(1)"
+ line 249, "pan.___", state 989, "(1)"
+ line 253, "pan.___", state 1001, "(1)"
+ line 257, "pan.___", state 1009, "(1)"
+ line 268, "pan.___", state 1040, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1049, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1062, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1071, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1087, "(1)"
+ line 249, "pan.___", state 1095, "(1)"
+ line 253, "pan.___", state 1107, "(1)"
+ line 257, "pan.___", state 1115, "(1)"
+ line 272, "pan.___", state 1141, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1154, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1163, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1179, "(1)"
+ line 249, "pan.___", state 1187, "(1)"
+ line 253, "pan.___", state 1199, "(1)"
+ line 257, "pan.___", state 1207, "(1)"
+ line 268, "pan.___", state 1238, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1247, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1260, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1269, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1285, "(1)"
+ line 249, "pan.___", state 1293, "(1)"
+ line 253, "pan.___", state 1305, "(1)"
+ line 257, "pan.___", state 1313, "(1)"
+ line 268, "pan.___", state 1330, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1332, "(1)"
+ line 272, "pan.___", state 1339, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1341, "(1)"
+ line 272, "pan.___", state 1342, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1342, "else"
+ line 270, "pan.___", state 1347, "((i<1))"
+ line 270, "pan.___", state 1347, "((i>=1))"
+ line 276, "pan.___", state 1352, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1354, "(1)"
+ line 276, "pan.___", state 1355, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1355, "else"
+ line 280, "pan.___", state 1361, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1363, "(1)"
+ line 280, "pan.___", state 1364, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1364, "else"
+ line 278, "pan.___", state 1369, "((i<2))"
+ line 278, "pan.___", state 1369, "((i>=2))"
+ line 245, "pan.___", state 1377, "(1)"
+ line 249, "pan.___", state 1385, "(1)"
+ line 249, "pan.___", state 1386, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1386, "else"
+ line 247, "pan.___", state 1391, "((i<1))"
+ line 247, "pan.___", state 1391, "((i>=1))"
+ line 253, "pan.___", state 1397, "(1)"
+ line 253, "pan.___", state 1398, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1398, "else"
+ line 257, "pan.___", state 1405, "(1)"
+ line 257, "pan.___", state 1406, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1406, "else"
+ line 262, "pan.___", state 1415, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1415, "else"
+ line 1296, "pan.___", state 1418, "i = 0"
+ line 1296, "pan.___", state 1420, "reader_barrier = 1"
+ line 1296, "pan.___", state 1431, "((i<1))"
+ line 1296, "pan.___", state 1431, "((i>=1))"
+ line 268, "pan.___", state 1436, "cache_dirty_urcu_gp_ctr = 0"
+ line 268, "pan.___", state 1438, "(1)"
+ line 272, "pan.___", state 1445, "cache_dirty_urcu_active_readers = 0"
+ line 272, "pan.___", state 1447, "(1)"
+ line 272, "pan.___", state 1448, "(cache_dirty_urcu_active_readers)"
+ line 272, "pan.___", state 1448, "else"
+ line 270, "pan.___", state 1453, "((i<1))"
+ line 270, "pan.___", state 1453, "((i>=1))"
+ line 276, "pan.___", state 1458, "cache_dirty_rcu_ptr = 0"
+ line 276, "pan.___", state 1460, "(1)"
+ line 276, "pan.___", state 1461, "(cache_dirty_rcu_ptr)"
+ line 276, "pan.___", state 1461, "else"
+ line 280, "pan.___", state 1467, "cache_dirty_rcu_data[i] = 0"
+ line 280, "pan.___", state 1469, "(1)"
+ line 280, "pan.___", state 1470, "(cache_dirty_rcu_data[i])"
+ line 280, "pan.___", state 1470, "else"
+ line 278, "pan.___", state 1475, "((i<2))"
+ line 278, "pan.___", state 1475, "((i>=2))"
+ line 245, "pan.___", state 1483, "(1)"
+ line 249, "pan.___", state 1491, "(1)"
+ line 249, "pan.___", state 1492, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 1492, "else"
+ line 247, "pan.___", state 1497, "((i<1))"
+ line 247, "pan.___", state 1497, "((i>=1))"
+ line 253, "pan.___", state 1503, "(1)"
+ line 253, "pan.___", state 1504, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 1504, "else"
+ line 257, "pan.___", state 1511, "(1)"
+ line 257, "pan.___", state 1512, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 1512, "else"
+ line 262, "pan.___", state 1521, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 1521, "else"
+ line 295, "pan.___", state 1523, "(cache_dirty_urcu_gp_ctr)"
+ line 295, "pan.___", state 1523, "else"
+ line 1296, "pan.___", state 1524, "(cache_dirty_urcu_gp_ctr)"
+ line 1296, "pan.___", state 1524, "else"
+ line 272, "pan.___", state 1537, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1550, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1559, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1575, "(1)"
+ line 249, "pan.___", state 1583, "(1)"
+ line 253, "pan.___", state 1595, "(1)"
+ line 257, "pan.___", state 1603, "(1)"
+ line 268, "pan.___", state 1634, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1643, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1656, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1665, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1681, "(1)"
+ line 249, "pan.___", state 1689, "(1)"
+ line 253, "pan.___", state 1701, "(1)"
+ line 257, "pan.___", state 1709, "(1)"
+ line 1304, "pan.___", state 1725, "-end-"
+ (212 of 1725 states)
+unreached in proctype :init:
+ line 1319, "pan.___", state 13, "((i<1))"
+ line 1319, "pan.___", state 13, "((i>=1))"
+ (1 of 28 states)
+unreached in proctype :never:
+ line 1367, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 1.71e+04 seconds
+pan: rate 2490.8226 states/second
+pan: avg transition delay 1.5631e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-ipi'
--- /dev/null
+#define SINGLE_FLIP
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ make urcu_free | tee urcu_free.log
+ make urcu_free_no_mb | tee urcu_free_no_mb.log
+ make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth= 4773 States= 1e+06 Transitions= 6.22e+08 Memory= 542.717 t= 624 R= 2e+03
+Depth= 5040 States= 2e+06 Transitions= 1.3e+09 Memory= 618.986 t= 1.33e+03 R= 1e+03
+Depth= 5040 States= 3e+06 Transitions= 1.95e+09 Memory= 695.256 t= 2.03e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 5040 States= 4e+06 Transitions= 2.64e+09 Memory= 802.647 t= 2.73e+03 R= 1e+03
+Depth= 5040 States= 5e+06 Transitions= 3.3e+09 Memory= 878.916 t= 3.41e+03 R= 1e+03
+Depth= 5141 States= 6e+06 Transitions= 3.99e+09 Memory= 955.186 t= 4.12e+03 R= 1e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim - (none specified)
+ assertion violations +
+ cycle checks - (disabled by -DSAFETY)
+ invalid end states +
+
+State-vector 72 byte, depth reached 5141, errors: 0
+ 6711104 states, stored
+4.4393201e+09 states, matched
+4.4460312e+09 transitions (= stored+matched)
+2.5322962e+10 atomic steps
+hash conflicts: 3.3332015e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 640.021 equivalent memory usage for states (stored*(State-vector + overhead))
+ 519.783 actual memory usage for states (compression: 81.21%)
+ state-vector as stored = 53 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1009.483 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 410, ".input.spin", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 82, "(1)"
+ line 437, ".input.spin", state 112, "(1)"
+ line 441, ".input.spin", state 125, "(1)"
+ line 596, ".input.spin", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 410, ".input.spin", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 218, "(1)"
+ line 437, ".input.spin", state 248, "(1)"
+ line 441, ".input.spin", state 261, "(1)"
+ line 410, ".input.spin", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 347, "(1)"
+ line 437, ".input.spin", state 377, "(1)"
+ line 441, ".input.spin", state 390, "(1)"
+ line 410, ".input.spin", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 415, "(1)"
+ line 410, ".input.spin", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 416, "else"
+ line 410, ".input.spin", state 419, "(1)"
+ line 414, ".input.spin", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 429, "(1)"
+ line 414, ".input.spin", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 430, "else"
+ line 414, ".input.spin", state 433, "(1)"
+ line 414, ".input.spin", state 434, "(1)"
+ line 414, ".input.spin", state 434, "(1)"
+ line 412, ".input.spin", state 439, "((i<1))"
+ line 412, ".input.spin", state 439, "((i>=1))"
+ line 419, ".input.spin", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 447, "(1)"
+ line 419, ".input.spin", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 448, "else"
+ line 419, ".input.spin", state 451, "(1)"
+ line 419, ".input.spin", state 452, "(1)"
+ line 419, ".input.spin", state 452, "(1)"
+ line 423, ".input.spin", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 461, "(1)"
+ line 423, ".input.spin", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 462, "else"
+ line 423, ".input.spin", state 465, "(1)"
+ line 423, ".input.spin", state 466, "(1)"
+ line 423, ".input.spin", state 466, "(1)"
+ line 421, ".input.spin", state 471, "((i<2))"
+ line 421, ".input.spin", state 471, "((i>=2))"
+ line 428, ".input.spin", state 478, "(1)"
+ line 428, ".input.spin", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, ".input.spin", state 479, "else"
+ line 428, ".input.spin", state 482, "(1)"
+ line 428, ".input.spin", state 483, "(1)"
+ line 428, ".input.spin", state 483, "(1)"
+ line 432, ".input.spin", state 491, "(1)"
+ line 432, ".input.spin", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, ".input.spin", state 492, "else"
+ line 432, ".input.spin", state 495, "(1)"
+ line 432, ".input.spin", state 496, "(1)"
+ line 432, ".input.spin", state 496, "(1)"
+ line 430, ".input.spin", state 501, "((i<1))"
+ line 430, ".input.spin", state 501, "((i>=1))"
+ line 437, ".input.spin", state 508, "(1)"
+ line 437, ".input.spin", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, ".input.spin", state 509, "else"
+ line 437, ".input.spin", state 512, "(1)"
+ line 437, ".input.spin", state 513, "(1)"
+ line 437, ".input.spin", state 513, "(1)"
+ line 441, ".input.spin", state 521, "(1)"
+ line 441, ".input.spin", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, ".input.spin", state 522, "else"
+ line 441, ".input.spin", state 525, "(1)"
+ line 441, ".input.spin", state 526, "(1)"
+ line 441, ".input.spin", state 526, "(1)"
+ line 439, ".input.spin", state 531, "((i<2))"
+ line 439, ".input.spin", state 531, "((i>=2))"
+ line 449, ".input.spin", state 535, "(1)"
+ line 449, ".input.spin", state 535, "(1)"
+ line 596, ".input.spin", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 596, ".input.spin", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 596, ".input.spin", state 540, "(1)"
+ line 271, ".input.spin", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 555, "(1)"
+ line 279, ".input.spin", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 591, "(1)"
+ line 252, ".input.spin", state 599, "(1)"
+ line 256, ".input.spin", state 611, "(1)"
+ line 260, ".input.spin", state 619, "(1)"
+ line 410, ".input.spin", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 702, "(1)"
+ line 432, ".input.spin", state 715, "(1)"
+ line 437, ".input.spin", state 732, "(1)"
+ line 441, ".input.spin", state 745, "(1)"
+ line 410, ".input.spin", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 838, "(1)"
+ line 437, ".input.spin", state 868, "(1)"
+ line 441, ".input.spin", state 881, "(1)"
+ line 410, ".input.spin", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 904, "(1)"
+ line 410, ".input.spin", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 905, "else"
+ line 410, ".input.spin", state 908, "(1)"
+ line 414, ".input.spin", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 918, "(1)"
+ line 414, ".input.spin", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 919, "else"
+ line 414, ".input.spin", state 922, "(1)"
+ line 414, ".input.spin", state 923, "(1)"
+ line 414, ".input.spin", state 923, "(1)"
+ line 412, ".input.spin", state 928, "((i<1))"
+ line 412, ".input.spin", state 928, "((i>=1))"
+ line 419, ".input.spin", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 936, "(1)"
+ line 419, ".input.spin", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 937, "else"
+ line 419, ".input.spin", state 940, "(1)"
+ line 419, ".input.spin", state 941, "(1)"
+ line 419, ".input.spin", state 941, "(1)"
+ line 423, ".input.spin", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 950, "(1)"
+ line 423, ".input.spin", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 951, "else"
+ line 423, ".input.spin", state 954, "(1)"
+ line 423, ".input.spin", state 955, "(1)"
+ line 423, ".input.spin", state 955, "(1)"
+ line 421, ".input.spin", state 960, "((i<2))"
+ line 421, ".input.spin", state 960, "((i>=2))"
+ line 428, ".input.spin", state 967, "(1)"
+ line 428, ".input.spin", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, ".input.spin", state 968, "else"
+ line 428, ".input.spin", state 971, "(1)"
+ line 428, ".input.spin", state 972, "(1)"
+ line 428, ".input.spin", state 972, "(1)"
+ line 432, ".input.spin", state 980, "(1)"
+ line 432, ".input.spin", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, ".input.spin", state 981, "else"
+ line 432, ".input.spin", state 984, "(1)"
+ line 432, ".input.spin", state 985, "(1)"
+ line 432, ".input.spin", state 985, "(1)"
+ line 430, ".input.spin", state 990, "((i<1))"
+ line 430, ".input.spin", state 990, "((i>=1))"
+ line 437, ".input.spin", state 997, "(1)"
+ line 437, ".input.spin", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, ".input.spin", state 998, "else"
+ line 437, ".input.spin", state 1001, "(1)"
+ line 437, ".input.spin", state 1002, "(1)"
+ line 437, ".input.spin", state 1002, "(1)"
+ line 441, ".input.spin", state 1010, "(1)"
+ line 441, ".input.spin", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, ".input.spin", state 1011, "else"
+ line 441, ".input.spin", state 1014, "(1)"
+ line 441, ".input.spin", state 1015, "(1)"
+ line 441, ".input.spin", state 1015, "(1)"
+ line 439, ".input.spin", state 1020, "((i<2))"
+ line 439, ".input.spin", state 1020, "((i>=2))"
+ line 449, ".input.spin", state 1024, "(1)"
+ line 449, ".input.spin", state 1024, "(1)"
+ line 604, ".input.spin", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 410, ".input.spin", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1098, "(1)"
+ line 432, ".input.spin", state 1111, "(1)"
+ line 437, ".input.spin", state 1128, "(1)"
+ line 441, ".input.spin", state 1141, "(1)"
+ line 410, ".input.spin", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1230, "(1)"
+ line 437, ".input.spin", state 1260, "(1)"
+ line 441, ".input.spin", state 1273, "(1)"
+ line 410, ".input.spin", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1363, "(1)"
+ line 437, ".input.spin", state 1393, "(1)"
+ line 441, ".input.spin", state 1406, "(1)"
+ line 410, ".input.spin", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1492, "(1)"
+ line 437, ".input.spin", state 1522, "(1)"
+ line 441, ".input.spin", state 1535, "(1)"
+ line 271, ".input.spin", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1605, "(1)"
+ line 252, ".input.spin", state 1613, "(1)"
+ line 256, ".input.spin", state 1625, "(1)"
+ line 260, ".input.spin", state 1633, "(1)"
+ line 410, ".input.spin", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1716, "(1)"
+ line 432, ".input.spin", state 1729, "(1)"
+ line 437, ".input.spin", state 1746, "(1)"
+ line 441, ".input.spin", state 1759, "(1)"
+ line 410, ".input.spin", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1845, "(1)"
+ line 432, ".input.spin", state 1858, "(1)"
+ line 437, ".input.spin", state 1875, "(1)"
+ line 441, ".input.spin", state 1888, "(1)"
+ line 410, ".input.spin", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 1977, "(1)"
+ line 437, ".input.spin", state 2007, "(1)"
+ line 441, ".input.spin", state 2020, "(1)"
+ line 643, ".input.spin", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 410, ".input.spin", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 2113, "(1)"
+ line 437, ".input.spin", state 2143, "(1)"
+ line 441, ".input.spin", state 2156, "(1)"
+ line 410, ".input.spin", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 2242, "(1)"
+ line 437, ".input.spin", state 2272, "(1)"
+ line 441, ".input.spin", state 2285, "(1)"
+ line 410, ".input.spin", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 2310, "(1)"
+ line 410, ".input.spin", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 2311, "else"
+ line 410, ".input.spin", state 2314, "(1)"
+ line 414, ".input.spin", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2324, "(1)"
+ line 414, ".input.spin", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 2325, "else"
+ line 414, ".input.spin", state 2328, "(1)"
+ line 414, ".input.spin", state 2329, "(1)"
+ line 414, ".input.spin", state 2329, "(1)"
+ line 412, ".input.spin", state 2334, "((i<1))"
+ line 412, ".input.spin", state 2334, "((i>=1))"
+ line 419, ".input.spin", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2342, "(1)"
+ line 419, ".input.spin", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 2343, "else"
+ line 419, ".input.spin", state 2346, "(1)"
+ line 419, ".input.spin", state 2347, "(1)"
+ line 419, ".input.spin", state 2347, "(1)"
+ line 423, ".input.spin", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2356, "(1)"
+ line 423, ".input.spin", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 2357, "else"
+ line 423, ".input.spin", state 2360, "(1)"
+ line 423, ".input.spin", state 2361, "(1)"
+ line 423, ".input.spin", state 2361, "(1)"
+ line 421, ".input.spin", state 2366, "((i<2))"
+ line 421, ".input.spin", state 2366, "((i>=2))"
+ line 428, ".input.spin", state 2373, "(1)"
+ line 428, ".input.spin", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, ".input.spin", state 2374, "else"
+ line 428, ".input.spin", state 2377, "(1)"
+ line 428, ".input.spin", state 2378, "(1)"
+ line 428, ".input.spin", state 2378, "(1)"
+ line 432, ".input.spin", state 2386, "(1)"
+ line 432, ".input.spin", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, ".input.spin", state 2387, "else"
+ line 432, ".input.spin", state 2390, "(1)"
+ line 432, ".input.spin", state 2391, "(1)"
+ line 432, ".input.spin", state 2391, "(1)"
+ line 430, ".input.spin", state 2396, "((i<1))"
+ line 430, ".input.spin", state 2396, "((i>=1))"
+ line 437, ".input.spin", state 2403, "(1)"
+ line 437, ".input.spin", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, ".input.spin", state 2404, "else"
+ line 437, ".input.spin", state 2407, "(1)"
+ line 437, ".input.spin", state 2408, "(1)"
+ line 437, ".input.spin", state 2408, "(1)"
+ line 441, ".input.spin", state 2416, "(1)"
+ line 441, ".input.spin", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, ".input.spin", state 2417, "else"
+ line 441, ".input.spin", state 2420, "(1)"
+ line 441, ".input.spin", state 2421, "(1)"
+ line 441, ".input.spin", state 2421, "(1)"
+ line 439, ".input.spin", state 2426, "((i<2))"
+ line 439, ".input.spin", state 2426, "((i>=2))"
+ line 449, ".input.spin", state 2430, "(1)"
+ line 449, ".input.spin", state 2430, "(1)"
+ line 643, ".input.spin", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 643, ".input.spin", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 643, ".input.spin", state 2435, "(1)"
+ line 271, ".input.spin", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2486, "(1)"
+ line 252, ".input.spin", state 2494, "(1)"
+ line 256, ".input.spin", state 2506, "(1)"
+ line 260, ".input.spin", state 2514, "(1)"
+ line 410, ".input.spin", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 2597, "(1)"
+ line 432, ".input.spin", state 2610, "(1)"
+ line 437, ".input.spin", state 2627, "(1)"
+ line 441, ".input.spin", state 2640, "(1)"
+ line 271, ".input.spin", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2711, "(1)"
+ line 252, ".input.spin", state 2719, "(1)"
+ line 256, ".input.spin", state 2731, "(1)"
+ line 260, ".input.spin", state 2739, "(1)"
+ line 410, ".input.spin", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 2822, "(1)"
+ line 432, ".input.spin", state 2835, "(1)"
+ line 437, ".input.spin", state 2852, "(1)"
+ line 441, ".input.spin", state 2865, "(1)"
+ line 410, ".input.spin", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 2951, "(1)"
+ line 432, ".input.spin", state 2964, "(1)"
+ line 437, ".input.spin", state 2981, "(1)"
+ line 441, ".input.spin", state 2994, "(1)"
+ line 248, ".input.spin", state 3027, "(1)"
+ line 256, ".input.spin", state 3047, "(1)"
+ line 260, ".input.spin", state 3055, "(1)"
+ line 248, ".input.spin", state 3070, "(1)"
+ line 252, ".input.spin", state 3078, "(1)"
+ line 256, ".input.spin", state 3090, "(1)"
+ line 260, ".input.spin", state 3098, "(1)"
+ line 897, ".input.spin", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 410, ".input.spin", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 83, "(1)"
+ line 432, ".input.spin", state 96, "(1)"
+ line 437, ".input.spin", state 113, "(1)"
+ line 271, ".input.spin", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, ".input.spin", state 276, "(1)"
+ line 432, ".input.spin", state 289, "(1)"
+ line 437, ".input.spin", state 306, "(1)"
+ line 441, ".input.spin", state 319, "(1)"
+ line 414, ".input.spin", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, ".input.spin", state 420, "(1)"
+ line 437, ".input.spin", state 437, "(1)"
+ line 441, ".input.spin", state 450, "(1)"
+ line 414, ".input.spin", state 495, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 513, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, ".input.spin", state 559, "(1)"
+ line 437, ".input.spin", state 576, "(1)"
+ line 441, ".input.spin", state 589, "(1)"
+ line 414, ".input.spin", state 624, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 642, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 656, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, ".input.spin", state 688, "(1)"
+ line 437, ".input.spin", state 705, "(1)"
+ line 441, ".input.spin", state 718, "(1)"
+ line 414, ".input.spin", state 755, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 773, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 787, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, ".input.spin", state 819, "(1)"
+ line 437, ".input.spin", state 836, "(1)"
+ line 441, ".input.spin", state 849, "(1)"
+ line 271, ".input.spin", state 904, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 913, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 928, "(1)"
+ line 283, ".input.spin", state 935, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 951, "(1)"
+ line 252, ".input.spin", state 959, "(1)"
+ line 256, ".input.spin", state 971, "(1)"
+ line 260, ".input.spin", state 979, "(1)"
+ line 275, ".input.spin", state 1004, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1017, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1026, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1042, "(1)"
+ line 252, ".input.spin", state 1050, "(1)"
+ line 256, ".input.spin", state 1062, "(1)"
+ line 260, ".input.spin", state 1070, "(1)"
+ line 275, ".input.spin", state 1095, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1108, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1117, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1133, "(1)"
+ line 252, ".input.spin", state 1141, "(1)"
+ line 256, ".input.spin", state 1153, "(1)"
+ line 260, ".input.spin", state 1161, "(1)"
+ line 275, ".input.spin", state 1186, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1199, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1208, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1224, "(1)"
+ line 252, ".input.spin", state 1232, "(1)"
+ line 256, ".input.spin", state 1244, "(1)"
+ line 260, ".input.spin", state 1252, "(1)"
+ line 1236, ".input.spin", state 1267, "-end-"
+ (71 of 1267 states)
+unreached in proctype :init:
+ (0 of 78 states)
+
+pan: elapsed time 4.59e+03 seconds
+pan: rate 1460.6376 states/second
+pan: avg transition delay 1.0334e-06 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1294)
+Depth= 5182 States= 1e+06 Transitions= 6.22e+08 Memory= 550.432 t= 762 R= 1e+03
+Depth= 5473 States= 2e+06 Transitions= 1.3e+09 Memory= 634.318 t= 1.62e+03 R= 1e+03
+Depth= 5473 States= 3e+06 Transitions= 1.95e+09 Memory= 718.303 t= 2.47e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 5473 States= 4e+06 Transitions= 2.64e+09 Memory= 833.311 t= 3.32e+03 R= 1e+03
+Depth= 5473 States= 5e+06 Transitions= 3.3e+09 Memory= 917.295 t= 4.14e+03 R= 1e+03
+Depth= 5582 States= 6e+06 Transitions= 3.99e+09 Memory= 1001.279 t= 5e+03 R= 1e+03
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5582, errors: 0
+ 6711104 states, stored
+4.4393362e+09 states, matched
+4.4460473e+09 transitions (= stored+matched)
+2.5322962e+10 atomic steps
+hash conflicts: 3.3328749e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 742.424 equivalent memory usage for states (stored*(State-vector + overhead))
+ 571.575 actual memory usage for states (compression: 76.99%)
+ state-vector as stored = 61 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1060.947 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 410, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 82, "(1)"
+ line 437, "pan.___", state 112, "(1)"
+ line 441, "pan.___", state 125, "(1)"
+ line 596, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 410, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 218, "(1)"
+ line 437, "pan.___", state 248, "(1)"
+ line 441, "pan.___", state 261, "(1)"
+ line 410, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 347, "(1)"
+ line 437, "pan.___", state 377, "(1)"
+ line 441, "pan.___", state 390, "(1)"
+ line 410, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 415, "(1)"
+ line 410, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 416, "else"
+ line 410, "pan.___", state 419, "(1)"
+ line 414, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 429, "(1)"
+ line 414, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 430, "else"
+ line 414, "pan.___", state 433, "(1)"
+ line 414, "pan.___", state 434, "(1)"
+ line 414, "pan.___", state 434, "(1)"
+ line 412, "pan.___", state 439, "((i<1))"
+ line 412, "pan.___", state 439, "((i>=1))"
+ line 419, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 447, "(1)"
+ line 419, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 448, "else"
+ line 419, "pan.___", state 451, "(1)"
+ line 419, "pan.___", state 452, "(1)"
+ line 419, "pan.___", state 452, "(1)"
+ line 423, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 461, "(1)"
+ line 423, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 462, "else"
+ line 423, "pan.___", state 465, "(1)"
+ line 423, "pan.___", state 466, "(1)"
+ line 423, "pan.___", state 466, "(1)"
+ line 421, "pan.___", state 471, "((i<2))"
+ line 421, "pan.___", state 471, "((i>=2))"
+ line 428, "pan.___", state 478, "(1)"
+ line 428, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, "pan.___", state 479, "else"
+ line 428, "pan.___", state 482, "(1)"
+ line 428, "pan.___", state 483, "(1)"
+ line 428, "pan.___", state 483, "(1)"
+ line 432, "pan.___", state 491, "(1)"
+ line 432, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, "pan.___", state 492, "else"
+ line 432, "pan.___", state 495, "(1)"
+ line 432, "pan.___", state 496, "(1)"
+ line 432, "pan.___", state 496, "(1)"
+ line 430, "pan.___", state 501, "((i<1))"
+ line 430, "pan.___", state 501, "((i>=1))"
+ line 437, "pan.___", state 508, "(1)"
+ line 437, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, "pan.___", state 509, "else"
+ line 437, "pan.___", state 512, "(1)"
+ line 437, "pan.___", state 513, "(1)"
+ line 437, "pan.___", state 513, "(1)"
+ line 441, "pan.___", state 521, "(1)"
+ line 441, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, "pan.___", state 522, "else"
+ line 441, "pan.___", state 525, "(1)"
+ line 441, "pan.___", state 526, "(1)"
+ line 441, "pan.___", state 526, "(1)"
+ line 439, "pan.___", state 531, "((i<2))"
+ line 439, "pan.___", state 531, "((i>=2))"
+ line 449, "pan.___", state 535, "(1)"
+ line 449, "pan.___", state 535, "(1)"
+ line 596, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 596, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 596, "pan.___", state 540, "(1)"
+ line 271, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 555, "(1)"
+ line 279, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 591, "(1)"
+ line 252, "pan.___", state 599, "(1)"
+ line 256, "pan.___", state 611, "(1)"
+ line 260, "pan.___", state 619, "(1)"
+ line 410, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 702, "(1)"
+ line 432, "pan.___", state 715, "(1)"
+ line 437, "pan.___", state 732, "(1)"
+ line 441, "pan.___", state 745, "(1)"
+ line 410, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 838, "(1)"
+ line 437, "pan.___", state 868, "(1)"
+ line 441, "pan.___", state 881, "(1)"
+ line 410, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 904, "(1)"
+ line 410, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 905, "else"
+ line 410, "pan.___", state 908, "(1)"
+ line 414, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 918, "(1)"
+ line 414, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 919, "else"
+ line 414, "pan.___", state 922, "(1)"
+ line 414, "pan.___", state 923, "(1)"
+ line 414, "pan.___", state 923, "(1)"
+ line 412, "pan.___", state 928, "((i<1))"
+ line 412, "pan.___", state 928, "((i>=1))"
+ line 419, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 936, "(1)"
+ line 419, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 937, "else"
+ line 419, "pan.___", state 940, "(1)"
+ line 419, "pan.___", state 941, "(1)"
+ line 419, "pan.___", state 941, "(1)"
+ line 423, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 950, "(1)"
+ line 423, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 951, "else"
+ line 423, "pan.___", state 954, "(1)"
+ line 423, "pan.___", state 955, "(1)"
+ line 423, "pan.___", state 955, "(1)"
+ line 421, "pan.___", state 960, "((i<2))"
+ line 421, "pan.___", state 960, "((i>=2))"
+ line 428, "pan.___", state 967, "(1)"
+ line 428, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, "pan.___", state 968, "else"
+ line 428, "pan.___", state 971, "(1)"
+ line 428, "pan.___", state 972, "(1)"
+ line 428, "pan.___", state 972, "(1)"
+ line 432, "pan.___", state 980, "(1)"
+ line 432, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, "pan.___", state 981, "else"
+ line 432, "pan.___", state 984, "(1)"
+ line 432, "pan.___", state 985, "(1)"
+ line 432, "pan.___", state 985, "(1)"
+ line 430, "pan.___", state 990, "((i<1))"
+ line 430, "pan.___", state 990, "((i>=1))"
+ line 437, "pan.___", state 997, "(1)"
+ line 437, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, "pan.___", state 998, "else"
+ line 437, "pan.___", state 1001, "(1)"
+ line 437, "pan.___", state 1002, "(1)"
+ line 437, "pan.___", state 1002, "(1)"
+ line 441, "pan.___", state 1010, "(1)"
+ line 441, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, "pan.___", state 1011, "else"
+ line 441, "pan.___", state 1014, "(1)"
+ line 441, "pan.___", state 1015, "(1)"
+ line 441, "pan.___", state 1015, "(1)"
+ line 439, "pan.___", state 1020, "((i<2))"
+ line 439, "pan.___", state 1020, "((i>=2))"
+ line 449, "pan.___", state 1024, "(1)"
+ line 449, "pan.___", state 1024, "(1)"
+ line 604, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 410, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1098, "(1)"
+ line 432, "pan.___", state 1111, "(1)"
+ line 437, "pan.___", state 1128, "(1)"
+ line 441, "pan.___", state 1141, "(1)"
+ line 410, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1230, "(1)"
+ line 437, "pan.___", state 1260, "(1)"
+ line 441, "pan.___", state 1273, "(1)"
+ line 410, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1363, "(1)"
+ line 437, "pan.___", state 1393, "(1)"
+ line 441, "pan.___", state 1406, "(1)"
+ line 410, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1492, "(1)"
+ line 437, "pan.___", state 1522, "(1)"
+ line 441, "pan.___", state 1535, "(1)"
+ line 271, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1605, "(1)"
+ line 252, "pan.___", state 1613, "(1)"
+ line 256, "pan.___", state 1625, "(1)"
+ line 260, "pan.___", state 1633, "(1)"
+ line 410, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1716, "(1)"
+ line 432, "pan.___", state 1729, "(1)"
+ line 437, "pan.___", state 1746, "(1)"
+ line 441, "pan.___", state 1759, "(1)"
+ line 410, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1845, "(1)"
+ line 432, "pan.___", state 1858, "(1)"
+ line 437, "pan.___", state 1875, "(1)"
+ line 441, "pan.___", state 1888, "(1)"
+ line 410, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 1977, "(1)"
+ line 437, "pan.___", state 2007, "(1)"
+ line 441, "pan.___", state 2020, "(1)"
+ line 643, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 410, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 2113, "(1)"
+ line 437, "pan.___", state 2143, "(1)"
+ line 441, "pan.___", state 2156, "(1)"
+ line 410, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 2242, "(1)"
+ line 437, "pan.___", state 2272, "(1)"
+ line 441, "pan.___", state 2285, "(1)"
+ line 410, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 2310, "(1)"
+ line 410, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 2311, "else"
+ line 410, "pan.___", state 2314, "(1)"
+ line 414, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2324, "(1)"
+ line 414, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 2325, "else"
+ line 414, "pan.___", state 2328, "(1)"
+ line 414, "pan.___", state 2329, "(1)"
+ line 414, "pan.___", state 2329, "(1)"
+ line 412, "pan.___", state 2334, "((i<1))"
+ line 412, "pan.___", state 2334, "((i>=1))"
+ line 419, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2342, "(1)"
+ line 419, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 2343, "else"
+ line 419, "pan.___", state 2346, "(1)"
+ line 419, "pan.___", state 2347, "(1)"
+ line 419, "pan.___", state 2347, "(1)"
+ line 423, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2356, "(1)"
+ line 423, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 2357, "else"
+ line 423, "pan.___", state 2360, "(1)"
+ line 423, "pan.___", state 2361, "(1)"
+ line 423, "pan.___", state 2361, "(1)"
+ line 421, "pan.___", state 2366, "((i<2))"
+ line 421, "pan.___", state 2366, "((i>=2))"
+ line 428, "pan.___", state 2373, "(1)"
+ line 428, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 428, "pan.___", state 2374, "else"
+ line 428, "pan.___", state 2377, "(1)"
+ line 428, "pan.___", state 2378, "(1)"
+ line 428, "pan.___", state 2378, "(1)"
+ line 432, "pan.___", state 2386, "(1)"
+ line 432, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 432, "pan.___", state 2387, "else"
+ line 432, "pan.___", state 2390, "(1)"
+ line 432, "pan.___", state 2391, "(1)"
+ line 432, "pan.___", state 2391, "(1)"
+ line 430, "pan.___", state 2396, "((i<1))"
+ line 430, "pan.___", state 2396, "((i>=1))"
+ line 437, "pan.___", state 2403, "(1)"
+ line 437, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 437, "pan.___", state 2404, "else"
+ line 437, "pan.___", state 2407, "(1)"
+ line 437, "pan.___", state 2408, "(1)"
+ line 437, "pan.___", state 2408, "(1)"
+ line 441, "pan.___", state 2416, "(1)"
+ line 441, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 441, "pan.___", state 2417, "else"
+ line 441, "pan.___", state 2420, "(1)"
+ line 441, "pan.___", state 2421, "(1)"
+ line 441, "pan.___", state 2421, "(1)"
+ line 439, "pan.___", state 2426, "((i<2))"
+ line 439, "pan.___", state 2426, "((i>=2))"
+ line 449, "pan.___", state 2430, "(1)"
+ line 449, "pan.___", state 2430, "(1)"
+ line 643, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 643, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 643, "pan.___", state 2435, "(1)"
+ line 271, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2486, "(1)"
+ line 252, "pan.___", state 2494, "(1)"
+ line 256, "pan.___", state 2506, "(1)"
+ line 260, "pan.___", state 2514, "(1)"
+ line 410, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 2597, "(1)"
+ line 432, "pan.___", state 2610, "(1)"
+ line 437, "pan.___", state 2627, "(1)"
+ line 441, "pan.___", state 2640, "(1)"
+ line 271, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2711, "(1)"
+ line 252, "pan.___", state 2719, "(1)"
+ line 256, "pan.___", state 2731, "(1)"
+ line 260, "pan.___", state 2739, "(1)"
+ line 410, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 2822, "(1)"
+ line 432, "pan.___", state 2835, "(1)"
+ line 437, "pan.___", state 2852, "(1)"
+ line 441, "pan.___", state 2865, "(1)"
+ line 410, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 2951, "(1)"
+ line 432, "pan.___", state 2964, "(1)"
+ line 437, "pan.___", state 2981, "(1)"
+ line 441, "pan.___", state 2994, "(1)"
+ line 248, "pan.___", state 3027, "(1)"
+ line 256, "pan.___", state 3047, "(1)"
+ line 260, "pan.___", state 3055, "(1)"
+ line 248, "pan.___", state 3070, "(1)"
+ line 252, "pan.___", state 3078, "(1)"
+ line 256, "pan.___", state 3090, "(1)"
+ line 260, "pan.___", state 3098, "(1)"
+ line 897, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 410, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 83, "(1)"
+ line 432, "pan.___", state 96, "(1)"
+ line 437, "pan.___", state 113, "(1)"
+ line 271, "pan.___", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 428, "pan.___", state 276, "(1)"
+ line 432, "pan.___", state 289, "(1)"
+ line 437, "pan.___", state 306, "(1)"
+ line 441, "pan.___", state 319, "(1)"
+ line 414, "pan.___", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, "pan.___", state 420, "(1)"
+ line 437, "pan.___", state 437, "(1)"
+ line 441, "pan.___", state 450, "(1)"
+ line 414, "pan.___", state 495, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 513, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, "pan.___", state 559, "(1)"
+ line 437, "pan.___", state 576, "(1)"
+ line 441, "pan.___", state 589, "(1)"
+ line 414, "pan.___", state 624, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 642, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 656, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, "pan.___", state 688, "(1)"
+ line 437, "pan.___", state 705, "(1)"
+ line 441, "pan.___", state 718, "(1)"
+ line 414, "pan.___", state 755, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 773, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 787, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 432, "pan.___", state 819, "(1)"
+ line 437, "pan.___", state 836, "(1)"
+ line 441, "pan.___", state 849, "(1)"
+ line 271, "pan.___", state 904, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 913, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 928, "(1)"
+ line 283, "pan.___", state 935, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 951, "(1)"
+ line 252, "pan.___", state 959, "(1)"
+ line 256, "pan.___", state 971, "(1)"
+ line 260, "pan.___", state 979, "(1)"
+ line 275, "pan.___", state 1004, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1017, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1026, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1042, "(1)"
+ line 252, "pan.___", state 1050, "(1)"
+ line 256, "pan.___", state 1062, "(1)"
+ line 260, "pan.___", state 1070, "(1)"
+ line 275, "pan.___", state 1095, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1108, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1117, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1133, "(1)"
+ line 252, "pan.___", state 1141, "(1)"
+ line 256, "pan.___", state 1153, "(1)"
+ line 260, "pan.___", state 1161, "(1)"
+ line 275, "pan.___", state 1186, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1199, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1208, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1224, "(1)"
+ line 252, "pan.___", state 1232, "(1)"
+ line 256, "pan.___", state 1244, "(1)"
+ line 260, "pan.___", state 1252, "(1)"
+ line 1236, "pan.___", state 1267, "-end-"
+ (71 of 1267 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1299, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 5.57e+03 seconds
+pan: rate 1203.9777 states/second
+pan: avg transition delay 1.2537e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+[] (!read_poison)
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 5985 States= 1e+06 Transitions= 3.71e+08 Memory= 550.432 t= 439 R= 2e+03
+Depth= 8926 States= 2e+06 Transitions= 9.51e+08 Memory= 634.416 t= 1.15e+03 R= 2e+03
+Depth= 8926 States= 3e+06 Transitions= 1.54e+09 Memory= 718.303 t= 1.89e+03 R= 2e+03
+pan: resizing hashtable to -w22.. done
+Depth= 8926 States= 4e+06 Transitions= 2.08e+09 Memory= 833.311 t= 2.56e+03 R= 2e+03
+Depth= 8926 States= 5e+06 Transitions= 2.46e+09 Memory= 917.295 t= 3.01e+03 R= 2e+03
+Depth= 8926 States= 6e+06 Transitions= 2.91e+09 Memory= 1001.279 t= 3.56e+03 R= 2e+03
+pan: claim violated! (at depth 1267)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 8926, errors: 1
+ 6822337 states, stored
+3.2012922e+09 states, matched
+3.2081145e+09 transitions (= stored+matched)
+1.7190132e+10 atomic steps
+hash conflicts: 2.341747e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 754.729 equivalent memory usage for states (stored*(State-vector + overhead))
+ 580.944 actual memory usage for states (compression: 76.97%)
+ state-vector as stored = 61 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1070.322 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 21, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 53, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 67, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 86, "(1)"
+ line 438, "pan.___", state 116, "(1)"
+ line 442, "pan.___", state 129, "(1)"
+ line 603, "pan.___", state 150, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 157, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 189, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 203, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 222, "(1)"
+ line 438, "pan.___", state 252, "(1)"
+ line 442, "pan.___", state 265, "(1)"
+ line 411, "pan.___", state 286, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 318, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 332, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 351, "(1)"
+ line 438, "pan.___", state 381, "(1)"
+ line 442, "pan.___", state 394, "(1)"
+ line 411, "pan.___", state 417, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 419, "(1)"
+ line 411, "pan.___", state 420, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 420, "else"
+ line 411, "pan.___", state 423, "(1)"
+ line 415, "pan.___", state 431, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 434, "else"
+ line 415, "pan.___", state 437, "(1)"
+ line 415, "pan.___", state 438, "(1)"
+ line 415, "pan.___", state 438, "(1)"
+ line 413, "pan.___", state 443, "((i<1))"
+ line 413, "pan.___", state 443, "((i>=1))"
+ line 420, "pan.___", state 449, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 452, "else"
+ line 420, "pan.___", state 455, "(1)"
+ line 420, "pan.___", state 456, "(1)"
+ line 420, "pan.___", state 456, "(1)"
+ line 424, "pan.___", state 463, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 466, "else"
+ line 424, "pan.___", state 469, "(1)"
+ line 424, "pan.___", state 470, "(1)"
+ line 424, "pan.___", state 470, "(1)"
+ line 422, "pan.___", state 475, "((i<2))"
+ line 422, "pan.___", state 475, "((i>=2))"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 483, "else"
+ line 429, "pan.___", state 486, "(1)"
+ line 429, "pan.___", state 487, "(1)"
+ line 429, "pan.___", state 487, "(1)"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 496, "else"
+ line 433, "pan.___", state 499, "(1)"
+ line 433, "pan.___", state 500, "(1)"
+ line 433, "pan.___", state 500, "(1)"
+ line 431, "pan.___", state 505, "((i<1))"
+ line 431, "pan.___", state 505, "((i>=1))"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 513, "else"
+ line 438, "pan.___", state 516, "(1)"
+ line 438, "pan.___", state 517, "(1)"
+ line 438, "pan.___", state 517, "(1)"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 526, "else"
+ line 442, "pan.___", state 529, "(1)"
+ line 442, "pan.___", state 530, "(1)"
+ line 442, "pan.___", state 530, "(1)"
+ line 440, "pan.___", state 535, "((i<2))"
+ line 440, "pan.___", state 535, "((i>=2))"
+ line 450, "pan.___", state 539, "(1)"
+ line 450, "pan.___", state 539, "(1)"
+ line 603, "pan.___", state 542, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 603, "pan.___", state 543, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 603, "pan.___", state 544, "(1)"
+ line 272, "pan.___", state 548, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 550, "(1)"
+ line 276, "pan.___", state 557, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 559, "(1)"
+ line 276, "pan.___", state 560, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 560, "else"
+ line 274, "pan.___", state 565, "((i<1))"
+ line 274, "pan.___", state 565, "((i>=1))"
+ line 280, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 572, "(1)"
+ line 280, "pan.___", state 573, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 573, "else"
+ line 284, "pan.___", state 579, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 581, "(1)"
+ line 284, "pan.___", state 582, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 582, "else"
+ line 282, "pan.___", state 587, "((i<2))"
+ line 282, "pan.___", state 587, "((i>=2))"
+ line 249, "pan.___", state 595, "(1)"
+ line 253, "pan.___", state 603, "(1)"
+ line 253, "pan.___", state 604, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 604, "else"
+ line 251, "pan.___", state 609, "((i<1))"
+ line 251, "pan.___", state 609, "((i>=1))"
+ line 257, "pan.___", state 615, "(1)"
+ line 257, "pan.___", state 616, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 616, "else"
+ line 261, "pan.___", state 623, "(1)"
+ line 261, "pan.___", state 624, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 624, "else"
+ line 266, "pan.___", state 633, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 633, "else"
+ line 299, "pan.___", state 635, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 635, "else"
+ line 411, "pan.___", state 641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 673, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 687, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 706, "(1)"
+ line 438, "pan.___", state 736, "(1)"
+ line 442, "pan.___", state 749, "(1)"
+ line 411, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 809, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 823, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 842, "(1)"
+ line 438, "pan.___", state 872, "(1)"
+ line 442, "pan.___", state 885, "(1)"
+ line 411, "pan.___", state 906, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 908, "(1)"
+ line 411, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 909, "else"
+ line 411, "pan.___", state 912, "(1)"
+ line 415, "pan.___", state 920, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 923, "else"
+ line 415, "pan.___", state 926, "(1)"
+ line 415, "pan.___", state 927, "(1)"
+ line 415, "pan.___", state 927, "(1)"
+ line 413, "pan.___", state 932, "((i<1))"
+ line 413, "pan.___", state 932, "((i>=1))"
+ line 420, "pan.___", state 938, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 941, "else"
+ line 420, "pan.___", state 944, "(1)"
+ line 420, "pan.___", state 945, "(1)"
+ line 420, "pan.___", state 945, "(1)"
+ line 424, "pan.___", state 952, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 955, "else"
+ line 424, "pan.___", state 958, "(1)"
+ line 424, "pan.___", state 959, "(1)"
+ line 424, "pan.___", state 959, "(1)"
+ line 422, "pan.___", state 964, "((i<2))"
+ line 422, "pan.___", state 964, "((i>=2))"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 972, "else"
+ line 429, "pan.___", state 975, "(1)"
+ line 429, "pan.___", state 976, "(1)"
+ line 429, "pan.___", state 976, "(1)"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 985, "else"
+ line 433, "pan.___", state 988, "(1)"
+ line 433, "pan.___", state 989, "(1)"
+ line 433, "pan.___", state 989, "(1)"
+ line 431, "pan.___", state 994, "((i<1))"
+ line 431, "pan.___", state 994, "((i>=1))"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 1002, "else"
+ line 438, "pan.___", state 1005, "(1)"
+ line 438, "pan.___", state 1006, "(1)"
+ line 438, "pan.___", state 1006, "(1)"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1015, "else"
+ line 442, "pan.___", state 1018, "(1)"
+ line 442, "pan.___", state 1019, "(1)"
+ line 442, "pan.___", state 1019, "(1)"
+ line 440, "pan.___", state 1024, "((i<2))"
+ line 440, "pan.___", state 1024, "((i>=2))"
+ line 450, "pan.___", state 1028, "(1)"
+ line 450, "pan.___", state 1028, "(1)"
+ line 611, "pan.___", state 1032, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1037, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1069, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1083, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1102, "(1)"
+ line 438, "pan.___", state 1132, "(1)"
+ line 442, "pan.___", state 1145, "(1)"
+ line 411, "pan.___", state 1169, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1201, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1215, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1234, "(1)"
+ line 438, "pan.___", state 1264, "(1)"
+ line 442, "pan.___", state 1277, "(1)"
+ line 411, "pan.___", state 1302, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1334, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1348, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1367, "(1)"
+ line 438, "pan.___", state 1397, "(1)"
+ line 442, "pan.___", state 1410, "(1)"
+ line 411, "pan.___", state 1431, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1463, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1477, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1496, "(1)"
+ line 438, "pan.___", state 1526, "(1)"
+ line 442, "pan.___", state 1539, "(1)"
+ line 272, "pan.___", state 1562, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1564, "(1)"
+ line 276, "pan.___", state 1571, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1573, "(1)"
+ line 276, "pan.___", state 1574, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1574, "else"
+ line 274, "pan.___", state 1579, "((i<1))"
+ line 274, "pan.___", state 1579, "((i>=1))"
+ line 280, "pan.___", state 1584, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1586, "(1)"
+ line 280, "pan.___", state 1587, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1587, "else"
+ line 284, "pan.___", state 1593, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1595, "(1)"
+ line 284, "pan.___", state 1596, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1596, "else"
+ line 282, "pan.___", state 1601, "((i<2))"
+ line 282, "pan.___", state 1601, "((i>=2))"
+ line 249, "pan.___", state 1609, "(1)"
+ line 253, "pan.___", state 1617, "(1)"
+ line 253, "pan.___", state 1618, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1618, "else"
+ line 251, "pan.___", state 1623, "((i<1))"
+ line 251, "pan.___", state 1623, "((i>=1))"
+ line 257, "pan.___", state 1629, "(1)"
+ line 257, "pan.___", state 1630, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1630, "else"
+ line 261, "pan.___", state 1637, "(1)"
+ line 261, "pan.___", state 1638, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1638, "else"
+ line 266, "pan.___", state 1647, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1647, "else"
+ line 299, "pan.___", state 1649, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1649, "else"
+ line 411, "pan.___", state 1655, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1687, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1701, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1720, "(1)"
+ line 438, "pan.___", state 1750, "(1)"
+ line 442, "pan.___", state 1763, "(1)"
+ line 411, "pan.___", state 1784, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1816, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1830, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1849, "(1)"
+ line 438, "pan.___", state 1879, "(1)"
+ line 442, "pan.___", state 1892, "(1)"
+ line 411, "pan.___", state 1916, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1948, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1962, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1981, "(1)"
+ line 438, "pan.___", state 2011, "(1)"
+ line 442, "pan.___", state 2024, "(1)"
+ line 650, "pan.___", state 2045, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2084, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2098, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2117, "(1)"
+ line 438, "pan.___", state 2147, "(1)"
+ line 442, "pan.___", state 2160, "(1)"
+ line 411, "pan.___", state 2181, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2213, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2227, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2246, "(1)"
+ line 438, "pan.___", state 2276, "(1)"
+ line 442, "pan.___", state 2289, "(1)"
+ line 411, "pan.___", state 2312, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2314, "(1)"
+ line 411, "pan.___", state 2315, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2315, "else"
+ line 411, "pan.___", state 2318, "(1)"
+ line 415, "pan.___", state 2326, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2329, "else"
+ line 415, "pan.___", state 2332, "(1)"
+ line 415, "pan.___", state 2333, "(1)"
+ line 415, "pan.___", state 2333, "(1)"
+ line 413, "pan.___", state 2338, "((i<1))"
+ line 413, "pan.___", state 2338, "((i>=1))"
+ line 420, "pan.___", state 2344, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2347, "else"
+ line 420, "pan.___", state 2350, "(1)"
+ line 420, "pan.___", state 2351, "(1)"
+ line 420, "pan.___", state 2351, "(1)"
+ line 424, "pan.___", state 2358, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2361, "else"
+ line 424, "pan.___", state 2364, "(1)"
+ line 424, "pan.___", state 2365, "(1)"
+ line 424, "pan.___", state 2365, "(1)"
+ line 422, "pan.___", state 2370, "((i<2))"
+ line 422, "pan.___", state 2370, "((i>=2))"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2378, "else"
+ line 429, "pan.___", state 2381, "(1)"
+ line 429, "pan.___", state 2382, "(1)"
+ line 429, "pan.___", state 2382, "(1)"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2391, "else"
+ line 433, "pan.___", state 2394, "(1)"
+ line 433, "pan.___", state 2395, "(1)"
+ line 433, "pan.___", state 2395, "(1)"
+ line 431, "pan.___", state 2400, "((i<1))"
+ line 431, "pan.___", state 2400, "((i>=1))"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2408, "else"
+ line 438, "pan.___", state 2411, "(1)"
+ line 438, "pan.___", state 2412, "(1)"
+ line 438, "pan.___", state 2412, "(1)"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2421, "else"
+ line 442, "pan.___", state 2424, "(1)"
+ line 442, "pan.___", state 2425, "(1)"
+ line 442, "pan.___", state 2425, "(1)"
+ line 440, "pan.___", state 2430, "((i<2))"
+ line 440, "pan.___", state 2430, "((i>=2))"
+ line 450, "pan.___", state 2434, "(1)"
+ line 450, "pan.___", state 2434, "(1)"
+ line 650, "pan.___", state 2437, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 650, "pan.___", state 2438, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 650, "pan.___", state 2439, "(1)"
+ line 272, "pan.___", state 2443, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 2445, "(1)"
+ line 276, "pan.___", state 2452, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2454, "(1)"
+ line 276, "pan.___", state 2455, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 2455, "else"
+ line 274, "pan.___", state 2460, "((i<1))"
+ line 274, "pan.___", state 2460, "((i>=1))"
+ line 280, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2467, "(1)"
+ line 280, "pan.___", state 2468, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 2468, "else"
+ line 284, "pan.___", state 2474, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2476, "(1)"
+ line 284, "pan.___", state 2477, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 2477, "else"
+ line 282, "pan.___", state 2482, "((i<2))"
+ line 282, "pan.___", state 2482, "((i>=2))"
+ line 249, "pan.___", state 2490, "(1)"
+ line 253, "pan.___", state 2498, "(1)"
+ line 253, "pan.___", state 2499, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2499, "else"
+ line 251, "pan.___", state 2504, "((i<1))"
+ line 251, "pan.___", state 2504, "((i>=1))"
+ line 257, "pan.___", state 2510, "(1)"
+ line 257, "pan.___", state 2511, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2511, "else"
+ line 261, "pan.___", state 2518, "(1)"
+ line 261, "pan.___", state 2519, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2519, "else"
+ line 266, "pan.___", state 2528, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2528, "else"
+ line 299, "pan.___", state 2530, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 2530, "else"
+ line 411, "pan.___", state 2536, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2568, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2582, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2601, "(1)"
+ line 438, "pan.___", state 2631, "(1)"
+ line 442, "pan.___", state 2644, "(1)"
+ line 272, "pan.___", state 2668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 2670, "(1)"
+ line 276, "pan.___", state 2677, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2679, "(1)"
+ line 276, "pan.___", state 2680, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 2680, "else"
+ line 274, "pan.___", state 2685, "((i<1))"
+ line 274, "pan.___", state 2685, "((i>=1))"
+ line 280, "pan.___", state 2690, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2692, "(1)"
+ line 280, "pan.___", state 2693, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 2693, "else"
+ line 284, "pan.___", state 2699, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2701, "(1)"
+ line 284, "pan.___", state 2702, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 2702, "else"
+ line 282, "pan.___", state 2707, "((i<2))"
+ line 282, "pan.___", state 2707, "((i>=2))"
+ line 249, "pan.___", state 2715, "(1)"
+ line 253, "pan.___", state 2723, "(1)"
+ line 253, "pan.___", state 2724, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2724, "else"
+ line 251, "pan.___", state 2729, "((i<1))"
+ line 251, "pan.___", state 2729, "((i>=1))"
+ line 257, "pan.___", state 2735, "(1)"
+ line 257, "pan.___", state 2736, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2736, "else"
+ line 261, "pan.___", state 2743, "(1)"
+ line 261, "pan.___", state 2744, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2744, "else"
+ line 266, "pan.___", state 2753, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2753, "else"
+ line 299, "pan.___", state 2755, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 2755, "else"
+ line 411, "pan.___", state 2761, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2793, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2807, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2826, "(1)"
+ line 438, "pan.___", state 2856, "(1)"
+ line 442, "pan.___", state 2869, "(1)"
+ line 411, "pan.___", state 2890, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2922, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2936, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2955, "(1)"
+ line 438, "pan.___", state 2985, "(1)"
+ line 442, "pan.___", state 2998, "(1)"
+ line 249, "pan.___", state 3031, "(1)"
+ line 257, "pan.___", state 3051, "(1)"
+ line 261, "pan.___", state 3059, "(1)"
+ line 249, "pan.___", state 3074, "(1)"
+ line 257, "pan.___", state 3094, "(1)"
+ line 261, "pan.___", state 3102, "(1)"
+ line 898, "pan.___", state 3119, "-end-"
+ (330 of 3119 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 20, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 26, "(1)"
+ line 415, "pan.___", state 34, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 40, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 413, "pan.___", state 46, "((i<1))"
+ line 413, "pan.___", state 46, "((i>=1))"
+ line 420, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 58, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 424, "pan.___", state 72, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 422, "pan.___", state 78, "((i<2))"
+ line 422, "pan.___", state 78, "((i>=2))"
+ line 429, "pan.___", state 85, "(1)"
+ line 429, "pan.___", state 86, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 86, "else"
+ line 429, "pan.___", state 89, "(1)"
+ line 429, "pan.___", state 90, "(1)"
+ line 429, "pan.___", state 90, "(1)"
+ line 433, "pan.___", state 98, "(1)"
+ line 433, "pan.___", state 99, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 99, "else"
+ line 433, "pan.___", state 102, "(1)"
+ line 433, "pan.___", state 103, "(1)"
+ line 433, "pan.___", state 103, "(1)"
+ line 431, "pan.___", state 108, "((i<1))"
+ line 431, "pan.___", state 108, "((i>=1))"
+ line 438, "pan.___", state 115, "(1)"
+ line 438, "pan.___", state 116, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 116, "else"
+ line 438, "pan.___", state 119, "(1)"
+ line 438, "pan.___", state 120, "(1)"
+ line 438, "pan.___", state 120, "(1)"
+ line 442, "pan.___", state 128, "(1)"
+ line 442, "pan.___", state 129, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 129, "else"
+ line 442, "pan.___", state 132, "(1)"
+ line 442, "pan.___", state 133, "(1)"
+ line 442, "pan.___", state 133, "(1)"
+ line 440, "pan.___", state 138, "((i<2))"
+ line 440, "pan.___", state 138, "((i>=2))"
+ line 450, "pan.___", state 142, "(1)"
+ line 450, "pan.___", state 142, "(1)"
+ line 272, "pan.___", state 151, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 160, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 274, "pan.___", state 168, "((i<1))"
+ line 274, "pan.___", state 168, "((i>=1))"
+ line 280, "pan.___", state 173, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 1021, "pan.___", state 201, "old_data = cached_rcu_ptr.val[_pid]"
+ line 1032, "pan.___", state 205, "_proc_urcu_writer = (_proc_urcu_writer|(1<<4))"
+ line 411, "pan.___", state 213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 219, "(1)"
+ line 415, "pan.___", state 227, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 233, "(1)"
+ line 415, "pan.___", state 234, "(1)"
+ line 415, "pan.___", state 234, "(1)"
+ line 413, "pan.___", state 239, "((i<1))"
+ line 413, "pan.___", state 239, "((i>=1))"
+ line 420, "pan.___", state 247, "(1)"
+ line 420, "pan.___", state 248, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 248, "else"
+ line 420, "pan.___", state 251, "(1)"
+ line 420, "pan.___", state 252, "(1)"
+ line 420, "pan.___", state 252, "(1)"
+ line 424, "pan.___", state 259, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 265, "(1)"
+ line 424, "pan.___", state 266, "(1)"
+ line 424, "pan.___", state 266, "(1)"
+ line 422, "pan.___", state 271, "((i<2))"
+ line 422, "pan.___", state 271, "((i>=2))"
+ line 429, "pan.___", state 278, "(1)"
+ line 429, "pan.___", state 279, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 279, "else"
+ line 429, "pan.___", state 282, "(1)"
+ line 429, "pan.___", state 283, "(1)"
+ line 429, "pan.___", state 283, "(1)"
+ line 433, "pan.___", state 291, "(1)"
+ line 433, "pan.___", state 292, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 292, "else"
+ line 433, "pan.___", state 295, "(1)"
+ line 433, "pan.___", state 296, "(1)"
+ line 433, "pan.___", state 296, "(1)"
+ line 431, "pan.___", state 301, "((i<1))"
+ line 431, "pan.___", state 301, "((i>=1))"
+ line 438, "pan.___", state 308, "(1)"
+ line 438, "pan.___", state 309, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 309, "else"
+ line 438, "pan.___", state 312, "(1)"
+ line 438, "pan.___", state 313, "(1)"
+ line 438, "pan.___", state 313, "(1)"
+ line 442, "pan.___", state 321, "(1)"
+ line 442, "pan.___", state 322, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 322, "else"
+ line 442, "pan.___", state 325, "(1)"
+ line 442, "pan.___", state 326, "(1)"
+ line 442, "pan.___", state 326, "(1)"
+ line 440, "pan.___", state 331, "((i<2))"
+ line 440, "pan.___", state 331, "((i>=2))"
+ line 450, "pan.___", state 335, "(1)"
+ line 450, "pan.___", state 335, "(1)"
+ line 411, "pan.___", state 346, "(1)"
+ line 411, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 347, "else"
+ line 411, "pan.___", state 350, "(1)"
+ line 415, "pan.___", state 358, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 364, "(1)"
+ line 415, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 365, "(1)"
+ line 413, "pan.___", state 370, "((i<1))"
+ line 413, "pan.___", state 370, "((i>=1))"
+ line 420, "pan.___", state 376, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 382, "(1)"
+ line 420, "pan.___", state 383, "(1)"
+ line 420, "pan.___", state 383, "(1)"
+ line 424, "pan.___", state 390, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 396, "(1)"
+ line 424, "pan.___", state 397, "(1)"
+ line 424, "pan.___", state 397, "(1)"
+ line 422, "pan.___", state 402, "((i<2))"
+ line 422, "pan.___", state 402, "((i>=2))"
+ line 429, "pan.___", state 409, "(1)"
+ line 429, "pan.___", state 410, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 410, "else"
+ line 429, "pan.___", state 413, "(1)"
+ line 429, "pan.___", state 414, "(1)"
+ line 429, "pan.___", state 414, "(1)"
+ line 433, "pan.___", state 422, "(1)"
+ line 433, "pan.___", state 423, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 423, "else"
+ line 433, "pan.___", state 426, "(1)"
+ line 433, "pan.___", state 427, "(1)"
+ line 433, "pan.___", state 427, "(1)"
+ line 431, "pan.___", state 432, "((i<1))"
+ line 431, "pan.___", state 432, "((i>=1))"
+ line 438, "pan.___", state 439, "(1)"
+ line 438, "pan.___", state 440, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 440, "else"
+ line 438, "pan.___", state 443, "(1)"
+ line 438, "pan.___", state 444, "(1)"
+ line 438, "pan.___", state 444, "(1)"
+ line 442, "pan.___", state 452, "(1)"
+ line 442, "pan.___", state 453, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 453, "else"
+ line 442, "pan.___", state 456, "(1)"
+ line 442, "pan.___", state 457, "(1)"
+ line 442, "pan.___", state 457, "(1)"
+ line 440, "pan.___", state 462, "((i<2))"
+ line 440, "pan.___", state 462, "((i>=2))"
+ line 450, "pan.___", state 466, "(1)"
+ line 450, "pan.___", state 466, "(1)"
+ line 1086, "pan.___", state 477, "_proc_urcu_writer = (_proc_urcu_writer&~((1<<9)))"
+ line 1091, "pan.___", state 478, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<8)|(1<<7))))"
+ line 411, "pan.___", state 483, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 489, "(1)"
+ line 415, "pan.___", state 497, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 503, "(1)"
+ line 415, "pan.___", state 504, "(1)"
+ line 415, "pan.___", state 504, "(1)"
+ line 413, "pan.___", state 509, "((i<1))"
+ line 413, "pan.___", state 509, "((i>=1))"
+ line 420, "pan.___", state 515, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 521, "(1)"
+ line 420, "pan.___", state 522, "(1)"
+ line 420, "pan.___", state 522, "(1)"
+ line 424, "pan.___", state 529, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 535, "(1)"
+ line 424, "pan.___", state 536, "(1)"
+ line 424, "pan.___", state 536, "(1)"
+ line 422, "pan.___", state 541, "((i<2))"
+ line 422, "pan.___", state 541, "((i>=2))"
+ line 429, "pan.___", state 548, "(1)"
+ line 429, "pan.___", state 549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 549, "else"
+ line 429, "pan.___", state 552, "(1)"
+ line 429, "pan.___", state 553, "(1)"
+ line 429, "pan.___", state 553, "(1)"
+ line 433, "pan.___", state 561, "(1)"
+ line 433, "pan.___", state 562, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 562, "else"
+ line 433, "pan.___", state 565, "(1)"
+ line 433, "pan.___", state 566, "(1)"
+ line 433, "pan.___", state 566, "(1)"
+ line 431, "pan.___", state 571, "((i<1))"
+ line 431, "pan.___", state 571, "((i>=1))"
+ line 438, "pan.___", state 578, "(1)"
+ line 438, "pan.___", state 579, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 579, "else"
+ line 438, "pan.___", state 582, "(1)"
+ line 438, "pan.___", state 583, "(1)"
+ line 438, "pan.___", state 583, "(1)"
+ line 442, "pan.___", state 591, "(1)"
+ line 442, "pan.___", state 592, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 592, "else"
+ line 442, "pan.___", state 595, "(1)"
+ line 442, "pan.___", state 596, "(1)"
+ line 442, "pan.___", state 596, "(1)"
+ line 450, "pan.___", state 605, "(1)"
+ line 450, "pan.___", state 605, "(1)"
+ line 411, "pan.___", state 612, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 626, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 644, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 677, "(1)"
+ line 433, "pan.___", state 690, "(1)"
+ line 438, "pan.___", state 707, "(1)"
+ line 442, "pan.___", state 720, "(1)"
+ line 415, "pan.___", state 757, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 775, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 789, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 821, "(1)"
+ line 438, "pan.___", state 838, "(1)"
+ line 442, "pan.___", state 851, "(1)"
+ line 1168, "pan.___", state 878, "_proc_urcu_writer = (_proc_urcu_writer|(1<<13))"
+ line 272, "pan.___", state 906, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 908, "(1)"
+ line 276, "pan.___", state 915, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 917, "(1)"
+ line 276, "pan.___", state 918, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 918, "else"
+ line 274, "pan.___", state 923, "((i<1))"
+ line 274, "pan.___", state 923, "((i>=1))"
+ line 280, "pan.___", state 928, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 930, "(1)"
+ line 280, "pan.___", state 931, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 931, "else"
+ line 284, "pan.___", state 937, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 939, "(1)"
+ line 284, "pan.___", state 940, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 940, "else"
+ line 282, "pan.___", state 945, "((i<2))"
+ line 282, "pan.___", state 945, "((i>=2))"
+ line 249, "pan.___", state 953, "(1)"
+ line 253, "pan.___", state 961, "(1)"
+ line 253, "pan.___", state 962, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 962, "else"
+ line 251, "pan.___", state 967, "((i<1))"
+ line 251, "pan.___", state 967, "((i>=1))"
+ line 257, "pan.___", state 973, "(1)"
+ line 257, "pan.___", state 974, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 974, "else"
+ line 261, "pan.___", state 981, "(1)"
+ line 261, "pan.___", state 982, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 982, "else"
+ line 266, "pan.___", state 991, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 991, "else"
+ line 299, "pan.___", state 993, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 993, "else"
+ line 272, "pan.___", state 997, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 999, "(1)"
+ line 276, "pan.___", state 1006, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1008, "(1)"
+ line 276, "pan.___", state 1009, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1009, "else"
+ line 274, "pan.___", state 1014, "((i<1))"
+ line 274, "pan.___", state 1014, "((i>=1))"
+ line 280, "pan.___", state 1019, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1021, "(1)"
+ line 280, "pan.___", state 1022, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1022, "else"
+ line 284, "pan.___", state 1028, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1030, "(1)"
+ line 284, "pan.___", state 1031, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1031, "else"
+ line 282, "pan.___", state 1036, "((i<2))"
+ line 282, "pan.___", state 1036, "((i>=2))"
+ line 249, "pan.___", state 1044, "(1)"
+ line 253, "pan.___", state 1052, "(1)"
+ line 253, "pan.___", state 1053, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1053, "else"
+ line 251, "pan.___", state 1058, "((i<1))"
+ line 251, "pan.___", state 1058, "((i>=1))"
+ line 257, "pan.___", state 1064, "(1)"
+ line 257, "pan.___", state 1065, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1065, "else"
+ line 261, "pan.___", state 1072, "(1)"
+ line 261, "pan.___", state 1073, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1073, "else"
+ line 266, "pan.___", state 1082, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1082, "else"
+ line 299, "pan.___", state 1084, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1084, "else"
+ line 276, "pan.___", state 1097, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1110, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1119, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1135, "(1)"
+ line 253, "pan.___", state 1143, "(1)"
+ line 257, "pan.___", state 1155, "(1)"
+ line 261, "pan.___", state 1163, "(1)"
+ line 272, "pan.___", state 1179, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1181, "(1)"
+ line 276, "pan.___", state 1188, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1190, "(1)"
+ line 276, "pan.___", state 1191, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1191, "else"
+ line 274, "pan.___", state 1196, "((i<1))"
+ line 274, "pan.___", state 1196, "((i>=1))"
+ line 280, "pan.___", state 1201, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1203, "(1)"
+ line 280, "pan.___", state 1204, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1204, "else"
+ line 284, "pan.___", state 1210, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1212, "(1)"
+ line 284, "pan.___", state 1213, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1213, "else"
+ line 282, "pan.___", state 1218, "((i<2))"
+ line 282, "pan.___", state 1218, "((i>=2))"
+ line 249, "pan.___", state 1226, "(1)"
+ line 253, "pan.___", state 1234, "(1)"
+ line 253, "pan.___", state 1235, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1235, "else"
+ line 251, "pan.___", state 1240, "((i<1))"
+ line 251, "pan.___", state 1240, "((i>=1))"
+ line 257, "pan.___", state 1246, "(1)"
+ line 257, "pan.___", state 1247, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1247, "else"
+ line 261, "pan.___", state 1254, "(1)"
+ line 261, "pan.___", state 1255, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1255, "else"
+ line 266, "pan.___", state 1264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1264, "else"
+ line 299, "pan.___", state 1266, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1266, "else"
+ line 1237, "pan.___", state 1269, "-end-"
+ (227 of 1269 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 3.93e+03 seconds
+pan: rate 1735.2351 states/second
+pan: avg transition delay 1.2255e-06 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define NO_MB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_RMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+pan: claim violated! (at depth 2092)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5332, errors: 1
+ 615700 states, stored
+3.8337558e+08 states, matched
+3.8399128e+08 transitions (= stored+matched)
+2.147943e+09 atomic steps
+hash conflicts: 90741041 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 68.113 equivalent memory usage for states (stored*(State-vector + overhead))
+ 52.415 actual memory usage for states (compression: 76.95%)
+ state-vector as stored = 61 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 518.108 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 82, "(1)"
+ line 438, "pan.___", state 112, "(1)"
+ line 442, "pan.___", state 125, "(1)"
+ line 597, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 218, "(1)"
+ line 438, "pan.___", state 248, "(1)"
+ line 442, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 347, "(1)"
+ line 438, "pan.___", state 377, "(1)"
+ line 442, "pan.___", state 390, "(1)"
+ line 411, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 415, "(1)"
+ line 411, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 416, "else"
+ line 411, "pan.___", state 419, "(1)"
+ line 415, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 429, "(1)"
+ line 415, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 430, "else"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 413, "pan.___", state 439, "((i<1))"
+ line 413, "pan.___", state 439, "((i>=1))"
+ line 420, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 447, "(1)"
+ line 420, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 448, "else"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 424, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 461, "(1)"
+ line 424, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 462, "else"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 422, "pan.___", state 471, "((i<2))"
+ line 422, "pan.___", state 471, "((i>=2))"
+ line 429, "pan.___", state 478, "(1)"
+ line 429, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 479, "else"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 433, "pan.___", state 491, "(1)"
+ line 433, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 492, "else"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 431, "pan.___", state 501, "((i<1))"
+ line 431, "pan.___", state 501, "((i>=1))"
+ line 438, "pan.___", state 508, "(1)"
+ line 438, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 509, "else"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 442, "pan.___", state 521, "(1)"
+ line 442, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 522, "else"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 440, "pan.___", state 531, "((i<2))"
+ line 440, "pan.___", state 531, "((i>=2))"
+ line 450, "pan.___", state 535, "(1)"
+ line 450, "pan.___", state 535, "(1)"
+ line 597, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 540, "(1)"
+ line 272, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 555, "(1)"
+ line 280, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 591, "(1)"
+ line 253, "pan.___", state 599, "(1)"
+ line 257, "pan.___", state 611, "(1)"
+ line 261, "pan.___", state 619, "(1)"
+ line 411, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 702, "(1)"
+ line 433, "pan.___", state 715, "(1)"
+ line 438, "pan.___", state 732, "(1)"
+ line 442, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 838, "(1)"
+ line 438, "pan.___", state 868, "(1)"
+ line 442, "pan.___", state 881, "(1)"
+ line 411, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 904, "(1)"
+ line 411, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 905, "else"
+ line 411, "pan.___", state 908, "(1)"
+ line 415, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 918, "(1)"
+ line 415, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 919, "else"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 413, "pan.___", state 928, "((i<1))"
+ line 413, "pan.___", state 928, "((i>=1))"
+ line 420, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 936, "(1)"
+ line 420, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 937, "else"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 424, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 950, "(1)"
+ line 424, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 951, "else"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 422, "pan.___", state 960, "((i<2))"
+ line 422, "pan.___", state 960, "((i>=2))"
+ line 429, "pan.___", state 967, "(1)"
+ line 429, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 968, "else"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 433, "pan.___", state 980, "(1)"
+ line 433, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 981, "else"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 431, "pan.___", state 990, "((i<1))"
+ line 431, "pan.___", state 990, "((i>=1))"
+ line 438, "pan.___", state 997, "(1)"
+ line 438, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 998, "else"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 442, "pan.___", state 1010, "(1)"
+ line 442, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1011, "else"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 440, "pan.___", state 1020, "((i<2))"
+ line 440, "pan.___", state 1020, "((i>=2))"
+ line 450, "pan.___", state 1024, "(1)"
+ line 450, "pan.___", state 1024, "(1)"
+ line 605, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1098, "(1)"
+ line 433, "pan.___", state 1111, "(1)"
+ line 438, "pan.___", state 1128, "(1)"
+ line 442, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1230, "(1)"
+ line 438, "pan.___", state 1260, "(1)"
+ line 442, "pan.___", state 1273, "(1)"
+ line 411, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1363, "(1)"
+ line 438, "pan.___", state 1393, "(1)"
+ line 442, "pan.___", state 1406, "(1)"
+ line 411, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1492, "(1)"
+ line 438, "pan.___", state 1522, "(1)"
+ line 442, "pan.___", state 1535, "(1)"
+ line 272, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1605, "(1)"
+ line 253, "pan.___", state 1613, "(1)"
+ line 257, "pan.___", state 1625, "(1)"
+ line 261, "pan.___", state 1633, "(1)"
+ line 411, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1716, "(1)"
+ line 433, "pan.___", state 1729, "(1)"
+ line 438, "pan.___", state 1746, "(1)"
+ line 442, "pan.___", state 1759, "(1)"
+ line 411, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1845, "(1)"
+ line 433, "pan.___", state 1858, "(1)"
+ line 438, "pan.___", state 1875, "(1)"
+ line 442, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1977, "(1)"
+ line 438, "pan.___", state 2007, "(1)"
+ line 442, "pan.___", state 2020, "(1)"
+ line 644, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2113, "(1)"
+ line 438, "pan.___", state 2143, "(1)"
+ line 442, "pan.___", state 2156, "(1)"
+ line 411, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2242, "(1)"
+ line 438, "pan.___", state 2272, "(1)"
+ line 442, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2310, "(1)"
+ line 411, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2311, "else"
+ line 411, "pan.___", state 2314, "(1)"
+ line 415, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2324, "(1)"
+ line 415, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2325, "else"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 413, "pan.___", state 2334, "((i<1))"
+ line 413, "pan.___", state 2334, "((i>=1))"
+ line 420, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2342, "(1)"
+ line 420, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2343, "else"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 424, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2356, "(1)"
+ line 424, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2357, "else"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 422, "pan.___", state 2366, "((i<2))"
+ line 422, "pan.___", state 2366, "((i>=2))"
+ line 429, "pan.___", state 2373, "(1)"
+ line 429, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2374, "else"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 433, "pan.___", state 2386, "(1)"
+ line 433, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2387, "else"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 431, "pan.___", state 2396, "((i<1))"
+ line 431, "pan.___", state 2396, "((i>=1))"
+ line 438, "pan.___", state 2403, "(1)"
+ line 438, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2404, "else"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 442, "pan.___", state 2416, "(1)"
+ line 442, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2417, "else"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 440, "pan.___", state 2426, "((i<2))"
+ line 440, "pan.___", state 2426, "((i>=2))"
+ line 450, "pan.___", state 2430, "(1)"
+ line 450, "pan.___", state 2430, "(1)"
+ line 644, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2435, "(1)"
+ line 272, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2486, "(1)"
+ line 253, "pan.___", state 2494, "(1)"
+ line 257, "pan.___", state 2506, "(1)"
+ line 261, "pan.___", state 2514, "(1)"
+ line 411, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2597, "(1)"
+ line 433, "pan.___", state 2610, "(1)"
+ line 438, "pan.___", state 2627, "(1)"
+ line 442, "pan.___", state 2640, "(1)"
+ line 272, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2711, "(1)"
+ line 253, "pan.___", state 2719, "(1)"
+ line 257, "pan.___", state 2731, "(1)"
+ line 261, "pan.___", state 2739, "(1)"
+ line 411, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2822, "(1)"
+ line 433, "pan.___", state 2835, "(1)"
+ line 438, "pan.___", state 2852, "(1)"
+ line 442, "pan.___", state 2865, "(1)"
+ line 411, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2951, "(1)"
+ line 433, "pan.___", state 2964, "(1)"
+ line 438, "pan.___", state 2981, "(1)"
+ line 442, "pan.___", state 2994, "(1)"
+ line 411, "pan.___", state 3027, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 3059, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 3073, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 3092, "(1)"
+ line 438, "pan.___", state 3122, "(1)"
+ line 442, "pan.___", state 3135, "(1)"
+ line 411, "pan.___", state 3154, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 3168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 3186, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 3200, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 3219, "(1)"
+ line 433, "pan.___", state 3232, "(1)"
+ line 438, "pan.___", state 3249, "(1)"
+ line 442, "pan.___", state 3262, "(1)"
+ line 898, "pan.___", state 3283, "-end-"
+ (290 of 3283 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 24, "(1)"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 38, "(1)"
+ line 415, "pan.___", state 39, "(1)"
+ line 415, "pan.___", state 39, "(1)"
+ line 413, "pan.___", state 44, "((i<1))"
+ line 413, "pan.___", state 44, "((i>=1))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 56, "(1)"
+ line 420, "pan.___", state 57, "(1)"
+ line 420, "pan.___", state 57, "(1)"
+ line 424, "pan.___", state 70, "(1)"
+ line 424, "pan.___", state 71, "(1)"
+ line 424, "pan.___", state 71, "(1)"
+ line 422, "pan.___", state 76, "((i<2))"
+ line 422, "pan.___", state 76, "((i>=2))"
+ line 429, "pan.___", state 83, "(1)"
+ line 429, "pan.___", state 84, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 84, "else"
+ line 429, "pan.___", state 87, "(1)"
+ line 429, "pan.___", state 88, "(1)"
+ line 429, "pan.___", state 88, "(1)"
+ line 433, "pan.___", state 96, "(1)"
+ line 433, "pan.___", state 97, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 97, "else"
+ line 433, "pan.___", state 100, "(1)"
+ line 433, "pan.___", state 101, "(1)"
+ line 433, "pan.___", state 101, "(1)"
+ line 431, "pan.___", state 106, "((i<1))"
+ line 431, "pan.___", state 106, "((i>=1))"
+ line 438, "pan.___", state 113, "(1)"
+ line 438, "pan.___", state 114, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 114, "else"
+ line 438, "pan.___", state 117, "(1)"
+ line 438, "pan.___", state 118, "(1)"
+ line 438, "pan.___", state 118, "(1)"
+ line 442, "pan.___", state 126, "(1)"
+ line 442, "pan.___", state 127, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 127, "else"
+ line 442, "pan.___", state 130, "(1)"
+ line 442, "pan.___", state 131, "(1)"
+ line 442, "pan.___", state 131, "(1)"
+ line 440, "pan.___", state 136, "((i<2))"
+ line 440, "pan.___", state 136, "((i>=2))"
+ line 450, "pan.___", state 140, "(1)"
+ line 450, "pan.___", state 140, "(1)"
+ line 272, "pan.___", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 276, "(1)"
+ line 433, "pan.___", state 289, "(1)"
+ line 438, "pan.___", state 306, "(1)"
+ line 442, "pan.___", state 319, "(1)"
+ line 415, "pan.___", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 420, "(1)"
+ line 438, "pan.___", state 437, "(1)"
+ line 442, "pan.___", state 450, "(1)"
+ line 415, "pan.___", state 495, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 513, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 559, "(1)"
+ line 438, "pan.___", state 576, "(1)"
+ line 442, "pan.___", state 589, "(1)"
+ line 415, "pan.___", state 624, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 642, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 656, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 688, "(1)"
+ line 438, "pan.___", state 705, "(1)"
+ line 442, "pan.___", state 718, "(1)"
+ line 415, "pan.___", state 755, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 773, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 787, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 819, "(1)"
+ line 438, "pan.___", state 836, "(1)"
+ line 442, "pan.___", state 849, "(1)"
+ line 272, "pan.___", state 904, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 913, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 928, "(1)"
+ line 284, "pan.___", state 935, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 951, "(1)"
+ line 253, "pan.___", state 959, "(1)"
+ line 257, "pan.___", state 971, "(1)"
+ line 261, "pan.___", state 979, "(1)"
+ line 276, "pan.___", state 1004, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1017, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1026, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1042, "(1)"
+ line 253, "pan.___", state 1050, "(1)"
+ line 257, "pan.___", state 1062, "(1)"
+ line 261, "pan.___", state 1070, "(1)"
+ line 276, "pan.___", state 1095, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1108, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1117, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1133, "(1)"
+ line 253, "pan.___", state 1141, "(1)"
+ line 257, "pan.___", state 1153, "(1)"
+ line 261, "pan.___", state 1161, "(1)"
+ line 276, "pan.___", state 1186, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1199, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1208, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1224, "(1)"
+ line 253, "pan.___", state 1232, "(1)"
+ line 257, "pan.___", state 1244, "(1)"
+ line 261, "pan.___", state 1252, "(1)"
+ line 1237, "pan.___", state 1267, "-end-"
+ (96 of 1267 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 474 seconds
+pan: rate 1298.3425 states/second
+pan: avg transition delay 1.235e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define NO_RMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_WMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 5131 States= 1e+06 Transitions= 5.44e+08 Memory= 550.432 t= 664 R= 2e+03
+Depth= 5131 States= 2e+06 Transitions= 1.26e+09 Memory= 634.318 t= 1.56e+03 R= 1e+03
+Depth= 5422 States= 3e+06 Transitions= 1.93e+09 Memory= 718.303 t= 2.43e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 5422 States= 4e+06 Transitions= 2.58e+09 Memory= 833.311 t= 3.23e+03 R= 1e+03
+Depth= 5422 States= 5e+06 Transitions= 3.25e+09 Memory= 917.295 t= 4.07e+03 R= 1e+03
+pan: claim violated! (at depth 1420)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5422, errors: 1
+ 5523708 states, stored
+3.5450503e+09 states, matched
+3.550574e+09 transitions (= stored+matched)
+2.0146324e+10 atomic steps
+hash conflicts: 2.4095106e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 611.067 equivalent memory usage for states (stored*(State-vector + overhead))
+ 471.813 actual memory usage for states (compression: 77.21%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 961.240 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 82, "(1)"
+ line 438, "pan.___", state 112, "(1)"
+ line 442, "pan.___", state 125, "(1)"
+ line 597, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 218, "(1)"
+ line 438, "pan.___", state 248, "(1)"
+ line 442, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 347, "(1)"
+ line 438, "pan.___", state 377, "(1)"
+ line 442, "pan.___", state 390, "(1)"
+ line 411, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 415, "(1)"
+ line 411, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 416, "else"
+ line 411, "pan.___", state 419, "(1)"
+ line 415, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 429, "(1)"
+ line 415, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 430, "else"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 413, "pan.___", state 439, "((i<1))"
+ line 413, "pan.___", state 439, "((i>=1))"
+ line 420, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 447, "(1)"
+ line 420, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 448, "else"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 424, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 461, "(1)"
+ line 424, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 462, "else"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 422, "pan.___", state 471, "((i<2))"
+ line 422, "pan.___", state 471, "((i>=2))"
+ line 429, "pan.___", state 478, "(1)"
+ line 429, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 479, "else"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 433, "pan.___", state 491, "(1)"
+ line 433, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 492, "else"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 431, "pan.___", state 501, "((i<1))"
+ line 431, "pan.___", state 501, "((i>=1))"
+ line 438, "pan.___", state 508, "(1)"
+ line 438, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 509, "else"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 442, "pan.___", state 521, "(1)"
+ line 442, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 522, "else"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 440, "pan.___", state 531, "((i<2))"
+ line 440, "pan.___", state 531, "((i>=2))"
+ line 450, "pan.___", state 535, "(1)"
+ line 450, "pan.___", state 535, "(1)"
+ line 597, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 540, "(1)"
+ line 272, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 555, "(1)"
+ line 280, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 591, "(1)"
+ line 253, "pan.___", state 599, "(1)"
+ line 257, "pan.___", state 611, "(1)"
+ line 261, "pan.___", state 619, "(1)"
+ line 411, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 702, "(1)"
+ line 433, "pan.___", state 715, "(1)"
+ line 438, "pan.___", state 732, "(1)"
+ line 442, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 838, "(1)"
+ line 438, "pan.___", state 868, "(1)"
+ line 442, "pan.___", state 881, "(1)"
+ line 411, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 904, "(1)"
+ line 411, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 905, "else"
+ line 411, "pan.___", state 908, "(1)"
+ line 415, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 918, "(1)"
+ line 415, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 919, "else"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 413, "pan.___", state 928, "((i<1))"
+ line 413, "pan.___", state 928, "((i>=1))"
+ line 420, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 936, "(1)"
+ line 420, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 937, "else"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 424, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 950, "(1)"
+ line 424, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 951, "else"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 422, "pan.___", state 960, "((i<2))"
+ line 422, "pan.___", state 960, "((i>=2))"
+ line 429, "pan.___", state 967, "(1)"
+ line 429, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 968, "else"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 433, "pan.___", state 980, "(1)"
+ line 433, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 981, "else"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 431, "pan.___", state 990, "((i<1))"
+ line 431, "pan.___", state 990, "((i>=1))"
+ line 438, "pan.___", state 997, "(1)"
+ line 438, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 998, "else"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 442, "pan.___", state 1010, "(1)"
+ line 442, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1011, "else"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 440, "pan.___", state 1020, "((i<2))"
+ line 440, "pan.___", state 1020, "((i>=2))"
+ line 450, "pan.___", state 1024, "(1)"
+ line 450, "pan.___", state 1024, "(1)"
+ line 605, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1098, "(1)"
+ line 433, "pan.___", state 1111, "(1)"
+ line 438, "pan.___", state 1128, "(1)"
+ line 442, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1230, "(1)"
+ line 438, "pan.___", state 1260, "(1)"
+ line 442, "pan.___", state 1273, "(1)"
+ line 411, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1363, "(1)"
+ line 438, "pan.___", state 1393, "(1)"
+ line 442, "pan.___", state 1406, "(1)"
+ line 411, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1492, "(1)"
+ line 438, "pan.___", state 1522, "(1)"
+ line 442, "pan.___", state 1535, "(1)"
+ line 272, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1605, "(1)"
+ line 253, "pan.___", state 1613, "(1)"
+ line 257, "pan.___", state 1625, "(1)"
+ line 261, "pan.___", state 1633, "(1)"
+ line 411, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1716, "(1)"
+ line 433, "pan.___", state 1729, "(1)"
+ line 438, "pan.___", state 1746, "(1)"
+ line 442, "pan.___", state 1759, "(1)"
+ line 411, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1845, "(1)"
+ line 433, "pan.___", state 1858, "(1)"
+ line 438, "pan.___", state 1875, "(1)"
+ line 442, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1977, "(1)"
+ line 438, "pan.___", state 2007, "(1)"
+ line 442, "pan.___", state 2020, "(1)"
+ line 644, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2113, "(1)"
+ line 438, "pan.___", state 2143, "(1)"
+ line 442, "pan.___", state 2156, "(1)"
+ line 411, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2242, "(1)"
+ line 438, "pan.___", state 2272, "(1)"
+ line 442, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2310, "(1)"
+ line 411, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2311, "else"
+ line 411, "pan.___", state 2314, "(1)"
+ line 415, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2324, "(1)"
+ line 415, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2325, "else"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 413, "pan.___", state 2334, "((i<1))"
+ line 413, "pan.___", state 2334, "((i>=1))"
+ line 420, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2342, "(1)"
+ line 420, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2343, "else"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 424, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2356, "(1)"
+ line 424, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2357, "else"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 422, "pan.___", state 2366, "((i<2))"
+ line 422, "pan.___", state 2366, "((i>=2))"
+ line 429, "pan.___", state 2373, "(1)"
+ line 429, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2374, "else"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 433, "pan.___", state 2386, "(1)"
+ line 433, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2387, "else"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 431, "pan.___", state 2396, "((i<1))"
+ line 431, "pan.___", state 2396, "((i>=1))"
+ line 438, "pan.___", state 2403, "(1)"
+ line 438, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2404, "else"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 442, "pan.___", state 2416, "(1)"
+ line 442, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2417, "else"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 440, "pan.___", state 2426, "((i<2))"
+ line 440, "pan.___", state 2426, "((i>=2))"
+ line 450, "pan.___", state 2430, "(1)"
+ line 450, "pan.___", state 2430, "(1)"
+ line 644, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2435, "(1)"
+ line 272, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2486, "(1)"
+ line 253, "pan.___", state 2494, "(1)"
+ line 257, "pan.___", state 2506, "(1)"
+ line 261, "pan.___", state 2514, "(1)"
+ line 411, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2597, "(1)"
+ line 433, "pan.___", state 2610, "(1)"
+ line 438, "pan.___", state 2627, "(1)"
+ line 442, "pan.___", state 2640, "(1)"
+ line 272, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2711, "(1)"
+ line 253, "pan.___", state 2719, "(1)"
+ line 257, "pan.___", state 2731, "(1)"
+ line 261, "pan.___", state 2739, "(1)"
+ line 411, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2822, "(1)"
+ line 433, "pan.___", state 2835, "(1)"
+ line 438, "pan.___", state 2852, "(1)"
+ line 442, "pan.___", state 2865, "(1)"
+ line 411, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2951, "(1)"
+ line 433, "pan.___", state 2964, "(1)"
+ line 438, "pan.___", state 2981, "(1)"
+ line 442, "pan.___", state 2994, "(1)"
+ line 249, "pan.___", state 3027, "(1)"
+ line 257, "pan.___", state 3047, "(1)"
+ line 261, "pan.___", state 3055, "(1)"
+ line 249, "pan.___", state 3070, "(1)"
+ line 253, "pan.___", state 3078, "(1)"
+ line 257, "pan.___", state 3090, "(1)"
+ line 261, "pan.___", state 3098, "(1)"
+ line 898, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 19, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 33, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 84, "(1)"
+ line 433, "pan.___", state 97, "(1)"
+ line 272, "pan.___", state 150, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 152, "(1)"
+ line 276, "pan.___", state 159, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 161, "(1)"
+ line 276, "pan.___", state 162, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 162, "else"
+ line 274, "pan.___", state 167, "((i<1))"
+ line 274, "pan.___", state 167, "((i>=1))"
+ line 280, "pan.___", state 172, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 174, "(1)"
+ line 280, "pan.___", state 175, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 175, "else"
+ line 284, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 183, "(1)"
+ line 284, "pan.___", state 184, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 184, "else"
+ line 289, "pan.___", state 193, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 289, "pan.___", state 193, "else"
+ line 411, "pan.___", state 212, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 226, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 244, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 258, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 277, "(1)"
+ line 433, "pan.___", state 290, "(1)"
+ line 438, "pan.___", state 307, "(1)"
+ line 442, "pan.___", state 320, "(1)"
+ line 415, "pan.___", state 357, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 375, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 389, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 421, "(1)"
+ line 438, "pan.___", state 438, "(1)"
+ line 442, "pan.___", state 451, "(1)"
+ line 415, "pan.___", state 496, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 514, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 528, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 560, "(1)"
+ line 438, "pan.___", state 577, "(1)"
+ line 442, "pan.___", state 590, "(1)"
+ line 415, "pan.___", state 625, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 643, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 657, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 689, "(1)"
+ line 438, "pan.___", state 706, "(1)"
+ line 442, "pan.___", state 719, "(1)"
+ line 415, "pan.___", state 756, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 774, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 788, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 820, "(1)"
+ line 438, "pan.___", state 837, "(1)"
+ line 442, "pan.___", state 850, "(1)"
+ line 272, "pan.___", state 905, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 914, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 952, "(1)"
+ line 253, "pan.___", state 960, "(1)"
+ line 257, "pan.___", state 972, "(1)"
+ line 261, "pan.___", state 980, "(1)"
+ line 276, "pan.___", state 1005, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1018, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1027, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1043, "(1)"
+ line 253, "pan.___", state 1051, "(1)"
+ line 257, "pan.___", state 1063, "(1)"
+ line 261, "pan.___", state 1071, "(1)"
+ line 276, "pan.___", state 1096, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1109, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1118, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1134, "(1)"
+ line 253, "pan.___", state 1142, "(1)"
+ line 257, "pan.___", state 1154, "(1)"
+ line 261, "pan.___", state 1162, "(1)"
+ line 276, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1200, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1209, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1225, "(1)"
+ line 253, "pan.___", state 1233, "(1)"
+ line 257, "pan.___", state 1245, "(1)"
+ line 261, "pan.___", state 1253, "(1)"
+ line 1237, "pan.___", state 1268, "-end-"
+ (77 of 1268 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 4.43e+03 seconds
+pan: rate 1246.6728 states/second
+pan: avg transition delay 1.2479e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define NO_WMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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+1276:2:3459
+1277:2:3467
+1278:2:3468
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+1282:2:3486
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+1284:2:3491
+1285:2:3499
+1286:2:3500
+1287:2:3504
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+1292:2:3505
+1293:2:3513
+1294:2:3518
+1295:2:3519
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+1298:2:3532
+1299:2:3543
+1300:2:3548
+1301:2:3549
+1302:2:3560
+1303:2:3561
+1304:2:3562
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+1306:2:3561
+1307:2:3562
+1308:2:3573
+1309:2:3582
+1310:0:4463
+1311:2:3128
+1312:0:4463
+1313:2:3588
+1314:0:4463
+1315:2:4111
+1316:2:4112
+1317:2:4116
+1318:2:4120
+1319:2:4121
+1320:2:4125
+1321:2:4133
+1322:2:4134
+1323:2:4138
+1324:2:4142
+1325:2:4143
+1326:2:4138
+1327:2:4142
+1328:2:4143
+1329:2:4147
+1330:2:4154
+1331:2:4161
+1332:2:4162
+1333:2:4169
+1334:2:4174
+1335:2:4181
+1336:2:4182
+1337:2:4181
+1338:2:4182
+1339:2:4189
+1340:2:4193
+1341:0:4463
+1342:2:3590
+1343:2:3591
+1344:0:4463
+1345:2:3128
+1346:0:4463
+1347:2:3453
+1348:2:3454
+1349:2:3458
+1350:2:3459
+1351:2:3467
+1352:2:3468
+1353:2:3472
+1354:2:3473
+1355:2:3481
+1356:2:3486
+1357:2:3490
+1358:2:3491
+1359:2:3499
+1360:2:3500
+1361:2:3504
+1362:2:3505
+1363:2:3499
+1364:2:3500
+1365:2:3504
+1366:2:3505
+1367:2:3513
+1368:2:3518
+1369:2:3519
+1370:2:3530
+1371:2:3531
+1372:2:3532
+1373:2:3543
+1374:2:3548
+1375:2:3549
+1376:2:3560
+1377:2:3561
+1378:2:3562
+1379:2:3560
+1380:2:3561
+1381:2:3562
+1382:2:3573
+1383:2:3582
+1384:0:4463
+1385:2:3128
+1386:0:4463
+1387:2:3588
+1388:0:4463
+1389:2:4111
+1390:2:4112
+1391:2:4116
+1392:2:4120
+1393:2:4121
+1394:2:4125
+1395:2:4133
+1396:2:4134
+1397:2:4138
+1398:2:4142
+1399:2:4143
+1400:2:4138
+1401:2:4142
+1402:2:4143
+1403:2:4147
+1404:2:4154
+1405:2:4161
+1406:2:4162
+1407:2:4169
+1408:2:4174
+1409:2:4181
+1410:2:4182
+1411:2:4181
+1412:2:4182
+1413:2:4189
+1414:2:4193
+1415:0:4463
+1416:1:1291
+1417:1:1292
+1418:0:4461
+1419:1:11
+1420:0:4467
+1421:1:2299
--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 5164 States= 1e+06 Transitions= 4.75e+08 Memory= 550.432 t= 582 R= 2e+03
+Depth= 5746 States= 2e+06 Transitions= 1.02e+09 Memory= 634.318 t= 1.27e+03 R= 2e+03
+pan: claim violated! (at depth 1144)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5746, errors: 1
+ 2322493 states, stored
+1.1944827e+09 states, matched
+1.1968052e+09 transitions (= stored+matched)
+6.6651798e+09 atomic steps
+hash conflicts: 7.6855101e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 256.929 equivalent memory usage for states (stored*(State-vector + overhead))
+ 195.871 actual memory usage for states (compression: 76.24%)
+ state-vector as stored = 60 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 661.467 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 82, "(1)"
+ line 438, "pan.___", state 112, "(1)"
+ line 442, "pan.___", state 125, "(1)"
+ line 597, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 218, "(1)"
+ line 438, "pan.___", state 248, "(1)"
+ line 442, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 347, "(1)"
+ line 438, "pan.___", state 377, "(1)"
+ line 442, "pan.___", state 390, "(1)"
+ line 411, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 415, "(1)"
+ line 411, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 416, "else"
+ line 411, "pan.___", state 419, "(1)"
+ line 415, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 429, "(1)"
+ line 415, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 430, "else"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 413, "pan.___", state 439, "((i<1))"
+ line 413, "pan.___", state 439, "((i>=1))"
+ line 420, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 447, "(1)"
+ line 420, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 448, "else"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 424, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 461, "(1)"
+ line 424, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 462, "else"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 422, "pan.___", state 471, "((i<2))"
+ line 422, "pan.___", state 471, "((i>=2))"
+ line 429, "pan.___", state 478, "(1)"
+ line 429, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 479, "else"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 433, "pan.___", state 491, "(1)"
+ line 433, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 492, "else"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 431, "pan.___", state 501, "((i<1))"
+ line 431, "pan.___", state 501, "((i>=1))"
+ line 438, "pan.___", state 508, "(1)"
+ line 438, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 509, "else"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 442, "pan.___", state 521, "(1)"
+ line 442, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 522, "else"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 440, "pan.___", state 531, "((i<2))"
+ line 440, "pan.___", state 531, "((i>=2))"
+ line 450, "pan.___", state 535, "(1)"
+ line 450, "pan.___", state 535, "(1)"
+ line 597, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 540, "(1)"
+ line 272, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 555, "(1)"
+ line 280, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 591, "(1)"
+ line 253, "pan.___", state 599, "(1)"
+ line 257, "pan.___", state 611, "(1)"
+ line 261, "pan.___", state 619, "(1)"
+ line 411, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 702, "(1)"
+ line 433, "pan.___", state 715, "(1)"
+ line 438, "pan.___", state 732, "(1)"
+ line 442, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 838, "(1)"
+ line 438, "pan.___", state 868, "(1)"
+ line 442, "pan.___", state 881, "(1)"
+ line 411, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 904, "(1)"
+ line 411, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 905, "else"
+ line 411, "pan.___", state 908, "(1)"
+ line 415, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 918, "(1)"
+ line 415, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 919, "else"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 413, "pan.___", state 928, "((i<1))"
+ line 413, "pan.___", state 928, "((i>=1))"
+ line 420, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 936, "(1)"
+ line 420, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 937, "else"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 424, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 950, "(1)"
+ line 424, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 951, "else"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 422, "pan.___", state 960, "((i<2))"
+ line 422, "pan.___", state 960, "((i>=2))"
+ line 429, "pan.___", state 967, "(1)"
+ line 429, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 968, "else"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 433, "pan.___", state 980, "(1)"
+ line 433, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 981, "else"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 431, "pan.___", state 990, "((i<1))"
+ line 431, "pan.___", state 990, "((i>=1))"
+ line 438, "pan.___", state 997, "(1)"
+ line 438, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 998, "else"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 442, "pan.___", state 1010, "(1)"
+ line 442, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1011, "else"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 440, "pan.___", state 1020, "((i<2))"
+ line 440, "pan.___", state 1020, "((i>=2))"
+ line 450, "pan.___", state 1024, "(1)"
+ line 450, "pan.___", state 1024, "(1)"
+ line 605, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1098, "(1)"
+ line 433, "pan.___", state 1111, "(1)"
+ line 438, "pan.___", state 1128, "(1)"
+ line 442, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1230, "(1)"
+ line 438, "pan.___", state 1260, "(1)"
+ line 442, "pan.___", state 1273, "(1)"
+ line 411, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1363, "(1)"
+ line 438, "pan.___", state 1393, "(1)"
+ line 442, "pan.___", state 1406, "(1)"
+ line 411, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1492, "(1)"
+ line 438, "pan.___", state 1522, "(1)"
+ line 442, "pan.___", state 1535, "(1)"
+ line 272, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1605, "(1)"
+ line 253, "pan.___", state 1613, "(1)"
+ line 257, "pan.___", state 1625, "(1)"
+ line 261, "pan.___", state 1633, "(1)"
+ line 411, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1716, "(1)"
+ line 433, "pan.___", state 1729, "(1)"
+ line 438, "pan.___", state 1746, "(1)"
+ line 442, "pan.___", state 1759, "(1)"
+ line 411, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1845, "(1)"
+ line 433, "pan.___", state 1858, "(1)"
+ line 438, "pan.___", state 1875, "(1)"
+ line 442, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1977, "(1)"
+ line 438, "pan.___", state 2007, "(1)"
+ line 442, "pan.___", state 2020, "(1)"
+ line 644, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2113, "(1)"
+ line 438, "pan.___", state 2143, "(1)"
+ line 442, "pan.___", state 2156, "(1)"
+ line 411, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2242, "(1)"
+ line 438, "pan.___", state 2272, "(1)"
+ line 442, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2310, "(1)"
+ line 411, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2311, "else"
+ line 411, "pan.___", state 2314, "(1)"
+ line 415, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2324, "(1)"
+ line 415, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2325, "else"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 413, "pan.___", state 2334, "((i<1))"
+ line 413, "pan.___", state 2334, "((i>=1))"
+ line 420, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2342, "(1)"
+ line 420, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2343, "else"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 424, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2356, "(1)"
+ line 424, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2357, "else"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 422, "pan.___", state 2366, "((i<2))"
+ line 422, "pan.___", state 2366, "((i>=2))"
+ line 429, "pan.___", state 2373, "(1)"
+ line 429, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2374, "else"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 433, "pan.___", state 2386, "(1)"
+ line 433, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2387, "else"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 431, "pan.___", state 2396, "((i<1))"
+ line 431, "pan.___", state 2396, "((i>=1))"
+ line 438, "pan.___", state 2403, "(1)"
+ line 438, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2404, "else"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 442, "pan.___", state 2416, "(1)"
+ line 442, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2417, "else"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 440, "pan.___", state 2426, "((i<2))"
+ line 440, "pan.___", state 2426, "((i>=2))"
+ line 450, "pan.___", state 2430, "(1)"
+ line 450, "pan.___", state 2430, "(1)"
+ line 644, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2435, "(1)"
+ line 272, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2486, "(1)"
+ line 253, "pan.___", state 2494, "(1)"
+ line 257, "pan.___", state 2506, "(1)"
+ line 261, "pan.___", state 2514, "(1)"
+ line 411, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2597, "(1)"
+ line 433, "pan.___", state 2610, "(1)"
+ line 438, "pan.___", state 2627, "(1)"
+ line 442, "pan.___", state 2640, "(1)"
+ line 272, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2711, "(1)"
+ line 253, "pan.___", state 2719, "(1)"
+ line 257, "pan.___", state 2731, "(1)"
+ line 261, "pan.___", state 2739, "(1)"
+ line 411, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2822, "(1)"
+ line 433, "pan.___", state 2835, "(1)"
+ line 438, "pan.___", state 2852, "(1)"
+ line 442, "pan.___", state 2865, "(1)"
+ line 411, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2951, "(1)"
+ line 433, "pan.___", state 2964, "(1)"
+ line 438, "pan.___", state 2981, "(1)"
+ line 442, "pan.___", state 2994, "(1)"
+ line 249, "pan.___", state 3027, "(1)"
+ line 257, "pan.___", state 3047, "(1)"
+ line 261, "pan.___", state 3055, "(1)"
+ line 249, "pan.___", state 3070, "(1)"
+ line 253, "pan.___", state 3078, "(1)"
+ line 257, "pan.___", state 3090, "(1)"
+ line 261, "pan.___", state 3098, "(1)"
+ line 898, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 22, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 36, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 54, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 87, "(1)"
+ line 433, "pan.___", state 100, "(1)"
+ line 438, "pan.___", state 117, "(1)"
+ line 272, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 162, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 175, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 215, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 229, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 247, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 261, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 280, "(1)"
+ line 433, "pan.___", state 293, "(1)"
+ line 438, "pan.___", state 310, "(1)"
+ line 442, "pan.___", state 323, "(1)"
+ line 415, "pan.___", state 360, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 378, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 392, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 424, "(1)"
+ line 438, "pan.___", state 441, "(1)"
+ line 442, "pan.___", state 454, "(1)"
+ line 411, "pan.___", state 484, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 498, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 516, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 530, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 549, "(1)"
+ line 433, "pan.___", state 562, "(1)"
+ line 438, "pan.___", state 579, "(1)"
+ line 442, "pan.___", state 592, "(1)"
+ line 411, "pan.___", state 613, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 615, "(1)"
+ line 411, "pan.___", state 616, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 616, "else"
+ line 411, "pan.___", state 619, "(1)"
+ line 415, "pan.___", state 627, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 629, "(1)"
+ line 415, "pan.___", state 630, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 630, "else"
+ line 415, "pan.___", state 633, "(1)"
+ line 415, "pan.___", state 634, "(1)"
+ line 415, "pan.___", state 634, "(1)"
+ line 413, "pan.___", state 639, "((i<1))"
+ line 413, "pan.___", state 639, "((i>=1))"
+ line 420, "pan.___", state 645, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 647, "(1)"
+ line 420, "pan.___", state 648, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 648, "else"
+ line 420, "pan.___", state 651, "(1)"
+ line 420, "pan.___", state 652, "(1)"
+ line 420, "pan.___", state 652, "(1)"
+ line 424, "pan.___", state 659, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 661, "(1)"
+ line 424, "pan.___", state 662, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 662, "else"
+ line 424, "pan.___", state 665, "(1)"
+ line 424, "pan.___", state 666, "(1)"
+ line 424, "pan.___", state 666, "(1)"
+ line 422, "pan.___", state 671, "((i<2))"
+ line 422, "pan.___", state 671, "((i>=2))"
+ line 429, "pan.___", state 678, "(1)"
+ line 429, "pan.___", state 679, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 679, "else"
+ line 429, "pan.___", state 682, "(1)"
+ line 429, "pan.___", state 683, "(1)"
+ line 429, "pan.___", state 683, "(1)"
+ line 433, "pan.___", state 691, "(1)"
+ line 433, "pan.___", state 692, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 692, "else"
+ line 433, "pan.___", state 695, "(1)"
+ line 433, "pan.___", state 696, "(1)"
+ line 433, "pan.___", state 696, "(1)"
+ line 431, "pan.___", state 701, "((i<1))"
+ line 431, "pan.___", state 701, "((i>=1))"
+ line 438, "pan.___", state 708, "(1)"
+ line 438, "pan.___", state 709, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 709, "else"
+ line 438, "pan.___", state 712, "(1)"
+ line 438, "pan.___", state 713, "(1)"
+ line 438, "pan.___", state 713, "(1)"
+ line 442, "pan.___", state 721, "(1)"
+ line 442, "pan.___", state 722, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 722, "else"
+ line 442, "pan.___", state 725, "(1)"
+ line 442, "pan.___", state 726, "(1)"
+ line 442, "pan.___", state 726, "(1)"
+ line 440, "pan.___", state 731, "((i<2))"
+ line 440, "pan.___", state 731, "((i>=2))"
+ line 450, "pan.___", state 735, "(1)"
+ line 450, "pan.___", state 735, "(1)"
+ line 1117, "pan.___", state 739, "_proc_urcu_writer = (_proc_urcu_writer|(1<<10))"
+ line 411, "pan.___", state 744, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 746, "(1)"
+ line 411, "pan.___", state 747, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 747, "else"
+ line 411, "pan.___", state 750, "(1)"
+ line 415, "pan.___", state 758, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 760, "(1)"
+ line 415, "pan.___", state 761, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 761, "else"
+ line 415, "pan.___", state 764, "(1)"
+ line 415, "pan.___", state 765, "(1)"
+ line 415, "pan.___", state 765, "(1)"
+ line 413, "pan.___", state 770, "((i<1))"
+ line 413, "pan.___", state 770, "((i>=1))"
+ line 420, "pan.___", state 776, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 778, "(1)"
+ line 420, "pan.___", state 779, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 779, "else"
+ line 420, "pan.___", state 782, "(1)"
+ line 420, "pan.___", state 783, "(1)"
+ line 420, "pan.___", state 783, "(1)"
+ line 424, "pan.___", state 790, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 792, "(1)"
+ line 424, "pan.___", state 793, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 793, "else"
+ line 424, "pan.___", state 796, "(1)"
+ line 424, "pan.___", state 797, "(1)"
+ line 424, "pan.___", state 797, "(1)"
+ line 422, "pan.___", state 802, "((i<2))"
+ line 422, "pan.___", state 802, "((i>=2))"
+ line 429, "pan.___", state 809, "(1)"
+ line 429, "pan.___", state 810, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 810, "else"
+ line 429, "pan.___", state 813, "(1)"
+ line 429, "pan.___", state 814, "(1)"
+ line 429, "pan.___", state 814, "(1)"
+ line 433, "pan.___", state 822, "(1)"
+ line 433, "pan.___", state 823, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 823, "else"
+ line 433, "pan.___", state 826, "(1)"
+ line 433, "pan.___", state 827, "(1)"
+ line 433, "pan.___", state 827, "(1)"
+ line 431, "pan.___", state 832, "((i<1))"
+ line 431, "pan.___", state 832, "((i>=1))"
+ line 438, "pan.___", state 839, "(1)"
+ line 438, "pan.___", state 840, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 840, "else"
+ line 438, "pan.___", state 843, "(1)"
+ line 438, "pan.___", state 844, "(1)"
+ line 438, "pan.___", state 844, "(1)"
+ line 442, "pan.___", state 852, "(1)"
+ line 442, "pan.___", state 853, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 853, "else"
+ line 442, "pan.___", state 856, "(1)"
+ line 442, "pan.___", state 857, "(1)"
+ line 442, "pan.___", state 857, "(1)"
+ line 440, "pan.___", state 862, "((i<2))"
+ line 440, "pan.___", state 862, "((i>=2))"
+ line 450, "pan.___", state 866, "(1)"
+ line 450, "pan.___", state 866, "(1)"
+ line 1133, "pan.___", state 871, "_proc_urcu_writer = (_proc_urcu_writer|(1<<11))"
+ line 1128, "pan.___", state 872, "(((tmp2&((1<<7)-1))&&((tmp2^0)&(1<<7))))"
+ line 1128, "pan.___", state 872, "else"
+ line 1153, "pan.___", state 876, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<12)|(1<<11))))"
+ line 272, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 931, "(1)"
+ line 284, "pan.___", state 938, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 954, "(1)"
+ line 253, "pan.___", state 962, "(1)"
+ line 257, "pan.___", state 974, "(1)"
+ line 261, "pan.___", state 982, "(1)"
+ line 276, "pan.___", state 1007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1020, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1029, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1045, "(1)"
+ line 253, "pan.___", state 1053, "(1)"
+ line 257, "pan.___", state 1065, "(1)"
+ line 261, "pan.___", state 1073, "(1)"
+ line 272, "pan.___", state 1089, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1091, "(1)"
+ line 276, "pan.___", state 1098, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1100, "(1)"
+ line 276, "pan.___", state 1101, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1101, "else"
+ line 274, "pan.___", state 1106, "((i<1))"
+ line 274, "pan.___", state 1106, "((i>=1))"
+ line 280, "pan.___", state 1111, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1113, "(1)"
+ line 280, "pan.___", state 1114, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1114, "else"
+ line 284, "pan.___", state 1120, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1122, "(1)"
+ line 284, "pan.___", state 1123, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1123, "else"
+ line 282, "pan.___", state 1128, "((i<2))"
+ line 282, "pan.___", state 1128, "((i>=2))"
+ line 249, "pan.___", state 1136, "(1)"
+ line 253, "pan.___", state 1144, "(1)"
+ line 253, "pan.___", state 1145, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1145, "else"
+ line 251, "pan.___", state 1150, "((i<1))"
+ line 251, "pan.___", state 1150, "((i>=1))"
+ line 257, "pan.___", state 1156, "(1)"
+ line 257, "pan.___", state 1157, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1157, "else"
+ line 261, "pan.___", state 1164, "(1)"
+ line 261, "pan.___", state 1165, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1165, "else"
+ line 266, "pan.___", state 1174, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1174, "else"
+ line 299, "pan.___", state 1176, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1176, "else"
+ line 276, "pan.___", state 1189, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1202, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1227, "(1)"
+ line 253, "pan.___", state 1235, "(1)"
+ line 257, "pan.___", state 1247, "(1)"
+ line 261, "pan.___", state 1255, "(1)"
+ line 1237, "pan.___", state 1270, "-end-"
+ (161 of 1270 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 1.49e+03 seconds
+pan: rate 1556.4638 states/second
+pan: avg transition delay 1.2468e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define SINGLE_FLIP
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+depth 23: Claim reached state 9 (line 1300)
+depth 1143: Claim reached state 9 (line 1299)
+Depth= 6515 States= 1e+06 Transitions= 5.44e+08 Memory= 507.561 t= 715 R= 1e+03
+Depth= 6515 States= 2e+06 Transitions= 1.44e+09 Memory= 545.940 t= 1.93e+03 R= 1e+03
+Depth= 6515 States= 3e+06 Transitions= 2.29e+09 Memory= 584.416 t= 3.08e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 6515 States= 4e+06 Transitions= 3.07e+09 Memory= 646.299 t= 4.13e+03 R= 1e+03
+Depth= 6515 States= 5e+06 Transitions= 3.84e+09 Memory= 681.065 t= 5.17e+03 R= 1e+03
+Depth= 6515 States= 6e+06 Transitions= 4.91e+09 Memory= 728.916 t= 6.63e+03 R= 9e+02
+Depth= 6515 States= 7e+06 Transitions= 5.88e+09 Memory= 767.393 t= 7.96e+03 R= 9e+02
+Depth= 6515 States= 8e+06 Transitions= 6.76e+09 Memory= 808.018 t= 9.16e+03 R= 9e+02
+Depth= 6515 States= 9e+06 Transitions= 7.69e+09 Memory= 846.885 t= 1.04e+04 R= 9e+02
+pan: resizing hashtable to -w24.. done
+Depth= 6515 States= 1e+07 Transitions= 8.63e+09 Memory= 1015.705 t= 1.17e+04 R= 9e+02
+Depth= 6515 States= 1.1e+07 Transitions= 9.44e+09 Memory= 1054.572 t= 1.28e+04 R= 9e+02
+Depth= 6515 States= 1.2e+07 Transitions= 1.02e+10 Memory= 1095.490 t= 1.39e+04 R= 9e+02
+Depth= 6515 States= 1.3e+07 Transitions= 1.11e+10 Memory= 1129.182 t= 1.51e+04 R= 9e+02
+Depth= 6515 States= 1.4e+07 Transitions= 1.22e+10 Memory= 1173.518 t= 1.65e+04 R= 8e+02
+Depth= 6515 States= 1.5e+07 Transitions= 1.3e+10 Memory= 1207.893 t= 1.76e+04 R= 9e+02
+Depth= 6515 States= 1.6e+07 Transitions= 1.38e+10 Memory= 1234.065 t= 1.86e+04 R= 9e+02
+Depth= 6515 States= 1.7e+07 Transitions= 1.47e+10 Memory= 1277.424 t= 1.99e+04 R= 9e+02
+Depth= 6515 States= 1.8e+07 Transitions= 1.58e+10 Memory= 1325.568 t= 2.13e+04 R= 8e+02
+Depth= 6515 States= 1.9e+07 Transitions= 1.67e+10 Memory= 1366.486 t= 2.26e+04 R= 8e+02
+Depth= 6515 States= 2e+07 Transitions= 1.76e+10 Memory= 1405.940 t= 2.38e+04 R= 8e+02
+Depth= 6515 States= 2.1e+07 Transitions= 1.85e+10 Memory= 1450.080 t= 2.51e+04 R= 8e+02
+Depth= 6515 States= 2.2e+07 Transitions= 1.94e+10 Memory= 1491.291 t= 2.63e+04 R= 8e+02
+Depth= 6515 States= 2.3e+07 Transitions= 2.02e+10 Memory= 1530.744 t= 2.74e+04 R= 8e+02
+Depth= 6515 States= 2.4e+07 Transitions= 2.12e+10 Memory= 1565.217 t= 2.87e+04 R= 8e+02
+Depth= 6515 States= 2.5e+07 Transitions= 2.22e+10 Memory= 1608.479 t= 3e+04 R= 8e+02
+Depth= 6515 States= 2.6e+07 Transitions= 2.3e+10 Memory= 1634.651 t= 3.11e+04 R= 8e+02
+Depth= 6515 States= 2.7e+07 Transitions= 2.4e+10 Memory= 1685.725 t= 3.25e+04 R= 8e+02
+Depth= 6515 States= 2.8e+07 Transitions= 2.49e+10 Memory= 1724.885 t= 3.37e+04 R= 8e+02
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 6515, errors: 0
+ 13561338 states, stored (2.88138e+07 visited)
+2.5567499e+10 states, matched
+2.5596313e+10 transitions (= visited+matched)
+1.4615258e+11 atomic steps
+hash conflicts: 8.6536644e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1500.240 equivalent memory usage for states (stored*(State-vector + overhead))
+ 1175.180 actual memory usage for states (compression: 78.33%)
+ state-vector as stored = 63 byte + 28 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1760.236 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 82, "(1)"
+ line 438, "pan.___", state 112, "(1)"
+ line 442, "pan.___", state 125, "(1)"
+ line 597, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 218, "(1)"
+ line 438, "pan.___", state 248, "(1)"
+ line 442, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 347, "(1)"
+ line 438, "pan.___", state 377, "(1)"
+ line 442, "pan.___", state 390, "(1)"
+ line 411, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 415, "(1)"
+ line 411, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 416, "else"
+ line 411, "pan.___", state 419, "(1)"
+ line 415, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 429, "(1)"
+ line 415, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 430, "else"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 413, "pan.___", state 439, "((i<1))"
+ line 413, "pan.___", state 439, "((i>=1))"
+ line 420, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 447, "(1)"
+ line 420, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 448, "else"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 424, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 461, "(1)"
+ line 424, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 462, "else"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 422, "pan.___", state 471, "((i<2))"
+ line 422, "pan.___", state 471, "((i>=2))"
+ line 429, "pan.___", state 478, "(1)"
+ line 429, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 479, "else"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 433, "pan.___", state 491, "(1)"
+ line 433, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 492, "else"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 431, "pan.___", state 501, "((i<1))"
+ line 431, "pan.___", state 501, "((i>=1))"
+ line 438, "pan.___", state 508, "(1)"
+ line 438, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 509, "else"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 442, "pan.___", state 521, "(1)"
+ line 442, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 522, "else"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 440, "pan.___", state 531, "((i<2))"
+ line 440, "pan.___", state 531, "((i>=2))"
+ line 450, "pan.___", state 535, "(1)"
+ line 450, "pan.___", state 535, "(1)"
+ line 597, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 540, "(1)"
+ line 272, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 555, "(1)"
+ line 280, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 591, "(1)"
+ line 253, "pan.___", state 599, "(1)"
+ line 257, "pan.___", state 611, "(1)"
+ line 261, "pan.___", state 619, "(1)"
+ line 411, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 702, "(1)"
+ line 433, "pan.___", state 715, "(1)"
+ line 438, "pan.___", state 732, "(1)"
+ line 442, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 838, "(1)"
+ line 438, "pan.___", state 868, "(1)"
+ line 442, "pan.___", state 881, "(1)"
+ line 411, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 904, "(1)"
+ line 411, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 905, "else"
+ line 411, "pan.___", state 908, "(1)"
+ line 415, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 918, "(1)"
+ line 415, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 919, "else"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 413, "pan.___", state 928, "((i<1))"
+ line 413, "pan.___", state 928, "((i>=1))"
+ line 420, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 936, "(1)"
+ line 420, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 937, "else"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 424, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 950, "(1)"
+ line 424, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 951, "else"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 422, "pan.___", state 960, "((i<2))"
+ line 422, "pan.___", state 960, "((i>=2))"
+ line 429, "pan.___", state 967, "(1)"
+ line 429, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 968, "else"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 433, "pan.___", state 980, "(1)"
+ line 433, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 981, "else"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 431, "pan.___", state 990, "((i<1))"
+ line 431, "pan.___", state 990, "((i>=1))"
+ line 438, "pan.___", state 997, "(1)"
+ line 438, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 998, "else"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 442, "pan.___", state 1010, "(1)"
+ line 442, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1011, "else"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 440, "pan.___", state 1020, "((i<2))"
+ line 440, "pan.___", state 1020, "((i>=2))"
+ line 450, "pan.___", state 1024, "(1)"
+ line 450, "pan.___", state 1024, "(1)"
+ line 605, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1098, "(1)"
+ line 433, "pan.___", state 1111, "(1)"
+ line 438, "pan.___", state 1128, "(1)"
+ line 442, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1230, "(1)"
+ line 438, "pan.___", state 1260, "(1)"
+ line 442, "pan.___", state 1273, "(1)"
+ line 411, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1363, "(1)"
+ line 438, "pan.___", state 1393, "(1)"
+ line 442, "pan.___", state 1406, "(1)"
+ line 411, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1492, "(1)"
+ line 438, "pan.___", state 1522, "(1)"
+ line 442, "pan.___", state 1535, "(1)"
+ line 272, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1605, "(1)"
+ line 253, "pan.___", state 1613, "(1)"
+ line 257, "pan.___", state 1625, "(1)"
+ line 261, "pan.___", state 1633, "(1)"
+ line 411, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1716, "(1)"
+ line 433, "pan.___", state 1729, "(1)"
+ line 438, "pan.___", state 1746, "(1)"
+ line 442, "pan.___", state 1759, "(1)"
+ line 411, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1845, "(1)"
+ line 433, "pan.___", state 1858, "(1)"
+ line 438, "pan.___", state 1875, "(1)"
+ line 442, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1977, "(1)"
+ line 438, "pan.___", state 2007, "(1)"
+ line 442, "pan.___", state 2020, "(1)"
+ line 644, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2113, "(1)"
+ line 438, "pan.___", state 2143, "(1)"
+ line 442, "pan.___", state 2156, "(1)"
+ line 411, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2242, "(1)"
+ line 438, "pan.___", state 2272, "(1)"
+ line 442, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2310, "(1)"
+ line 411, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2311, "else"
+ line 411, "pan.___", state 2314, "(1)"
+ line 415, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2324, "(1)"
+ line 415, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2325, "else"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 413, "pan.___", state 2334, "((i<1))"
+ line 413, "pan.___", state 2334, "((i>=1))"
+ line 420, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2342, "(1)"
+ line 420, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2343, "else"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 424, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2356, "(1)"
+ line 424, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2357, "else"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 422, "pan.___", state 2366, "((i<2))"
+ line 422, "pan.___", state 2366, "((i>=2))"
+ line 429, "pan.___", state 2373, "(1)"
+ line 429, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2374, "else"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 433, "pan.___", state 2386, "(1)"
+ line 433, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2387, "else"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 431, "pan.___", state 2396, "((i<1))"
+ line 431, "pan.___", state 2396, "((i>=1))"
+ line 438, "pan.___", state 2403, "(1)"
+ line 438, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2404, "else"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 442, "pan.___", state 2416, "(1)"
+ line 442, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2417, "else"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 440, "pan.___", state 2426, "((i<2))"
+ line 440, "pan.___", state 2426, "((i>=2))"
+ line 450, "pan.___", state 2430, "(1)"
+ line 450, "pan.___", state 2430, "(1)"
+ line 644, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2435, "(1)"
+ line 272, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2486, "(1)"
+ line 253, "pan.___", state 2494, "(1)"
+ line 257, "pan.___", state 2506, "(1)"
+ line 261, "pan.___", state 2514, "(1)"
+ line 411, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2597, "(1)"
+ line 433, "pan.___", state 2610, "(1)"
+ line 438, "pan.___", state 2627, "(1)"
+ line 442, "pan.___", state 2640, "(1)"
+ line 272, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2711, "(1)"
+ line 253, "pan.___", state 2719, "(1)"
+ line 257, "pan.___", state 2731, "(1)"
+ line 261, "pan.___", state 2739, "(1)"
+ line 411, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2822, "(1)"
+ line 433, "pan.___", state 2835, "(1)"
+ line 438, "pan.___", state 2852, "(1)"
+ line 442, "pan.___", state 2865, "(1)"
+ line 411, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2951, "(1)"
+ line 433, "pan.___", state 2964, "(1)"
+ line 438, "pan.___", state 2981, "(1)"
+ line 442, "pan.___", state 2994, "(1)"
+ line 249, "pan.___", state 3027, "(1)"
+ line 257, "pan.___", state 3047, "(1)"
+ line 261, "pan.___", state 3055, "(1)"
+ line 249, "pan.___", state 3070, "(1)"
+ line 253, "pan.___", state 3078, "(1)"
+ line 257, "pan.___", state 3090, "(1)"
+ line 261, "pan.___", state 3098, "(1)"
+ line 898, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 83, "(1)"
+ line 433, "pan.___", state 96, "(1)"
+ line 438, "pan.___", state 113, "(1)"
+ line 272, "pan.___", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 276, "(1)"
+ line 433, "pan.___", state 289, "(1)"
+ line 438, "pan.___", state 306, "(1)"
+ line 442, "pan.___", state 319, "(1)"
+ line 415, "pan.___", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 420, "(1)"
+ line 438, "pan.___", state 437, "(1)"
+ line 442, "pan.___", state 450, "(1)"
+ line 415, "pan.___", state 495, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 513, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 559, "(1)"
+ line 438, "pan.___", state 576, "(1)"
+ line 442, "pan.___", state 589, "(1)"
+ line 415, "pan.___", state 624, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 642, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 656, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 688, "(1)"
+ line 438, "pan.___", state 705, "(1)"
+ line 442, "pan.___", state 718, "(1)"
+ line 415, "pan.___", state 755, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 773, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 787, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 819, "(1)"
+ line 438, "pan.___", state 836, "(1)"
+ line 442, "pan.___", state 849, "(1)"
+ line 272, "pan.___", state 899, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 908, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 921, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 946, "(1)"
+ line 253, "pan.___", state 954, "(1)"
+ line 257, "pan.___", state 966, "(1)"
+ line 261, "pan.___", state 974, "(1)"
+ line 272, "pan.___", state 994, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1003, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1018, "(1)"
+ line 284, "pan.___", state 1025, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1041, "(1)"
+ line 253, "pan.___", state 1049, "(1)"
+ line 257, "pan.___", state 1061, "(1)"
+ line 261, "pan.___", state 1069, "(1)"
+ line 276, "pan.___", state 1094, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1107, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1116, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1132, "(1)"
+ line 253, "pan.___", state 1140, "(1)"
+ line 257, "pan.___", state 1152, "(1)"
+ line 261, "pan.___", state 1160, "(1)"
+ line 276, "pan.___", state 1185, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1198, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1207, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1223, "(1)"
+ line 253, "pan.___", state 1231, "(1)"
+ line 257, "pan.___", state 1243, "(1)"
+ line 261, "pan.___", state 1251, "(1)"
+ line 276, "pan.___", state 1276, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1289, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1298, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1314, "(1)"
+ line 253, "pan.___", state 1322, "(1)"
+ line 257, "pan.___", state 1334, "(1)"
+ line 261, "pan.___", state 1342, "(1)"
+ line 1237, "pan.___", state 1357, "-end-"
+ (78 of 1357 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1302, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 3.47e+04 seconds
+pan: rate 831.51243 states/second
+pan: avg transition delay 1.3538e-06 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define READER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+depth 23: Claim reached state 9 (line 1300)
+depth 1559: Claim reached state 9 (line 1299)
+Depth= 4420 States= 1e+06 Transitions= 6.06e+08 Memory= 491.936 t= 782 R= 1e+03
+Depth= 4420 States= 2e+06 Transitions= 1.36e+09 Memory= 516.838 t= 1.76e+03 R= 1e+03
+Depth= 4477 States= 3e+06 Transitions= 1.91e+09 Memory= 542.424 t= 2.47e+03 R= 1e+03
+pan: resizing hashtable to -w22.. done
+Depth= 4770 States= 4e+06 Transitions= 2.71e+09 Memory= 598.545 t= 3.51e+03 R= 1e+03
+Depth= 4829 States= 5e+06 Transitions= 3.25e+09 Memory= 623.838 t= 4.2e+03 R= 1e+03
+Depth= 5120 States= 6e+06 Transitions= 4.02e+09 Memory= 648.838 t= 5.19e+03 R= 1e+03
+Depth= 5188 States= 7e+06 Transitions= 4.89e+09 Memory= 693.662 t= 6.32e+03 R= 1e+03
+Depth= 5188 States= 8e+06 Transitions= 5.86e+09 Memory= 742.588 t= 7.58e+03 R= 1e+03
+Depth= 5188 States= 9e+06 Transitions= 6.88e+09 Memory= 781.651 t= 8.92e+03 R= 1e+03
+pan: resizing hashtable to -w24.. done
+Depth= 5188 States= 1e+07 Transitions= 7.86e+09 Memory= 952.229 t= 1.02e+04 R= 1e+03
+Depth= 5188 States= 1.1e+07 Transitions= 8.82e+09 Memory= 991.096 t= 1.15e+04 R= 1e+03
+Depth= 5436 States= 1.2e+07 Transitions= 9.74e+09 Memory= 1031.037 t= 1.27e+04 R= 9e+02
+Depth= 5479 States= 1.3e+07 Transitions= 1.07e+10 Memory= 1074.006 t= 1.4e+04 R= 9e+02
+Depth= 5479 States= 1.4e+07 Transitions= 1.16e+10 Memory= 1117.658 t= 1.52e+04 R= 9e+02
+Depth= 5479 States= 1.5e+07 Transitions= 1.25e+10 Memory= 1160.529 t= 1.63e+04 R= 9e+02
+Depth= 5479 States= 1.6e+07 Transitions= 1.36e+10 Memory= 1208.772 t= 1.77e+04 R= 9e+02
+Depth= 5479 States= 1.7e+07 Transitions= 1.45e+10 Memory= 1253.401 t= 1.88e+04 R= 9e+02
+Depth= 5479 States= 1.8e+07 Transitions= 1.54e+10 Memory= 1278.986 t= 2.01e+04 R= 9e+02
+Depth= 5479 States= 1.9e+07 Transitions= 1.64e+10 Memory= 1333.186 t= 2.14e+04 R= 9e+02
+Depth= 5479 States= 2e+07 Transitions= 1.73e+10 Memory= 1370.979 t= 2.26e+04 R= 9e+02
+Depth= 5479 States= 2.1e+07 Transitions= 1.83e+10 Memory= 1415.998 t= 2.39e+04 R= 9e+02
+Depth= 5479 States= 2.2e+07 Transitions= 1.92e+10 Memory= 1455.940 t= 2.51e+04 R= 9e+02
+Depth= 5479 States= 2.3e+07 Transitions= 2.02e+10 Memory= 1499.397 t= 2.63e+04 R= 9e+02
+Depth= 5479 States= 2.4e+07 Transitions= 2.1e+10 Memory= 1542.951 t= 2.75e+04 R= 9e+02
+Depth= 5588 States= 2.5e+07 Transitions= 2.21e+10 Memory= 1589.533 t= 2.89e+04 R= 9e+02
+Depth= 5588 States= 2.6e+07 Transitions= 2.31e+10 Memory= 1630.647 t= 3.02e+04 R= 9e+02
+Depth= 5588 States= 2.7e+07 Transitions= 2.4e+10 Memory= 1669.123 t= 3.14e+04 R= 9e+02
+Depth= 5588 States= 2.8e+07 Transitions= 2.5e+10 Memory= 1714.533 t= 3.27e+04 R= 9e+02
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5588, errors: 0
+ 13563866 states, stored (2.88596e+07 visited)
+2.5765769e+10 states, matched
+2.5794629e+10 transitions (= visited+matched)
+1.4717516e+11 atomic steps
+hash conflicts: 6.8547236e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1500.519 equivalent memory usage for states (stored*(State-vector + overhead))
+ 1175.436 actual memory usage for states (compression: 78.34%)
+ state-vector as stored = 63 byte + 28 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1760.432 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 82, "(1)"
+ line 438, "pan.___", state 112, "(1)"
+ line 442, "pan.___", state 125, "(1)"
+ line 597, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 218, "(1)"
+ line 438, "pan.___", state 248, "(1)"
+ line 442, "pan.___", state 261, "(1)"
+ line 411, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 347, "(1)"
+ line 438, "pan.___", state 377, "(1)"
+ line 442, "pan.___", state 390, "(1)"
+ line 411, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 415, "(1)"
+ line 411, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 416, "else"
+ line 411, "pan.___", state 419, "(1)"
+ line 415, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 429, "(1)"
+ line 415, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 430, "else"
+ line 415, "pan.___", state 433, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 415, "pan.___", state 434, "(1)"
+ line 413, "pan.___", state 439, "((i<1))"
+ line 413, "pan.___", state 439, "((i>=1))"
+ line 420, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 447, "(1)"
+ line 420, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 448, "else"
+ line 420, "pan.___", state 451, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 420, "pan.___", state 452, "(1)"
+ line 424, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 461, "(1)"
+ line 424, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 462, "else"
+ line 424, "pan.___", state 465, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 424, "pan.___", state 466, "(1)"
+ line 422, "pan.___", state 471, "((i<2))"
+ line 422, "pan.___", state 471, "((i>=2))"
+ line 429, "pan.___", state 478, "(1)"
+ line 429, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 479, "else"
+ line 429, "pan.___", state 482, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 429, "pan.___", state 483, "(1)"
+ line 433, "pan.___", state 491, "(1)"
+ line 433, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 492, "else"
+ line 433, "pan.___", state 495, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 433, "pan.___", state 496, "(1)"
+ line 431, "pan.___", state 501, "((i<1))"
+ line 431, "pan.___", state 501, "((i>=1))"
+ line 438, "pan.___", state 508, "(1)"
+ line 438, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 509, "else"
+ line 438, "pan.___", state 512, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 438, "pan.___", state 513, "(1)"
+ line 442, "pan.___", state 521, "(1)"
+ line 442, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 522, "else"
+ line 442, "pan.___", state 525, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 442, "pan.___", state 526, "(1)"
+ line 440, "pan.___", state 531, "((i<2))"
+ line 440, "pan.___", state 531, "((i>=2))"
+ line 450, "pan.___", state 535, "(1)"
+ line 450, "pan.___", state 535, "(1)"
+ line 597, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 540, "(1)"
+ line 272, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 555, "(1)"
+ line 280, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 591, "(1)"
+ line 253, "pan.___", state 599, "(1)"
+ line 257, "pan.___", state 611, "(1)"
+ line 261, "pan.___", state 619, "(1)"
+ line 411, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 702, "(1)"
+ line 433, "pan.___", state 715, "(1)"
+ line 438, "pan.___", state 732, "(1)"
+ line 442, "pan.___", state 745, "(1)"
+ line 411, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 838, "(1)"
+ line 438, "pan.___", state 868, "(1)"
+ line 442, "pan.___", state 881, "(1)"
+ line 411, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 904, "(1)"
+ line 411, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 905, "else"
+ line 411, "pan.___", state 908, "(1)"
+ line 415, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 918, "(1)"
+ line 415, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 919, "else"
+ line 415, "pan.___", state 922, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 415, "pan.___", state 923, "(1)"
+ line 413, "pan.___", state 928, "((i<1))"
+ line 413, "pan.___", state 928, "((i>=1))"
+ line 420, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 936, "(1)"
+ line 420, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 937, "else"
+ line 420, "pan.___", state 940, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 420, "pan.___", state 941, "(1)"
+ line 424, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 950, "(1)"
+ line 424, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 951, "else"
+ line 424, "pan.___", state 954, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 424, "pan.___", state 955, "(1)"
+ line 422, "pan.___", state 960, "((i<2))"
+ line 422, "pan.___", state 960, "((i>=2))"
+ line 429, "pan.___", state 967, "(1)"
+ line 429, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 968, "else"
+ line 429, "pan.___", state 971, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 429, "pan.___", state 972, "(1)"
+ line 433, "pan.___", state 980, "(1)"
+ line 433, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 981, "else"
+ line 433, "pan.___", state 984, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 433, "pan.___", state 985, "(1)"
+ line 431, "pan.___", state 990, "((i<1))"
+ line 431, "pan.___", state 990, "((i>=1))"
+ line 438, "pan.___", state 997, "(1)"
+ line 438, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 998, "else"
+ line 438, "pan.___", state 1001, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 438, "pan.___", state 1002, "(1)"
+ line 442, "pan.___", state 1010, "(1)"
+ line 442, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 1011, "else"
+ line 442, "pan.___", state 1014, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 442, "pan.___", state 1015, "(1)"
+ line 440, "pan.___", state 1020, "((i<2))"
+ line 440, "pan.___", state 1020, "((i>=2))"
+ line 450, "pan.___", state 1024, "(1)"
+ line 450, "pan.___", state 1024, "(1)"
+ line 605, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1098, "(1)"
+ line 433, "pan.___", state 1111, "(1)"
+ line 438, "pan.___", state 1128, "(1)"
+ line 442, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1230, "(1)"
+ line 438, "pan.___", state 1260, "(1)"
+ line 442, "pan.___", state 1273, "(1)"
+ line 411, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1363, "(1)"
+ line 438, "pan.___", state 1393, "(1)"
+ line 442, "pan.___", state 1406, "(1)"
+ line 411, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1492, "(1)"
+ line 438, "pan.___", state 1522, "(1)"
+ line 442, "pan.___", state 1535, "(1)"
+ line 272, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1605, "(1)"
+ line 253, "pan.___", state 1613, "(1)"
+ line 257, "pan.___", state 1625, "(1)"
+ line 261, "pan.___", state 1633, "(1)"
+ line 411, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1716, "(1)"
+ line 433, "pan.___", state 1729, "(1)"
+ line 438, "pan.___", state 1746, "(1)"
+ line 442, "pan.___", state 1759, "(1)"
+ line 411, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1845, "(1)"
+ line 433, "pan.___", state 1858, "(1)"
+ line 438, "pan.___", state 1875, "(1)"
+ line 442, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 1977, "(1)"
+ line 438, "pan.___", state 2007, "(1)"
+ line 442, "pan.___", state 2020, "(1)"
+ line 644, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2113, "(1)"
+ line 438, "pan.___", state 2143, "(1)"
+ line 442, "pan.___", state 2156, "(1)"
+ line 411, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2242, "(1)"
+ line 438, "pan.___", state 2272, "(1)"
+ line 442, "pan.___", state 2285, "(1)"
+ line 411, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2310, "(1)"
+ line 411, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2311, "else"
+ line 411, "pan.___", state 2314, "(1)"
+ line 415, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2324, "(1)"
+ line 415, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2325, "else"
+ line 415, "pan.___", state 2328, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 415, "pan.___", state 2329, "(1)"
+ line 413, "pan.___", state 2334, "((i<1))"
+ line 413, "pan.___", state 2334, "((i>=1))"
+ line 420, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2342, "(1)"
+ line 420, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2343, "else"
+ line 420, "pan.___", state 2346, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 420, "pan.___", state 2347, "(1)"
+ line 424, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2356, "(1)"
+ line 424, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2357, "else"
+ line 424, "pan.___", state 2360, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 424, "pan.___", state 2361, "(1)"
+ line 422, "pan.___", state 2366, "((i<2))"
+ line 422, "pan.___", state 2366, "((i>=2))"
+ line 429, "pan.___", state 2373, "(1)"
+ line 429, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 429, "pan.___", state 2374, "else"
+ line 429, "pan.___", state 2377, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 429, "pan.___", state 2378, "(1)"
+ line 433, "pan.___", state 2386, "(1)"
+ line 433, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 433, "pan.___", state 2387, "else"
+ line 433, "pan.___", state 2390, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 433, "pan.___", state 2391, "(1)"
+ line 431, "pan.___", state 2396, "((i<1))"
+ line 431, "pan.___", state 2396, "((i>=1))"
+ line 438, "pan.___", state 2403, "(1)"
+ line 438, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 438, "pan.___", state 2404, "else"
+ line 438, "pan.___", state 2407, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 438, "pan.___", state 2408, "(1)"
+ line 442, "pan.___", state 2416, "(1)"
+ line 442, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 442, "pan.___", state 2417, "else"
+ line 442, "pan.___", state 2420, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 442, "pan.___", state 2421, "(1)"
+ line 440, "pan.___", state 2426, "((i<2))"
+ line 440, "pan.___", state 2426, "((i>=2))"
+ line 450, "pan.___", state 2430, "(1)"
+ line 450, "pan.___", state 2430, "(1)"
+ line 644, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2435, "(1)"
+ line 272, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2486, "(1)"
+ line 253, "pan.___", state 2494, "(1)"
+ line 257, "pan.___", state 2506, "(1)"
+ line 261, "pan.___", state 2514, "(1)"
+ line 411, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2597, "(1)"
+ line 433, "pan.___", state 2610, "(1)"
+ line 438, "pan.___", state 2627, "(1)"
+ line 442, "pan.___", state 2640, "(1)"
+ line 272, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2711, "(1)"
+ line 253, "pan.___", state 2719, "(1)"
+ line 257, "pan.___", state 2731, "(1)"
+ line 261, "pan.___", state 2739, "(1)"
+ line 411, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2822, "(1)"
+ line 433, "pan.___", state 2835, "(1)"
+ line 438, "pan.___", state 2852, "(1)"
+ line 442, "pan.___", state 2865, "(1)"
+ line 411, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 2951, "(1)"
+ line 433, "pan.___", state 2964, "(1)"
+ line 438, "pan.___", state 2981, "(1)"
+ line 442, "pan.___", state 2994, "(1)"
+ line 249, "pan.___", state 3027, "(1)"
+ line 257, "pan.___", state 3047, "(1)"
+ line 261, "pan.___", state 3055, "(1)"
+ line 249, "pan.___", state 3070, "(1)"
+ line 253, "pan.___", state 3078, "(1)"
+ line 257, "pan.___", state 3090, "(1)"
+ line 261, "pan.___", state 3098, "(1)"
+ line 898, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 83, "(1)"
+ line 433, "pan.___", state 96, "(1)"
+ line 438, "pan.___", state 113, "(1)"
+ line 272, "pan.___", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 429, "pan.___", state 276, "(1)"
+ line 433, "pan.___", state 289, "(1)"
+ line 438, "pan.___", state 306, "(1)"
+ line 442, "pan.___", state 319, "(1)"
+ line 415, "pan.___", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 420, "(1)"
+ line 438, "pan.___", state 437, "(1)"
+ line 442, "pan.___", state 450, "(1)"
+ line 415, "pan.___", state 495, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 513, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 559, "(1)"
+ line 438, "pan.___", state 576, "(1)"
+ line 442, "pan.___", state 589, "(1)"
+ line 415, "pan.___", state 624, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 642, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 656, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 688, "(1)"
+ line 438, "pan.___", state 705, "(1)"
+ line 442, "pan.___", state 718, "(1)"
+ line 415, "pan.___", state 755, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 773, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 787, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 433, "pan.___", state 819, "(1)"
+ line 438, "pan.___", state 836, "(1)"
+ line 442, "pan.___", state 849, "(1)"
+ line 272, "pan.___", state 904, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 913, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 928, "(1)"
+ line 284, "pan.___", state 935, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 951, "(1)"
+ line 253, "pan.___", state 959, "(1)"
+ line 257, "pan.___", state 971, "(1)"
+ line 261, "pan.___", state 979, "(1)"
+ line 276, "pan.___", state 1004, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1017, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1026, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1042, "(1)"
+ line 253, "pan.___", state 1050, "(1)"
+ line 257, "pan.___", state 1062, "(1)"
+ line 261, "pan.___", state 1070, "(1)"
+ line 276, "pan.___", state 1095, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1108, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1117, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1133, "(1)"
+ line 253, "pan.___", state 1141, "(1)"
+ line 257, "pan.___", state 1153, "(1)"
+ line 261, "pan.___", state 1161, "(1)"
+ line 276, "pan.___", state 1186, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1199, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1208, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1224, "(1)"
+ line 253, "pan.___", state 1232, "(1)"
+ line 257, "pan.___", state 1244, "(1)"
+ line 261, "pan.___", state 1252, "(1)"
+ line 1237, "pan.___", state 1267, "-end-"
+ (71 of 1267 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1302, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 3.38e+04 seconds
+pan: rate 854.75351 states/second
+pan: avg transition delay 1.3089e-06 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1296)
+depth 23: Claim reached state 9 (line 1301)
+depth 1559: Claim reached state 9 (line 1300)
+pan: acceptance cycle (at depth 6380)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 7421, errors: 1
+ 55319 states, stored (173044 visited)
+ 69543507 states, matched
+ 69716551 transitions (= visited+matched)
+3.7666148e+08 atomic steps
+hash conflicts: 1148679 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 6.120 equivalent memory usage for states (stored*(State-vector + overhead))
+ 5.332 actual memory usage for states (compression: 87.12%)
+ state-vector as stored = 73 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 471.037 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 412, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 82, "(1)"
+ line 439, "pan.___", state 112, "(1)"
+ line 443, "pan.___", state 125, "(1)"
+ line 598, "pan.___", state 146, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 412, "pan.___", state 153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 185, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 199, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 218, "(1)"
+ line 439, "pan.___", state 248, "(1)"
+ line 443, "pan.___", state 261, "(1)"
+ line 412, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 314, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 328, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 347, "(1)"
+ line 439, "pan.___", state 377, "(1)"
+ line 443, "pan.___", state 390, "(1)"
+ line 412, "pan.___", state 413, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 415, "(1)"
+ line 412, "pan.___", state 416, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 416, "else"
+ line 412, "pan.___", state 419, "(1)"
+ line 416, "pan.___", state 427, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 429, "(1)"
+ line 416, "pan.___", state 430, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 430, "else"
+ line 416, "pan.___", state 433, "(1)"
+ line 416, "pan.___", state 434, "(1)"
+ line 416, "pan.___", state 434, "(1)"
+ line 414, "pan.___", state 439, "((i<1))"
+ line 414, "pan.___", state 439, "((i>=1))"
+ line 421, "pan.___", state 445, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 447, "(1)"
+ line 421, "pan.___", state 448, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 448, "else"
+ line 421, "pan.___", state 451, "(1)"
+ line 421, "pan.___", state 452, "(1)"
+ line 421, "pan.___", state 452, "(1)"
+ line 425, "pan.___", state 459, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 461, "(1)"
+ line 425, "pan.___", state 462, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 462, "else"
+ line 425, "pan.___", state 465, "(1)"
+ line 425, "pan.___", state 466, "(1)"
+ line 425, "pan.___", state 466, "(1)"
+ line 423, "pan.___", state 471, "((i<2))"
+ line 423, "pan.___", state 471, "((i>=2))"
+ line 430, "pan.___", state 478, "(1)"
+ line 430, "pan.___", state 479, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 479, "else"
+ line 430, "pan.___", state 482, "(1)"
+ line 430, "pan.___", state 483, "(1)"
+ line 430, "pan.___", state 483, "(1)"
+ line 434, "pan.___", state 491, "(1)"
+ line 434, "pan.___", state 492, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 492, "else"
+ line 434, "pan.___", state 495, "(1)"
+ line 434, "pan.___", state 496, "(1)"
+ line 434, "pan.___", state 496, "(1)"
+ line 432, "pan.___", state 501, "((i<1))"
+ line 432, "pan.___", state 501, "((i>=1))"
+ line 439, "pan.___", state 508, "(1)"
+ line 439, "pan.___", state 509, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 509, "else"
+ line 439, "pan.___", state 512, "(1)"
+ line 439, "pan.___", state 513, "(1)"
+ line 439, "pan.___", state 513, "(1)"
+ line 443, "pan.___", state 521, "(1)"
+ line 443, "pan.___", state 522, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 522, "else"
+ line 443, "pan.___", state 525, "(1)"
+ line 443, "pan.___", state 526, "(1)"
+ line 443, "pan.___", state 526, "(1)"
+ line 441, "pan.___", state 531, "((i<2))"
+ line 441, "pan.___", state 531, "((i>=2))"
+ line 451, "pan.___", state 535, "(1)"
+ line 451, "pan.___", state 535, "(1)"
+ line 598, "pan.___", state 538, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 598, "pan.___", state 539, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 598, "pan.___", state 540, "(1)"
+ line 273, "pan.___", state 544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 555, "(1)"
+ line 281, "pan.___", state 566, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 575, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 591, "(1)"
+ line 254, "pan.___", state 599, "(1)"
+ line 258, "pan.___", state 611, "(1)"
+ line 262, "pan.___", state 619, "(1)"
+ line 412, "pan.___", state 637, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 651, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 669, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 683, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 702, "(1)"
+ line 434, "pan.___", state 715, "(1)"
+ line 439, "pan.___", state 732, "(1)"
+ line 443, "pan.___", state 745, "(1)"
+ line 412, "pan.___", state 773, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 805, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 819, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 838, "(1)"
+ line 439, "pan.___", state 868, "(1)"
+ line 443, "pan.___", state 881, "(1)"
+ line 412, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 904, "(1)"
+ line 412, "pan.___", state 905, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 905, "else"
+ line 412, "pan.___", state 908, "(1)"
+ line 416, "pan.___", state 916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 918, "(1)"
+ line 416, "pan.___", state 919, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 919, "else"
+ line 416, "pan.___", state 922, "(1)"
+ line 416, "pan.___", state 923, "(1)"
+ line 416, "pan.___", state 923, "(1)"
+ line 414, "pan.___", state 928, "((i<1))"
+ line 414, "pan.___", state 928, "((i>=1))"
+ line 421, "pan.___", state 934, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 936, "(1)"
+ line 421, "pan.___", state 937, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 937, "else"
+ line 421, "pan.___", state 940, "(1)"
+ line 421, "pan.___", state 941, "(1)"
+ line 421, "pan.___", state 941, "(1)"
+ line 425, "pan.___", state 948, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 950, "(1)"
+ line 425, "pan.___", state 951, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 951, "else"
+ line 425, "pan.___", state 954, "(1)"
+ line 425, "pan.___", state 955, "(1)"
+ line 425, "pan.___", state 955, "(1)"
+ line 423, "pan.___", state 960, "((i<2))"
+ line 423, "pan.___", state 960, "((i>=2))"
+ line 430, "pan.___", state 967, "(1)"
+ line 430, "pan.___", state 968, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 968, "else"
+ line 430, "pan.___", state 971, "(1)"
+ line 430, "pan.___", state 972, "(1)"
+ line 430, "pan.___", state 972, "(1)"
+ line 434, "pan.___", state 980, "(1)"
+ line 434, "pan.___", state 981, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 981, "else"
+ line 434, "pan.___", state 984, "(1)"
+ line 434, "pan.___", state 985, "(1)"
+ line 434, "pan.___", state 985, "(1)"
+ line 432, "pan.___", state 990, "((i<1))"
+ line 432, "pan.___", state 990, "((i>=1))"
+ line 439, "pan.___", state 997, "(1)"
+ line 439, "pan.___", state 998, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 998, "else"
+ line 439, "pan.___", state 1001, "(1)"
+ line 439, "pan.___", state 1002, "(1)"
+ line 439, "pan.___", state 1002, "(1)"
+ line 443, "pan.___", state 1010, "(1)"
+ line 443, "pan.___", state 1011, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 1011, "else"
+ line 443, "pan.___", state 1014, "(1)"
+ line 443, "pan.___", state 1015, "(1)"
+ line 443, "pan.___", state 1015, "(1)"
+ line 441, "pan.___", state 1020, "((i<2))"
+ line 441, "pan.___", state 1020, "((i>=2))"
+ line 451, "pan.___", state 1024, "(1)"
+ line 451, "pan.___", state 1024, "(1)"
+ line 606, "pan.___", state 1028, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 412, "pan.___", state 1033, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1047, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1065, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1079, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1098, "(1)"
+ line 434, "pan.___", state 1111, "(1)"
+ line 439, "pan.___", state 1128, "(1)"
+ line 443, "pan.___", state 1141, "(1)"
+ line 412, "pan.___", state 1165, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1197, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1211, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1230, "(1)"
+ line 439, "pan.___", state 1260, "(1)"
+ line 443, "pan.___", state 1273, "(1)"
+ line 412, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1363, "(1)"
+ line 439, "pan.___", state 1393, "(1)"
+ line 443, "pan.___", state 1406, "(1)"
+ line 412, "pan.___", state 1427, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1492, "(1)"
+ line 439, "pan.___", state 1522, "(1)"
+ line 443, "pan.___", state 1535, "(1)"
+ line 273, "pan.___", state 1558, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 1580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 1589, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1605, "(1)"
+ line 254, "pan.___", state 1613, "(1)"
+ line 258, "pan.___", state 1625, "(1)"
+ line 262, "pan.___", state 1633, "(1)"
+ line 412, "pan.___", state 1651, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1716, "(1)"
+ line 434, "pan.___", state 1729, "(1)"
+ line 439, "pan.___", state 1746, "(1)"
+ line 443, "pan.___", state 1759, "(1)"
+ line 412, "pan.___", state 1780, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1794, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1812, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1826, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1845, "(1)"
+ line 434, "pan.___", state 1858, "(1)"
+ line 439, "pan.___", state 1875, "(1)"
+ line 443, "pan.___", state 1888, "(1)"
+ line 412, "pan.___", state 1912, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1944, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1958, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1977, "(1)"
+ line 439, "pan.___", state 2007, "(1)"
+ line 443, "pan.___", state 2020, "(1)"
+ line 645, "pan.___", state 2041, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 412, "pan.___", state 2048, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2080, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2094, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 2113, "(1)"
+ line 439, "pan.___", state 2143, "(1)"
+ line 443, "pan.___", state 2156, "(1)"
+ line 412, "pan.___", state 2177, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2209, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 2242, "(1)"
+ line 439, "pan.___", state 2272, "(1)"
+ line 443, "pan.___", state 2285, "(1)"
+ line 412, "pan.___", state 2308, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 2310, "(1)"
+ line 412, "pan.___", state 2311, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 2311, "else"
+ line 412, "pan.___", state 2314, "(1)"
+ line 416, "pan.___", state 2322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2324, "(1)"
+ line 416, "pan.___", state 2325, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 2325, "else"
+ line 416, "pan.___", state 2328, "(1)"
+ line 416, "pan.___", state 2329, "(1)"
+ line 416, "pan.___", state 2329, "(1)"
+ line 414, "pan.___", state 2334, "((i<1))"
+ line 414, "pan.___", state 2334, "((i>=1))"
+ line 421, "pan.___", state 2340, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2342, "(1)"
+ line 421, "pan.___", state 2343, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 2343, "else"
+ line 421, "pan.___", state 2346, "(1)"
+ line 421, "pan.___", state 2347, "(1)"
+ line 421, "pan.___", state 2347, "(1)"
+ line 425, "pan.___", state 2354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2356, "(1)"
+ line 425, "pan.___", state 2357, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 2357, "else"
+ line 425, "pan.___", state 2360, "(1)"
+ line 425, "pan.___", state 2361, "(1)"
+ line 425, "pan.___", state 2361, "(1)"
+ line 423, "pan.___", state 2366, "((i<2))"
+ line 423, "pan.___", state 2366, "((i>=2))"
+ line 430, "pan.___", state 2373, "(1)"
+ line 430, "pan.___", state 2374, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 2374, "else"
+ line 430, "pan.___", state 2377, "(1)"
+ line 430, "pan.___", state 2378, "(1)"
+ line 430, "pan.___", state 2378, "(1)"
+ line 434, "pan.___", state 2386, "(1)"
+ line 434, "pan.___", state 2387, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 2387, "else"
+ line 434, "pan.___", state 2390, "(1)"
+ line 434, "pan.___", state 2391, "(1)"
+ line 434, "pan.___", state 2391, "(1)"
+ line 432, "pan.___", state 2396, "((i<1))"
+ line 432, "pan.___", state 2396, "((i>=1))"
+ line 439, "pan.___", state 2403, "(1)"
+ line 439, "pan.___", state 2404, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 2404, "else"
+ line 439, "pan.___", state 2407, "(1)"
+ line 439, "pan.___", state 2408, "(1)"
+ line 439, "pan.___", state 2408, "(1)"
+ line 443, "pan.___", state 2416, "(1)"
+ line 443, "pan.___", state 2417, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 2417, "else"
+ line 443, "pan.___", state 2420, "(1)"
+ line 443, "pan.___", state 2421, "(1)"
+ line 443, "pan.___", state 2421, "(1)"
+ line 441, "pan.___", state 2426, "((i<2))"
+ line 441, "pan.___", state 2426, "((i>=2))"
+ line 451, "pan.___", state 2430, "(1)"
+ line 451, "pan.___", state 2430, "(1)"
+ line 645, "pan.___", state 2433, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 645, "pan.___", state 2434, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 645, "pan.___", state 2435, "(1)"
+ line 273, "pan.___", state 2439, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 2461, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 2470, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2486, "(1)"
+ line 254, "pan.___", state 2494, "(1)"
+ line 258, "pan.___", state 2506, "(1)"
+ line 262, "pan.___", state 2514, "(1)"
+ line 412, "pan.___", state 2532, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2546, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2564, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2578, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 2597, "(1)"
+ line 434, "pan.___", state 2610, "(1)"
+ line 439, "pan.___", state 2627, "(1)"
+ line 443, "pan.___", state 2640, "(1)"
+ line 273, "pan.___", state 2664, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 2673, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 2686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 2695, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2711, "(1)"
+ line 254, "pan.___", state 2719, "(1)"
+ line 258, "pan.___", state 2731, "(1)"
+ line 262, "pan.___", state 2739, "(1)"
+ line 412, "pan.___", state 2757, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 2822, "(1)"
+ line 434, "pan.___", state 2835, "(1)"
+ line 439, "pan.___", state 2852, "(1)"
+ line 443, "pan.___", state 2865, "(1)"
+ line 412, "pan.___", state 2886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2918, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2932, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 2951, "(1)"
+ line 434, "pan.___", state 2964, "(1)"
+ line 439, "pan.___", state 2981, "(1)"
+ line 443, "pan.___", state 2994, "(1)"
+ line 250, "pan.___", state 3027, "(1)"
+ line 258, "pan.___", state 3047, "(1)"
+ line 262, "pan.___", state 3055, "(1)"
+ line 250, "pan.___", state 3070, "(1)"
+ line 254, "pan.___", state 3078, "(1)"
+ line 258, "pan.___", state 3090, "(1)"
+ line 262, "pan.___", state 3098, "(1)"
+ line 899, "pan.___", state 3115, "-end-"
+ (283 of 3115 states)
+unreached in proctype urcu_writer
+ line 412, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 24, "(1)"
+ line 416, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 38, "(1)"
+ line 416, "pan.___", state 39, "(1)"
+ line 416, "pan.___", state 39, "(1)"
+ line 414, "pan.___", state 44, "((i<1))"
+ line 414, "pan.___", state 44, "((i>=1))"
+ line 421, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 56, "(1)"
+ line 421, "pan.___", state 57, "(1)"
+ line 421, "pan.___", state 57, "(1)"
+ line 425, "pan.___", state 64, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 70, "(1)"
+ line 425, "pan.___", state 71, "(1)"
+ line 425, "pan.___", state 71, "(1)"
+ line 423, "pan.___", state 76, "((i<2))"
+ line 423, "pan.___", state 76, "((i>=2))"
+ line 430, "pan.___", state 83, "(1)"
+ line 430, "pan.___", state 84, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 84, "else"
+ line 430, "pan.___", state 87, "(1)"
+ line 430, "pan.___", state 88, "(1)"
+ line 430, "pan.___", state 88, "(1)"
+ line 434, "pan.___", state 96, "(1)"
+ line 434, "pan.___", state 97, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 97, "else"
+ line 434, "pan.___", state 100, "(1)"
+ line 434, "pan.___", state 101, "(1)"
+ line 434, "pan.___", state 101, "(1)"
+ line 432, "pan.___", state 106, "((i<1))"
+ line 432, "pan.___", state 106, "((i>=1))"
+ line 439, "pan.___", state 113, "(1)"
+ line 439, "pan.___", state 114, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 114, "else"
+ line 439, "pan.___", state 117, "(1)"
+ line 439, "pan.___", state 118, "(1)"
+ line 439, "pan.___", state 118, "(1)"
+ line 443, "pan.___", state 126, "(1)"
+ line 443, "pan.___", state 127, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 127, "else"
+ line 443, "pan.___", state 130, "(1)"
+ line 443, "pan.___", state 131, "(1)"
+ line 443, "pan.___", state 131, "(1)"
+ line 441, "pan.___", state 136, "((i<2))"
+ line 441, "pan.___", state 136, "((i>=2))"
+ line 451, "pan.___", state 140, "(1)"
+ line 451, "pan.___", state 140, "(1)"
+ line 273, "pan.___", state 149, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 158, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 166, "((i<1))"
+ line 275, "pan.___", state 166, "((i>=1))"
+ line 281, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 1022, "pan.___", state 199, "old_data = cached_rcu_ptr.val[_pid]"
+ line 412, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 217, "(1)"
+ line 416, "pan.___", state 225, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 231, "(1)"
+ line 416, "pan.___", state 232, "(1)"
+ line 416, "pan.___", state 232, "(1)"
+ line 414, "pan.___", state 237, "((i<1))"
+ line 414, "pan.___", state 237, "((i>=1))"
+ line 421, "pan.___", state 243, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 249, "(1)"
+ line 421, "pan.___", state 250, "(1)"
+ line 421, "pan.___", state 250, "(1)"
+ line 425, "pan.___", state 257, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 263, "(1)"
+ line 425, "pan.___", state 264, "(1)"
+ line 425, "pan.___", state 264, "(1)"
+ line 423, "pan.___", state 269, "((i<2))"
+ line 423, "pan.___", state 269, "((i>=2))"
+ line 430, "pan.___", state 276, "(1)"
+ line 430, "pan.___", state 277, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 277, "else"
+ line 430, "pan.___", state 280, "(1)"
+ line 430, "pan.___", state 281, "(1)"
+ line 430, "pan.___", state 281, "(1)"
+ line 434, "pan.___", state 289, "(1)"
+ line 434, "pan.___", state 290, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 290, "else"
+ line 434, "pan.___", state 293, "(1)"
+ line 434, "pan.___", state 294, "(1)"
+ line 434, "pan.___", state 294, "(1)"
+ line 432, "pan.___", state 299, "((i<1))"
+ line 432, "pan.___", state 299, "((i>=1))"
+ line 439, "pan.___", state 306, "(1)"
+ line 439, "pan.___", state 307, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 307, "else"
+ line 439, "pan.___", state 310, "(1)"
+ line 439, "pan.___", state 311, "(1)"
+ line 439, "pan.___", state 311, "(1)"
+ line 443, "pan.___", state 319, "(1)"
+ line 443, "pan.___", state 320, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 320, "else"
+ line 443, "pan.___", state 323, "(1)"
+ line 443, "pan.___", state 324, "(1)"
+ line 443, "pan.___", state 324, "(1)"
+ line 441, "pan.___", state 329, "((i<2))"
+ line 441, "pan.___", state 329, "((i>=2))"
+ line 451, "pan.___", state 333, "(1)"
+ line 451, "pan.___", state 333, "(1)"
+ line 412, "pan.___", state 344, "(1)"
+ line 412, "pan.___", state 345, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 345, "else"
+ line 412, "pan.___", state 348, "(1)"
+ line 416, "pan.___", state 356, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 362, "(1)"
+ line 416, "pan.___", state 363, "(1)"
+ line 416, "pan.___", state 363, "(1)"
+ line 414, "pan.___", state 368, "((i<1))"
+ line 414, "pan.___", state 368, "((i>=1))"
+ line 421, "pan.___", state 374, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 380, "(1)"
+ line 421, "pan.___", state 381, "(1)"
+ line 421, "pan.___", state 381, "(1)"
+ line 425, "pan.___", state 388, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 394, "(1)"
+ line 425, "pan.___", state 395, "(1)"
+ line 425, "pan.___", state 395, "(1)"
+ line 423, "pan.___", state 400, "((i<2))"
+ line 423, "pan.___", state 400, "((i>=2))"
+ line 430, "pan.___", state 407, "(1)"
+ line 430, "pan.___", state 408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 408, "else"
+ line 430, "pan.___", state 411, "(1)"
+ line 430, "pan.___", state 412, "(1)"
+ line 430, "pan.___", state 412, "(1)"
+ line 434, "pan.___", state 420, "(1)"
+ line 434, "pan.___", state 421, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 421, "else"
+ line 434, "pan.___", state 424, "(1)"
+ line 434, "pan.___", state 425, "(1)"
+ line 434, "pan.___", state 425, "(1)"
+ line 432, "pan.___", state 430, "((i<1))"
+ line 432, "pan.___", state 430, "((i>=1))"
+ line 439, "pan.___", state 437, "(1)"
+ line 439, "pan.___", state 438, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 438, "else"
+ line 439, "pan.___", state 441, "(1)"
+ line 439, "pan.___", state 442, "(1)"
+ line 439, "pan.___", state 442, "(1)"
+ line 443, "pan.___", state 450, "(1)"
+ line 443, "pan.___", state 451, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 451, "else"
+ line 443, "pan.___", state 454, "(1)"
+ line 443, "pan.___", state 455, "(1)"
+ line 443, "pan.___", state 455, "(1)"
+ line 441, "pan.___", state 460, "((i<2))"
+ line 441, "pan.___", state 460, "((i>=2))"
+ line 451, "pan.___", state 464, "(1)"
+ line 451, "pan.___", state 464, "(1)"
+ line 412, "pan.___", state 477, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 479, "(1)"
+ line 412, "pan.___", state 480, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 480, "else"
+ line 412, "pan.___", state 483, "(1)"
+ line 416, "pan.___", state 491, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 493, "(1)"
+ line 416, "pan.___", state 494, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 494, "else"
+ line 416, "pan.___", state 497, "(1)"
+ line 416, "pan.___", state 498, "(1)"
+ line 416, "pan.___", state 498, "(1)"
+ line 414, "pan.___", state 503, "((i<1))"
+ line 414, "pan.___", state 503, "((i>=1))"
+ line 421, "pan.___", state 509, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 511, "(1)"
+ line 421, "pan.___", state 512, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 512, "else"
+ line 421, "pan.___", state 515, "(1)"
+ line 421, "pan.___", state 516, "(1)"
+ line 421, "pan.___", state 516, "(1)"
+ line 425, "pan.___", state 523, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 525, "(1)"
+ line 425, "pan.___", state 526, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 526, "else"
+ line 425, "pan.___", state 529, "(1)"
+ line 425, "pan.___", state 530, "(1)"
+ line 425, "pan.___", state 530, "(1)"
+ line 423, "pan.___", state 535, "((i<2))"
+ line 423, "pan.___", state 535, "((i>=2))"
+ line 430, "pan.___", state 542, "(1)"
+ line 430, "pan.___", state 543, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 543, "else"
+ line 430, "pan.___", state 546, "(1)"
+ line 430, "pan.___", state 547, "(1)"
+ line 430, "pan.___", state 547, "(1)"
+ line 434, "pan.___", state 555, "(1)"
+ line 434, "pan.___", state 556, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 556, "else"
+ line 434, "pan.___", state 559, "(1)"
+ line 434, "pan.___", state 560, "(1)"
+ line 434, "pan.___", state 560, "(1)"
+ line 432, "pan.___", state 565, "((i<1))"
+ line 432, "pan.___", state 565, "((i>=1))"
+ line 439, "pan.___", state 572, "(1)"
+ line 439, "pan.___", state 573, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 573, "else"
+ line 439, "pan.___", state 576, "(1)"
+ line 439, "pan.___", state 577, "(1)"
+ line 439, "pan.___", state 577, "(1)"
+ line 443, "pan.___", state 585, "(1)"
+ line 443, "pan.___", state 586, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 586, "else"
+ line 443, "pan.___", state 589, "(1)"
+ line 443, "pan.___", state 590, "(1)"
+ line 443, "pan.___", state 590, "(1)"
+ line 451, "pan.___", state 599, "(1)"
+ line 451, "pan.___", state 599, "(1)"
+ line 412, "pan.___", state 605, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 611, "(1)"
+ line 416, "pan.___", state 619, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 625, "(1)"
+ line 416, "pan.___", state 626, "(1)"
+ line 416, "pan.___", state 626, "(1)"
+ line 414, "pan.___", state 631, "((i<1))"
+ line 414, "pan.___", state 631, "((i>=1))"
+ line 421, "pan.___", state 637, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 643, "(1)"
+ line 421, "pan.___", state 644, "(1)"
+ line 421, "pan.___", state 644, "(1)"
+ line 425, "pan.___", state 651, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 657, "(1)"
+ line 425, "pan.___", state 658, "(1)"
+ line 425, "pan.___", state 658, "(1)"
+ line 423, "pan.___", state 663, "((i<2))"
+ line 423, "pan.___", state 663, "((i>=2))"
+ line 430, "pan.___", state 670, "(1)"
+ line 430, "pan.___", state 671, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 671, "else"
+ line 430, "pan.___", state 674, "(1)"
+ line 430, "pan.___", state 675, "(1)"
+ line 430, "pan.___", state 675, "(1)"
+ line 434, "pan.___", state 683, "(1)"
+ line 434, "pan.___", state 684, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 684, "else"
+ line 434, "pan.___", state 687, "(1)"
+ line 434, "pan.___", state 688, "(1)"
+ line 434, "pan.___", state 688, "(1)"
+ line 432, "pan.___", state 693, "((i<1))"
+ line 432, "pan.___", state 693, "((i>=1))"
+ line 439, "pan.___", state 700, "(1)"
+ line 439, "pan.___", state 701, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 701, "else"
+ line 439, "pan.___", state 704, "(1)"
+ line 439, "pan.___", state 705, "(1)"
+ line 439, "pan.___", state 705, "(1)"
+ line 443, "pan.___", state 713, "(1)"
+ line 443, "pan.___", state 714, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 714, "else"
+ line 443, "pan.___", state 717, "(1)"
+ line 443, "pan.___", state 718, "(1)"
+ line 443, "pan.___", state 718, "(1)"
+ line 451, "pan.___", state 727, "(1)"
+ line 451, "pan.___", state 727, "(1)"
+ line 412, "pan.___", state 734, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 740, "(1)"
+ line 416, "pan.___", state 748, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 754, "(1)"
+ line 416, "pan.___", state 755, "(1)"
+ line 416, "pan.___", state 755, "(1)"
+ line 414, "pan.___", state 760, "((i<1))"
+ line 414, "pan.___", state 760, "((i>=1))"
+ line 421, "pan.___", state 766, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 772, "(1)"
+ line 421, "pan.___", state 773, "(1)"
+ line 421, "pan.___", state 773, "(1)"
+ line 425, "pan.___", state 780, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 786, "(1)"
+ line 425, "pan.___", state 787, "(1)"
+ line 425, "pan.___", state 787, "(1)"
+ line 423, "pan.___", state 792, "((i<2))"
+ line 423, "pan.___", state 792, "((i>=2))"
+ line 430, "pan.___", state 799, "(1)"
+ line 430, "pan.___", state 800, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 430, "pan.___", state 800, "else"
+ line 430, "pan.___", state 803, "(1)"
+ line 430, "pan.___", state 804, "(1)"
+ line 430, "pan.___", state 804, "(1)"
+ line 434, "pan.___", state 812, "(1)"
+ line 434, "pan.___", state 813, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 434, "pan.___", state 813, "else"
+ line 434, "pan.___", state 816, "(1)"
+ line 434, "pan.___", state 817, "(1)"
+ line 434, "pan.___", state 817, "(1)"
+ line 432, "pan.___", state 822, "((i<1))"
+ line 432, "pan.___", state 822, "((i>=1))"
+ line 439, "pan.___", state 829, "(1)"
+ line 439, "pan.___", state 830, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 439, "pan.___", state 830, "else"
+ line 439, "pan.___", state 833, "(1)"
+ line 439, "pan.___", state 834, "(1)"
+ line 439, "pan.___", state 834, "(1)"
+ line 443, "pan.___", state 842, "(1)"
+ line 443, "pan.___", state 843, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 443, "pan.___", state 843, "else"
+ line 443, "pan.___", state 846, "(1)"
+ line 443, "pan.___", state 847, "(1)"
+ line 443, "pan.___", state 847, "(1)"
+ line 441, "pan.___", state 852, "((i<2))"
+ line 441, "pan.___", state 852, "((i>=2))"
+ line 451, "pan.___", state 856, "(1)"
+ line 451, "pan.___", state 856, "(1)"
+ line 416, "pan.___", state 879, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 897, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 911, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 434, "pan.___", state 943, "(1)"
+ line 439, "pan.___", state 960, "(1)"
+ line 443, "pan.___", state 973, "(1)"
+ line 412, "pan.___", state 999, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1013, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1031, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1045, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 430, "pan.___", state 1064, "(1)"
+ line 434, "pan.___", state 1077, "(1)"
+ line 439, "pan.___", state 1094, "(1)"
+ line 443, "pan.___", state 1107, "(1)"
+ line 273, "pan.___", state 1153, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 1162, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 1170, "((i<1))"
+ line 275, "pan.___", state 1170, "((i>=1))"
+ line 281, "pan.___", state 1177, "(1)"
+ line 281, "pan.___", state 1178, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 281, "pan.___", state 1178, "else"
+ line 285, "pan.___", state 1184, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1192, "((i<2))"
+ line 283, "pan.___", state 1192, "((i>=2))"
+ line 250, "pan.___", state 1200, "(1)"
+ line 254, "pan.___", state 1208, "(1)"
+ line 254, "pan.___", state 1209, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 1209, "else"
+ line 252, "pan.___", state 1214, "((i<1))"
+ line 252, "pan.___", state 1214, "((i>=1))"
+ line 258, "pan.___", state 1220, "(1)"
+ line 258, "pan.___", state 1221, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 1221, "else"
+ line 262, "pan.___", state 1228, "(1)"
+ line 262, "pan.___", state 1229, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 1229, "else"
+ line 267, "pan.___", state 1238, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 1238, "else"
+ line 277, "pan.___", state 1253, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 1266, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 1275, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1291, "(1)"
+ line 254, "pan.___", state 1299, "(1)"
+ line 258, "pan.___", state 1311, "(1)"
+ line 262, "pan.___", state 1319, "(1)"
+ line 1238, "pan.___", state 1334, "-end-"
+ (242 of 1334 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1303, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 88.5 seconds
+pan: rate 1954.1954 states/second
+pan: avg transition delay 1.2701e-06 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-alpha-no-ipi'
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+#define ARCH_ALPHA
+//#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64 -DCOLLAPSE
+#CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ #make urcu_free | tee urcu_free.log
+ #make urcu_free_no_mb | tee urcu_free_no_mb.log
+ #make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ #make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ #make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ #make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1294)
+Depth= 9223 States= 1e+06 Transitions= 6.87e+06 Memory= 516.350 t= 19.4 R= 5e+04
+Depth= 9223 States= 2e+06 Transitions= 1.47e+07 Memory= 563.713 t= 43.1 R= 5e+04
+Depth= 9223 States= 3e+06 Transitions= 2.46e+07 Memory= 613.127 t= 73.9 R= 4e+04
+pan: resizing hashtable to -w22.. done
+Depth= 9223 States= 4e+06 Transitions= 3.19e+07 Memory= 690.440 t= 95.5 R= 4e+04
+Depth= 9223 States= 5e+06 Transitions= 3.95e+07 Memory= 736.533 t= 118 R= 4e+04
+Depth= 9223 States= 6e+06 Transitions= 5.71e+07 Memory= 785.068 t= 174 R= 3e+04
+Depth= 9223 States= 7e+06 Transitions= 6.81e+07 Memory= 834.580 t= 209 R= 3e+04
+Depth= 9223 States= 8e+06 Transitions= 8.22e+07 Memory= 883.311 t= 254 R= 3e+04
+Depth= 9223 States= 9e+06 Transitions= 9.54e+07 Memory= 932.139 t= 296 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 9223 States= 1e+07 Transitions= 1.08e+08 Memory= 1104.670 t= 338 R= 3e+04
+Depth= 9223 States= 1.1e+07 Transitions= 1.21e+08 Memory= 1155.451 t= 375 R= 3e+04
+Depth= 9223 States= 1.2e+07 Transitions= 1.3e+08 Memory= 1205.744 t= 403 R= 3e+04
+Depth= 9223 States= 1.3e+07 Transitions= 1.42e+08 Memory= 1254.572 t= 442 R= 3e+04
+Depth= 9223 States= 1.4e+07 Transitions= 1.72e+08 Memory= 1302.717 t= 539 R= 3e+04
+Depth= 9223 States= 1.5e+07 Transitions= 1.91e+08 Memory= 1354.768 t= 600 R= 3e+04
+Depth= 9223 States= 1.6e+07 Transitions= 2.08e+08 Memory= 1405.842 t= 653 R= 2e+04
+Depth= 9223 States= 1.7e+07 Transitions= 2.2e+08 Memory= 1456.818 t= 691 R= 2e+04
+Depth= 9223 States= 1.8e+07 Transitions= 2.39e+08 Memory= 1506.135 t= 751 R= 2e+04
+Depth= 9223 States= 1.9e+07 Transitions= 2.55e+08 Memory= 1556.330 t= 801 R= 2e+04
+Depth= 9223 States= 2e+07 Transitions= 2.72e+08 Memory= 1604.084 t= 856 R= 2e+04
+Depth= 9285 States= 2.1e+07 Transitions= 2.85e+08 Memory= 1650.080 t= 898 R= 2e+04
+Depth= 9324 States= 2.2e+07 Transitions= 2.99e+08 Memory= 1696.760 t= 941 R= 2e+04
+Depth= 9324 States= 2.3e+07 Transitions= 3.1e+08 Memory= 1746.369 t= 976 R= 2e+04
+Depth= 9324 States= 2.4e+07 Transitions= 3.21e+08 Memory= 1792.561 t= 1.01e+03 R= 2e+04
+Depth= 9324 States= 2.5e+07 Transitions= 3.34e+08 Memory= 1841.096 t= 1.05e+03 R= 2e+04
+Depth= 9324 States= 2.6e+07 Transitions= 3.45e+08 Memory= 1890.998 t= 1.09e+03 R= 2e+04
+Depth= 9324 States= 2.7e+07 Transitions= 3.59e+08 Memory= 1940.412 t= 1.13e+03 R= 2e+04
+Depth= 9324 States= 2.8e+07 Transitions= 3.71e+08 Memory= 1987.776 t= 1.17e+03 R= 2e+04
+Depth= 9324 States= 2.9e+07 Transitions= 3.84e+08 Memory= 2034.846 t= 1.21e+03 R= 2e+04
+Depth= 9324 States= 3e+07 Transitions= 3.96e+08 Memory= 2081.233 t= 1.25e+03 R= 2e+04
+Depth= 9324 States= 3.1e+07 Transitions= 4.09e+08 Memory= 2129.865 t= 1.29e+03 R= 2e+04
+Depth= 9324 States= 3.2e+07 Transitions= 4.19e+08 Memory= 2179.670 t= 1.32e+03 R= 2e+04
+Depth= 9324 States= 3.3e+07 Transitions= 4.3e+08 Memory= 2227.717 t= 1.36e+03 R= 2e+04
+Depth= 9324 States= 3.4e+07 Transitions= 4.44e+08 Memory= 2277.033 t= 1.4e+03 R= 2e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9324 States= 3.5e+07 Transitions= 4.6e+08 Memory= 2824.190 t= 1.46e+03 R= 2e+04
--- /dev/null
+[] (!read_poison)
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+#define NO_RMB
--- /dev/null
+#define NO_WMB
--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+depth 7: Claim reached state 9 (line 1367)
+depth 131: Claim reached state 9 (line 1366)
+Depth= 108226 States= 1e+06 Transitions= 1.1e+07 Memory= 495.354 t= 32.5 R= 3e+04
+Depth= 108226 States= 2e+06 Transitions= 2.2e+07 Memory= 526.018 t= 65.8 R= 3e+04
+Depth= 108226 States= 3e+06 Transitions= 3.31e+07 Memory= 555.510 t= 99.5 R= 3e+04
+pan: resizing hashtable to -w22.. done
+Depth= 108226 States= 4e+06 Transitions= 4.38e+07 Memory= 615.733 t= 132 R= 3e+04
+Depth= 108226 States= 5e+06 Transitions= 5.47e+07 Memory= 644.346 t= 164 R= 3e+04
+Depth= 108226 States= 6e+06 Transitions= 6.54e+07 Memory= 671.983 t= 197 R= 3e+04
+Depth= 108226 States= 7e+06 Transitions= 7.64e+07 Memory= 700.108 t= 230 R= 3e+04
+Depth= 110273 States= 8e+06 Transitions= 8.89e+07 Memory= 728.428 t= 268 R= 3e+04
+Depth= 110273 States= 9e+06 Transitions= 1.02e+08 Memory= 757.920 t= 310 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 110273 States= 1e+07 Transitions= 1.14e+08 Memory= 911.408 t= 347 R= 3e+04
+Depth= 110273 States= 1.1e+07 Transitions= 1.26e+08 Memory= 939.924 t= 380 R= 3e+04
+Depth= 110273 States= 1.2e+07 Transitions= 1.37e+08 Memory= 968.440 t= 414 R= 3e+04
+Depth= 110273 States= 1.3e+07 Transitions= 1.58e+08 Memory= 996.272 t= 479 R= 3e+04
+Depth= 110273 States= 1.4e+07 Transitions= 1.69e+08 Memory= 1026.545 t= 513 R= 3e+04
+Depth= 110273 States= 1.5e+07 Transitions= 1.81e+08 Memory= 1055.451 t= 550 R= 3e+04
+Depth= 110273 States= 1.6e+07 Transitions= 1.92e+08 Memory= 1084.943 t= 583 R= 3e+04
+Depth= 110273 States= 1.7e+07 Transitions= 2.03e+08 Memory= 1114.045 t= 615 R= 3e+04
+Depth= 110273 States= 1.8e+07 Transitions= 2.14e+08 Memory= 1144.318 t= 647 R= 3e+04
+Depth= 110273 States= 1.9e+07 Transitions= 2.25e+08 Memory= 1173.420 t= 680 R= 3e+04
+Depth= 110273 States= 2e+07 Transitions= 2.36e+08 Memory= 1202.717 t= 713 R= 3e+04
+Depth= 110273 States= 2.1e+07 Transitions= 2.47e+08 Memory= 1232.404 t= 746 R= 3e+04
+Depth= 110273 States= 2.2e+07 Transitions= 2.58e+08 Memory= 1262.092 t= 778 R= 3e+04
+Depth= 110273 States= 2.3e+07 Transitions= 2.69e+08 Memory= 1290.119 t= 811 R= 3e+04
+Depth= 110273 States= 2.4e+07 Transitions= 2.82e+08 Memory= 1317.268 t= 851 R= 3e+04
+Depth= 110273 States= 2.5e+07 Transitions= 2.96e+08 Memory= 1345.783 t= 893 R= 3e+04
+Depth= 110273 States= 2.6e+07 Transitions= 3.13e+08 Memory= 1373.615 t= 948 R= 3e+04
+Depth= 110273 States= 2.7e+07 Transitions= 3.48e+08 Memory= 1403.889 t= 1.06e+03 R= 3e+04
+Depth= 110273 States= 2.8e+07 Transitions= 3.7e+08 Memory= 1434.651 t= 1.13e+03 R= 2e+04
+Depth= 110273 States= 2.9e+07 Transitions= 3.84e+08 Memory= 1464.338 t= 1.17e+03 R= 2e+04
+Depth= 110273 States= 3e+07 Transitions= 4.04e+08 Memory= 1492.365 t= 1.24e+03 R= 2e+04
+Depth= 110273 States= 3.1e+07 Transitions= 4.26e+08 Memory= 1520.490 t= 1.31e+03 R= 2e+04
+Depth= 110273 States= 3.2e+07 Transitions= 4.42e+08 Memory= 1550.080 t= 1.36e+03 R= 2e+04
+Depth= 110273 States= 3.3e+07 Transitions= 4.63e+08 Memory= 1578.791 t= 1.42e+03 R= 2e+04
+Depth= 110273 States= 3.4e+07 Transitions= 4.87e+08 Memory= 1605.842 t= 1.5e+03 R= 2e+04
+pan: resizing hashtable to -w26.. done
+Depth= 110273 States= 3.5e+07 Transitions= 5.01e+08 Memory= 2130.147 t= 1.55e+03 R= 2e+04
+Depth= 110273 States= 3.6e+07 Transitions= 5.22e+08 Memory= 2158.467 t= 1.61e+03 R= 2e+04
+Depth= 110273 States= 3.7e+07 Transitions= 5.4e+08 Memory= 2186.006 t= 1.67e+03 R= 2e+04
+Depth= 110273 States= 3.8e+07 Transitions= 5.61e+08 Memory= 2213.545 t= 1.74e+03 R= 2e+04
+Depth= 110273 States= 3.9e+07 Transitions= 5.82e+08 Memory= 2242.061 t= 1.82e+03 R= 2e+04
+Depth= 110273 States= 4e+07 Transitions= 6e+08 Memory= 2270.088 t= 1.87e+03 R= 2e+04
+Depth= 110273 States= 4.1e+07 Transitions= 6.18e+08 Memory= 2298.408 t= 1.93e+03 R= 2e+04
+Depth= 110273 States= 4.2e+07 Transitions= 6.37e+08 Memory= 2325.850 t= 1.99e+03 R= 2e+04
+Depth= 110273 States= 4.3e+07 Transitions= 6.65e+08 Memory= 2352.803 t= 2.08e+03 R= 2e+04
+Depth= 110273 States= 4.4e+07 Transitions= 6.82e+08 Memory= 2380.733 t= 2.13e+03 R= 2e+04
+Depth= 110273 States= 4.5e+07 Transitions= 6.99e+08 Memory= 2408.076 t= 2.18e+03 R= 2e+04
+Depth= 110273 States= 4.6e+07 Transitions= 7.12e+08 Memory= 2434.346 t= 2.23e+03 R= 2e+04
+Depth= 110273 States= 4.7e+07 Transitions= 7.26e+08 Memory= 2462.959 t= 2.27e+03 R= 2e+04
+Depth= 110273 States= 4.8e+07 Transitions= 7.4e+08 Memory= 2493.721 t= 2.31e+03 R= 2e+04
+Depth= 110273 States= 4.9e+07 Transitions= 7.53e+08 Memory= 2522.627 t= 2.35e+03 R= 2e+04
+Depth= 110273 States= 5e+07 Transitions= 7.66e+08 Memory= 2552.803 t= 2.39e+03 R= 2e+04
+Depth= 110273 States= 5.1e+07 Transitions= 7.77e+08 Memory= 2583.565 t= 2.42e+03 R= 2e+04
+Depth= 110273 States= 5.2e+07 Transitions= 7.9e+08 Memory= 2611.006 t= 2.46e+03 R= 2e+04
+Depth= 110273 States= 5.3e+07 Transitions= 8.16e+08 Memory= 2641.182 t= 2.54e+03 R= 2e+04
+Depth= 110273 States= 5.4e+07 Transitions= 8.52e+08 Memory= 2673.213 t= 2.66e+03 R= 2e+04
+Depth= 110273 States= 5.5e+07 Transitions= 8.93e+08 Memory= 2707.197 t= 2.79e+03 R= 2e+04
+Depth= 110273 States= 5.6e+07 Transitions= 9.4e+08 Memory= 2738.447 t= 2.94e+03 R= 2e+04
+Depth= 110273 States= 5.7e+07 Transitions= 9.81e+08 Memory= 2767.354 t= 3.08e+03 R= 2e+04
+Depth= 110273 States= 5.8e+07 Transitions= 1.01e+09 Memory= 2794.111 t= 3.16e+03 R= 2e+04
+Depth= 110273 States= 5.9e+07 Transitions= 1.02e+09 Memory= 2822.529 t= 3.21e+03 R= 2e+04
+Depth= 110273 States= 6e+07 Transitions= 1.05e+09 Memory= 2850.654 t= 3.28e+03 R= 2e+04
+Depth= 110273 States= 6.1e+07 Transitions= 1.08e+09 Memory= 2879.170 t= 3.39e+03 R= 2e+04
+Depth= 110273 States= 6.2e+07 Transitions= 1.1e+09 Memory= 2908.858 t= 3.44e+03 R= 2e+04
+Depth= 110273 States= 6.3e+07 Transitions= 1.11e+09 Memory= 2935.908 t= 3.49e+03 R= 2e+04
+Depth= 110273 States= 6.4e+07 Transitions= 1.13e+09 Memory= 2960.518 t= 3.54e+03 R= 2e+04
+Depth= 110273 States= 6.5e+07 Transitions= 1.14e+09 Memory= 2990.205 t= 3.58e+03 R= 2e+04
+Depth= 110273 States= 6.6e+07 Transitions= 1.17e+09 Memory= 3018.721 t= 3.67e+03 R= 2e+04
+Depth= 110273 States= 6.7e+07 Transitions= 1.18e+09 Memory= 3047.041 t= 3.71e+03 R= 2e+04
+Depth= 110273 States= 6.8e+07 Transitions= 1.21e+09 Memory= 3074.580 t= 3.79e+03 R= 2e+04
+Depth= 110273 States= 6.9e+07 Transitions= 1.23e+09 Memory= 3101.826 t= 3.87e+03 R= 2e+04
+Depth= 110273 States= 7e+07 Transitions= 1.27e+09 Memory= 3130.635 t= 3.98e+03 R= 2e+04
+Depth= 110273 States= 7.1e+07 Transitions= 1.29e+09 Memory= 3157.197 t= 4.06e+03 R= 2e+04
+Depth= 110273 States= 7.2e+07 Transitions= 1.32e+09 Memory= 3184.443 t= 4.16e+03 R= 2e+04
+Depth= 110273 States= 7.3e+07 Transitions= 1.34e+09 Memory= 3211.690 t= 4.24e+03 R= 2e+04
+Depth= 110273 States= 7.4e+07 Transitions= 1.37e+09 Memory= 3239.229 t= 4.32e+03 R= 2e+04
+Depth= 110273 States= 7.5e+07 Transitions= 1.38e+09 Memory= 3266.670 t= 4.38e+03 R= 2e+04
+Depth= 110273 States= 7.6e+07 Transitions= 1.41e+09 Memory= 3294.307 t= 4.46e+03 R= 2e+04
+Depth= 110273 States= 7.7e+07 Transitions= 1.44e+09 Memory= 3322.432 t= 4.55e+03 R= 2e+04
+Depth= 110273 States= 7.8e+07 Transitions= 1.46e+09 Memory= 3352.608 t= 4.62e+03 R= 2e+04
+Depth= 110273 States= 7.9e+07 Transitions= 1.47e+09 Memory= 3378.193 t= 4.66e+03 R= 2e+04
+Depth= 110273 States= 8e+07 Transitions= 1.49e+09 Memory= 3407.490 t= 4.71e+03 R= 2e+04
+Depth= 110273 States= 8.1e+07 Transitions= 1.52e+09 Memory= 3436.397 t= 4.8e+03 R= 2e+04
+Depth= 110273 States= 8.2e+07 Transitions= 1.53e+09 Memory= 3461.690 t= 4.84e+03 R= 2e+04
+Depth= 110273 States= 8.3e+07 Transitions= 1.56e+09 Memory= 3491.182 t= 4.92e+03 R= 2e+04
+Depth= 110273 States= 8.4e+07 Transitions= 1.57e+09 Memory= 3519.990 t= 4.98e+03 R= 2e+04
+Depth= 110273 States= 8.5e+07 Transitions= 1.59e+09 Memory= 3546.065 t= 5.02e+03 R= 2e+04
+Depth= 110273 States= 8.6e+07 Transitions= 1.6e+09 Memory= 3575.459 t= 5.07e+03 R= 2e+04
+Depth= 110273 States= 8.7e+07 Transitions= 1.63e+09 Memory= 3605.049 t= 5.14e+03 R= 2e+04
+Depth= 110273 States= 8.8e+07 Transitions= 1.64e+09 Memory= 3632.588 t= 5.2e+03 R= 2e+04
+Depth= 110273 States= 8.9e+07 Transitions= 1.66e+09 Memory= 3661.787 t= 5.26e+03 R= 2e+04
+Depth= 110273 States= 9e+07 Transitions= 1.68e+09 Memory= 3688.154 t= 5.3e+03 R= 2e+04
+Depth= 110273 States= 9.1e+07 Transitions= 1.7e+09 Memory= 3715.986 t= 5.36e+03 R= 2e+04
+Depth= 110273 States= 9.2e+07 Transitions= 1.71e+09 Memory= 3743.623 t= 5.41e+03 R= 2e+04
+Depth= 110273 States= 9.3e+07 Transitions= 1.73e+09 Memory= 3771.358 t= 5.46e+03 R= 2e+04
+Depth= 110273 States= 9.4e+07 Transitions= 1.75e+09 Memory= 3797.920 t= 5.53e+03 R= 2e+04
+Depth= 110273 States= 9.5e+07 Transitions= 1.77e+09 Memory= 3827.119 t= 5.6e+03 R= 2e+04
+Depth= 110273 States= 9.6e+07 Transitions= 1.79e+09 Memory= 3858.858 t= 5.64e+03 R= 2e+04
+Depth= 110273 States= 9.7e+07 Transitions= 1.8e+09 Memory= 3885.713 t= 5.7e+03 R= 2e+04
+Depth= 110273 States= 9.8e+07 Transitions= 1.82e+09 Memory= 3914.717 t= 5.75e+03 R= 2e+04
+Depth= 110273 States= 9.9e+07 Transitions= 1.84e+09 Memory= 3941.670 t= 5.81e+03 R= 2e+04
+Depth= 110273 States= 1e+08 Transitions= 1.86e+09 Memory= 3968.818 t= 5.87e+03 R= 2e+04
+Depth= 110273 States= 1.01e+08 Transitions= 1.88e+09 Memory= 3994.990 t= 5.94e+03 R= 2e+04
+Depth= 110273 States= 1.02e+08 Transitions= 1.9e+09 Memory= 4023.311 t= 6.01e+03 R= 2e+04
+Depth= 110273 States= 1.03e+08 Transitions= 1.92e+09 Memory= 4053.193 t= 6.08e+03 R= 2e+04
+Depth= 110273 States= 1.04e+08 Transitions= 1.94e+09 Memory= 4078.389 t= 6.12e+03 R= 2e+04
+Depth= 110273 States= 1.05e+08 Transitions= 1.96e+09 Memory= 4108.467 t= 6.2e+03 R= 2e+04
+Depth= 110273 States= 1.06e+08 Transitions= 1.98e+09 Memory= 4137.080 t= 6.25e+03 R= 2e+04
+Depth= 110273 States= 1.07e+08 Transitions= 1.99e+09 Memory= 4163.740 t= 6.29e+03 R= 2e+04
+Depth= 110273 States= 1.08e+08 Transitions= 2.01e+09 Memory= 4191.768 t= 6.35e+03 R= 2e+04
+Depth= 110273 States= 1.09e+08 Transitions= 2.03e+09 Memory= 4221.651 t= 6.4e+03 R= 2e+04
+Depth= 110273 States= 1.1e+08 Transitions= 2.04e+09 Memory= 4249.971 t= 6.45e+03 R= 2e+04
+Depth= 110273 States= 1.11e+08 Transitions= 2.07e+09 Memory= 4278.877 t= 6.52e+03 R= 2e+04
+Depth= 110273 States= 1.12e+08 Transitions= 2.09e+09 Memory= 4308.174 t= 6.59e+03 R= 2e+04
+Depth= 110273 States= 1.13e+08 Transitions= 2.1e+09 Memory= 4333.760 t= 6.64e+03 R= 2e+04
+Depth= 110273 States= 1.14e+08 Transitions= 2.13e+09 Memory= 4363.740 t= 6.71e+03 R= 2e+04
+Depth= 110273 States= 1.15e+08 Transitions= 2.14e+09 Memory= 4392.158 t= 6.76e+03 R= 2e+04
+Depth= 110273 States= 1.16e+08 Transitions= 2.16e+09 Memory= 4419.014 t= 6.81e+03 R= 2e+04
+Depth= 110273 States= 1.17e+08 Transitions= 2.17e+09 Memory= 4446.846 t= 6.86e+03 R= 2e+04
+Depth= 110273 States= 1.18e+08 Transitions= 2.19e+09 Memory= 4476.338 t= 6.91e+03 R= 2e+04
+Depth= 110273 States= 1.19e+08 Transitions= 2.21e+09 Memory= 4505.440 t= 6.96e+03 R= 2e+04
+Depth= 110273 States= 1.2e+08 Transitions= 2.22e+09 Memory= 4529.561 t= 7.01e+03 R= 2e+04
+Depth= 110273 States= 1.21e+08 Transitions= 2.24e+09 Memory= 4557.588 t= 7.07e+03 R= 2e+04
+Depth= 110273 States= 1.22e+08 Transitions= 2.26e+09 Memory= 4584.736 t= 7.12e+03 R= 2e+04
+Depth= 110273 States= 1.23e+08 Transitions= 2.27e+09 Memory= 4612.764 t= 7.18e+03 R= 2e+04
+Depth= 110273 States= 1.24e+08 Transitions= 2.29e+09 Memory= 4640.303 t= 7.22e+03 R= 2e+04
+Depth= 110273 States= 1.25e+08 Transitions= 2.32e+09 Memory= 4669.404 t= 7.32e+03 R= 2e+04
+Depth= 110273 States= 1.26e+08 Transitions= 2.35e+09 Memory= 4698.018 t= 7.44e+03 R= 2e+04
+Depth= 110273 States= 1.27e+08 Transitions= 2.37e+09 Memory= 4728.877 t= 7.49e+03 R= 2e+04
+Depth= 110273 States= 1.28e+08 Transitions= 2.38e+09 Memory= 4757.393 t= 7.54e+03 R= 2e+04
+Depth= 110273 States= 1.29e+08 Transitions= 2.4e+09 Memory= 4785.811 t= 7.6e+03 R= 2e+04
+Depth= 110273 States= 1.3e+08 Transitions= 2.42e+09 Memory= 4814.033 t= 7.66e+03 R= 2e+04
+Depth= 110273 States= 1.31e+08 Transitions= 2.44e+09 Memory= 4843.428 t= 7.72e+03 R= 2e+04
+Depth= 110273 States= 1.32e+08 Transitions= 2.46e+09 Memory= 4871.943 t= 7.78e+03 R= 2e+04
+Depth= 110273 States= 1.33e+08 Transitions= 2.49e+09 Memory= 4898.311 t= 7.88e+03 R= 2e+04
+Depth= 110273 States= 1.34e+08 Transitions= 2.51e+09 Memory= 4926.143 t= 7.95e+03 R= 2e+04
+Depth= 110273 States= 1.35e+08 Transitions= 2.54e+09 Memory= 4953.389 t= 8.02e+03 R= 2e+04
+pan: resizing hashtable to -w28.. done
+Depth= 110273 States= 1.36e+08 Transitions= 2.56e+09 Memory= 7001.389 t= 8.13e+03 R= 2e+04
+Depth= 110273 States= 1.37e+08 Transitions= 2.58e+09 Memory= 7001.389 t= 8.19e+03 R= 2e+04
+Depth= 110273 States= 1.38e+08 Transitions= 2.61e+09 Memory= 7018.381 t= 8.26e+03 R= 2e+04
+Depth= 110273 States= 1.39e+08 Transitions= 2.63e+09 Memory= 7045.236 t= 8.33e+03 R= 2e+04
+Depth= 110273 States= 1.4e+08 Transitions= 2.65e+09 Memory= 7073.068 t= 8.39e+03 R= 2e+04
+Depth= 110273 States= 1.41e+08 Transitions= 2.68e+09 Memory= 7100.022 t= 8.48e+03 R= 2e+04
+Depth= 110273 States= 1.42e+08 Transitions= 2.7e+09 Memory= 7128.733 t= 8.54e+03 R= 2e+04
+Depth= 110273 States= 1.43e+08 Transitions= 2.72e+09 Memory= 7155.686 t= 8.6e+03 R= 2e+04
+Depth= 110273 States= 1.44e+08 Transitions= 2.73e+09 Memory= 7181.662 t= 8.65e+03 R= 2e+04
+Depth= 110273 States= 1.45e+08 Transitions= 2.74e+09 Memory= 7209.885 t= 8.69e+03 R= 2e+04
+Depth= 110273 States= 1.46e+08 Transitions= 2.76e+09 Memory= 7239.963 t= 8.73e+03 R= 2e+04
+Depth= 110273 States= 1.47e+08 Transitions= 2.77e+09 Memory= 7269.846 t= 8.77e+03 R= 2e+04
+Depth= 110273 States= 1.48e+08 Transitions= 2.79e+09 Memory= 7299.533 t= 8.82e+03 R= 2e+04
+Depth= 110273 States= 1.49e+08 Transitions= 2.8e+09 Memory= 7327.365 t= 8.87e+03 R= 2e+04
+Depth= 110273 States= 1.5e+08 Transitions= 2.82e+09 Memory= 7356.760 t= 8.92e+03 R= 2e+04
+Depth= 110273 States= 1.51e+08 Transitions= 2.84e+09 Memory= 7384.983 t= 8.97e+03 R= 2e+04
+Depth= 110273 States= 1.52e+08 Transitions= 2.85e+09 Memory= 7412.522 t= 9.02e+03 R= 2e+04
+Depth= 110273 States= 1.53e+08 Transitions= 2.87e+09 Memory= 7440.256 t= 9.09e+03 R= 2e+04
+Depth= 110273 States= 1.54e+08 Transitions= 2.91e+09 Memory= 7471.604 t= 9.2e+03 R= 2e+04
+Depth= 110273 States= 1.55e+08 Transitions= 2.95e+09 Memory= 7506.662 t= 9.32e+03 R= 2e+04
+Depth= 110273 States= 1.56e+08 Transitions= 3e+09 Memory= 7540.744 t= 9.48e+03 R= 2e+04
+Depth= 110273 States= 1.57e+08 Transitions= 3.04e+09 Memory= 7570.041 t= 9.62e+03 R= 2e+04
+Depth= 110273 States= 1.58e+08 Transitions= 3.07e+09 Memory= 7593.772 t= 9.72e+03 R= 2e+04
+Depth= 110273 States= 1.59e+08 Transitions= 3.09e+09 Memory= 7622.580 t= 9.77e+03 R= 2e+04
+Depth= 110273 States= 1.6e+08 Transitions= 3.11e+09 Memory= 7650.315 t= 9.83e+03 R= 2e+04
+Depth= 110273 States= 1.61e+08 Transitions= 3.14e+09 Memory= 7678.733 t= 9.93e+03 R= 2e+04
+Depth= 110273 States= 1.62e+08 Transitions= 3.16e+09 Memory= 7707.639 t= 1e+04 R= 2e+04
+Depth= 110273 States= 1.63e+08 Transitions= 3.18e+09 Memory= 7735.276 t= 1.01e+04 R= 2e+04
+Depth= 110273 States= 1.64e+08 Transitions= 3.2e+09 Memory= 7761.350 t= 1.01e+04 R= 2e+04
+Depth= 110273 States= 1.65e+08 Transitions= 3.21e+09 Memory= 7787.326 t= 1.02e+04 R= 2e+04
+Depth= 110273 States= 1.66e+08 Transitions= 3.23e+09 Memory= 7817.111 t= 1.02e+04 R= 2e+04
+Depth= 110273 States= 1.67e+08 Transitions= 3.25e+09 Memory= 7844.065 t= 1.03e+04 R= 2e+04
+Depth= 110273 States= 1.68e+08 Transitions= 3.28e+09 Memory= 7871.213 t= 1.04e+04 R= 2e+04
+Depth= 110273 States= 1.69e+08 Transitions= 3.3e+09 Memory= 7898.264 t= 1.04e+04 R= 2e+04
+Depth= 110273 States= 1.7e+08 Transitions= 3.32e+09 Memory= 7925.608 t= 1.05e+04 R= 2e+04
+Depth= 110273 States= 1.71e+08 Transitions= 3.35e+09 Memory= 7952.658 t= 1.06e+04 R= 2e+04
+Depth= 110273 States= 1.72e+08 Transitions= 3.38e+09 Memory= 7981.467 t= 1.07e+04 R= 2e+04
+Depth= 110273 States= 1.73e+08 Transitions= 3.4e+09 Memory= 8009.592 t= 1.08e+04 R= 2e+04
+Depth= 110273 States= 1.74e+08 Transitions= 3.43e+09 Memory= 8036.154 t= 1.08e+04 R= 2e+04
+Depth= 110273 States= 1.75e+08 Transitions= 3.45e+09 Memory= 8063.108 t= 1.09e+04 R= 2e+04
+Depth= 110273 States= 1.76e+08 Transitions= 3.48e+09 Memory= 8091.428 t= 1.1e+04 R= 2e+04
+Depth= 110273 States= 1.77e+08 Transitions= 3.5e+09 Memory= 8119.943 t= 1.11e+04 R= 2e+04
+Depth= 110273 States= 1.78e+08 Transitions= 3.53e+09 Memory= 8148.459 t= 1.12e+04 R= 2e+04
+Depth= 110273 States= 1.79e+08 Transitions= 3.54e+09 Memory= 8176.779 t= 1.12e+04 R= 2e+04
+Depth= 110273 States= 1.8e+08 Transitions= 3.56e+09 Memory= 8202.463 t= 1.12e+04 R= 2e+04
+Depth= 110273 States= 1.81e+08 Transitions= 3.58e+09 Memory= 8232.053 t= 1.13e+04 R= 2e+04
+Depth= 110273 States= 1.82e+08 Transitions= 3.6e+09 Memory= 8260.178 t= 1.14e+04 R= 2e+04
+Depth= 110273 States= 1.83e+08 Transitions= 3.62e+09 Memory= 8288.596 t= 1.14e+04 R= 2e+04
+Depth= 110273 States= 1.84e+08 Transitions= 3.64e+09 Memory= 8317.502 t= 1.15e+04 R= 2e+04
+Depth= 110273 States= 1.85e+08 Transitions= 3.66e+09 Memory= 8342.697 t= 1.16e+04 R= 2e+04
+Depth= 110273 States= 1.86e+08 Transitions= 3.67e+09 Memory= 8371.506 t= 1.16e+04 R= 2e+04
+Depth= 110273 States= 1.87e+08 Transitions= 3.69e+09 Memory= 8400.803 t= 1.17e+04 R= 2e+04
+Depth= 110273 States= 1.88e+08 Transitions= 3.71e+09 Memory= 8428.440 t= 1.17e+04 R= 2e+04
+Depth= 110273 States= 1.89e+08 Transitions= 3.73e+09 Memory= 8458.029 t= 1.18e+04 R= 2e+04
+Depth= 110273 States= 1.9e+08 Transitions= 3.75e+09 Memory= 8484.885 t= 1.18e+04 R= 2e+04
+Depth= 110273 States= 1.91e+08 Transitions= 3.76e+09 Memory= 8512.522 t= 1.19e+04 R= 2e+04
+Depth= 110273 States= 1.92e+08 Transitions= 3.78e+09 Memory= 8540.549 t= 1.19e+04 R= 2e+04
+Depth= 110273 States= 1.93e+08 Transitions= 3.79e+09 Memory= 8567.893 t= 1.2e+04 R= 2e+04
+Depth= 110273 States= 1.94e+08 Transitions= 3.82e+09 Memory= 8595.041 t= 1.21e+04 R= 2e+04
+Depth= 110273 States= 1.95e+08 Transitions= 3.84e+09 Memory= 8626.584 t= 1.21e+04 R= 2e+04
+Depth= 110273 States= 1.96e+08 Transitions= 3.85e+09 Memory= 8655.295 t= 1.22e+04 R= 2e+04
+Depth= 110273 States= 1.97e+08 Transitions= 3.87e+09 Memory= 8683.908 t= 1.22e+04 R= 2e+04
+Depth= 110273 States= 1.98e+08 Transitions= 3.89e+09 Memory= 8711.447 t= 1.23e+04 R= 2e+04
+Depth= 110273 States= 1.99e+08 Transitions= 3.91e+09 Memory= 8738.108 t= 1.23e+04 R= 2e+04
+Depth= 110273 States= 2e+08 Transitions= 3.93e+09 Memory= 8766.818 t= 1.24e+04 R= 2e+04
+Depth= 110273 States= 2.01e+08 Transitions= 3.95e+09 Memory= 8796.701 t= 1.25e+04 R= 2e+04
+Depth= 110273 States= 2.02e+08 Transitions= 3.96e+09 Memory= 8821.897 t= 1.25e+04 R= 2e+04
+Depth= 110273 States= 2.03e+08 Transitions= 3.99e+09 Memory= 8852.072 t= 1.26e+04 R= 2e+04
+Depth= 110273 States= 2.04e+08 Transitions= 4e+09 Memory= 8880.490 t= 1.26e+04 R= 2e+04
+Depth= 110273 States= 2.05e+08 Transitions= 4.02e+09 Memory= 8907.541 t= 1.27e+04 R= 2e+04
+Depth= 110273 States= 2.06e+08 Transitions= 4.03e+09 Memory= 8935.373 t= 1.27e+04 R= 2e+04
+Depth= 110273 States= 2.07e+08 Transitions= 4.05e+09 Memory= 8965.354 t= 1.28e+04 R= 2e+04
+Depth= 110273 States= 2.08e+08 Transitions= 4.07e+09 Memory= 8993.674 t= 1.28e+04 R= 2e+04
+Depth= 110273 States= 2.09e+08 Transitions= 4.09e+09 Memory= 9022.190 t= 1.29e+04 R= 2e+04
+Depth= 110273 States= 2.1e+08 Transitions= 4.11e+09 Memory= 9052.072 t= 1.3e+04 R= 2e+04
+Depth= 110273 States= 2.11e+08 Transitions= 4.13e+09 Memory= 9077.268 t= 1.3e+04 R= 2e+04
+Depth= 110273 States= 2.12e+08 Transitions= 4.15e+09 Memory= 9107.248 t= 1.31e+04 R= 2e+04
+Depth= 110273 States= 2.13e+08 Transitions= 4.16e+09 Memory= 9135.861 t= 1.31e+04 R= 2e+04
+Depth= 110273 States= 2.14e+08 Transitions= 4.18e+09 Memory= 9162.619 t= 1.32e+04 R= 2e+04
+Depth= 110273 States= 2.15e+08 Transitions= 4.2e+09 Memory= 9190.549 t= 1.32e+04 R= 2e+04
+Depth= 110273 States= 2.16e+08 Transitions= 4.21e+09 Memory= 9220.139 t= 1.33e+04 R= 2e+04
+Depth= 110273 States= 2.17e+08 Transitions= 4.23e+09 Memory= 9248.947 t= 1.33e+04 R= 2e+04
+Depth= 110273 States= 2.18e+08 Transitions= 4.25e+09 Memory= 9273.166 t= 1.34e+04 R= 2e+04
+Depth= 110273 States= 2.19e+08 Transitions= 4.26e+09 Memory= 9301.096 t= 1.34e+04 R= 2e+04
+Depth= 110273 States= 2.2e+08 Transitions= 4.28e+09 Memory= 9329.221 t= 1.35e+04 R= 2e+04
+Depth= 110273 States= 2.21e+08 Transitions= 4.29e+09 Memory= 9356.858 t= 1.35e+04 R= 2e+04
+Depth= 110273 States= 2.22e+08 Transitions= 4.32e+09 Memory= 9384.494 t= 1.36e+04 R= 2e+04
+Depth= 110273 States= 2.23e+08 Transitions= 4.35e+09 Memory= 9414.279 t= 1.37e+04 R= 2e+04
+Depth= 110273 States= 2.24e+08 Transitions= 4.37e+09 Memory= 9445.139 t= 1.38e+04 R= 2e+04
+Depth= 110273 States= 2.25e+08 Transitions= 4.39e+09 Memory= 9473.361 t= 1.38e+04 R= 2e+04
+Depth= 110273 States= 2.26e+08 Transitions= 4.4e+09 Memory= 9502.365 t= 1.39e+04 R= 2e+04
+Depth= 110273 States= 2.27e+08 Transitions= 4.42e+09 Memory= 9530.783 t= 1.39e+04 R= 2e+04
+Depth= 110273 States= 2.28e+08 Transitions= 4.44e+09 Memory= 9559.592 t= 1.4e+04 R= 2e+04
+Depth= 110273 States= 2.29e+08 Transitions= 4.47e+09 Memory= 9586.838 t= 1.41e+04 R= 2e+04
+Depth= 110273 States= 2.3e+08 Transitions= 4.49e+09 Memory= 9612.815 t= 1.42e+04 R= 2e+04
+Depth= 110273 States= 2.31e+08 Transitions= 4.52e+09 Memory= 9639.572 t= 1.42e+04 R= 2e+04
+Depth= 110273 States= 2.32e+08 Transitions= 4.54e+09 Memory= 9666.233 t= 1.43e+04 R= 2e+04
+Depth= 110273 States= 2.33e+08 Transitions= 4.57e+09 Memory= 9692.307 t= 1.44e+04 R= 2e+04
+Depth= 110273 States= 2.34e+08 Transitions= 4.59e+09 Memory= 9718.186 t= 1.45e+04 R= 2e+04
+Depth= 110273 States= 2.35e+08 Transitions= 4.61e+09 Memory= 9746.604 t= 1.45e+04 R= 2e+04
+Depth= 110273 States= 2.36e+08 Transitions= 4.63e+09 Memory= 9772.678 t= 1.46e+04 R= 2e+04
+Depth= 110273 States= 2.37e+08 Transitions= 4.65e+09 Memory= 9799.826 t= 1.46e+04 R= 2e+04
+Depth= 110273 States= 2.38e+08 Transitions= 4.67e+09 Memory= 9826.779 t= 1.47e+04 R= 2e+04
+Depth= 110273 States= 2.39e+08 Transitions= 4.7e+09 Memory= 9853.342 t= 1.48e+04 R= 2e+04
+Depth= 110273 States= 2.4e+08 Transitions= 4.72e+09 Memory= 9879.709 t= 1.49e+04 R= 2e+04
+Depth= 110273 States= 2.41e+08 Transitions= 4.75e+09 Memory= 9906.174 t= 1.49e+04 R= 2e+04
+Depth= 110273 States= 2.42e+08 Transitions= 4.77e+09 Memory= 9934.006 t= 1.5e+04 R= 2e+04
+Depth= 110273 States= 2.43e+08 Transitions= 4.79e+09 Memory= 9960.471 t= 1.51e+04 R= 2e+04
+Depth= 110273 States= 2.44e+08 Transitions= 4.81e+09 Memory= 9987.229 t= 1.51e+04 R= 2e+04
+Depth= 110273 States= 2.45e+08 Transitions= 4.83e+09 Memory= 10014.084 t= 1.52e+04 R= 2e+04
+Depth= 110273 States= 2.46e+08 Transitions= 4.85e+09 Memory= 10040.842 t= 1.53e+04 R= 2e+04
+Depth= 110273 States= 2.47e+08 Transitions= 4.87e+09 Memory= 10067.404 t= 1.53e+04 R= 2e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 110273, errors: 0
+1.5183145e+08 states, stored (2.47605e+08 visited)
+4.6348493e+09 states, matched
+4.8824543e+09 transitions (= visited+matched)
+7.5925477e+10 atomic steps
+hash conflicts: 9.7802755e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+16796.540 equivalent memory usage for states (stored*(State-vector + overhead))
+ 7578.458 actual memory usage for states (compression: 45.12%)
+ state-vector as stored = 16 byte + 36 byte overhead
+ 2048.000 memory used for hash table (-w28)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1.290 memory lost to fragmentation
+10082.932 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 547261 4207 4043 2 2 ]
+unreached in proctype urcu_reader
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 222, "(1)"
+ line 253, "pan.___", state 242, "(1)"
+ line 257, "pan.___", state 250, "(1)"
+ line 687, "pan.___", state 269, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 276, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 308, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 322, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 340, "(1)"
+ line 253, "pan.___", state 360, "(1)"
+ line 257, "pan.___", state 368, "(1)"
+ line 407, "pan.___", state 387, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 419, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 433, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 451, "(1)"
+ line 253, "pan.___", state 471, "(1)"
+ line 257, "pan.___", state 479, "(1)"
+ line 407, "pan.___", state 500, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 502, "(1)"
+ line 407, "pan.___", state 503, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 503, "else"
+ line 407, "pan.___", state 506, "(1)"
+ line 411, "pan.___", state 514, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 516, "(1)"
+ line 411, "pan.___", state 517, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 517, "else"
+ line 411, "pan.___", state 520, "(1)"
+ line 411, "pan.___", state 521, "(1)"
+ line 411, "pan.___", state 521, "(1)"
+ line 409, "pan.___", state 526, "((i<1))"
+ line 409, "pan.___", state 526, "((i>=1))"
+ line 416, "pan.___", state 532, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 534, "(1)"
+ line 416, "pan.___", state 535, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 535, "else"
+ line 416, "pan.___", state 538, "(1)"
+ line 416, "pan.___", state 539, "(1)"
+ line 416, "pan.___", state 539, "(1)"
+ line 420, "pan.___", state 546, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 548, "(1)"
+ line 420, "pan.___", state 549, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 549, "else"
+ line 420, "pan.___", state 552, "(1)"
+ line 420, "pan.___", state 553, "(1)"
+ line 420, "pan.___", state 553, "(1)"
+ line 418, "pan.___", state 558, "((i<2))"
+ line 418, "pan.___", state 558, "((i>=2))"
+ line 245, "pan.___", state 564, "(1)"
+ line 249, "pan.___", state 572, "(1)"
+ line 249, "pan.___", state 573, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 573, "else"
+ line 247, "pan.___", state 578, "((i<1))"
+ line 247, "pan.___", state 578, "((i>=1))"
+ line 253, "pan.___", state 584, "(1)"
+ line 253, "pan.___", state 585, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 585, "else"
+ line 257, "pan.___", state 592, "(1)"
+ line 257, "pan.___", state 593, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 593, "else"
+ line 255, "pan.___", state 598, "((i<2))"
+ line 255, "pan.___", state 598, "((i>=2))"
+ line 262, "pan.___", state 602, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 602, "else"
+ line 427, "pan.___", state 604, "(1)"
+ line 427, "pan.___", state 604, "(1)"
+ line 687, "pan.___", state 607, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 608, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 609, "(1)"
+ line 407, "pan.___", state 616, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 648, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 680, "(1)"
+ line 253, "pan.___", state 700, "(1)"
+ line 257, "pan.___", state 708, "(1)"
+ line 407, "pan.___", state 734, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 766, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 780, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 798, "(1)"
+ line 253, "pan.___", state 818, "(1)"
+ line 257, "pan.___", state 826, "(1)"
+ line 407, "pan.___", state 845, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 847, "(1)"
+ line 407, "pan.___", state 848, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 848, "else"
+ line 407, "pan.___", state 851, "(1)"
+ line 411, "pan.___", state 859, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 861, "(1)"
+ line 411, "pan.___", state 862, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 862, "else"
+ line 411, "pan.___", state 865, "(1)"
+ line 411, "pan.___", state 866, "(1)"
+ line 411, "pan.___", state 866, "(1)"
+ line 409, "pan.___", state 871, "((i<1))"
+ line 409, "pan.___", state 871, "((i>=1))"
+ line 416, "pan.___", state 877, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 879, "(1)"
+ line 416, "pan.___", state 880, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 880, "else"
+ line 416, "pan.___", state 883, "(1)"
+ line 416, "pan.___", state 884, "(1)"
+ line 416, "pan.___", state 884, "(1)"
+ line 420, "pan.___", state 891, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 893, "(1)"
+ line 420, "pan.___", state 894, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 894, "else"
+ line 420, "pan.___", state 897, "(1)"
+ line 420, "pan.___", state 898, "(1)"
+ line 420, "pan.___", state 898, "(1)"
+ line 418, "pan.___", state 903, "((i<2))"
+ line 418, "pan.___", state 903, "((i>=2))"
+ line 245, "pan.___", state 909, "(1)"
+ line 249, "pan.___", state 917, "(1)"
+ line 249, "pan.___", state 918, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 918, "else"
+ line 247, "pan.___", state 923, "((i<1))"
+ line 247, "pan.___", state 923, "((i>=1))"
+ line 253, "pan.___", state 929, "(1)"
+ line 253, "pan.___", state 930, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 930, "else"
+ line 257, "pan.___", state 937, "(1)"
+ line 257, "pan.___", state 938, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 938, "else"
+ line 255, "pan.___", state 943, "((i<2))"
+ line 255, "pan.___", state 943, "((i>=2))"
+ line 262, "pan.___", state 947, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 947, "else"
+ line 427, "pan.___", state 949, "(1)"
+ line 427, "pan.___", state 949, "(1)"
+ line 695, "pan.___", state 953, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 958, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 990, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1004, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1022, "(1)"
+ line 253, "pan.___", state 1042, "(1)"
+ line 257, "pan.___", state 1050, "(1)"
+ line 407, "pan.___", state 1072, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1104, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1118, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1136, "(1)"
+ line 253, "pan.___", state 1156, "(1)"
+ line 257, "pan.___", state 1164, "(1)"
+ line 407, "pan.___", state 1187, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1219, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1233, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1251, "(1)"
+ line 253, "pan.___", state 1271, "(1)"
+ line 257, "pan.___", state 1279, "(1)"
+ line 407, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1330, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1344, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1362, "(1)"
+ line 253, "pan.___", state 1382, "(1)"
+ line 257, "pan.___", state 1390, "(1)"
+ line 407, "pan.___", state 1414, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1446, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1460, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1478, "(1)"
+ line 253, "pan.___", state 1498, "(1)"
+ line 257, "pan.___", state 1506, "(1)"
+ line 407, "pan.___", state 1525, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1557, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1571, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1589, "(1)"
+ line 253, "pan.___", state 1609, "(1)"
+ line 257, "pan.___", state 1617, "(1)"
+ line 407, "pan.___", state 1639, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1671, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1685, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1703, "(1)"
+ line 253, "pan.___", state 1723, "(1)"
+ line 257, "pan.___", state 1731, "(1)"
+ line 734, "pan.___", state 1750, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 1757, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1789, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1803, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1821, "(1)"
+ line 253, "pan.___", state 1841, "(1)"
+ line 257, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1868, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1900, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1914, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1932, "(1)"
+ line 253, "pan.___", state 1952, "(1)"
+ line 257, "pan.___", state 1960, "(1)"
+ line 407, "pan.___", state 1981, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 1983, "(1)"
+ line 407, "pan.___", state 1984, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 1984, "else"
+ line 407, "pan.___", state 1987, "(1)"
+ line 411, "pan.___", state 1995, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 1997, "(1)"
+ line 411, "pan.___", state 1998, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 1998, "else"
+ line 411, "pan.___", state 2001, "(1)"
+ line 411, "pan.___", state 2002, "(1)"
+ line 411, "pan.___", state 2002, "(1)"
+ line 409, "pan.___", state 2007, "((i<1))"
+ line 409, "pan.___", state 2007, "((i>=1))"
+ line 416, "pan.___", state 2013, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2015, "(1)"
+ line 416, "pan.___", state 2016, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2016, "else"
+ line 416, "pan.___", state 2019, "(1)"
+ line 416, "pan.___", state 2020, "(1)"
+ line 416, "pan.___", state 2020, "(1)"
+ line 420, "pan.___", state 2027, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2029, "(1)"
+ line 420, "pan.___", state 2030, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2030, "else"
+ line 420, "pan.___", state 2033, "(1)"
+ line 420, "pan.___", state 2034, "(1)"
+ line 420, "pan.___", state 2034, "(1)"
+ line 418, "pan.___", state 2039, "((i<2))"
+ line 418, "pan.___", state 2039, "((i>=2))"
+ line 245, "pan.___", state 2045, "(1)"
+ line 249, "pan.___", state 2053, "(1)"
+ line 249, "pan.___", state 2054, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 2054, "else"
+ line 247, "pan.___", state 2059, "((i<1))"
+ line 247, "pan.___", state 2059, "((i>=1))"
+ line 253, "pan.___", state 2065, "(1)"
+ line 253, "pan.___", state 2066, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 2066, "else"
+ line 257, "pan.___", state 2073, "(1)"
+ line 257, "pan.___", state 2074, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 2074, "else"
+ line 255, "pan.___", state 2079, "((i<2))"
+ line 255, "pan.___", state 2079, "((i>=2))"
+ line 262, "pan.___", state 2083, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 2083, "else"
+ line 427, "pan.___", state 2085, "(1)"
+ line 427, "pan.___", state 2085, "(1)"
+ line 734, "pan.___", state 2088, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2089, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2090, "(1)"
+ line 407, "pan.___", state 2097, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2129, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2143, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2161, "(1)"
+ line 253, "pan.___", state 2181, "(1)"
+ line 257, "pan.___", state 2189, "(1)"
+ line 407, "pan.___", state 2214, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2246, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2260, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2278, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2306, "(1)"
+ line 407, "pan.___", state 2325, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2357, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2371, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2389, "(1)"
+ line 253, "pan.___", state 2409, "(1)"
+ line 257, "pan.___", state 2417, "(1)"
+ line 245, "pan.___", state 2448, "(1)"
+ line 253, "pan.___", state 2468, "(1)"
+ line 257, "pan.___", state 2476, "(1)"
+ line 245, "pan.___", state 2491, "(1)"
+ line 253, "pan.___", state 2511, "(1)"
+ line 257, "pan.___", state 2519, "(1)"
+ line 929, "pan.___", state 2536, "-end-"
+ (221 of 2536 states)
+unreached in proctype urcu_writer
+ line 407, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 245, "pan.___", state 109, "(1)"
+ line 249, "pan.___", state 117, "(1)"
+ line 253, "pan.___", state 129, "(1)"
+ line 268, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 167, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 180, "cache_dirty_rcu_ptr = 0"
+ line 407, "pan.___", state 220, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 234, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 252, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 284, "(1)"
+ line 249, "pan.___", state 292, "(1)"
+ line 253, "pan.___", state 304, "(1)"
+ line 257, "pan.___", state 312, "(1)"
+ line 411, "pan.___", state 347, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 365, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 379, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 405, "(1)"
+ line 253, "pan.___", state 417, "(1)"
+ line 257, "pan.___", state 425, "(1)"
+ line 411, "pan.___", state 468, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 486, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 500, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 526, "(1)"
+ line 253, "pan.___", state 538, "(1)"
+ line 257, "pan.___", state 546, "(1)"
+ line 411, "pan.___", state 579, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 597, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 611, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 637, "(1)"
+ line 253, "pan.___", state 649, "(1)"
+ line 257, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 692, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 710, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 724, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 750, "(1)"
+ line 253, "pan.___", state 762, "(1)"
+ line 257, "pan.___", state 770, "(1)"
+ line 268, "pan.___", state 818, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 827, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 840, "cache_dirty_rcu_ptr = 0"
+ line 245, "pan.___", state 865, "(1)"
+ line 249, "pan.___", state 873, "(1)"
+ line 253, "pan.___", state 885, "(1)"
+ line 257, "pan.___", state 893, "(1)"
+ line 268, "pan.___", state 924, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 933, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 946, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 955, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 971, "(1)"
+ line 249, "pan.___", state 979, "(1)"
+ line 253, "pan.___", state 991, "(1)"
+ line 257, "pan.___", state 999, "(1)"
+ line 268, "pan.___", state 1020, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1029, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1044, "(1)"
+ line 280, "pan.___", state 1051, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1067, "(1)"
+ line 249, "pan.___", state 1075, "(1)"
+ line 253, "pan.___", state 1087, "(1)"
+ line 257, "pan.___", state 1095, "(1)"
+ line 268, "pan.___", state 1126, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1135, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1148, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1157, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1173, "(1)"
+ line 249, "pan.___", state 1181, "(1)"
+ line 253, "pan.___", state 1193, "(1)"
+ line 257, "pan.___", state 1201, "(1)"
+ line 272, "pan.___", state 1227, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1240, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1249, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1265, "(1)"
+ line 249, "pan.___", state 1273, "(1)"
+ line 253, "pan.___", state 1285, "(1)"
+ line 257, "pan.___", state 1293, "(1)"
+ line 268, "pan.___", state 1324, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1333, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1346, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1355, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1371, "(1)"
+ line 249, "pan.___", state 1379, "(1)"
+ line 253, "pan.___", state 1391, "(1)"
+ line 257, "pan.___", state 1399, "(1)"
+ line 272, "pan.___", state 1425, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1438, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1447, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1463, "(1)"
+ line 249, "pan.___", state 1471, "(1)"
+ line 253, "pan.___", state 1483, "(1)"
+ line 257, "pan.___", state 1491, "(1)"
+ line 268, "pan.___", state 1522, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1531, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1544, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1553, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1569, "(1)"
+ line 249, "pan.___", state 1577, "(1)"
+ line 253, "pan.___", state 1589, "(1)"
+ line 257, "pan.___", state 1597, "(1)"
+ line 272, "pan.___", state 1623, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1636, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1645, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1661, "(1)"
+ line 249, "pan.___", state 1669, "(1)"
+ line 253, "pan.___", state 1681, "(1)"
+ line 257, "pan.___", state 1689, "(1)"
+ line 268, "pan.___", state 1720, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1729, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1742, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1751, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1767, "(1)"
+ line 249, "pan.___", state 1775, "(1)"
+ line 253, "pan.___", state 1787, "(1)"
+ line 257, "pan.___", state 1795, "(1)"
+ line 1304, "pan.___", state 1811, "-end-"
+ (118 of 1811 states)
+unreached in proctype :init:
+ (0 of 28 states)
+unreached in proctype :never:
+ line 1369, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 1.54e+04 seconds
+pan: rate 16109.46 states/second
+pan: avg transition delay 3.148e-06 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
--- /dev/null
+#define READER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1362)
+depth 7: Claim reached state 9 (line 1367)
+depth 50: Claim reached state 9 (line 1366)
+Depth= 7070 States= 1e+06 Transitions= 1.16e+07 Memory= 493.010 t= 34.5 R= 3e+04
+Depth= 7070 States= 2e+06 Transitions= 2.31e+07 Memory= 521.330 t= 69.3 R= 3e+04
+Depth= 7070 States= 3e+06 Transitions= 3.43e+07 Memory= 549.455 t= 103 R= 3e+04
+pan: resizing hashtable to -w22.. done
+Depth= 8814 States= 4e+06 Transitions= 4.57e+07 Memory= 607.041 t= 138 R= 3e+04
+Depth= 8814 States= 5e+06 Transitions= 5.73e+07 Memory= 632.920 t= 174 R= 3e+04
+Depth= 8814 States= 6e+06 Transitions= 7.04e+07 Memory= 662.217 t= 215 R= 3e+04
+Depth= 8814 States= 7e+06 Transitions= 8.38e+07 Memory= 690.049 t= 257 R= 3e+04
+Depth= 8814 States= 8e+06 Transitions= 9.59e+07 Memory= 717.588 t= 294 R= 3e+04
+Depth= 8814 States= 9e+06 Transitions= 1.08e+08 Memory= 745.127 t= 332 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 8814 States= 1e+07 Transitions= 1.29e+08 Memory= 897.639 t= 398 R= 3e+04
+Depth= 8814 States= 1.1e+07 Transitions= 1.41e+08 Memory= 926.154 t= 434 R= 3e+04
+Depth= 8814 States= 1.2e+07 Transitions= 1.53e+08 Memory= 953.401 t= 471 R= 3e+04
+Depth= 8814 States= 1.3e+07 Transitions= 1.64e+08 Memory= 980.940 t= 505 R= 3e+04
+Depth= 8814 States= 1.4e+07 Transitions= 1.75e+08 Memory= 1010.725 t= 539 R= 3e+04
+Depth= 8814 States= 1.5e+07 Transitions= 1.87e+08 Memory= 1037.580 t= 573 R= 3e+04
+Depth= 8814 States= 1.6e+07 Transitions= 1.98e+08 Memory= 1064.924 t= 607 R= 3e+04
+Depth= 8814 States= 1.7e+07 Transitions= 2.09e+08 Memory= 1094.904 t= 641 R= 3e+04
+Depth= 8814 States= 1.8e+07 Transitions= 2.23e+08 Memory= 1119.514 t= 683 R= 3e+04
+Depth= 8814 States= 1.9e+07 Transitions= 2.36e+08 Memory= 1146.662 t= 725 R= 3e+04
+Depth= 8814 States= 2e+07 Transitions= 2.57e+08 Memory= 1174.201 t= 790 R= 3e+04
+Depth= 8814 States= 2.1e+07 Transitions= 2.93e+08 Memory= 1205.549 t= 908 R= 2e+04
+Depth= 9015 States= 2.2e+07 Transitions= 3.11e+08 Memory= 1235.822 t= 965 R= 2e+04
+Depth= 9015 States= 2.3e+07 Transitions= 3.25e+08 Memory= 1264.533 t= 1.01e+03 R= 2e+04
+Depth= 9015 States= 2.4e+07 Transitions= 3.45e+08 Memory= 1293.244 t= 1.07e+03 R= 2e+04
+Depth= 9015 States= 2.5e+07 Transitions= 3.67e+08 Memory= 1321.467 t= 1.14e+03 R= 2e+04
+Depth= 9015 States= 2.6e+07 Transitions= 3.84e+08 Memory= 1350.764 t= 1.2e+03 R= 2e+04
+Depth= 9015 States= 2.7e+07 Transitions= 4.07e+08 Memory= 1380.158 t= 1.27e+03 R= 2e+04
+Depth= 9015 States= 2.8e+07 Transitions= 4.29e+08 Memory= 1405.940 t= 1.34e+03 R= 2e+04
+Depth= 9015 States= 2.9e+07 Transitions= 4.48e+08 Memory= 1433.381 t= 1.4e+03 R= 2e+04
+Depth= 9015 States= 3e+07 Transitions= 4.66e+08 Memory= 1461.506 t= 1.46e+03 R= 2e+04
+Depth= 9015 States= 3.1e+07 Transitions= 4.86e+08 Memory= 1489.143 t= 1.52e+03 R= 2e+04
+Depth= 9015 States= 3.2e+07 Transitions= 5.1e+08 Memory= 1516.486 t= 1.6e+03 R= 2e+04
+Depth= 9015 States= 3.3e+07 Transitions= 5.29e+08 Memory= 1543.733 t= 1.66e+03 R= 2e+04
+Depth= 9015 States= 3.4e+07 Transitions= 5.47e+08 Memory= 1571.760 t= 1.72e+03 R= 2e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9015 States= 3.5e+07 Transitions= 5.69e+08 Memory= 2095.088 t= 1.79e+03 R= 2e+04
+Depth= 9015 States= 3.6e+07 Transitions= 5.95e+08 Memory= 2122.041 t= 1.87e+03 R= 2e+04
+Depth= 9015 States= 3.7e+07 Transitions= 6.12e+08 Memory= 2149.971 t= 1.93e+03 R= 2e+04
+Depth= 9015 States= 3.8e+07 Transitions= 6.29e+08 Memory= 2176.045 t= 1.98e+03 R= 2e+04
+Depth= 9015 States= 3.9e+07 Transitions= 6.42e+08 Memory= 2204.268 t= 2.02e+03 R= 2e+04
+Depth= 9015 States= 4e+07 Transitions= 6.56e+08 Memory= 2233.565 t= 2.06e+03 R= 2e+04
+Depth= 9015 States= 4.1e+07 Transitions= 6.69e+08 Memory= 2264.424 t= 2.1e+03 R= 2e+04
+Depth= 9015 States= 4.2e+07 Transitions= 6.82e+08 Memory= 2292.940 t= 2.14e+03 R= 2e+04
+Depth= 9015 States= 4.3e+07 Transitions= 6.95e+08 Memory= 2322.529 t= 2.18e+03 R= 2e+04
+Depth= 9015 States= 4.4e+07 Transitions= 7.07e+08 Memory= 2350.654 t= 2.22e+03 R= 2e+04
+Depth= 9015 States= 4.5e+07 Transitions= 7.28e+08 Memory= 2378.193 t= 2.29e+03 R= 2e+04
+Depth= 9015 States= 4.6e+07 Transitions= 7.63e+08 Memory= 2409.443 t= 2.4e+03 R= 2e+04
+Depth= 9015 States= 4.7e+07 Transitions= 7.99e+08 Memory= 2445.088 t= 2.52e+03 R= 2e+04
+Depth= 9015 States= 4.8e+07 Transitions= 8.49e+08 Memory= 2479.072 t= 2.69e+03 R= 2e+04
+Depth= 9015 States= 4.9e+07 Transitions= 8.91e+08 Memory= 2508.076 t= 2.82e+03 R= 2e+04
+Depth= 9015 States= 5e+07 Transitions= 9.24e+08 Memory= 2532.295 t= 2.93e+03 R= 2e+04
+Depth= 9015 States= 5.1e+07 Transitions= 9.39e+08 Memory= 2561.494 t= 2.98e+03 R= 2e+04
+Depth= 9015 States= 5.2e+07 Transitions= 9.6e+08 Memory= 2589.522 t= 3.05e+03 R= 2e+04
+Depth= 9015 States= 5.3e+07 Transitions= 9.99e+08 Memory= 2617.158 t= 3.17e+03 R= 2e+04
+Depth= 9015 States= 5.4e+07 Transitions= 1.01e+09 Memory= 2647.725 t= 3.22e+03 R= 2e+04
+Depth= 9015 States= 5.5e+07 Transitions= 1.03e+09 Memory= 2674.580 t= 3.27e+03 R= 2e+04
+Depth= 9015 States= 5.6e+07 Transitions= 1.05e+09 Memory= 2701.143 t= 3.32e+03 R= 2e+04
+Depth= 9015 States= 5.7e+07 Transitions= 1.06e+09 Memory= 2730.928 t= 3.36e+03 R= 2e+04
+Depth= 9015 States= 5.8e+07 Transitions= 1.09e+09 Memory= 2759.053 t= 3.45e+03 R= 2e+04
+Depth= 9015 States= 5.9e+07 Transitions= 1.1e+09 Memory= 2786.983 t= 3.5e+03 R= 2e+04
+Depth= 9015 States= 6e+07 Transitions= 1.13e+09 Memory= 2814.619 t= 3.6e+03 R= 2e+04
+Depth= 9015 States= 6.1e+07 Transitions= 1.15e+09 Memory= 2841.670 t= 3.66e+03 R= 2e+04
+Depth= 9015 States= 6.2e+07 Transitions= 1.19e+09 Memory= 2870.576 t= 3.77e+03 R= 2e+04
+Depth= 9015 States= 6.3e+07 Transitions= 1.21e+09 Memory= 2897.627 t= 3.84e+03 R= 2e+04
+Depth= 9015 States= 6.4e+07 Transitions= 1.24e+09 Memory= 2925.166 t= 3.94e+03 R= 2e+04
+Depth= 9015 States= 6.5e+07 Transitions= 1.26e+09 Memory= 2952.803 t= 4.01e+03 R= 2e+04
+Depth= 9015 States= 6.6e+07 Transitions= 1.28e+09 Memory= 2979.756 t= 4.09e+03 R= 2e+04
+Depth= 9015 States= 6.7e+07 Transitions= 1.3e+09 Memory= 3007.686 t= 4.15e+03 R= 2e+04
+Depth= 9015 States= 6.8e+07 Transitions= 1.33e+09 Memory= 3035.811 t= 4.23e+03 R= 2e+04
+Depth= 9015 States= 6.9e+07 Transitions= 1.36e+09 Memory= 3063.838 t= 4.32e+03 R= 2e+04
+Depth= 9522 States= 7e+07 Transitions= 1.38e+09 Memory= 3094.795 t= 4.39e+03 R= 2e+04
+Depth= 9522 States= 7.1e+07 Transitions= 1.39e+09 Memory= 3120.186 t= 4.43e+03 R= 2e+04
+Depth= 9522 States= 7.2e+07 Transitions= 1.41e+09 Memory= 3149.971 t= 4.5e+03 R= 2e+04
+Depth= 9553 States= 7.3e+07 Transitions= 1.44e+09 Memory= 3179.365 t= 4.57e+03 R= 2e+04
+Depth= 9553 States= 7.4e+07 Transitions= 1.45e+09 Memory= 3205.244 t= 4.61e+03 R= 2e+04
+Depth= 9553 States= 7.5e+07 Transitions= 1.47e+09 Memory= 3235.225 t= 4.69e+03 R= 2e+04
+Depth= 9553 States= 7.6e+07 Transitions= 1.49e+09 Memory= 3263.545 t= 4.75e+03 R= 2e+04
+Depth= 9553 States= 7.7e+07 Transitions= 1.51e+09 Memory= 3290.401 t= 4.8e+03 R= 2e+04
+Depth= 9553 States= 7.8e+07 Transitions= 1.52e+09 Memory= 3319.795 t= 4.84e+03 R= 2e+04
+Depth= 9553 States= 7.9e+07 Transitions= 1.54e+09 Memory= 3349.190 t= 4.91e+03 R= 2e+04
+Depth= 9553 States= 8e+07 Transitions= 1.56e+09 Memory= 3377.803 t= 4.98e+03 R= 2e+04
+Depth= 9553 States= 8.1e+07 Transitions= 1.58e+09 Memory= 3406.904 t= 5.04e+03 R= 2e+04
+Depth= 9553 States= 8.2e+07 Transitions= 1.6e+09 Memory= 3434.443 t= 5.08e+03 R= 2e+04
+Depth= 9553 States= 8.3e+07 Transitions= 1.61e+09 Memory= 3462.178 t= 5.14e+03 R= 2e+04
+Depth= 9553 States= 8.4e+07 Transitions= 1.63e+09 Memory= 3490.205 t= 5.18e+03 R= 2e+04
+Depth= 9553 States= 8.5e+07 Transitions= 1.65e+09 Memory= 3517.549 t= 5.24e+03 R= 2e+04
+Depth= 9553 States= 8.6e+07 Transitions= 1.67e+09 Memory= 3544.502 t= 5.31e+03 R= 2e+04
+Depth= 9553 States= 8.7e+07 Transitions= 1.69e+09 Memory= 3574.190 t= 5.38e+03 R= 2e+04
+Depth= 9553 States= 8.8e+07 Transitions= 1.7e+09 Memory= 3606.026 t= 5.42e+03 R= 2e+04
+Depth= 9553 States= 8.9e+07 Transitions= 1.72e+09 Memory= 3632.588 t= 5.48e+03 R= 2e+04
+Depth= 9553 States= 9e+07 Transitions= 1.74e+09 Memory= 3662.080 t= 5.53e+03 R= 2e+04
+Depth= 9553 States= 9.1e+07 Transitions= 1.76e+09 Memory= 3689.229 t= 5.59e+03 R= 2e+04
+Depth= 9553 States= 9.2e+07 Transitions= 1.78e+09 Memory= 3716.572 t= 5.65e+03 R= 2e+04
+Depth= 9553 States= 9.3e+07 Transitions= 1.8e+09 Memory= 3743.135 t= 5.72e+03 R= 2e+04
+Depth= 9553 States= 9.4e+07 Transitions= 1.82e+09 Memory= 3771.553 t= 5.8e+03 R= 2e+04
+Depth= 9553 States= 9.5e+07 Transitions= 1.84e+09 Memory= 3801.436 t= 5.86e+03 R= 2e+04
+Depth= 9553 States= 9.6e+07 Transitions= 1.86e+09 Memory= 3827.803 t= 5.91e+03 R= 2e+04
+Depth= 9553 States= 9.7e+07 Transitions= 1.88e+09 Memory= 3857.881 t= 5.99e+03 R= 2e+04
+Depth= 9553 States= 9.8e+07 Transitions= 1.9e+09 Memory= 3886.494 t= 6.03e+03 R= 2e+04
+Depth= 9553 States= 9.9e+07 Transitions= 1.91e+09 Memory= 3914.229 t= 6.08e+03 R= 2e+04
+Depth= 9553 States= 1e+08 Transitions= 1.93e+09 Memory= 3942.549 t= 6.13e+03 R= 2e+04
+Depth= 9553 States= 1.01e+08 Transitions= 1.94e+09 Memory= 3972.236 t= 6.19e+03 R= 2e+04
+Depth= 9553 States= 1.02e+08 Transitions= 1.96e+09 Memory= 4001.729 t= 6.24e+03 R= 2e+04
+Depth= 9553 States= 1.03e+08 Transitions= 1.98e+09 Memory= 4030.049 t= 6.3e+03 R= 2e+04
+Depth= 9553 States= 1.04e+08 Transitions= 2e+09 Memory= 4059.639 t= 6.38e+03 R= 2e+04
+Depth= 9553 States= 1.05e+08 Transitions= 2.02e+09 Memory= 4086.006 t= 6.43e+03 R= 2e+04
+Depth= 9553 States= 1.06e+08 Transitions= 2.04e+09 Memory= 4115.889 t= 6.49e+03 R= 2e+04
+Depth= 9553 States= 1.07e+08 Transitions= 2.06e+09 Memory= 4144.990 t= 6.55e+03 R= 2e+04
+Depth= 9553 States= 1.08e+08 Transitions= 2.07e+09 Memory= 4172.822 t= 6.6e+03 R= 2e+04
+Depth= 9553 States= 1.09e+08 Transitions= 2.09e+09 Memory= 4200.752 t= 6.65e+03 R= 2e+04
+Depth= 9553 States= 1.1e+08 Transitions= 2.11e+09 Memory= 4230.147 t= 6.7e+03 R= 2e+04
+Depth= 9553 States= 1.11e+08 Transitions= 2.12e+09 Memory= 4259.932 t= 6.75e+03 R= 2e+04
+Depth= 9553 States= 1.12e+08 Transitions= 2.14e+09 Memory= 4284.541 t= 6.81e+03 R= 2e+04
+Depth= 9553 States= 1.13e+08 Transitions= 2.16e+09 Memory= 4312.471 t= 6.86e+03 R= 2e+04
+Depth= 9553 States= 1.14e+08 Transitions= 2.17e+09 Memory= 4340.401 t= 6.91e+03 R= 2e+04
+Depth= 9553 States= 1.15e+08 Transitions= 2.19e+09 Memory= 4368.526 t= 6.97e+03 R= 2e+04
+Depth= 9553 States= 1.16e+08 Transitions= 2.21e+09 Memory= 4396.651 t= 7.02e+03 R= 2e+04
+Depth= 9553 States= 1.17e+08 Transitions= 2.23e+09 Memory= 4423.897 t= 7.1e+03 R= 2e+04
+Depth= 9553 States= 1.18e+08 Transitions= 2.27e+09 Memory= 4453.779 t= 7.22e+03 R= 2e+04
+Depth= 9553 States= 1.19e+08 Transitions= 2.29e+09 Memory= 4483.955 t= 7.29e+03 R= 2e+04
+Depth= 9553 States= 1.2e+08 Transitions= 2.3e+09 Memory= 4513.545 t= 7.33e+03 R= 2e+04
+Depth= 9553 States= 1.21e+08 Transitions= 2.32e+09 Memory= 4541.279 t= 7.4e+03 R= 2e+04
+Depth= 9553 States= 1.22e+08 Transitions= 2.34e+09 Memory= 4569.893 t= 7.45e+03 R= 2e+04
+Depth= 9553 States= 1.23e+08 Transitions= 2.36e+09 Memory= 4599.483 t= 7.52e+03 R= 2e+04
+Depth= 9553 States= 1.24e+08 Transitions= 2.38e+09 Memory= 4627.705 t= 7.58e+03 R= 2e+04
+Depth= 9553 States= 1.25e+08 Transitions= 2.41e+09 Memory= 4654.658 t= 7.68e+03 R= 2e+04
+Depth= 9553 States= 1.26e+08 Transitions= 2.43e+09 Memory= 4681.807 t= 7.76e+03 R= 2e+04
+Depth= 9553 States= 1.27e+08 Transitions= 2.45e+09 Memory= 4708.760 t= 7.83e+03 R= 2e+04
+Depth= 9553 States= 1.28e+08 Transitions= 2.48e+09 Memory= 4735.518 t= 7.93e+03 R= 2e+04
+Depth= 9553 States= 1.29e+08 Transitions= 2.5e+09 Memory= 4762.178 t= 8e+03 R= 2e+04
+Depth= 9553 States= 1.3e+08 Transitions= 2.52e+09 Memory= 4790.303 t= 8.07e+03 R= 2e+04
+Depth= 9553 States= 1.31e+08 Transitions= 2.55e+09 Memory= 4817.451 t= 8.15e+03 R= 2e+04
+Depth= 9553 States= 1.32e+08 Transitions= 2.57e+09 Memory= 4845.186 t= 8.22e+03 R= 2e+04
+Depth= 9553 States= 1.33e+08 Transitions= 2.59e+09 Memory= 4872.139 t= 8.3e+03 R= 2e+04
+Depth= 9553 States= 1.34e+08 Transitions= 2.61e+09 Memory= 4900.850 t= 8.37e+03 R= 2e+04
+Depth= 9553 States= 1.35e+08 Transitions= 2.63e+09 Memory= 4927.803 t= 8.43e+03 R= 2e+04
+pan: resizing hashtable to -w28.. done
+Depth= 9553 States= 1.36e+08 Transitions= 2.65e+09 Memory= 6975.803 t= 8.5e+03 R= 2e+04
+Depth= 9553 States= 1.37e+08 Transitions= 2.66e+09 Memory= 6975.803 t= 8.54e+03 R= 2e+04
+Depth= 9553 States= 1.38e+08 Transitions= 2.67e+09 Memory= 6996.799 t= 8.58e+03 R= 2e+04
+Depth= 9553 States= 1.39e+08 Transitions= 2.69e+09 Memory= 7026.779 t= 8.62e+03 R= 2e+04
+Depth= 9553 States= 1.4e+08 Transitions= 2.7e+09 Memory= 7056.467 t= 8.68e+03 R= 2e+04
+Depth= 9553 States= 1.41e+08 Transitions= 2.72e+09 Memory= 7084.787 t= 8.72e+03 R= 2e+04
+Depth= 9553 States= 1.42e+08 Transitions= 2.74e+09 Memory= 7114.084 t= 8.77e+03 R= 2e+04
+Depth= 9553 States= 1.43e+08 Transitions= 2.75e+09 Memory= 7143.088 t= 8.82e+03 R= 2e+04
+Depth= 9553 States= 1.44e+08 Transitions= 2.77e+09 Memory= 7170.920 t= 8.88e+03 R= 2e+04
+Depth= 9553 States= 1.45e+08 Transitions= 2.79e+09 Memory= 7198.166 t= 8.94e+03 R= 2e+04
+Depth= 9553 States= 1.46e+08 Transitions= 2.82e+09 Memory= 7229.514 t= 9.06e+03 R= 2e+04
+Depth= 9553 States= 1.47e+08 Transitions= 2.86e+09 Memory= 7265.158 t= 9.18e+03 R= 2e+04
+Depth= 9553 States= 1.48e+08 Transitions= 2.91e+09 Memory= 7299.143 t= 9.34e+03 R= 2e+04
+Depth= 9553 States= 1.49e+08 Transitions= 2.95e+09 Memory= 7327.170 t= 9.47e+03 R= 2e+04
+Depth= 9553 States= 1.5e+08 Transitions= 2.99e+09 Memory= 7352.561 t= 9.59e+03 R= 2e+04
+Depth= 9553 States= 1.51e+08 Transitions= 3e+09 Memory= 7380.881 t= 9.64e+03 R= 2e+04
+Depth= 9553 States= 1.52e+08 Transitions= 3.02e+09 Memory= 7408.908 t= 9.7e+03 R= 2e+04
+Depth= 9553 States= 1.53e+08 Transitions= 3.05e+09 Memory= 7437.033 t= 9.8e+03 R= 2e+04
+Depth= 9553 States= 1.54e+08 Transitions= 3.08e+09 Memory= 7465.744 t= 9.89e+03 R= 2e+04
+Depth= 9553 States= 1.55e+08 Transitions= 3.1e+09 Memory= 7493.869 t= 9.95e+03 R= 2e+04
+Depth= 9553 States= 1.56e+08 Transitions= 3.11e+09 Memory= 7520.529 t= 9.99e+03 R= 2e+04
+Depth= 9553 States= 1.57e+08 Transitions= 3.13e+09 Memory= 7547.092 t= 1e+04 R= 2e+04
+Depth= 9553 States= 1.58e+08 Transitions= 3.14e+09 Memory= 7577.170 t= 1.01e+04 R= 2e+04
+Depth= 9553 States= 1.59e+08 Transitions= 3.17e+09 Memory= 7604.611 t= 1.02e+04 R= 2e+04
+Depth= 9553 States= 1.6e+08 Transitions= 3.19e+09 Memory= 7631.955 t= 1.02e+04 R= 2e+04
+Depth= 9553 States= 1.61e+08 Transitions= 3.21e+09 Memory= 7659.299 t= 1.03e+04 R= 2e+04
+Depth= 9553 States= 1.62e+08 Transitions= 3.24e+09 Memory= 7686.740 t= 1.04e+04 R= 2e+04
+Depth= 9553 States= 1.63e+08 Transitions= 3.27e+09 Memory= 7713.791 t= 1.05e+04 R= 2e+04
+Depth= 9553 States= 1.64e+08 Transitions= 3.29e+09 Memory= 7743.186 t= 1.06e+04 R= 2e+04
+Depth= 9553 States= 1.65e+08 Transitions= 3.31e+09 Memory= 7771.604 t= 1.06e+04 R= 2e+04
+Depth= 9553 States= 1.66e+08 Transitions= 3.34e+09 Memory= 7797.971 t= 1.07e+04 R= 2e+04
+Depth= 9553 States= 1.67e+08 Transitions= 3.37e+09 Memory= 7825.217 t= 1.08e+04 R= 2e+04
+Depth= 9553 States= 1.68e+08 Transitions= 3.39e+09 Memory= 7853.733 t= 1.09e+04 R= 2e+04
+Depth= 9553 States= 1.69e+08 Transitions= 3.41e+09 Memory= 7880.686 t= 1.09e+04 R= 2e+04
+Depth= 9553 States= 1.7e+08 Transitions= 3.44e+09 Memory= 7909.690 t= 1.1e+04 R= 2e+04
+Depth= 9553 States= 1.71e+08 Transitions= 3.46e+09 Memory= 7939.279 t= 1.11e+04 R= 2e+04
+Depth= 9553 States= 1.72e+08 Transitions= 3.47e+09 Memory= 7964.768 t= 1.11e+04 R= 2e+04
+Depth= 9553 States= 1.73e+08 Transitions= 3.5e+09 Memory= 7994.260 t= 1.12e+04 R= 2e+04
+Depth= 9553 States= 1.74e+08 Transitions= 3.52e+09 Memory= 8023.850 t= 1.13e+04 R= 2e+04
+Depth= 9553 States= 1.75e+08 Transitions= 3.53e+09 Memory= 8051.877 t= 1.13e+04 R= 2e+04
+Depth= 9553 States= 1.76e+08 Transitions= 3.56e+09 Memory= 8080.979 t= 1.14e+04 R= 2e+04
+Depth= 9553 States= 1.77e+08 Transitions= 3.57e+09 Memory= 8107.834 t= 1.15e+04 R= 2e+04
+Depth= 9553 States= 1.78e+08 Transitions= 3.59e+09 Memory= 8137.033 t= 1.15e+04 R= 2e+04
+Depth= 9553 States= 1.79e+08 Transitions= 3.61e+09 Memory= 8165.158 t= 1.16e+04 R= 2e+04
+Depth= 9553 States= 1.8e+08 Transitions= 3.63e+09 Memory= 8194.065 t= 1.16e+04 R= 2e+04
+Depth= 9553 States= 1.81e+08 Transitions= 3.65e+09 Memory= 8222.971 t= 1.17e+04 R= 2e+04
+Depth= 9553 States= 1.82e+08 Transitions= 3.66e+09 Memory= 8251.096 t= 1.17e+04 R= 2e+04
+Depth= 9553 States= 1.83e+08 Transitions= 3.68e+09 Memory= 8279.514 t= 1.18e+04 R= 2e+04
+Depth= 9553 States= 1.84e+08 Transitions= 3.69e+09 Memory= 8307.151 t= 1.18e+04 R= 2e+04
+Depth= 9553 States= 1.85e+08 Transitions= 3.71e+09 Memory= 8334.787 t= 1.19e+04 R= 2e+04
+Depth= 9553 States= 1.86e+08 Transitions= 3.73e+09 Memory= 8361.838 t= 1.2e+04 R= 2e+04
+Depth= 9553 States= 1.87e+08 Transitions= 3.75e+09 Memory= 8392.209 t= 1.2e+04 R= 2e+04
+Depth= 9553 States= 1.88e+08 Transitions= 3.77e+09 Memory= 8423.361 t= 1.21e+04 R= 2e+04
+Depth= 9553 States= 1.89e+08 Transitions= 3.78e+09 Memory= 8449.826 t= 1.21e+04 R= 2e+04
+Depth= 9553 States= 1.9e+08 Transitions= 3.8e+09 Memory= 8479.026 t= 1.22e+04 R= 2e+04
+Depth= 9553 States= 1.91e+08 Transitions= 3.82e+09 Memory= 8506.076 t= 1.22e+04 R= 2e+04
+Depth= 9553 States= 1.92e+08 Transitions= 3.84e+09 Memory= 8533.029 t= 1.23e+04 R= 2e+04
+Depth= 9553 States= 1.93e+08 Transitions= 3.86e+09 Memory= 8563.889 t= 1.24e+04 R= 2e+04
+Depth= 9553 States= 1.94e+08 Transitions= 3.88e+09 Memory= 8590.744 t= 1.24e+04 R= 2e+04
+Depth= 9553 States= 1.95e+08 Transitions= 3.9e+09 Memory= 8620.334 t= 1.25e+04 R= 2e+04
+Depth= 9553 States= 1.96e+08 Transitions= 3.92e+09 Memory= 8649.826 t= 1.25e+04 R= 2e+04
+Depth= 9553 States= 1.97e+08 Transitions= 3.93e+09 Memory= 8676.486 t= 1.26e+04 R= 2e+04
+Depth= 9553 States= 1.98e+08 Transitions= 3.95e+09 Memory= 8705.197 t= 1.26e+04 R= 2e+04
+Depth= 9553 States= 1.99e+08 Transitions= 3.96e+09 Memory= 8734.006 t= 1.27e+04 R= 2e+04
+Depth= 9553 States= 2e+08 Transitions= 3.98e+09 Memory= 8764.279 t= 1.27e+04 R= 2e+04
+Depth= 9553 States= 2.01e+08 Transitions= 4e+09 Memory= 8792.209 t= 1.28e+04 R= 2e+04
+Depth= 9553 States= 2.02e+08 Transitions= 4.03e+09 Memory= 8821.408 t= 1.29e+04 R= 2e+04
+Depth= 9553 States= 2.03e+08 Transitions= 4.04e+09 Memory= 8849.338 t= 1.29e+04 R= 2e+04
+Depth= 9553 States= 2.04e+08 Transitions= 4.06e+09 Memory= 8878.733 t= 1.3e+04 R= 2e+04
+Depth= 9553 States= 2.05e+08 Transitions= 4.08e+09 Memory= 8908.322 t= 1.31e+04 R= 2e+04
+Depth= 9553 States= 2.06e+08 Transitions= 4.09e+09 Memory= 8934.494 t= 1.31e+04 R= 2e+04
+Depth= 9553 States= 2.07e+08 Transitions= 4.11e+09 Memory= 8963.498 t= 1.32e+04 R= 2e+04
+Depth= 9553 States= 2.08e+08 Transitions= 4.13e+09 Memory= 8991.818 t= 1.32e+04 R= 2e+04
+Depth= 9553 States= 2.09e+08 Transitions= 4.14e+09 Memory= 9022.287 t= 1.33e+04 R= 2e+04
+Depth= 9553 States= 2.1e+08 Transitions= 4.16e+09 Memory= 9047.580 t= 1.33e+04 R= 2e+04
+Depth= 9553 States= 2.11e+08 Transitions= 4.18e+09 Memory= 9075.412 t= 1.34e+04 R= 2e+04
+Depth= 9553 States= 2.12e+08 Transitions= 4.19e+09 Memory= 9103.244 t= 1.34e+04 R= 2e+04
+Depth= 9553 States= 2.13e+08 Transitions= 4.21e+09 Memory= 9131.467 t= 1.35e+04 R= 2e+04
+Depth= 9553 States= 2.14e+08 Transitions= 4.22e+09 Memory= 9159.006 t= 1.35e+04 R= 2e+04
+Depth= 9553 States= 2.15e+08 Transitions= 4.26e+09 Memory= 9188.010 t= 1.36e+04 R= 2e+04
+Depth= 9553 States= 2.16e+08 Transitions= 4.29e+09 Memory= 9218.283 t= 1.37e+04 R= 2e+04
+Depth= 9553 States= 2.17e+08 Transitions= 4.3e+09 Memory= 9246.897 t= 1.37e+04 R= 2e+04
+Depth= 9553 States= 2.18e+08 Transitions= 4.32e+09 Memory= 9276.193 t= 1.38e+04 R= 2e+04
+Depth= 9553 States= 2.19e+08 Transitions= 4.33e+09 Memory= 9305.002 t= 1.39e+04 R= 2e+04
+Depth= 9553 States= 2.2e+08 Transitions= 4.35e+09 Memory= 9334.299 t= 1.39e+04 R= 2e+04
+Depth= 9553 States= 2.21e+08 Transitions= 4.37e+09 Memory= 9362.619 t= 1.4e+04 R= 2e+04
+Depth= 9553 States= 2.22e+08 Transitions= 4.4e+09 Memory= 9388.108 t= 1.41e+04 R= 2e+04
+Depth= 9553 States= 2.23e+08 Transitions= 4.43e+09 Memory= 9415.354 t= 1.42e+04 R= 2e+04
+Depth= 9553 States= 2.24e+08 Transitions= 4.45e+09 Memory= 9442.111 t= 1.42e+04 R= 2e+04
+Depth= 9553 States= 2.25e+08 Transitions= 4.48e+09 Memory= 9468.967 t= 1.43e+04 R= 2e+04
+Depth= 9553 States= 2.26e+08 Transitions= 4.5e+09 Memory= 9495.041 t= 1.44e+04 R= 2e+04
+Depth= 9553 States= 2.27e+08 Transitions= 4.52e+09 Memory= 9522.580 t= 1.44e+04 R= 2e+04
+Depth= 9553 States= 2.28e+08 Transitions= 4.54e+09 Memory= 9549.631 t= 1.45e+04 R= 2e+04
+Depth= 9553 States= 2.29e+08 Transitions= 4.56e+09 Memory= 9576.096 t= 1.46e+04 R= 2e+04
+Depth= 9553 States= 2.3e+08 Transitions= 4.59e+09 Memory= 9602.268 t= 1.47e+04 R= 2e+04
+Depth= 9553 States= 2.31e+08 Transitions= 4.6e+09 Memory= 9630.197 t= 1.47e+04 R= 2e+04
+Depth= 9553 States= 2.32e+08 Transitions= 4.63e+09 Memory= 9656.858 t= 1.48e+04 R= 2e+04
+Depth= 9553 States= 2.33e+08 Transitions= 4.66e+09 Memory= 9683.713 t= 1.49e+04 R= 2e+04
+Depth= 9553 States= 2.34e+08 Transitions= 4.68e+09 Memory= 9710.373 t= 1.5e+04 R= 2e+04
+Depth= 9553 States= 2.35e+08 Transitions= 4.7e+09 Memory= 9738.108 t= 1.5e+04 R= 2e+04
+Depth= 9553 States= 2.36e+08 Transitions= 4.72e+09 Memory= 9765.158 t= 1.51e+04 R= 2e+04
+Depth= 9553 States= 2.37e+08 Transitions= 4.74e+09 Memory= 9792.404 t= 1.52e+04 R= 2e+04
+Depth= 9553 States= 2.38e+08 Transitions= 4.77e+09 Memory= 9818.576 t= 1.52e+04 R= 2e+04
+Depth= 9553 States= 2.39e+08 Transitions= 4.79e+09 Memory= 9845.432 t= 1.53e+04 R= 2e+04
+Depth= 9553 States= 2.4e+08 Transitions= 4.8e+09 Memory= 9871.701 t= 1.53e+04 R= 2e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 9553, errors: 0
+1.4728139e+08 states, stored (2.40187e+08 visited)
+4.565323e+09 states, matched
+4.8055096e+09 transitions (= visited+matched)
+7.4787137e+10 atomic steps
+hash conflicts: 1.0275497e+09 (resolved)
+
+Stats on memory usage (in Megabytes):
+16293.183 equivalent memory usage for states (stored*(State-vector + overhead))
+ 7372.383 actual memory usage for states (compression: 45.25%)
+ state-vector as stored = 16 byte + 36 byte overhead
+ 2048.000 memory used for hash table (-w28)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1.367 memory lost to fragmentation
+ 9876.779 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 592075 4097 3828 2 2 ]
+unreached in proctype urcu_reader
+ line 268, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 276, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 104, "(1)"
+ line 249, "pan.___", state 112, "(1)"
+ line 253, "pan.___", state 124, "(1)"
+ line 257, "pan.___", state 132, "(1)"
+ line 407, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 222, "(1)"
+ line 253, "pan.___", state 242, "(1)"
+ line 257, "pan.___", state 250, "(1)"
+ line 687, "pan.___", state 269, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 407, "pan.___", state 276, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 308, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 322, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 340, "(1)"
+ line 253, "pan.___", state 360, "(1)"
+ line 257, "pan.___", state 368, "(1)"
+ line 407, "pan.___", state 387, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 419, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 433, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 451, "(1)"
+ line 253, "pan.___", state 471, "(1)"
+ line 257, "pan.___", state 479, "(1)"
+ line 407, "pan.___", state 500, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 502, "(1)"
+ line 407, "pan.___", state 503, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 503, "else"
+ line 407, "pan.___", state 506, "(1)"
+ line 411, "pan.___", state 514, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 516, "(1)"
+ line 411, "pan.___", state 517, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 517, "else"
+ line 411, "pan.___", state 520, "(1)"
+ line 411, "pan.___", state 521, "(1)"
+ line 411, "pan.___", state 521, "(1)"
+ line 409, "pan.___", state 526, "((i<1))"
+ line 409, "pan.___", state 526, "((i>=1))"
+ line 416, "pan.___", state 532, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 534, "(1)"
+ line 416, "pan.___", state 535, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 535, "else"
+ line 416, "pan.___", state 538, "(1)"
+ line 416, "pan.___", state 539, "(1)"
+ line 416, "pan.___", state 539, "(1)"
+ line 420, "pan.___", state 546, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 548, "(1)"
+ line 420, "pan.___", state 549, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 549, "else"
+ line 420, "pan.___", state 552, "(1)"
+ line 420, "pan.___", state 553, "(1)"
+ line 420, "pan.___", state 553, "(1)"
+ line 418, "pan.___", state 558, "((i<2))"
+ line 418, "pan.___", state 558, "((i>=2))"
+ line 245, "pan.___", state 564, "(1)"
+ line 249, "pan.___", state 572, "(1)"
+ line 249, "pan.___", state 573, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 573, "else"
+ line 247, "pan.___", state 578, "((i<1))"
+ line 247, "pan.___", state 578, "((i>=1))"
+ line 253, "pan.___", state 584, "(1)"
+ line 253, "pan.___", state 585, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 585, "else"
+ line 257, "pan.___", state 592, "(1)"
+ line 257, "pan.___", state 593, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 593, "else"
+ line 255, "pan.___", state 598, "((i<2))"
+ line 255, "pan.___", state 598, "((i>=2))"
+ line 262, "pan.___", state 602, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 602, "else"
+ line 427, "pan.___", state 604, "(1)"
+ line 427, "pan.___", state 604, "(1)"
+ line 687, "pan.___", state 607, "cached_urcu_active_readers = (tmp+1)"
+ line 687, "pan.___", state 608, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 687, "pan.___", state 609, "(1)"
+ line 407, "pan.___", state 616, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 648, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 662, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 680, "(1)"
+ line 253, "pan.___", state 700, "(1)"
+ line 257, "pan.___", state 708, "(1)"
+ line 407, "pan.___", state 734, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 766, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 780, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 798, "(1)"
+ line 253, "pan.___", state 818, "(1)"
+ line 257, "pan.___", state 826, "(1)"
+ line 407, "pan.___", state 845, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 847, "(1)"
+ line 407, "pan.___", state 848, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 848, "else"
+ line 407, "pan.___", state 851, "(1)"
+ line 411, "pan.___", state 859, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 861, "(1)"
+ line 411, "pan.___", state 862, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 862, "else"
+ line 411, "pan.___", state 865, "(1)"
+ line 411, "pan.___", state 866, "(1)"
+ line 411, "pan.___", state 866, "(1)"
+ line 409, "pan.___", state 871, "((i<1))"
+ line 409, "pan.___", state 871, "((i>=1))"
+ line 416, "pan.___", state 877, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 879, "(1)"
+ line 416, "pan.___", state 880, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 880, "else"
+ line 416, "pan.___", state 883, "(1)"
+ line 416, "pan.___", state 884, "(1)"
+ line 416, "pan.___", state 884, "(1)"
+ line 420, "pan.___", state 891, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 893, "(1)"
+ line 420, "pan.___", state 894, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 894, "else"
+ line 420, "pan.___", state 897, "(1)"
+ line 420, "pan.___", state 898, "(1)"
+ line 420, "pan.___", state 898, "(1)"
+ line 418, "pan.___", state 903, "((i<2))"
+ line 418, "pan.___", state 903, "((i>=2))"
+ line 245, "pan.___", state 909, "(1)"
+ line 249, "pan.___", state 917, "(1)"
+ line 249, "pan.___", state 918, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 918, "else"
+ line 247, "pan.___", state 923, "((i<1))"
+ line 247, "pan.___", state 923, "((i>=1))"
+ line 253, "pan.___", state 929, "(1)"
+ line 253, "pan.___", state 930, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 930, "else"
+ line 257, "pan.___", state 937, "(1)"
+ line 257, "pan.___", state 938, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 938, "else"
+ line 255, "pan.___", state 943, "((i<2))"
+ line 255, "pan.___", state 943, "((i>=2))"
+ line 262, "pan.___", state 947, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 947, "else"
+ line 427, "pan.___", state 949, "(1)"
+ line 427, "pan.___", state 949, "(1)"
+ line 695, "pan.___", state 953, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 407, "pan.___", state 958, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 990, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1004, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1022, "(1)"
+ line 253, "pan.___", state 1042, "(1)"
+ line 257, "pan.___", state 1050, "(1)"
+ line 407, "pan.___", state 1072, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1104, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1118, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1136, "(1)"
+ line 253, "pan.___", state 1156, "(1)"
+ line 257, "pan.___", state 1164, "(1)"
+ line 407, "pan.___", state 1187, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1219, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1233, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1251, "(1)"
+ line 253, "pan.___", state 1271, "(1)"
+ line 257, "pan.___", state 1279, "(1)"
+ line 407, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1330, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1344, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1362, "(1)"
+ line 253, "pan.___", state 1382, "(1)"
+ line 257, "pan.___", state 1390, "(1)"
+ line 407, "pan.___", state 1414, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1446, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1460, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1478, "(1)"
+ line 253, "pan.___", state 1498, "(1)"
+ line 257, "pan.___", state 1506, "(1)"
+ line 407, "pan.___", state 1525, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1557, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1571, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1589, "(1)"
+ line 253, "pan.___", state 1609, "(1)"
+ line 257, "pan.___", state 1617, "(1)"
+ line 407, "pan.___", state 1639, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1671, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1685, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1703, "(1)"
+ line 253, "pan.___", state 1723, "(1)"
+ line 257, "pan.___", state 1731, "(1)"
+ line 734, "pan.___", state 1750, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 407, "pan.___", state 1757, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1789, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1803, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1821, "(1)"
+ line 253, "pan.___", state 1841, "(1)"
+ line 257, "pan.___", state 1849, "(1)"
+ line 407, "pan.___", state 1868, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 1900, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 1914, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1932, "(1)"
+ line 253, "pan.___", state 1952, "(1)"
+ line 257, "pan.___", state 1960, "(1)"
+ line 407, "pan.___", state 1981, "cache_dirty_urcu_gp_ctr = 0"
+ line 407, "pan.___", state 1983, "(1)"
+ line 407, "pan.___", state 1984, "(cache_dirty_urcu_gp_ctr)"
+ line 407, "pan.___", state 1984, "else"
+ line 407, "pan.___", state 1987, "(1)"
+ line 411, "pan.___", state 1995, "cache_dirty_urcu_active_readers = 0"
+ line 411, "pan.___", state 1997, "(1)"
+ line 411, "pan.___", state 1998, "(cache_dirty_urcu_active_readers)"
+ line 411, "pan.___", state 1998, "else"
+ line 411, "pan.___", state 2001, "(1)"
+ line 411, "pan.___", state 2002, "(1)"
+ line 411, "pan.___", state 2002, "(1)"
+ line 409, "pan.___", state 2007, "((i<1))"
+ line 409, "pan.___", state 2007, "((i>=1))"
+ line 416, "pan.___", state 2013, "cache_dirty_rcu_ptr = 0"
+ line 416, "pan.___", state 2015, "(1)"
+ line 416, "pan.___", state 2016, "(cache_dirty_rcu_ptr)"
+ line 416, "pan.___", state 2016, "else"
+ line 416, "pan.___", state 2019, "(1)"
+ line 416, "pan.___", state 2020, "(1)"
+ line 416, "pan.___", state 2020, "(1)"
+ line 420, "pan.___", state 2027, "cache_dirty_rcu_data[i] = 0"
+ line 420, "pan.___", state 2029, "(1)"
+ line 420, "pan.___", state 2030, "(cache_dirty_rcu_data[i])"
+ line 420, "pan.___", state 2030, "else"
+ line 420, "pan.___", state 2033, "(1)"
+ line 420, "pan.___", state 2034, "(1)"
+ line 420, "pan.___", state 2034, "(1)"
+ line 418, "pan.___", state 2039, "((i<2))"
+ line 418, "pan.___", state 2039, "((i>=2))"
+ line 245, "pan.___", state 2045, "(1)"
+ line 249, "pan.___", state 2053, "(1)"
+ line 249, "pan.___", state 2054, "(!(cache_dirty_urcu_active_readers))"
+ line 249, "pan.___", state 2054, "else"
+ line 247, "pan.___", state 2059, "((i<1))"
+ line 247, "pan.___", state 2059, "((i>=1))"
+ line 253, "pan.___", state 2065, "(1)"
+ line 253, "pan.___", state 2066, "(!(cache_dirty_rcu_ptr))"
+ line 253, "pan.___", state 2066, "else"
+ line 257, "pan.___", state 2073, "(1)"
+ line 257, "pan.___", state 2074, "(!(cache_dirty_rcu_data[i]))"
+ line 257, "pan.___", state 2074, "else"
+ line 255, "pan.___", state 2079, "((i<2))"
+ line 255, "pan.___", state 2079, "((i>=2))"
+ line 262, "pan.___", state 2083, "(!(cache_dirty_urcu_gp_ctr))"
+ line 262, "pan.___", state 2083, "else"
+ line 427, "pan.___", state 2085, "(1)"
+ line 427, "pan.___", state 2085, "(1)"
+ line 734, "pan.___", state 2088, "cached_urcu_active_readers = (tmp+1)"
+ line 734, "pan.___", state 2089, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 734, "pan.___", state 2090, "(1)"
+ line 407, "pan.___", state 2097, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2129, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2143, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2161, "(1)"
+ line 253, "pan.___", state 2181, "(1)"
+ line 257, "pan.___", state 2189, "(1)"
+ line 407, "pan.___", state 2214, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2246, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2260, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2278, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2306, "(1)"
+ line 407, "pan.___", state 2325, "cache_dirty_urcu_gp_ctr = 0"
+ line 416, "pan.___", state 2357, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 2371, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 2389, "(1)"
+ line 253, "pan.___", state 2409, "(1)"
+ line 257, "pan.___", state 2417, "(1)"
+ line 245, "pan.___", state 2448, "(1)"
+ line 253, "pan.___", state 2468, "(1)"
+ line 257, "pan.___", state 2476, "(1)"
+ line 245, "pan.___", state 2491, "(1)"
+ line 253, "pan.___", state 2511, "(1)"
+ line 257, "pan.___", state 2519, "(1)"
+ line 929, "pan.___", state 2536, "-end-"
+ (221 of 2536 states)
+unreached in proctype urcu_writer
+ line 407, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 245, "pan.___", state 109, "(1)"
+ line 249, "pan.___", state 117, "(1)"
+ line 253, "pan.___", state 129, "(1)"
+ line 268, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 167, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 180, "cache_dirty_rcu_ptr = 0"
+ line 407, "pan.___", state 220, "cache_dirty_urcu_gp_ctr = 0"
+ line 411, "pan.___", state 234, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 252, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 266, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 284, "(1)"
+ line 249, "pan.___", state 292, "(1)"
+ line 253, "pan.___", state 304, "(1)"
+ line 257, "pan.___", state 312, "(1)"
+ line 411, "pan.___", state 347, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 365, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 379, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 405, "(1)"
+ line 253, "pan.___", state 417, "(1)"
+ line 257, "pan.___", state 425, "(1)"
+ line 411, "pan.___", state 468, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 486, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 500, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 526, "(1)"
+ line 253, "pan.___", state 538, "(1)"
+ line 257, "pan.___", state 546, "(1)"
+ line 411, "pan.___", state 579, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 597, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 611, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 637, "(1)"
+ line 253, "pan.___", state 649, "(1)"
+ line 257, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 692, "cache_dirty_urcu_active_readers = 0"
+ line 416, "pan.___", state 710, "cache_dirty_rcu_ptr = 0"
+ line 420, "pan.___", state 724, "cache_dirty_rcu_data[i] = 0"
+ line 249, "pan.___", state 750, "(1)"
+ line 253, "pan.___", state 762, "(1)"
+ line 257, "pan.___", state 770, "(1)"
+ line 268, "pan.___", state 823, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 832, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 847, "(1)"
+ line 280, "pan.___", state 854, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 870, "(1)"
+ line 249, "pan.___", state 878, "(1)"
+ line 253, "pan.___", state 890, "(1)"
+ line 257, "pan.___", state 898, "(1)"
+ line 268, "pan.___", state 929, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 938, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 951, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 960, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 976, "(1)"
+ line 249, "pan.___", state 984, "(1)"
+ line 253, "pan.___", state 996, "(1)"
+ line 257, "pan.___", state 1004, "(1)"
+ line 272, "pan.___", state 1030, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1043, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1052, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1068, "(1)"
+ line 249, "pan.___", state 1076, "(1)"
+ line 253, "pan.___", state 1088, "(1)"
+ line 257, "pan.___", state 1096, "(1)"
+ line 268, "pan.___", state 1127, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1136, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1149, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1158, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1174, "(1)"
+ line 249, "pan.___", state 1182, "(1)"
+ line 253, "pan.___", state 1194, "(1)"
+ line 257, "pan.___", state 1202, "(1)"
+ line 272, "pan.___", state 1228, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1241, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1250, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1266, "(1)"
+ line 249, "pan.___", state 1274, "(1)"
+ line 253, "pan.___", state 1286, "(1)"
+ line 257, "pan.___", state 1294, "(1)"
+ line 268, "pan.___", state 1325, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1334, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1347, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1356, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1372, "(1)"
+ line 249, "pan.___", state 1380, "(1)"
+ line 253, "pan.___", state 1392, "(1)"
+ line 257, "pan.___", state 1400, "(1)"
+ line 272, "pan.___", state 1426, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1439, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1448, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1464, "(1)"
+ line 249, "pan.___", state 1472, "(1)"
+ line 253, "pan.___", state 1484, "(1)"
+ line 257, "pan.___", state 1492, "(1)"
+ line 268, "pan.___", state 1523, "cache_dirty_urcu_gp_ctr = 0"
+ line 272, "pan.___", state 1532, "cache_dirty_urcu_active_readers = 0"
+ line 276, "pan.___", state 1545, "cache_dirty_rcu_ptr = 0"
+ line 280, "pan.___", state 1554, "cache_dirty_rcu_data[i] = 0"
+ line 245, "pan.___", state 1570, "(1)"
+ line 249, "pan.___", state 1578, "(1)"
+ line 253, "pan.___", state 1590, "(1)"
+ line 257, "pan.___", state 1598, "(1)"
+ line 1304, "pan.___", state 1614, "-end-"
+ (103 of 1614 states)
+unreached in proctype :init:
+ (0 of 28 states)
+unreached in proctype :never:
+ line 1369, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 1.54e+04 seconds
+pan: rate 15645.145 states/second
+pan: avg transition delay 3.1947e-06 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DCOLLAPSE -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1363)
+depth 7: Claim reached state 9 (line 1368)
+depth 50: Claim reached state 9 (line 1367)
+Depth= 7070 States= 1e+06 Transitions= 1.16e+07 Memory= 492.912 t= 33.7 R= 3e+04
+Depth= 7070 States= 2e+06 Transitions= 2.31e+07 Memory= 521.233 t= 68 R= 3e+04
+Depth= 7070 States= 3e+06 Transitions= 3.43e+07 Memory= 549.358 t= 102 R= 3e+04
+pan: resizing hashtable to -w22.. done
+pan: acceptance cycle (at depth 1558)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+ + Compression
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 80 byte, depth reached 7070, errors: 1
+ 1856640 states, stored (3.13554e+06 visited)
+ 32657997 states, matched
+ 35793542 transitions (= visited+matched)
+5.1088012e+08 atomic steps
+hash conflicts: 10885217 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 205.393 equivalent memory usage for states (stored*(State-vector + overhead))
+ 93.456 actual memory usage for states (compression: 45.50%)
+ state-vector as stored = 17 byte + 36 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 583.115 total actual memory usage
+
+nr of templates: [ globals chans procs ]
+collapse counts: [ 12368 744 254 2 2 ]
+unreached in proctype urcu_reader
+ line 269, "pan.___", state 57, "cache_dirty_urcu_gp_ctr = 0"
+ line 277, "pan.___", state 79, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 88, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 104, "(1)"
+ line 250, "pan.___", state 112, "(1)"
+ line 254, "pan.___", state 124, "(1)"
+ line 258, "pan.___", state 132, "(1)"
+ line 408, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 190, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 204, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 222, "(1)"
+ line 254, "pan.___", state 242, "(1)"
+ line 258, "pan.___", state 250, "(1)"
+ line 688, "pan.___", state 269, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 408, "pan.___", state 276, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 308, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 322, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 340, "(1)"
+ line 254, "pan.___", state 360, "(1)"
+ line 258, "pan.___", state 368, "(1)"
+ line 408, "pan.___", state 387, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 419, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 433, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 451, "(1)"
+ line 254, "pan.___", state 471, "(1)"
+ line 258, "pan.___", state 479, "(1)"
+ line 408, "pan.___", state 500, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 502, "(1)"
+ line 408, "pan.___", state 503, "(cache_dirty_urcu_gp_ctr)"
+ line 408, "pan.___", state 503, "else"
+ line 408, "pan.___", state 506, "(1)"
+ line 412, "pan.___", state 514, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 516, "(1)"
+ line 412, "pan.___", state 517, "(cache_dirty_urcu_active_readers)"
+ line 412, "pan.___", state 517, "else"
+ line 412, "pan.___", state 520, "(1)"
+ line 412, "pan.___", state 521, "(1)"
+ line 412, "pan.___", state 521, "(1)"
+ line 410, "pan.___", state 526, "((i<1))"
+ line 410, "pan.___", state 526, "((i>=1))"
+ line 417, "pan.___", state 532, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 534, "(1)"
+ line 417, "pan.___", state 535, "(cache_dirty_rcu_ptr)"
+ line 417, "pan.___", state 535, "else"
+ line 417, "pan.___", state 538, "(1)"
+ line 417, "pan.___", state 539, "(1)"
+ line 417, "pan.___", state 539, "(1)"
+ line 421, "pan.___", state 546, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 548, "(1)"
+ line 421, "pan.___", state 549, "(cache_dirty_rcu_data[i])"
+ line 421, "pan.___", state 549, "else"
+ line 421, "pan.___", state 552, "(1)"
+ line 421, "pan.___", state 553, "(1)"
+ line 421, "pan.___", state 553, "(1)"
+ line 419, "pan.___", state 558, "((i<2))"
+ line 419, "pan.___", state 558, "((i>=2))"
+ line 246, "pan.___", state 564, "(1)"
+ line 250, "pan.___", state 572, "(1)"
+ line 250, "pan.___", state 573, "(!(cache_dirty_urcu_active_readers))"
+ line 250, "pan.___", state 573, "else"
+ line 248, "pan.___", state 578, "((i<1))"
+ line 248, "pan.___", state 578, "((i>=1))"
+ line 254, "pan.___", state 584, "(1)"
+ line 254, "pan.___", state 585, "(!(cache_dirty_rcu_ptr))"
+ line 254, "pan.___", state 585, "else"
+ line 258, "pan.___", state 592, "(1)"
+ line 258, "pan.___", state 593, "(!(cache_dirty_rcu_data[i]))"
+ line 258, "pan.___", state 593, "else"
+ line 256, "pan.___", state 598, "((i<2))"
+ line 256, "pan.___", state 598, "((i>=2))"
+ line 263, "pan.___", state 602, "(!(cache_dirty_urcu_gp_ctr))"
+ line 263, "pan.___", state 602, "else"
+ line 428, "pan.___", state 604, "(1)"
+ line 428, "pan.___", state 604, "(1)"
+ line 688, "pan.___", state 607, "cached_urcu_active_readers = (tmp+1)"
+ line 688, "pan.___", state 608, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 688, "pan.___", state 609, "(1)"
+ line 408, "pan.___", state 616, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 648, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 662, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 680, "(1)"
+ line 254, "pan.___", state 700, "(1)"
+ line 258, "pan.___", state 708, "(1)"
+ line 408, "pan.___", state 734, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 766, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 780, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 798, "(1)"
+ line 254, "pan.___", state 818, "(1)"
+ line 258, "pan.___", state 826, "(1)"
+ line 408, "pan.___", state 845, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 847, "(1)"
+ line 408, "pan.___", state 848, "(cache_dirty_urcu_gp_ctr)"
+ line 408, "pan.___", state 848, "else"
+ line 408, "pan.___", state 851, "(1)"
+ line 412, "pan.___", state 859, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 861, "(1)"
+ line 412, "pan.___", state 862, "(cache_dirty_urcu_active_readers)"
+ line 412, "pan.___", state 862, "else"
+ line 412, "pan.___", state 865, "(1)"
+ line 412, "pan.___", state 866, "(1)"
+ line 412, "pan.___", state 866, "(1)"
+ line 410, "pan.___", state 871, "((i<1))"
+ line 410, "pan.___", state 871, "((i>=1))"
+ line 417, "pan.___", state 877, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 879, "(1)"
+ line 417, "pan.___", state 880, "(cache_dirty_rcu_ptr)"
+ line 417, "pan.___", state 880, "else"
+ line 417, "pan.___", state 883, "(1)"
+ line 417, "pan.___", state 884, "(1)"
+ line 417, "pan.___", state 884, "(1)"
+ line 421, "pan.___", state 891, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 893, "(1)"
+ line 421, "pan.___", state 894, "(cache_dirty_rcu_data[i])"
+ line 421, "pan.___", state 894, "else"
+ line 421, "pan.___", state 897, "(1)"
+ line 421, "pan.___", state 898, "(1)"
+ line 421, "pan.___", state 898, "(1)"
+ line 419, "pan.___", state 903, "((i<2))"
+ line 419, "pan.___", state 903, "((i>=2))"
+ line 246, "pan.___", state 909, "(1)"
+ line 250, "pan.___", state 917, "(1)"
+ line 250, "pan.___", state 918, "(!(cache_dirty_urcu_active_readers))"
+ line 250, "pan.___", state 918, "else"
+ line 248, "pan.___", state 923, "((i<1))"
+ line 248, "pan.___", state 923, "((i>=1))"
+ line 254, "pan.___", state 929, "(1)"
+ line 254, "pan.___", state 930, "(!(cache_dirty_rcu_ptr))"
+ line 254, "pan.___", state 930, "else"
+ line 258, "pan.___", state 937, "(1)"
+ line 258, "pan.___", state 938, "(!(cache_dirty_rcu_data[i]))"
+ line 258, "pan.___", state 938, "else"
+ line 256, "pan.___", state 943, "((i<2))"
+ line 256, "pan.___", state 943, "((i>=2))"
+ line 263, "pan.___", state 947, "(!(cache_dirty_urcu_gp_ctr))"
+ line 263, "pan.___", state 947, "else"
+ line 428, "pan.___", state 949, "(1)"
+ line 428, "pan.___", state 949, "(1)"
+ line 696, "pan.___", state 953, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 408, "pan.___", state 958, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 990, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1004, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1022, "(1)"
+ line 254, "pan.___", state 1042, "(1)"
+ line 258, "pan.___", state 1050, "(1)"
+ line 408, "pan.___", state 1072, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1104, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1118, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1136, "(1)"
+ line 254, "pan.___", state 1156, "(1)"
+ line 258, "pan.___", state 1164, "(1)"
+ line 408, "pan.___", state 1187, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1219, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1233, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1251, "(1)"
+ line 254, "pan.___", state 1271, "(1)"
+ line 258, "pan.___", state 1279, "(1)"
+ line 408, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1330, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1344, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1362, "(1)"
+ line 254, "pan.___", state 1382, "(1)"
+ line 258, "pan.___", state 1390, "(1)"
+ line 408, "pan.___", state 1414, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1446, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1460, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1478, "(1)"
+ line 254, "pan.___", state 1498, "(1)"
+ line 258, "pan.___", state 1506, "(1)"
+ line 408, "pan.___", state 1525, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1557, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1571, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1589, "(1)"
+ line 254, "pan.___", state 1609, "(1)"
+ line 258, "pan.___", state 1617, "(1)"
+ line 408, "pan.___", state 1639, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1671, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1685, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1703, "(1)"
+ line 254, "pan.___", state 1723, "(1)"
+ line 258, "pan.___", state 1731, "(1)"
+ line 735, "pan.___", state 1750, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 408, "pan.___", state 1757, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1789, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1803, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1821, "(1)"
+ line 254, "pan.___", state 1841, "(1)"
+ line 258, "pan.___", state 1849, "(1)"
+ line 408, "pan.___", state 1868, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 1900, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 1914, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1932, "(1)"
+ line 254, "pan.___", state 1952, "(1)"
+ line 258, "pan.___", state 1960, "(1)"
+ line 408, "pan.___", state 1981, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 1983, "(1)"
+ line 408, "pan.___", state 1984, "(cache_dirty_urcu_gp_ctr)"
+ line 408, "pan.___", state 1984, "else"
+ line 408, "pan.___", state 1987, "(1)"
+ line 412, "pan.___", state 1995, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 1997, "(1)"
+ line 412, "pan.___", state 1998, "(cache_dirty_urcu_active_readers)"
+ line 412, "pan.___", state 1998, "else"
+ line 412, "pan.___", state 2001, "(1)"
+ line 412, "pan.___", state 2002, "(1)"
+ line 412, "pan.___", state 2002, "(1)"
+ line 410, "pan.___", state 2007, "((i<1))"
+ line 410, "pan.___", state 2007, "((i>=1))"
+ line 417, "pan.___", state 2013, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 2015, "(1)"
+ line 417, "pan.___", state 2016, "(cache_dirty_rcu_ptr)"
+ line 417, "pan.___", state 2016, "else"
+ line 417, "pan.___", state 2019, "(1)"
+ line 417, "pan.___", state 2020, "(1)"
+ line 417, "pan.___", state 2020, "(1)"
+ line 421, "pan.___", state 2027, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 2029, "(1)"
+ line 421, "pan.___", state 2030, "(cache_dirty_rcu_data[i])"
+ line 421, "pan.___", state 2030, "else"
+ line 421, "pan.___", state 2033, "(1)"
+ line 421, "pan.___", state 2034, "(1)"
+ line 421, "pan.___", state 2034, "(1)"
+ line 419, "pan.___", state 2039, "((i<2))"
+ line 419, "pan.___", state 2039, "((i>=2))"
+ line 246, "pan.___", state 2045, "(1)"
+ line 250, "pan.___", state 2053, "(1)"
+ line 250, "pan.___", state 2054, "(!(cache_dirty_urcu_active_readers))"
+ line 250, "pan.___", state 2054, "else"
+ line 248, "pan.___", state 2059, "((i<1))"
+ line 248, "pan.___", state 2059, "((i>=1))"
+ line 254, "pan.___", state 2065, "(1)"
+ line 254, "pan.___", state 2066, "(!(cache_dirty_rcu_ptr))"
+ line 254, "pan.___", state 2066, "else"
+ line 258, "pan.___", state 2073, "(1)"
+ line 258, "pan.___", state 2074, "(!(cache_dirty_rcu_data[i]))"
+ line 258, "pan.___", state 2074, "else"
+ line 256, "pan.___", state 2079, "((i<2))"
+ line 256, "pan.___", state 2079, "((i>=2))"
+ line 263, "pan.___", state 2083, "(!(cache_dirty_urcu_gp_ctr))"
+ line 263, "pan.___", state 2083, "else"
+ line 428, "pan.___", state 2085, "(1)"
+ line 428, "pan.___", state 2085, "(1)"
+ line 735, "pan.___", state 2088, "cached_urcu_active_readers = (tmp+1)"
+ line 735, "pan.___", state 2089, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 735, "pan.___", state 2090, "(1)"
+ line 408, "pan.___", state 2097, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 2129, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 2143, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 2161, "(1)"
+ line 254, "pan.___", state 2181, "(1)"
+ line 258, "pan.___", state 2189, "(1)"
+ line 408, "pan.___", state 2214, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 2246, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 2260, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 2278, "(1)"
+ line 254, "pan.___", state 2298, "(1)"
+ line 258, "pan.___", state 2306, "(1)"
+ line 408, "pan.___", state 2325, "cache_dirty_urcu_gp_ctr = 0"
+ line 417, "pan.___", state 2357, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 2371, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 2389, "(1)"
+ line 254, "pan.___", state 2409, "(1)"
+ line 258, "pan.___", state 2417, "(1)"
+ line 246, "pan.___", state 2448, "(1)"
+ line 254, "pan.___", state 2468, "(1)"
+ line 258, "pan.___", state 2476, "(1)"
+ line 246, "pan.___", state 2491, "(1)"
+ line 254, "pan.___", state 2511, "(1)"
+ line 258, "pan.___", state 2519, "(1)"
+ line 930, "pan.___", state 2536, "-end-"
+ (221 of 2536 states)
+unreached in proctype urcu_writer
+ line 408, "pan.___", state 45, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 59, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 77, "cache_dirty_rcu_ptr = 0"
+ line 246, "pan.___", state 109, "(1)"
+ line 250, "pan.___", state 117, "(1)"
+ line 254, "pan.___", state 129, "(1)"
+ line 269, "pan.___", state 158, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 167, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 180, "cache_dirty_rcu_ptr = 0"
+ line 408, "pan.___", state 220, "cache_dirty_urcu_gp_ctr = 0"
+ line 412, "pan.___", state 234, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 252, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 266, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 284, "(1)"
+ line 250, "pan.___", state 292, "(1)"
+ line 254, "pan.___", state 304, "(1)"
+ line 258, "pan.___", state 312, "(1)"
+ line 412, "pan.___", state 347, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 365, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 379, "cache_dirty_rcu_data[i] = 0"
+ line 250, "pan.___", state 405, "(1)"
+ line 254, "pan.___", state 417, "(1)"
+ line 258, "pan.___", state 425, "(1)"
+ line 408, "pan.___", state 450, "cache_dirty_urcu_gp_ctr = 0"
+ line 408, "pan.___", state 452, "(1)"
+ line 408, "pan.___", state 453, "(cache_dirty_urcu_gp_ctr)"
+ line 408, "pan.___", state 453, "else"
+ line 408, "pan.___", state 456, "(1)"
+ line 412, "pan.___", state 464, "cache_dirty_urcu_active_readers = 0"
+ line 412, "pan.___", state 466, "(1)"
+ line 412, "pan.___", state 467, "(cache_dirty_urcu_active_readers)"
+ line 412, "pan.___", state 467, "else"
+ line 412, "pan.___", state 470, "(1)"
+ line 412, "pan.___", state 471, "(1)"
+ line 412, "pan.___", state 471, "(1)"
+ line 410, "pan.___", state 476, "((i<1))"
+ line 410, "pan.___", state 476, "((i>=1))"
+ line 417, "pan.___", state 482, "cache_dirty_rcu_ptr = 0"
+ line 417, "pan.___", state 484, "(1)"
+ line 417, "pan.___", state 485, "(cache_dirty_rcu_ptr)"
+ line 417, "pan.___", state 485, "else"
+ line 417, "pan.___", state 488, "(1)"
+ line 417, "pan.___", state 489, "(1)"
+ line 417, "pan.___", state 489, "(1)"
+ line 421, "pan.___", state 496, "cache_dirty_rcu_data[i] = 0"
+ line 421, "pan.___", state 498, "(1)"
+ line 421, "pan.___", state 499, "(cache_dirty_rcu_data[i])"
+ line 421, "pan.___", state 499, "else"
+ line 421, "pan.___", state 502, "(1)"
+ line 421, "pan.___", state 503, "(1)"
+ line 421, "pan.___", state 503, "(1)"
+ line 419, "pan.___", state 508, "((i<2))"
+ line 419, "pan.___", state 508, "((i>=2))"
+ line 246, "pan.___", state 514, "(1)"
+ line 250, "pan.___", state 522, "(1)"
+ line 250, "pan.___", state 523, "(!(cache_dirty_urcu_active_readers))"
+ line 250, "pan.___", state 523, "else"
+ line 248, "pan.___", state 528, "((i<1))"
+ line 248, "pan.___", state 528, "((i>=1))"
+ line 254, "pan.___", state 534, "(1)"
+ line 254, "pan.___", state 535, "(!(cache_dirty_rcu_ptr))"
+ line 254, "pan.___", state 535, "else"
+ line 258, "pan.___", state 542, "(1)"
+ line 258, "pan.___", state 543, "(!(cache_dirty_rcu_data[i]))"
+ line 258, "pan.___", state 543, "else"
+ line 263, "pan.___", state 552, "(!(cache_dirty_urcu_gp_ctr))"
+ line 263, "pan.___", state 552, "else"
+ line 428, "pan.___", state 554, "(1)"
+ line 428, "pan.___", state 554, "(1)"
+ line 412, "pan.___", state 574, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 592, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 606, "cache_dirty_rcu_data[i] = 0"
+ line 250, "pan.___", state 632, "(1)"
+ line 254, "pan.___", state 644, "(1)"
+ line 258, "pan.___", state 652, "(1)"
+ line 412, "pan.___", state 685, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 703, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 717, "cache_dirty_rcu_data[i] = 0"
+ line 250, "pan.___", state 743, "(1)"
+ line 254, "pan.___", state 755, "(1)"
+ line 258, "pan.___", state 763, "(1)"
+ line 412, "pan.___", state 798, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 816, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 830, "cache_dirty_rcu_data[i] = 0"
+ line 250, "pan.___", state 856, "(1)"
+ line 254, "pan.___", state 868, "(1)"
+ line 258, "pan.___", state 876, "(1)"
+ line 412, "pan.___", state 914, "cache_dirty_urcu_active_readers = 0"
+ line 417, "pan.___", state 932, "cache_dirty_rcu_ptr = 0"
+ line 421, "pan.___", state 946, "cache_dirty_rcu_data[i] = 0"
+ line 250, "pan.___", state 972, "(1)"
+ line 254, "pan.___", state 984, "(1)"
+ line 258, "pan.___", state 992, "(1)"
+ line 269, "pan.___", state 1036, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1045, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1060, "(1)"
+ line 281, "pan.___", state 1067, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1083, "(1)"
+ line 250, "pan.___", state 1091, "(1)"
+ line 254, "pan.___", state 1103, "(1)"
+ line 258, "pan.___", state 1111, "(1)"
+ line 269, "pan.___", state 1142, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1151, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1164, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1173, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1189, "(1)"
+ line 250, "pan.___", state 1197, "(1)"
+ line 254, "pan.___", state 1209, "(1)"
+ line 258, "pan.___", state 1217, "(1)"
+ line 273, "pan.___", state 1243, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1256, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1265, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1281, "(1)"
+ line 250, "pan.___", state 1289, "(1)"
+ line 254, "pan.___", state 1301, "(1)"
+ line 258, "pan.___", state 1309, "(1)"
+ line 269, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr = 0"
+ line 273, "pan.___", state 1349, "cache_dirty_urcu_active_readers = 0"
+ line 277, "pan.___", state 1362, "cache_dirty_rcu_ptr = 0"
+ line 281, "pan.___", state 1371, "cache_dirty_rcu_data[i] = 0"
+ line 246, "pan.___", state 1387, "(1)"
+ line 250, "pan.___", state 1395, "(1)"
+ line 254, "pan.___", state 1407, "(1)"
+ line 258, "pan.___", state 1415, "(1)"
+ line 1305, "pan.___", state 1431, "-end-"
+ (110 of 1431 states)
+unreached in proctype :init:
+ (0 of 28 states)
+unreached in proctype :never:
+ line 1370, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 106 seconds
+pan: rate 29466.638 states/second
+pan: avg transition delay 2.9729e-06 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi-compress'
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x;
+
+#define DECLARE_PROC_CACHED_VAR(type, x)\
+ type cached_##x; \
+ bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v) \
+ mem_##x = v;
+
+#define INIT_PROC_CACHED_VAR(x, v) \
+ cache_dirty_##x = 0; \
+ cached_##x = v;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x)
+
+#define READ_CACHED_VAR(x) (cached_##x)
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x = v; \
+ cache_dirty_##x = 1; \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x; \
+ cache_dirty_##x = 0; \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x = mem_##x; \
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ /* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_gp_ctr);
+ /* Note ! currently only one reader */
+ DECLARE_PROC_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+ /* RCU data */
+ DECLARE_PROC_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+ /* RCU pointer */
+#if (SLAB_SIZE == 2)
+ DECLARE_PROC_CACHED_VAR(bit, rcu_ptr);
+#else
+ DECLARE_PROC_CACHED_VAR(byte, rcu_ptr);
+#endif
+
+ atomic {
+ INIT_PROC_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_PROC_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_PROC_CACHED_VAR(urcu_active_readers[i], 0);
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_PROC_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_PROC_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1);
+ INIT_CACHED_VAR(rcu_ptr, 0);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
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--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ make urcu_free | tee urcu_free.log
+ make urcu_free_no_mb | tee urcu_free_no_mb.log
+ make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1294)
+Depth= 9223 States= 1e+06 Transitions= 6.87e+06 Memory= 550.432 t= 16.6 R= 6e+04
+Depth= 9223 States= 2e+06 Transitions= 1.47e+07 Memory= 634.318 t= 36.7 R= 5e+04
+Depth= 9223 States= 3e+06 Transitions= 2.46e+07 Memory= 718.303 t= 62.6 R= 5e+04
+pan: resizing hashtable to -w22.. done
+Depth= 9223 States= 4e+06 Transitions= 3.19e+07 Memory= 833.311 t= 81.2 R= 5e+04
+Depth= 9223 States= 5e+06 Transitions= 3.95e+07 Memory= 917.295 t= 100 R= 5e+04
+Depth= 9223 States= 6e+06 Transitions= 5.71e+07 Memory= 1001.279 t= 149 R= 4e+04
+Depth= 9223 States= 7e+06 Transitions= 6.81e+07 Memory= 1085.264 t= 178 R= 4e+04
+Depth= 9223 States= 8e+06 Transitions= 8.22e+07 Memory= 1169.151 t= 216 R= 4e+04
+Depth= 9223 States= 9e+06 Transitions= 9.54e+07 Memory= 1253.135 t= 252 R= 4e+04
+pan: resizing hashtable to -w24.. done
+Depth= 9223 States= 1e+07 Transitions= 1.08e+08 Memory= 1461.115 t= 288 R= 3e+04
+Depth= 9223 States= 1.1e+07 Transitions= 1.21e+08 Memory= 1545.100 t= 321 R= 3e+04
+Depth= 9223 States= 1.2e+07 Transitions= 1.3e+08 Memory= 1629.084 t= 345 R= 3e+04
+Depth= 9223 States= 1.3e+07 Transitions= 1.42e+08 Memory= 1713.068 t= 378 R= 3e+04
+Depth= 9223 States= 1.4e+07 Transitions= 1.72e+08 Memory= 1797.053 t= 463 R= 3e+04
+Depth= 9223 States= 1.5e+07 Transitions= 1.91e+08 Memory= 1881.037 t= 516 R= 3e+04
+Depth= 9223 States= 1.6e+07 Transitions= 2.08e+08 Memory= 1964.924 t= 562 R= 3e+04
+Depth= 9223 States= 1.7e+07 Transitions= 2.2e+08 Memory= 2048.908 t= 595 R= 3e+04
+Depth= 9223 States= 1.8e+07 Transitions= 2.39e+08 Memory= 2132.893 t= 647 R= 3e+04
+Depth= 9223 States= 1.9e+07 Transitions= 2.55e+08 Memory= 2216.877 t= 691 R= 3e+04
+Depth= 9223 States= 2e+07 Transitions= 2.72e+08 Memory= 2300.861 t= 739 R= 3e+04
+Depth= 9285 States= 2.1e+07 Transitions= 2.85e+08 Memory= 2384.846 t= 774 R= 3e+04
+Depth= 9324 States= 2.2e+07 Transitions= 2.99e+08 Memory= 2468.830 t= 812 R= 3e+04
+Depth= 9324 States= 2.3e+07 Transitions= 3.1e+08 Memory= 2552.717 t= 842 R= 3e+04
+Depth= 9324 States= 2.4e+07 Transitions= 3.21e+08 Memory= 2636.701 t= 873 R= 3e+04
+Depth= 9324 States= 2.5e+07 Transitions= 3.34e+08 Memory= 2720.686 t= 908 R= 3e+04
+Depth= 9324 States= 2.6e+07 Transitions= 3.45e+08 Memory= 2804.670 t= 939 R= 3e+04
+Depth= 9324 States= 2.7e+07 Transitions= 3.59e+08 Memory= 2888.654 t= 975 R= 3e+04
+Depth= 9324 States= 2.8e+07 Transitions= 3.71e+08 Memory= 2972.639 t= 1.01e+03 R= 3e+04
+Depth= 9324 States= 2.9e+07 Transitions= 3.84e+08 Memory= 3056.526 t= 1.04e+03 R= 3e+04
+Depth= 9324 States= 3e+07 Transitions= 3.96e+08 Memory= 3140.510 t= 1.08e+03 R= 3e+04
+Depth= 9324 States= 3.1e+07 Transitions= 4.09e+08 Memory= 3224.494 t= 1.11e+03 R= 3e+04
+Depth= 9324 States= 3.2e+07 Transitions= 4.19e+08 Memory= 3308.479 t= 1.14e+03 R= 3e+04
+Depth= 9324 States= 3.3e+07 Transitions= 4.3e+08 Memory= 3392.463 t= 1.17e+03 R= 3e+04
+Depth= 9324 States= 3.4e+07 Transitions= 4.44e+08 Memory= 3476.447 t= 1.21e+03 R= 3e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9324 States= 3.5e+07 Transitions= 4.6e+08 Memory= 4056.416 t= 1.26e+03 R= 3e+04
+Depth= 9324 States= 3.6e+07 Transitions= 4.73e+08 Memory= 4140.401 t= 1.3e+03 R= 3e+04
+Depth= 9324 States= 3.7e+07 Transitions= 4.89e+08 Memory= 4224.385 t= 1.34e+03 R= 3e+04
+Depth= 9324 States= 3.8e+07 Transitions= 5.04e+08 Memory= 4308.369 t= 1.38e+03 R= 3e+04
+Depth= 9324 States= 3.9e+07 Transitions= 5.18e+08 Memory= 4392.354 t= 1.42e+03 R= 3e+04
+Depth= 9324 States= 4e+07 Transitions= 5.28e+08 Memory= 4476.338 t= 1.44e+03 R= 3e+04
+Depth= 9324 States= 4.1e+07 Transitions= 5.38e+08 Memory= 4560.225 t= 1.47e+03 R= 3e+04
+Depth= 9324 States= 4.2e+07 Transitions= 5.5e+08 Memory= 4644.209 t= 1.5e+03 R= 3e+04
+Depth= 9324 States= 4.3e+07 Transitions= 5.76e+08 Memory= 4728.193 t= 1.58e+03 R= 3e+04
+Depth= 9324 States= 4.4e+07 Transitions= 6.01e+08 Memory= 4812.178 t= 1.65e+03 R= 3e+04
+Depth= 9324 States= 4.5e+07 Transitions= 6.18e+08 Memory= 4896.162 t= 1.69e+03 R= 3e+04
+Depth= 9324 States= 4.6e+07 Transitions= 6.29e+08 Memory= 4980.147 t= 1.72e+03 R= 3e+04
+Depth= 9324 States= 4.7e+07 Transitions= 6.44e+08 Memory= 5064.131 t= 1.76e+03 R= 3e+04
+Depth= 9324 States= 4.8e+07 Transitions= 6.63e+08 Memory= 5148.018 t= 1.82e+03 R= 3e+04
+Depth= 9324 States= 4.9e+07 Transitions= 6.8e+08 Memory= 5232.002 t= 1.86e+03 R= 3e+04
+Depth= 9324 States= 5e+07 Transitions= 6.94e+08 Memory= 5315.986 t= 1.9e+03 R= 3e+04
+Depth= 9324 States= 5.1e+07 Transitions= 7.07e+08 Memory= 5399.971 t= 1.94e+03 R= 3e+04
+Depth= 9324 States= 5.2e+07 Transitions= 7.19e+08 Memory= 5483.955 t= 1.97e+03 R= 3e+04
+Depth= 9324 States= 5.3e+07 Transitions= 7.33e+08 Memory= 5567.940 t= 2.01e+03 R= 3e+04
+Depth= 9324 States= 5.4e+07 Transitions= 7.43e+08 Memory= 5651.826 t= 2.03e+03 R= 3e+04
+Depth= 9324 States= 5.5e+07 Transitions= 7.56e+08 Memory= 5735.811 t= 2.07e+03 R= 3e+04
+Depth= 9324 States= 5.6e+07 Transitions= 7.67e+08 Memory= 5819.795 t= 2.1e+03 R= 3e+04
+Depth= 9324 States= 5.7e+07 Transitions= 7.82e+08 Memory= 5903.779 t= 2.14e+03 R= 3e+04
+Depth= 9324 States= 5.8e+07 Transitions= 7.92e+08 Memory= 5987.764 t= 2.17e+03 R= 3e+04
+Depth= 9324 States= 5.9e+07 Transitions= 8.05e+08 Memory= 6071.748 t= 2.2e+03 R= 3e+04
+Depth= 9324 States= 6e+07 Transitions= 8.17e+08 Memory= 6155.733 t= 2.23e+03 R= 3e+04
+Depth= 9324 States= 6.1e+07 Transitions= 8.27e+08 Memory= 6239.619 t= 2.26e+03 R= 3e+04
+Depth= 9324 States= 6.2e+07 Transitions= 8.39e+08 Memory= 6323.604 t= 2.29e+03 R= 3e+04
+Depth= 9324 States= 6.3e+07 Transitions= 8.57e+08 Memory= 6407.588 t= 2.34e+03 R= 3e+04
+Depth= 9324 States= 6.4e+07 Transitions= 8.68e+08 Memory= 6491.572 t= 2.37e+03 R= 3e+04
+Depth= 9324 States= 6.5e+07 Transitions= 8.83e+08 Memory= 6575.557 t= 2.41e+03 R= 3e+04
+Depth= 9324 States= 6.6e+07 Transitions= 8.98e+08 Memory= 6659.541 t= 2.45e+03 R= 3e+04
+Depth= 9324 States= 6.7e+07 Transitions= 9.13e+08 Memory= 6743.428 t= 2.49e+03 R= 3e+04
+Depth= 9324 States= 6.8e+07 Transitions= 9.28e+08 Memory= 6827.412 t= 2.53e+03 R= 3e+04
+Depth= 9324 States= 6.9e+07 Transitions= 9.42e+08 Memory= 6911.397 t= 2.57e+03 R= 3e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 9324, errors: 0
+ 69786664 states, stored
+8.8218731e+08 states, matched
+9.5197398e+08 transitions (= stored+matched)
+1.4613809e+10 atomic steps
+hash conflicts: 5.3037519e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7720.235 equivalent memory usage for states (stored*(State-vector + overhead))
+ 6011.129 actual memory usage for states (compression: 77.86%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 3.383 memory lost to fragmentation
+ 6977.510 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 271, "pan.___", state 30, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 61, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 77, "(1)"
+ line 252, "pan.___", state 85, "(1)"
+ line 256, "pan.___", state 97, "(1)"
+ line 260, "pan.___", state 105, "(1)"
+ line 410, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 163, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 177, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 195, "(1)"
+ line 256, "pan.___", state 215, "(1)"
+ line 260, "pan.___", state 223, "(1)"
+ line 690, "pan.___", state 242, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 410, "pan.___", state 249, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 281, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 295, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 313, "(1)"
+ line 256, "pan.___", state 333, "(1)"
+ line 260, "pan.___", state 341, "(1)"
+ line 410, "pan.___", state 360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 392, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 406, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 424, "(1)"
+ line 256, "pan.___", state 444, "(1)"
+ line 260, "pan.___", state 452, "(1)"
+ line 410, "pan.___", state 473, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 475, "(1)"
+ line 410, "pan.___", state 476, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 476, "else"
+ line 410, "pan.___", state 479, "(1)"
+ line 414, "pan.___", state 487, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 489, "(1)"
+ line 414, "pan.___", state 490, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 490, "else"
+ line 414, "pan.___", state 493, "(1)"
+ line 414, "pan.___", state 494, "(1)"
+ line 414, "pan.___", state 494, "(1)"
+ line 412, "pan.___", state 499, "((i<1))"
+ line 412, "pan.___", state 499, "((i>=1))"
+ line 419, "pan.___", state 505, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 507, "(1)"
+ line 419, "pan.___", state 508, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 508, "else"
+ line 419, "pan.___", state 511, "(1)"
+ line 419, "pan.___", state 512, "(1)"
+ line 419, "pan.___", state 512, "(1)"
+ line 423, "pan.___", state 519, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 521, "(1)"
+ line 423, "pan.___", state 522, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 522, "else"
+ line 423, "pan.___", state 525, "(1)"
+ line 423, "pan.___", state 526, "(1)"
+ line 423, "pan.___", state 526, "(1)"
+ line 421, "pan.___", state 531, "((i<2))"
+ line 421, "pan.___", state 531, "((i>=2))"
+ line 248, "pan.___", state 537, "(1)"
+ line 252, "pan.___", state 545, "(1)"
+ line 252, "pan.___", state 546, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 546, "else"
+ line 250, "pan.___", state 551, "((i<1))"
+ line 250, "pan.___", state 551, "((i>=1))"
+ line 256, "pan.___", state 557, "(1)"
+ line 256, "pan.___", state 558, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 558, "else"
+ line 260, "pan.___", state 565, "(1)"
+ line 260, "pan.___", state 566, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 566, "else"
+ line 258, "pan.___", state 571, "((i<2))"
+ line 258, "pan.___", state 571, "((i>=2))"
+ line 265, "pan.___", state 575, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 575, "else"
+ line 430, "pan.___", state 577, "(1)"
+ line 430, "pan.___", state 577, "(1)"
+ line 690, "pan.___", state 580, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 690, "pan.___", state 581, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 690, "pan.___", state 582, "(1)"
+ line 410, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 621, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 635, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 653, "(1)"
+ line 256, "pan.___", state 673, "(1)"
+ line 260, "pan.___", state 681, "(1)"
+ line 410, "pan.___", state 707, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 739, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 753, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 771, "(1)"
+ line 256, "pan.___", state 791, "(1)"
+ line 260, "pan.___", state 799, "(1)"
+ line 410, "pan.___", state 818, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 820, "(1)"
+ line 410, "pan.___", state 821, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 821, "else"
+ line 410, "pan.___", state 824, "(1)"
+ line 414, "pan.___", state 832, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 834, "(1)"
+ line 414, "pan.___", state 835, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 835, "else"
+ line 414, "pan.___", state 838, "(1)"
+ line 414, "pan.___", state 839, "(1)"
+ line 414, "pan.___", state 839, "(1)"
+ line 412, "pan.___", state 844, "((i<1))"
+ line 412, "pan.___", state 844, "((i>=1))"
+ line 419, "pan.___", state 850, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 852, "(1)"
+ line 419, "pan.___", state 853, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 853, "else"
+ line 419, "pan.___", state 856, "(1)"
+ line 419, "pan.___", state 857, "(1)"
+ line 419, "pan.___", state 857, "(1)"
+ line 423, "pan.___", state 864, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 866, "(1)"
+ line 423, "pan.___", state 867, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 867, "else"
+ line 423, "pan.___", state 870, "(1)"
+ line 423, "pan.___", state 871, "(1)"
+ line 423, "pan.___", state 871, "(1)"
+ line 421, "pan.___", state 876, "((i<2))"
+ line 421, "pan.___", state 876, "((i>=2))"
+ line 248, "pan.___", state 882, "(1)"
+ line 252, "pan.___", state 890, "(1)"
+ line 252, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 891, "else"
+ line 250, "pan.___", state 896, "((i<1))"
+ line 250, "pan.___", state 896, "((i>=1))"
+ line 256, "pan.___", state 902, "(1)"
+ line 256, "pan.___", state 903, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 903, "else"
+ line 260, "pan.___", state 910, "(1)"
+ line 260, "pan.___", state 911, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 911, "else"
+ line 258, "pan.___", state 916, "((i<2))"
+ line 258, "pan.___", state 916, "((i>=2))"
+ line 265, "pan.___", state 920, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 920, "else"
+ line 430, "pan.___", state 922, "(1)"
+ line 430, "pan.___", state 922, "(1)"
+ line 698, "pan.___", state 926, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 410, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 963, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 977, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 995, "(1)"
+ line 256, "pan.___", state 1015, "(1)"
+ line 260, "pan.___", state 1023, "(1)"
+ line 410, "pan.___", state 1045, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1077, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1091, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1109, "(1)"
+ line 256, "pan.___", state 1129, "(1)"
+ line 260, "pan.___", state 1137, "(1)"
+ line 410, "pan.___", state 1160, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1192, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1206, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1224, "(1)"
+ line 256, "pan.___", state 1244, "(1)"
+ line 260, "pan.___", state 1252, "(1)"
+ line 410, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1303, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1317, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1335, "(1)"
+ line 256, "pan.___", state 1355, "(1)"
+ line 260, "pan.___", state 1363, "(1)"
+ line 410, "pan.___", state 1387, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1419, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1433, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1451, "(1)"
+ line 256, "pan.___", state 1471, "(1)"
+ line 260, "pan.___", state 1479, "(1)"
+ line 410, "pan.___", state 1498, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1530, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1544, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1562, "(1)"
+ line 256, "pan.___", state 1582, "(1)"
+ line 260, "pan.___", state 1590, "(1)"
+ line 410, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1644, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1658, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1676, "(1)"
+ line 256, "pan.___", state 1696, "(1)"
+ line 260, "pan.___", state 1704, "(1)"
+ line 737, "pan.___", state 1723, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 410, "pan.___", state 1730, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1762, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1776, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1794, "(1)"
+ line 256, "pan.___", state 1814, "(1)"
+ line 260, "pan.___", state 1822, "(1)"
+ line 410, "pan.___", state 1841, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1873, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1887, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1905, "(1)"
+ line 256, "pan.___", state 1925, "(1)"
+ line 260, "pan.___", state 1933, "(1)"
+ line 410, "pan.___", state 1954, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 1956, "(1)"
+ line 410, "pan.___", state 1957, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 1957, "else"
+ line 410, "pan.___", state 1960, "(1)"
+ line 414, "pan.___", state 1968, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1970, "(1)"
+ line 414, "pan.___", state 1971, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 1971, "else"
+ line 414, "pan.___", state 1974, "(1)"
+ line 414, "pan.___", state 1975, "(1)"
+ line 414, "pan.___", state 1975, "(1)"
+ line 412, "pan.___", state 1980, "((i<1))"
+ line 412, "pan.___", state 1980, "((i>=1))"
+ line 419, "pan.___", state 1986, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1988, "(1)"
+ line 419, "pan.___", state 1989, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 1989, "else"
+ line 419, "pan.___", state 1992, "(1)"
+ line 419, "pan.___", state 1993, "(1)"
+ line 419, "pan.___", state 1993, "(1)"
+ line 423, "pan.___", state 2000, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2002, "(1)"
+ line 423, "pan.___", state 2003, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 2003, "else"
+ line 423, "pan.___", state 2006, "(1)"
+ line 423, "pan.___", state 2007, "(1)"
+ line 423, "pan.___", state 2007, "(1)"
+ line 421, "pan.___", state 2012, "((i<2))"
+ line 421, "pan.___", state 2012, "((i>=2))"
+ line 248, "pan.___", state 2018, "(1)"
+ line 252, "pan.___", state 2026, "(1)"
+ line 252, "pan.___", state 2027, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 2027, "else"
+ line 250, "pan.___", state 2032, "((i<1))"
+ line 250, "pan.___", state 2032, "((i>=1))"
+ line 256, "pan.___", state 2038, "(1)"
+ line 256, "pan.___", state 2039, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 2039, "else"
+ line 260, "pan.___", state 2046, "(1)"
+ line 260, "pan.___", state 2047, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 2047, "else"
+ line 258, "pan.___", state 2052, "((i<2))"
+ line 258, "pan.___", state 2052, "((i>=2))"
+ line 265, "pan.___", state 2056, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 2056, "else"
+ line 430, "pan.___", state 2058, "(1)"
+ line 430, "pan.___", state 2058, "(1)"
+ line 737, "pan.___", state 2061, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 737, "pan.___", state 2062, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 737, "pan.___", state 2063, "(1)"
+ line 410, "pan.___", state 2070, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2102, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2116, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2134, "(1)"
+ line 256, "pan.___", state 2154, "(1)"
+ line 260, "pan.___", state 2162, "(1)"
+ line 410, "pan.___", state 2187, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2219, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2233, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2251, "(1)"
+ line 256, "pan.___", state 2271, "(1)"
+ line 260, "pan.___", state 2279, "(1)"
+ line 410, "pan.___", state 2298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2362, "(1)"
+ line 256, "pan.___", state 2382, "(1)"
+ line 260, "pan.___", state 2390, "(1)"
+ line 248, "pan.___", state 2421, "(1)"
+ line 256, "pan.___", state 2441, "(1)"
+ line 260, "pan.___", state 2449, "(1)"
+ line 248, "pan.___", state 2464, "(1)"
+ line 256, "pan.___", state 2484, "(1)"
+ line 260, "pan.___", state 2492, "(1)"
+ line 897, "pan.___", state 2509, "-end-"
+ (221 of 2509 states)
+unreached in proctype urcu_writer
+ line 410, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 82, "(1)"
+ line 252, "pan.___", state 90, "(1)"
+ line 256, "pan.___", state 102, "(1)"
+ line 271, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 257, "(1)"
+ line 252, "pan.___", state 265, "(1)"
+ line 256, "pan.___", state 277, "(1)"
+ line 260, "pan.___", state 285, "(1)"
+ line 414, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 378, "(1)"
+ line 256, "pan.___", state 390, "(1)"
+ line 260, "pan.___", state 398, "(1)"
+ line 414, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 499, "(1)"
+ line 256, "pan.___", state 511, "(1)"
+ line 260, "pan.___", state 519, "(1)"
+ line 414, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 610, "(1)"
+ line 256, "pan.___", state 622, "(1)"
+ line 260, "pan.___", state 630, "(1)"
+ line 414, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 723, "(1)"
+ line 256, "pan.___", state 735, "(1)"
+ line 260, "pan.___", state 743, "(1)"
+ line 271, "pan.___", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 820, "(1)"
+ line 283, "pan.___", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 843, "(1)"
+ line 252, "pan.___", state 851, "(1)"
+ line 256, "pan.___", state 863, "(1)"
+ line 260, "pan.___", state 871, "(1)"
+ line 271, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 911, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 924, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 933, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 949, "(1)"
+ line 252, "pan.___", state 957, "(1)"
+ line 256, "pan.___", state 969, "(1)"
+ line 260, "pan.___", state 977, "(1)"
+ line 275, "pan.___", state 1003, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1016, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1025, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1041, "(1)"
+ line 252, "pan.___", state 1049, "(1)"
+ line 256, "pan.___", state 1061, "(1)"
+ line 260, "pan.___", state 1069, "(1)"
+ line 271, "pan.___", state 1100, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 1109, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1122, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1131, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1147, "(1)"
+ line 252, "pan.___", state 1155, "(1)"
+ line 256, "pan.___", state 1167, "(1)"
+ line 260, "pan.___", state 1175, "(1)"
+ line 275, "pan.___", state 1201, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1214, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1239, "(1)"
+ line 252, "pan.___", state 1247, "(1)"
+ line 256, "pan.___", state 1259, "(1)"
+ line 260, "pan.___", state 1267, "(1)"
+ line 271, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 1307, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1320, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1329, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1345, "(1)"
+ line 252, "pan.___", state 1353, "(1)"
+ line 256, "pan.___", state 1365, "(1)"
+ line 260, "pan.___", state 1373, "(1)"
+ line 275, "pan.___", state 1399, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1412, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1421, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1437, "(1)"
+ line 252, "pan.___", state 1445, "(1)"
+ line 256, "pan.___", state 1457, "(1)"
+ line 260, "pan.___", state 1465, "(1)"
+ line 271, "pan.___", state 1496, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 1505, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1518, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1543, "(1)"
+ line 252, "pan.___", state 1551, "(1)"
+ line 256, "pan.___", state 1563, "(1)"
+ line 260, "pan.___", state 1571, "(1)"
+ line 1236, "pan.___", state 1587, "-end-"
+ (103 of 1587 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1299, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 2.6e+03 seconds
+pan: rate 26856.415 states/second
+pan: avg transition delay 2.7296e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
--- /dev/null
+[] (!read_poison)
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 8619 States= 1e+06 Transitions= 8e+06 Memory= 550.432 t= 20.2 R= 5e+04
+Depth= 8619 States= 2e+06 Transitions= 1.8e+07 Memory= 634.318 t= 46.3 R= 4e+04
+Depth= 8619 States= 3e+06 Transitions= 2.53e+07 Memory= 718.303 t= 64.9 R= 5e+04
+pan: resizing hashtable to -w22.. done
+Depth= 8619 States= 4e+06 Transitions= 3.53e+07 Memory= 833.311 t= 91.4 R= 4e+04
+Depth= 8619 States= 5e+06 Transitions= 5.71e+07 Memory= 917.295 t= 152 R= 3e+04
+Depth= 8619 States= 6e+06 Transitions= 6.81e+07 Memory= 1001.279 t= 181 R= 3e+04
+Depth= 8619 States= 7e+06 Transitions= 8.02e+07 Memory= 1085.264 t= 214 R= 3e+04
+Depth= 8619 States= 8e+06 Transitions= 8.9e+07 Memory= 1169.151 t= 238 R= 3e+04
+pan: claim violated! (at depth 1359)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 8619, errors: 1
+ 8162162 states, stored
+ 81941434 states, matched
+ 90103596 transitions (= stored+matched)
+1.3256628e+09 atomic steps
+hash conflicts: 60101961 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 902.949 equivalent memory usage for states (stored*(State-vector + overhead))
+ 693.526 actual memory usage for states (compression: 76.81%)
+ state-vector as stored = 61 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1182.822 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 272, "pan.___", state 34, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 56, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 65, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 253, "pan.___", state 89, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 700, "pan.___", state 246, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 253, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 285, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 299, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 317, "(1)"
+ line 257, "pan.___", state 337, "(1)"
+ line 261, "pan.___", state 345, "(1)"
+ line 411, "pan.___", state 364, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 396, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 410, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 428, "(1)"
+ line 257, "pan.___", state 448, "(1)"
+ line 261, "pan.___", state 456, "(1)"
+ line 411, "pan.___", state 477, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 479, "(1)"
+ line 411, "pan.___", state 480, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 480, "else"
+ line 411, "pan.___", state 483, "(1)"
+ line 415, "pan.___", state 491, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 493, "(1)"
+ line 415, "pan.___", state 494, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 494, "else"
+ line 415, "pan.___", state 497, "(1)"
+ line 415, "pan.___", state 498, "(1)"
+ line 415, "pan.___", state 498, "(1)"
+ line 413, "pan.___", state 503, "((i<1))"
+ line 413, "pan.___", state 503, "((i>=1))"
+ line 420, "pan.___", state 509, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 511, "(1)"
+ line 420, "pan.___", state 512, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 512, "else"
+ line 420, "pan.___", state 515, "(1)"
+ line 420, "pan.___", state 516, "(1)"
+ line 420, "pan.___", state 516, "(1)"
+ line 424, "pan.___", state 523, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 525, "(1)"
+ line 424, "pan.___", state 526, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 526, "else"
+ line 424, "pan.___", state 529, "(1)"
+ line 424, "pan.___", state 530, "(1)"
+ line 424, "pan.___", state 530, "(1)"
+ line 422, "pan.___", state 535, "((i<2))"
+ line 422, "pan.___", state 535, "((i>=2))"
+ line 249, "pan.___", state 541, "(1)"
+ line 253, "pan.___", state 549, "(1)"
+ line 253, "pan.___", state 550, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 550, "else"
+ line 251, "pan.___", state 555, "((i<1))"
+ line 251, "pan.___", state 555, "((i>=1))"
+ line 257, "pan.___", state 561, "(1)"
+ line 257, "pan.___", state 562, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 562, "else"
+ line 261, "pan.___", state 569, "(1)"
+ line 261, "pan.___", state 570, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 570, "else"
+ line 259, "pan.___", state 575, "((i<2))"
+ line 259, "pan.___", state 575, "((i>=2))"
+ line 266, "pan.___", state 579, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 579, "else"
+ line 431, "pan.___", state 581, "(1)"
+ line 431, "pan.___", state 581, "(1)"
+ line 700, "pan.___", state 584, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 700, "pan.___", state 585, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 700, "pan.___", state 586, "(1)"
+ line 411, "pan.___", state 593, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 625, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 639, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 657, "(1)"
+ line 257, "pan.___", state 677, "(1)"
+ line 261, "pan.___", state 685, "(1)"
+ line 411, "pan.___", state 711, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 743, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 757, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 775, "(1)"
+ line 257, "pan.___", state 795, "(1)"
+ line 261, "pan.___", state 803, "(1)"
+ line 411, "pan.___", state 822, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 824, "(1)"
+ line 411, "pan.___", state 825, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 825, "else"
+ line 411, "pan.___", state 828, "(1)"
+ line 415, "pan.___", state 836, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 838, "(1)"
+ line 415, "pan.___", state 839, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 839, "else"
+ line 415, "pan.___", state 842, "(1)"
+ line 415, "pan.___", state 843, "(1)"
+ line 415, "pan.___", state 843, "(1)"
+ line 413, "pan.___", state 848, "((i<1))"
+ line 413, "pan.___", state 848, "((i>=1))"
+ line 420, "pan.___", state 854, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 856, "(1)"
+ line 420, "pan.___", state 857, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 857, "else"
+ line 420, "pan.___", state 860, "(1)"
+ line 420, "pan.___", state 861, "(1)"
+ line 420, "pan.___", state 861, "(1)"
+ line 424, "pan.___", state 868, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 870, "(1)"
+ line 424, "pan.___", state 871, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 871, "else"
+ line 424, "pan.___", state 874, "(1)"
+ line 424, "pan.___", state 875, "(1)"
+ line 424, "pan.___", state 875, "(1)"
+ line 422, "pan.___", state 880, "((i<2))"
+ line 422, "pan.___", state 880, "((i>=2))"
+ line 249, "pan.___", state 886, "(1)"
+ line 253, "pan.___", state 894, "(1)"
+ line 253, "pan.___", state 895, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 895, "else"
+ line 251, "pan.___", state 900, "((i<1))"
+ line 251, "pan.___", state 900, "((i>=1))"
+ line 257, "pan.___", state 906, "(1)"
+ line 257, "pan.___", state 907, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 907, "else"
+ line 261, "pan.___", state 914, "(1)"
+ line 261, "pan.___", state 915, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 915, "else"
+ line 259, "pan.___", state 920, "((i<2))"
+ line 259, "pan.___", state 920, "((i>=2))"
+ line 266, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 924, "else"
+ line 431, "pan.___", state 926, "(1)"
+ line 431, "pan.___", state 926, "(1)"
+ line 708, "pan.___", state 930, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 935, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 967, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 981, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 999, "(1)"
+ line 257, "pan.___", state 1019, "(1)"
+ line 261, "pan.___", state 1027, "(1)"
+ line 411, "pan.___", state 1049, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1081, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1095, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1113, "(1)"
+ line 257, "pan.___", state 1133, "(1)"
+ line 261, "pan.___", state 1141, "(1)"
+ line 411, "pan.___", state 1164, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1196, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1210, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1228, "(1)"
+ line 257, "pan.___", state 1248, "(1)"
+ line 261, "pan.___", state 1256, "(1)"
+ line 411, "pan.___", state 1275, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1307, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1321, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1339, "(1)"
+ line 257, "pan.___", state 1359, "(1)"
+ line 261, "pan.___", state 1367, "(1)"
+ line 411, "pan.___", state 1391, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1423, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1437, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1455, "(1)"
+ line 257, "pan.___", state 1475, "(1)"
+ line 261, "pan.___", state 1483, "(1)"
+ line 411, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1534, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1548, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1566, "(1)"
+ line 257, "pan.___", state 1586, "(1)"
+ line 261, "pan.___", state 1594, "(1)"
+ line 411, "pan.___", state 1616, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1648, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1662, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1680, "(1)"
+ line 257, "pan.___", state 1700, "(1)"
+ line 261, "pan.___", state 1708, "(1)"
+ line 747, "pan.___", state 1727, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1734, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1766, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1780, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1798, "(1)"
+ line 257, "pan.___", state 1818, "(1)"
+ line 261, "pan.___", state 1826, "(1)"
+ line 411, "pan.___", state 1845, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1877, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1891, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1909, "(1)"
+ line 257, "pan.___", state 1929, "(1)"
+ line 261, "pan.___", state 1937, "(1)"
+ line 411, "pan.___", state 1958, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 1960, "(1)"
+ line 411, "pan.___", state 1961, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 1961, "else"
+ line 411, "pan.___", state 1964, "(1)"
+ line 415, "pan.___", state 1972, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1974, "(1)"
+ line 415, "pan.___", state 1975, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 1975, "else"
+ line 415, "pan.___", state 1978, "(1)"
+ line 415, "pan.___", state 1979, "(1)"
+ line 415, "pan.___", state 1979, "(1)"
+ line 413, "pan.___", state 1984, "((i<1))"
+ line 413, "pan.___", state 1984, "((i>=1))"
+ line 420, "pan.___", state 1990, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1992, "(1)"
+ line 420, "pan.___", state 1993, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 1993, "else"
+ line 420, "pan.___", state 1996, "(1)"
+ line 420, "pan.___", state 1997, "(1)"
+ line 420, "pan.___", state 1997, "(1)"
+ line 424, "pan.___", state 2004, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2006, "(1)"
+ line 424, "pan.___", state 2007, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2007, "else"
+ line 424, "pan.___", state 2010, "(1)"
+ line 424, "pan.___", state 2011, "(1)"
+ line 424, "pan.___", state 2011, "(1)"
+ line 422, "pan.___", state 2016, "((i<2))"
+ line 422, "pan.___", state 2016, "((i>=2))"
+ line 249, "pan.___", state 2022, "(1)"
+ line 253, "pan.___", state 2030, "(1)"
+ line 253, "pan.___", state 2031, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2031, "else"
+ line 251, "pan.___", state 2036, "((i<1))"
+ line 251, "pan.___", state 2036, "((i>=1))"
+ line 257, "pan.___", state 2042, "(1)"
+ line 257, "pan.___", state 2043, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2043, "else"
+ line 261, "pan.___", state 2050, "(1)"
+ line 261, "pan.___", state 2051, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2051, "else"
+ line 259, "pan.___", state 2056, "((i<2))"
+ line 259, "pan.___", state 2056, "((i>=2))"
+ line 266, "pan.___", state 2060, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2060, "else"
+ line 431, "pan.___", state 2062, "(1)"
+ line 431, "pan.___", state 2062, "(1)"
+ line 747, "pan.___", state 2065, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 747, "pan.___", state 2066, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 747, "pan.___", state 2067, "(1)"
+ line 411, "pan.___", state 2074, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2106, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2120, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2138, "(1)"
+ line 257, "pan.___", state 2158, "(1)"
+ line 261, "pan.___", state 2166, "(1)"
+ line 411, "pan.___", state 2191, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2223, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2237, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2255, "(1)"
+ line 257, "pan.___", state 2275, "(1)"
+ line 261, "pan.___", state 2283, "(1)"
+ line 411, "pan.___", state 2302, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2334, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2348, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2366, "(1)"
+ line 257, "pan.___", state 2386, "(1)"
+ line 261, "pan.___", state 2394, "(1)"
+ line 249, "pan.___", state 2425, "(1)"
+ line 257, "pan.___", state 2445, "(1)"
+ line 261, "pan.___", state 2453, "(1)"
+ line 249, "pan.___", state 2468, "(1)"
+ line 257, "pan.___", state 2488, "(1)"
+ line 261, "pan.___", state 2496, "(1)"
+ line 898, "pan.___", state 2513, "-end-"
+ (221 of 2513 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 20, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 26, "(1)"
+ line 415, "pan.___", state 34, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 40, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 413, "pan.___", state 46, "((i<1))"
+ line 413, "pan.___", state 46, "((i>=1))"
+ line 420, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 58, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 424, "pan.___", state 72, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 422, "pan.___", state 78, "((i<2))"
+ line 422, "pan.___", state 78, "((i>=2))"
+ line 249, "pan.___", state 84, "(1)"
+ line 253, "pan.___", state 92, "(1)"
+ line 253, "pan.___", state 93, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 93, "else"
+ line 251, "pan.___", state 98, "((i<1))"
+ line 251, "pan.___", state 98, "((i>=1))"
+ line 257, "pan.___", state 104, "(1)"
+ line 257, "pan.___", state 105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 105, "else"
+ line 261, "pan.___", state 112, "(1)"
+ line 261, "pan.___", state 113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 113, "else"
+ line 259, "pan.___", state 118, "((i<2))"
+ line 259, "pan.___", state 118, "((i>=2))"
+ line 266, "pan.___", state 122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 122, "else"
+ line 431, "pan.___", state 124, "(1)"
+ line 431, "pan.___", state 124, "(1)"
+ line 272, "pan.___", state 133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 142, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 274, "pan.___", state 150, "((i<1))"
+ line 274, "pan.___", state 150, "((i>=1))"
+ line 280, "pan.___", state 155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 1021, "pan.___", state 183, "old_data = cached_rcu_ptr.val[_pid]"
+ line 1032, "pan.___", state 187, "_proc_urcu_writer = (_proc_urcu_writer|(1<<4))"
+ line 411, "pan.___", state 195, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 201, "(1)"
+ line 415, "pan.___", state 209, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 215, "(1)"
+ line 415, "pan.___", state 216, "(1)"
+ line 415, "pan.___", state 216, "(1)"
+ line 420, "pan.___", state 229, "(1)"
+ line 424, "pan.___", state 241, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 259, "(1)"
+ line 253, "pan.___", state 267, "(1)"
+ line 261, "pan.___", state 287, "(1)"
+ line 431, "pan.___", state 299, "(1)"
+ line 431, "pan.___", state 299, "(1)"
+ line 415, "pan.___", state 322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 380, "(1)"
+ line 261, "pan.___", state 400, "(1)"
+ line 415, "pan.___", state 443, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 501, "(1)"
+ line 415, "pan.___", state 554, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 612, "(1)"
+ line 415, "pan.___", state 667, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 699, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 725, "(1)"
+ line 261, "pan.___", state 745, "(1)"
+ line 1168, "pan.___", state 770, "_proc_urcu_writer = (_proc_urcu_writer|(1<<13))"
+ line 272, "pan.___", state 798, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 800, "(1)"
+ line 276, "pan.___", state 807, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 809, "(1)"
+ line 276, "pan.___", state 810, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 810, "else"
+ line 274, "pan.___", state 815, "((i<1))"
+ line 274, "pan.___", state 815, "((i>=1))"
+ line 280, "pan.___", state 820, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 822, "(1)"
+ line 280, "pan.___", state 823, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 823, "else"
+ line 284, "pan.___", state 829, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 831, "(1)"
+ line 284, "pan.___", state 832, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 832, "else"
+ line 282, "pan.___", state 837, "((i<2))"
+ line 282, "pan.___", state 837, "((i>=2))"
+ line 249, "pan.___", state 845, "(1)"
+ line 253, "pan.___", state 853, "(1)"
+ line 253, "pan.___", state 854, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 854, "else"
+ line 251, "pan.___", state 859, "((i<1))"
+ line 251, "pan.___", state 859, "((i>=1))"
+ line 257, "pan.___", state 865, "(1)"
+ line 257, "pan.___", state 866, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 866, "else"
+ line 261, "pan.___", state 873, "(1)"
+ line 261, "pan.___", state 874, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 874, "else"
+ line 266, "pan.___", state 883, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 883, "else"
+ line 1222, "pan.___", state 899, "((i<1))"
+ line 1222, "pan.___", state 899, "((i>=1))"
+ line 272, "pan.___", state 904, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 906, "(1)"
+ line 276, "pan.___", state 913, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 915, "(1)"
+ line 276, "pan.___", state 916, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 916, "else"
+ line 274, "pan.___", state 921, "((i<1))"
+ line 274, "pan.___", state 921, "((i>=1))"
+ line 280, "pan.___", state 926, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 928, "(1)"
+ line 280, "pan.___", state 929, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 929, "else"
+ line 284, "pan.___", state 935, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 937, "(1)"
+ line 284, "pan.___", state 938, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 938, "else"
+ line 282, "pan.___", state 943, "((i<2))"
+ line 282, "pan.___", state 943, "((i>=2))"
+ line 249, "pan.___", state 951, "(1)"
+ line 253, "pan.___", state 959, "(1)"
+ line 253, "pan.___", state 960, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 960, "else"
+ line 251, "pan.___", state 965, "((i<1))"
+ line 251, "pan.___", state 965, "((i>=1))"
+ line 257, "pan.___", state 971, "(1)"
+ line 257, "pan.___", state 972, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 972, "else"
+ line 261, "pan.___", state 979, "(1)"
+ line 261, "pan.___", state 980, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 980, "else"
+ line 266, "pan.___", state 989, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 989, "else"
+ line 299, "pan.___", state 991, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 991, "else"
+ line 1222, "pan.___", state 992, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 1222, "pan.___", state 992, "else"
+ line 276, "pan.___", state 1005, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1018, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1027, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1043, "(1)"
+ line 253, "pan.___", state 1051, "(1)"
+ line 257, "pan.___", state 1063, "(1)"
+ line 261, "pan.___", state 1071, "(1)"
+ line 272, "pan.___", state 1102, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1111, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1124, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1133, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1149, "(1)"
+ line 253, "pan.___", state 1157, "(1)"
+ line 257, "pan.___", state 1169, "(1)"
+ line 261, "pan.___", state 1177, "(1)"
+ line 276, "pan.___", state 1203, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1225, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1241, "(1)"
+ line 253, "pan.___", state 1249, "(1)"
+ line 257, "pan.___", state 1261, "(1)"
+ line 261, "pan.___", state 1269, "(1)"
+ line 272, "pan.___", state 1300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1309, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1322, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1331, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1347, "(1)"
+ line 253, "pan.___", state 1355, "(1)"
+ line 257, "pan.___", state 1367, "(1)"
+ line 261, "pan.___", state 1375, "(1)"
+ line 272, "pan.___", state 1392, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1394, "(1)"
+ line 276, "pan.___", state 1401, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1403, "(1)"
+ line 276, "pan.___", state 1404, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1404, "else"
+ line 274, "pan.___", state 1409, "((i<1))"
+ line 274, "pan.___", state 1409, "((i>=1))"
+ line 280, "pan.___", state 1414, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1416, "(1)"
+ line 280, "pan.___", state 1417, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1417, "else"
+ line 284, "pan.___", state 1423, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1425, "(1)"
+ line 284, "pan.___", state 1426, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1426, "else"
+ line 282, "pan.___", state 1431, "((i<2))"
+ line 282, "pan.___", state 1431, "((i>=2))"
+ line 249, "pan.___", state 1439, "(1)"
+ line 253, "pan.___", state 1447, "(1)"
+ line 253, "pan.___", state 1448, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1448, "else"
+ line 251, "pan.___", state 1453, "((i<1))"
+ line 251, "pan.___", state 1453, "((i>=1))"
+ line 257, "pan.___", state 1459, "(1)"
+ line 257, "pan.___", state 1460, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1460, "else"
+ line 261, "pan.___", state 1467, "(1)"
+ line 261, "pan.___", state 1468, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1468, "else"
+ line 266, "pan.___", state 1477, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1477, "else"
+ line 1233, "pan.___", state 1480, "i = 0"
+ line 1233, "pan.___", state 1482, "reader_barrier = 1"
+ line 1233, "pan.___", state 1493, "((i<1))"
+ line 1233, "pan.___", state 1493, "((i>=1))"
+ line 272, "pan.___", state 1498, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1500, "(1)"
+ line 276, "pan.___", state 1507, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1509, "(1)"
+ line 276, "pan.___", state 1510, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1510, "else"
+ line 274, "pan.___", state 1515, "((i<1))"
+ line 274, "pan.___", state 1515, "((i>=1))"
+ line 280, "pan.___", state 1520, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1522, "(1)"
+ line 280, "pan.___", state 1523, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1523, "else"
+ line 284, "pan.___", state 1529, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1531, "(1)"
+ line 284, "pan.___", state 1532, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1532, "else"
+ line 282, "pan.___", state 1537, "((i<2))"
+ line 282, "pan.___", state 1537, "((i>=2))"
+ line 249, "pan.___", state 1545, "(1)"
+ line 253, "pan.___", state 1553, "(1)"
+ line 253, "pan.___", state 1554, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1554, "else"
+ line 251, "pan.___", state 1559, "((i<1))"
+ line 251, "pan.___", state 1559, "((i>=1))"
+ line 257, "pan.___", state 1565, "(1)"
+ line 257, "pan.___", state 1566, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1566, "else"
+ line 261, "pan.___", state 1573, "(1)"
+ line 261, "pan.___", state 1574, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1574, "else"
+ line 266, "pan.___", state 1583, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1583, "else"
+ line 299, "pan.___", state 1585, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1585, "else"
+ line 1233, "pan.___", state 1586, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 1233, "pan.___", state 1586, "else"
+ line 1237, "pan.___", state 1589, "-end-"
+ (179 of 1589 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 241 seconds
+pan: rate 33888.985 states/second
+pan: avg transition delay 2.673e-06 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
--- /dev/null
+#define NO_MB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_RMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 9420 States= 1e+06 Transitions= 7.12e+06 Memory= 550.432 t= 17.7 R= 6e+04
+Depth= 9420 States= 2e+06 Transitions= 1.53e+07 Memory= 634.318 t= 38.9 R= 5e+04
+Depth= 9420 States= 3e+06 Transitions= 2.54e+07 Memory= 718.303 t= 66.3 R= 5e+04
+pan: resizing hashtable to -w22.. done
+Depth= 9420 States= 4e+06 Transitions= 3.3e+07 Memory= 833.311 t= 86.1 R= 5e+04
+Depth= 9420 States= 5e+06 Transitions= 4.08e+07 Memory= 917.295 t= 106 R= 5e+04
+Depth= 9420 States= 6e+06 Transitions= 5.88e+07 Memory= 1001.279 t= 157 R= 4e+04
+Depth= 9420 States= 7e+06 Transitions= 7.01e+07 Memory= 1085.264 t= 187 R= 4e+04
+Depth= 9420 States= 8e+06 Transitions= 8.44e+07 Memory= 1169.151 t= 227 R= 4e+04
+Depth= 9420 States= 9e+06 Transitions= 9.77e+07 Memory= 1253.135 t= 264 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 9420 States= 1e+07 Transitions= 1.11e+08 Memory= 1461.115 t= 302 R= 3e+04
+Depth= 9420 States= 1.1e+07 Transitions= 1.24e+08 Memory= 1545.100 t= 336 R= 3e+04
+Depth= 9420 States= 1.2e+07 Transitions= 1.33e+08 Memory= 1629.084 t= 362 R= 3e+04
+Depth= 9420 States= 1.3e+07 Transitions= 1.46e+08 Memory= 1713.068 t= 397 R= 3e+04
+Depth= 9420 States= 1.4e+07 Transitions= 1.76e+08 Memory= 1797.053 t= 485 R= 3e+04
+Depth= 9420 States= 1.5e+07 Transitions= 1.95e+08 Memory= 1881.037 t= 540 R= 3e+04
+Depth= 9420 States= 1.6e+07 Transitions= 2.12e+08 Memory= 1964.924 t= 587 R= 3e+04
+Depth= 9420 States= 1.7e+07 Transitions= 2.25e+08 Memory= 2048.908 t= 622 R= 3e+04
+Depth= 9420 States= 1.8e+07 Transitions= 2.44e+08 Memory= 2132.893 t= 676 R= 3e+04
+Depth= 9420 States= 1.9e+07 Transitions= 2.6e+08 Memory= 2216.877 t= 721 R= 3e+04
+Depth= 9420 States= 2e+07 Transitions= 2.78e+08 Memory= 2300.861 t= 771 R= 3e+04
+Depth= 9522 States= 2.1e+07 Transitions= 2.91e+08 Memory= 2384.846 t= 808 R= 3e+04
+Depth= 9542 States= 2.2e+07 Transitions= 3.05e+08 Memory= 2468.830 t= 847 R= 3e+04
+Depth= 9542 States= 2.3e+07 Transitions= 3.16e+08 Memory= 2552.717 t= 878 R= 3e+04
+Depth= 9542 States= 2.4e+07 Transitions= 3.28e+08 Memory= 2636.701 t= 910 R= 3e+04
+Depth= 9542 States= 2.5e+07 Transitions= 3.41e+08 Memory= 2720.686 t= 947 R= 3e+04
+Depth= 9542 States= 2.6e+07 Transitions= 3.53e+08 Memory= 2804.670 t= 979 R= 3e+04
+Depth= 9542 States= 2.7e+07 Transitions= 3.66e+08 Memory= 2888.654 t= 1.02e+03 R= 3e+04
+Depth= 9542 States= 2.8e+07 Transitions= 3.79e+08 Memory= 2972.639 t= 1.05e+03 R= 3e+04
+Depth= 9542 States= 2.9e+07 Transitions= 3.92e+08 Memory= 3056.526 t= 1.09e+03 R= 3e+04
+Depth= 9542 States= 3e+07 Transitions= 4.04e+08 Memory= 3140.510 t= 1.12e+03 R= 3e+04
+Depth= 9542 States= 3.1e+07 Transitions= 4.17e+08 Memory= 3224.494 t= 1.16e+03 R= 3e+04
+Depth= 9542 States= 3.2e+07 Transitions= 4.28e+08 Memory= 3308.479 t= 1.19e+03 R= 3e+04
+Depth= 9542 States= 3.3e+07 Transitions= 4.39e+08 Memory= 3392.463 t= 1.22e+03 R= 3e+04
+Depth= 9542 States= 3.4e+07 Transitions= 4.53e+08 Memory= 3476.447 t= 1.26e+03 R= 3e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9542 States= 3.5e+07 Transitions= 4.7e+08 Memory= 4056.416 t= 1.32e+03 R= 3e+04
+Depth= 9542 States= 3.6e+07 Transitions= 4.83e+08 Memory= 4140.401 t= 1.35e+03 R= 3e+04
+Depth= 9542 States= 3.7e+07 Transitions= 4.99e+08 Memory= 4224.385 t= 1.4e+03 R= 3e+04
+Depth= 9542 States= 3.8e+07 Transitions= 5.14e+08 Memory= 4308.369 t= 1.44e+03 R= 3e+04
+Depth= 9542 States= 3.9e+07 Transitions= 5.29e+08 Memory= 4392.354 t= 1.48e+03 R= 3e+04
+Depth= 9542 States= 4e+07 Transitions= 5.39e+08 Memory= 4476.338 t= 1.51e+03 R= 3e+04
+Depth= 9542 States= 4.1e+07 Transitions= 5.49e+08 Memory= 4560.225 t= 1.53e+03 R= 3e+04
+Depth= 9542 States= 4.2e+07 Transitions= 5.61e+08 Memory= 4644.209 t= 1.56e+03 R= 3e+04
+Depth= 9542 States= 4.3e+07 Transitions= 5.88e+08 Memory= 4728.193 t= 1.64e+03 R= 3e+04
+Depth= 9542 States= 4.4e+07 Transitions= 6.14e+08 Memory= 4812.178 t= 1.72e+03 R= 3e+04
+Depth= 9542 States= 4.5e+07 Transitions= 6.31e+08 Memory= 4896.162 t= 1.76e+03 R= 3e+04
+Depth= 9542 States= 4.6e+07 Transitions= 6.41e+08 Memory= 4980.147 t= 1.79e+03 R= 3e+04
+Depth= 9542 States= 4.7e+07 Transitions= 6.57e+08 Memory= 5064.131 t= 1.84e+03 R= 3e+04
+Depth= 9542 States= 4.8e+07 Transitions= 6.76e+08 Memory= 5148.018 t= 1.89e+03 R= 3e+04
+Depth= 9542 States= 4.9e+07 Transitions= 6.93e+08 Memory= 5232.002 t= 1.94e+03 R= 3e+04
+Depth= 9542 States= 5e+07 Transitions= 7.08e+08 Memory= 5315.986 t= 1.98e+03 R= 3e+04
+Depth= 9542 States= 5.1e+07 Transitions= 7.21e+08 Memory= 5399.971 t= 2.02e+03 R= 3e+04
+Depth= 9542 States= 5.2e+07 Transitions= 7.34e+08 Memory= 5483.955 t= 2.05e+03 R= 3e+04
+Depth= 9542 States= 5.3e+07 Transitions= 7.47e+08 Memory= 5567.940 t= 2.09e+03 R= 3e+04
+Depth= 9542 States= 5.4e+07 Transitions= 7.58e+08 Memory= 5651.826 t= 2.12e+03 R= 3e+04
+Depth= 9542 States= 5.5e+07 Transitions= 7.71e+08 Memory= 5735.811 t= 2.15e+03 R= 3e+04
+Depth= 9542 States= 5.6e+07 Transitions= 7.83e+08 Memory= 5819.795 t= 2.19e+03 R= 3e+04
+Depth= 9542 States= 5.7e+07 Transitions= 7.98e+08 Memory= 5903.779 t= 2.23e+03 R= 3e+04
+Depth= 9542 States= 5.8e+07 Transitions= 8.08e+08 Memory= 5987.764 t= 2.25e+03 R= 3e+04
+Depth= 9542 States= 5.9e+07 Transitions= 8.22e+08 Memory= 6071.748 t= 2.29e+03 R= 3e+04
+Depth= 9542 States= 6e+07 Transitions= 8.33e+08 Memory= 6155.733 t= 2.32e+03 R= 3e+04
+Depth= 9542 States= 6.1e+07 Transitions= 8.44e+08 Memory= 6239.619 t= 2.35e+03 R= 3e+04
+Depth= 9542 States= 6.2e+07 Transitions= 8.56e+08 Memory= 6323.604 t= 2.39e+03 R= 3e+04
+Depth= 9542 States= 6.3e+07 Transitions= 8.74e+08 Memory= 6407.588 t= 2.44e+03 R= 3e+04
+Depth= 9542 States= 6.4e+07 Transitions= 8.86e+08 Memory= 6491.572 t= 2.47e+03 R= 3e+04
+Depth= 9542 States= 6.5e+07 Transitions= 9.01e+08 Memory= 6575.557 t= 2.51e+03 R= 3e+04
+Depth= 9542 States= 6.6e+07 Transitions= 9.17e+08 Memory= 6659.541 t= 2.55e+03 R= 3e+04
+Depth= 9542 States= 6.7e+07 Transitions= 9.31e+08 Memory= 6743.428 t= 2.59e+03 R= 3e+04
+Depth= 9542 States= 6.8e+07 Transitions= 9.46e+08 Memory= 6827.412 t= 2.64e+03 R= 3e+04
+Depth= 9542 States= 6.9e+07 Transitions= 9.6e+08 Memory= 6911.397 t= 2.67e+03 R= 3e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 9542, errors: 0
+ 69795266 states, stored
+9.0126381e+08 states, matched
+9.7105908e+08 transitions (= stored+matched)
+1.4943649e+10 atomic steps
+hash conflicts: 5.4028862e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7721.187 equivalent memory usage for states (stored*(State-vector + overhead))
+ 6011.798 actual memory usage for states (compression: 77.86%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 3.368 memory lost to fragmentation
+ 6978.193 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 272, "pan.___", state 30, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 61, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 77, "(1)"
+ line 253, "pan.___", state 85, "(1)"
+ line 257, "pan.___", state 97, "(1)"
+ line 261, "pan.___", state 105, "(1)"
+ line 411, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 163, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 177, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 195, "(1)"
+ line 257, "pan.___", state 215, "(1)"
+ line 261, "pan.___", state 223, "(1)"
+ line 691, "pan.___", state 242, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 249, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 281, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 295, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 313, "(1)"
+ line 257, "pan.___", state 333, "(1)"
+ line 261, "pan.___", state 341, "(1)"
+ line 411, "pan.___", state 360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 392, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 406, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 424, "(1)"
+ line 257, "pan.___", state 444, "(1)"
+ line 261, "pan.___", state 452, "(1)"
+ line 411, "pan.___", state 473, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 475, "(1)"
+ line 411, "pan.___", state 476, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 476, "else"
+ line 411, "pan.___", state 479, "(1)"
+ line 415, "pan.___", state 487, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 489, "(1)"
+ line 415, "pan.___", state 490, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 490, "else"
+ line 415, "pan.___", state 493, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 413, "pan.___", state 499, "((i<1))"
+ line 413, "pan.___", state 499, "((i>=1))"
+ line 420, "pan.___", state 505, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 507, "(1)"
+ line 420, "pan.___", state 508, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 508, "else"
+ line 420, "pan.___", state 511, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 424, "pan.___", state 519, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 521, "(1)"
+ line 424, "pan.___", state 522, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 522, "else"
+ line 424, "pan.___", state 525, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 422, "pan.___", state 531, "((i<2))"
+ line 422, "pan.___", state 531, "((i>=2))"
+ line 249, "pan.___", state 537, "(1)"
+ line 253, "pan.___", state 545, "(1)"
+ line 253, "pan.___", state 546, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 546, "else"
+ line 251, "pan.___", state 551, "((i<1))"
+ line 251, "pan.___", state 551, "((i>=1))"
+ line 257, "pan.___", state 557, "(1)"
+ line 257, "pan.___", state 558, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 558, "else"
+ line 261, "pan.___", state 565, "(1)"
+ line 261, "pan.___", state 566, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 566, "else"
+ line 259, "pan.___", state 571, "((i<2))"
+ line 259, "pan.___", state 571, "((i>=2))"
+ line 266, "pan.___", state 575, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 575, "else"
+ line 431, "pan.___", state 577, "(1)"
+ line 431, "pan.___", state 577, "(1)"
+ line 691, "pan.___", state 580, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 691, "pan.___", state 581, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 691, "pan.___", state 582, "(1)"
+ line 411, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 621, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 635, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 653, "(1)"
+ line 257, "pan.___", state 673, "(1)"
+ line 261, "pan.___", state 681, "(1)"
+ line 411, "pan.___", state 707, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 739, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 753, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 771, "(1)"
+ line 257, "pan.___", state 791, "(1)"
+ line 261, "pan.___", state 799, "(1)"
+ line 411, "pan.___", state 818, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 820, "(1)"
+ line 411, "pan.___", state 821, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 821, "else"
+ line 411, "pan.___", state 824, "(1)"
+ line 415, "pan.___", state 832, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 834, "(1)"
+ line 415, "pan.___", state 835, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 835, "else"
+ line 415, "pan.___", state 838, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 413, "pan.___", state 844, "((i<1))"
+ line 413, "pan.___", state 844, "((i>=1))"
+ line 420, "pan.___", state 850, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 852, "(1)"
+ line 420, "pan.___", state 853, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 853, "else"
+ line 420, "pan.___", state 856, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 424, "pan.___", state 864, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 866, "(1)"
+ line 424, "pan.___", state 867, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 867, "else"
+ line 424, "pan.___", state 870, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 422, "pan.___", state 876, "((i<2))"
+ line 422, "pan.___", state 876, "((i>=2))"
+ line 249, "pan.___", state 882, "(1)"
+ line 253, "pan.___", state 890, "(1)"
+ line 253, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 891, "else"
+ line 251, "pan.___", state 896, "((i<1))"
+ line 251, "pan.___", state 896, "((i>=1))"
+ line 257, "pan.___", state 902, "(1)"
+ line 257, "pan.___", state 903, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 903, "else"
+ line 261, "pan.___", state 910, "(1)"
+ line 261, "pan.___", state 911, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 911, "else"
+ line 259, "pan.___", state 916, "((i<2))"
+ line 259, "pan.___", state 916, "((i>=2))"
+ line 266, "pan.___", state 920, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 920, "else"
+ line 431, "pan.___", state 922, "(1)"
+ line 431, "pan.___", state 922, "(1)"
+ line 699, "pan.___", state 926, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 963, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 977, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 995, "(1)"
+ line 257, "pan.___", state 1015, "(1)"
+ line 261, "pan.___", state 1023, "(1)"
+ line 411, "pan.___", state 1045, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1077, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1091, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1109, "(1)"
+ line 257, "pan.___", state 1129, "(1)"
+ line 261, "pan.___", state 1137, "(1)"
+ line 411, "pan.___", state 1160, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1192, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1206, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1224, "(1)"
+ line 257, "pan.___", state 1244, "(1)"
+ line 261, "pan.___", state 1252, "(1)"
+ line 411, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1303, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1317, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1335, "(1)"
+ line 257, "pan.___", state 1355, "(1)"
+ line 261, "pan.___", state 1363, "(1)"
+ line 411, "pan.___", state 1387, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1419, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1433, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1451, "(1)"
+ line 257, "pan.___", state 1471, "(1)"
+ line 261, "pan.___", state 1479, "(1)"
+ line 411, "pan.___", state 1498, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1530, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1544, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1562, "(1)"
+ line 257, "pan.___", state 1582, "(1)"
+ line 261, "pan.___", state 1590, "(1)"
+ line 411, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1644, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1658, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1676, "(1)"
+ line 257, "pan.___", state 1696, "(1)"
+ line 261, "pan.___", state 1704, "(1)"
+ line 738, "pan.___", state 1723, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1730, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1762, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1776, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1794, "(1)"
+ line 257, "pan.___", state 1814, "(1)"
+ line 261, "pan.___", state 1822, "(1)"
+ line 411, "pan.___", state 1841, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1873, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1887, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1905, "(1)"
+ line 257, "pan.___", state 1925, "(1)"
+ line 261, "pan.___", state 1933, "(1)"
+ line 411, "pan.___", state 1954, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 1956, "(1)"
+ line 411, "pan.___", state 1957, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 1957, "else"
+ line 411, "pan.___", state 1960, "(1)"
+ line 415, "pan.___", state 1968, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1970, "(1)"
+ line 415, "pan.___", state 1971, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 1971, "else"
+ line 415, "pan.___", state 1974, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 413, "pan.___", state 1980, "((i<1))"
+ line 413, "pan.___", state 1980, "((i>=1))"
+ line 420, "pan.___", state 1986, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1988, "(1)"
+ line 420, "pan.___", state 1989, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 1989, "else"
+ line 420, "pan.___", state 1992, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 424, "pan.___", state 2000, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2002, "(1)"
+ line 424, "pan.___", state 2003, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2003, "else"
+ line 424, "pan.___", state 2006, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 422, "pan.___", state 2012, "((i<2))"
+ line 422, "pan.___", state 2012, "((i>=2))"
+ line 249, "pan.___", state 2018, "(1)"
+ line 253, "pan.___", state 2026, "(1)"
+ line 253, "pan.___", state 2027, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2027, "else"
+ line 251, "pan.___", state 2032, "((i<1))"
+ line 251, "pan.___", state 2032, "((i>=1))"
+ line 257, "pan.___", state 2038, "(1)"
+ line 257, "pan.___", state 2039, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2039, "else"
+ line 261, "pan.___", state 2046, "(1)"
+ line 261, "pan.___", state 2047, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2047, "else"
+ line 259, "pan.___", state 2052, "((i<2))"
+ line 259, "pan.___", state 2052, "((i>=2))"
+ line 266, "pan.___", state 2056, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2056, "else"
+ line 431, "pan.___", state 2058, "(1)"
+ line 431, "pan.___", state 2058, "(1)"
+ line 738, "pan.___", state 2061, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 738, "pan.___", state 2062, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 738, "pan.___", state 2063, "(1)"
+ line 411, "pan.___", state 2070, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2102, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2116, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2134, "(1)"
+ line 257, "pan.___", state 2154, "(1)"
+ line 261, "pan.___", state 2162, "(1)"
+ line 411, "pan.___", state 2187, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2219, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2233, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2251, "(1)"
+ line 257, "pan.___", state 2271, "(1)"
+ line 261, "pan.___", state 2279, "(1)"
+ line 411, "pan.___", state 2298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2362, "(1)"
+ line 257, "pan.___", state 2382, "(1)"
+ line 261, "pan.___", state 2390, "(1)"
+ line 411, "pan.___", state 2421, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2453, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2467, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2485, "(1)"
+ line 257, "pan.___", state 2505, "(1)"
+ line 261, "pan.___", state 2513, "(1)"
+ line 411, "pan.___", state 2530, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2562, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2576, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2594, "(1)"
+ line 257, "pan.___", state 2614, "(1)"
+ line 261, "pan.___", state 2622, "(1)"
+ line 898, "pan.___", state 2641, "-end-"
+ (227 of 2641 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 82, "(1)"
+ line 253, "pan.___", state 90, "(1)"
+ line 257, "pan.___", state 102, "(1)"
+ line 272, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 257, "(1)"
+ line 253, "pan.___", state 265, "(1)"
+ line 257, "pan.___", state 277, "(1)"
+ line 261, "pan.___", state 285, "(1)"
+ line 415, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 378, "(1)"
+ line 257, "pan.___", state 390, "(1)"
+ line 261, "pan.___", state 398, "(1)"
+ line 415, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 499, "(1)"
+ line 257, "pan.___", state 511, "(1)"
+ line 261, "pan.___", state 519, "(1)"
+ line 415, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 610, "(1)"
+ line 257, "pan.___", state 622, "(1)"
+ line 261, "pan.___", state 630, "(1)"
+ line 415, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 723, "(1)"
+ line 257, "pan.___", state 735, "(1)"
+ line 261, "pan.___", state 743, "(1)"
+ line 272, "pan.___", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 820, "(1)"
+ line 284, "pan.___", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 843, "(1)"
+ line 253, "pan.___", state 851, "(1)"
+ line 257, "pan.___", state 863, "(1)"
+ line 261, "pan.___", state 871, "(1)"
+ line 272, "pan.___", state 902, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 911, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 924, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 933, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 949, "(1)"
+ line 253, "pan.___", state 957, "(1)"
+ line 257, "pan.___", state 969, "(1)"
+ line 261, "pan.___", state 977, "(1)"
+ line 276, "pan.___", state 1003, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1016, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1025, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1041, "(1)"
+ line 253, "pan.___", state 1049, "(1)"
+ line 257, "pan.___", state 1061, "(1)"
+ line 261, "pan.___", state 1069, "(1)"
+ line 272, "pan.___", state 1100, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1109, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1122, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1131, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1147, "(1)"
+ line 253, "pan.___", state 1155, "(1)"
+ line 257, "pan.___", state 1167, "(1)"
+ line 261, "pan.___", state 1175, "(1)"
+ line 276, "pan.___", state 1201, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1214, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1223, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1239, "(1)"
+ line 253, "pan.___", state 1247, "(1)"
+ line 257, "pan.___", state 1259, "(1)"
+ line 261, "pan.___", state 1267, "(1)"
+ line 272, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1307, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1320, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1329, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1345, "(1)"
+ line 253, "pan.___", state 1353, "(1)"
+ line 257, "pan.___", state 1365, "(1)"
+ line 261, "pan.___", state 1373, "(1)"
+ line 276, "pan.___", state 1399, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1412, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1421, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1437, "(1)"
+ line 253, "pan.___", state 1445, "(1)"
+ line 257, "pan.___", state 1457, "(1)"
+ line 261, "pan.___", state 1465, "(1)"
+ line 272, "pan.___", state 1496, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1505, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1518, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1527, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1543, "(1)"
+ line 253, "pan.___", state 1551, "(1)"
+ line 257, "pan.___", state 1563, "(1)"
+ line 261, "pan.___", state 1571, "(1)"
+ line 1237, "pan.___", state 1587, "-end-"
+ (103 of 1587 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 2.7e+03 seconds
+pan: rate 25814.341 states/second
+pan: avg transition delay 2.7843e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
--- /dev/null
+#define NO_RMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define NO_WMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 9172 States= 1e+06 Transitions= 6.87e+06 Memory= 550.432 t= 17 R= 6e+04
+Depth= 9172 States= 2e+06 Transitions= 1.47e+07 Memory= 634.318 t= 37.6 R= 5e+04
+Depth= 9172 States= 3e+06 Transitions= 2.46e+07 Memory= 718.303 t= 64.2 R= 5e+04
+pan: resizing hashtable to -w22.. done
+Depth= 9172 States= 4e+06 Transitions= 3.19e+07 Memory= 833.311 t= 83.2 R= 5e+04
+Depth= 9172 States= 5e+06 Transitions= 3.95e+07 Memory= 917.295 t= 103 R= 5e+04
+Depth= 9172 States= 6e+06 Transitions= 5.71e+07 Memory= 1001.279 t= 152 R= 4e+04
+Depth= 9172 States= 7e+06 Transitions= 6.81e+07 Memory= 1085.264 t= 182 R= 4e+04
+Depth= 9172 States= 8e+06 Transitions= 8.22e+07 Memory= 1169.151 t= 221 R= 4e+04
+Depth= 9172 States= 9e+06 Transitions= 9.54e+07 Memory= 1253.135 t= 258 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 9172 States= 1e+07 Transitions= 1.08e+08 Memory= 1461.115 t= 295 R= 3e+04
+Depth= 9172 States= 1.1e+07 Transitions= 1.2e+08 Memory= 1545.100 t= 327 R= 3e+04
+Depth= 9172 States= 1.2e+07 Transitions= 1.27e+08 Memory= 1629.084 t= 344 R= 3e+04
+Depth= 9172 States= 1.3e+07 Transitions= 1.35e+08 Memory= 1713.068 t= 365 R= 4e+04
+Depth= 9172 States= 1.4e+07 Transitions= 1.46e+08 Memory= 1797.053 t= 394 R= 4e+04
+Depth= 9172 States= 1.5e+07 Transitions= 1.53e+08 Memory= 1881.037 t= 413 R= 4e+04
+Depth= 9172 States= 1.6e+07 Transitions= 1.6e+08 Memory= 1964.924 t= 432 R= 4e+04
+Depth= 9172 States= 1.7e+07 Transitions= 1.76e+08 Memory= 2048.908 t= 475 R= 4e+04
+Depth= 9172 States= 1.8e+07 Transitions= 1.9e+08 Memory= 2132.893 t= 515 R= 3e+04
+Depth= 9172 States= 1.9e+07 Transitions= 2.02e+08 Memory= 2216.877 t= 548 R= 3e+04
+Depth= 9172 States= 2e+07 Transitions= 2.15e+08 Memory= 2300.861 t= 585 R= 3e+04
+Depth= 9172 States= 2.1e+07 Transitions= 2.25e+08 Memory= 2384.846 t= 610 R= 3e+04
+Depth= 9172 States= 2.2e+07 Transitions= 2.38e+08 Memory= 2468.830 t= 646 R= 3e+04
+Depth= 9172 States= 2.3e+07 Transitions= 2.67e+08 Memory= 2552.717 t= 732 R= 3e+04
+Depth= 9172 States= 2.4e+07 Transitions= 2.86e+08 Memory= 2636.701 t= 785 R= 3e+04
+Depth= 9172 States= 2.5e+07 Transitions= 3.03e+08 Memory= 2720.686 t= 832 R= 3e+04
+Depth= 9172 States= 2.6e+07 Transitions= 3.12e+08 Memory= 2804.670 t= 857 R= 3e+04
+Depth= 9172 States= 2.7e+07 Transitions= 3.27e+08 Memory= 2888.654 t= 899 R= 3e+04
+Depth= 9172 States= 2.8e+07 Transitions= 3.57e+08 Memory= 2972.639 t= 987 R= 3e+04
+Depth= 9172 States= 2.9e+07 Transitions= 3.73e+08 Memory= 3056.526 t= 1.03e+03 R= 3e+04
+Depth= 9172 States= 3e+07 Transitions= 3.86e+08 Memory= 3140.510 t= 1.07e+03 R= 3e+04
+Depth= 9172 States= 3.1e+07 Transitions= 4.03e+08 Memory= 3224.494 t= 1.12e+03 R= 3e+04
+Depth= 9172 States= 3.2e+07 Transitions= 4.22e+08 Memory= 3308.479 t= 1.17e+03 R= 3e+04
+Depth= 9172 States= 3.3e+07 Transitions= 4.39e+08 Memory= 3392.463 t= 1.22e+03 R= 3e+04
+Depth= 9172 States= 3.4e+07 Transitions= 4.56e+08 Memory= 3476.447 t= 1.27e+03 R= 3e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9234 States= 3.5e+07 Transitions= 4.73e+08 Memory= 4056.416 t= 1.33e+03 R= 3e+04
+Depth= 9234 States= 3.6e+07 Transitions= 4.85e+08 Memory= 4140.401 t= 1.36e+03 R= 3e+04
+Depth= 9273 States= 3.7e+07 Transitions= 5e+08 Memory= 4224.385 t= 1.4e+03 R= 3e+04
+Depth= 9273 States= 3.8e+07 Transitions= 5.14e+08 Memory= 4308.369 t= 1.44e+03 R= 3e+04
+Depth= 9273 States= 3.9e+07 Transitions= 5.26e+08 Memory= 4392.354 t= 1.47e+03 R= 3e+04
+Depth= 9273 States= 4e+07 Transitions= 5.39e+08 Memory= 4476.338 t= 1.51e+03 R= 3e+04
+Depth= 9273 States= 4.1e+07 Transitions= 5.5e+08 Memory= 4560.322 t= 1.54e+03 R= 3e+04
+Depth= 9273 States= 4.2e+07 Transitions= 5.64e+08 Memory= 4644.209 t= 1.58e+03 R= 3e+04
+Depth= 9273 States= 4.3e+07 Transitions= 5.75e+08 Memory= 4728.193 t= 1.61e+03 R= 3e+04
+Depth= 9273 States= 4.4e+07 Transitions= 5.86e+08 Memory= 4812.178 t= 1.64e+03 R= 3e+04
+Depth= 9273 States= 4.5e+07 Transitions= 6.01e+08 Memory= 4896.162 t= 1.68e+03 R= 3e+04
+Depth= 9273 States= 4.6e+07 Transitions= 6.16e+08 Memory= 4980.147 t= 1.72e+03 R= 3e+04
+Depth= 9273 States= 4.7e+07 Transitions= 6.29e+08 Memory= 5064.131 t= 1.76e+03 R= 3e+04
+Depth= 9273 States= 4.8e+07 Transitions= 6.4e+08 Memory= 5148.018 t= 1.79e+03 R= 3e+04
+Depth= 9273 States= 4.9e+07 Transitions= 6.51e+08 Memory= 5232.002 t= 1.82e+03 R= 3e+04
+Depth= 9273 States= 5e+07 Transitions= 6.66e+08 Memory= 5315.986 t= 1.86e+03 R= 3e+04
+Depth= 9273 States= 5.1e+07 Transitions= 6.8e+08 Memory= 5399.971 t= 1.9e+03 R= 3e+04
+Depth= 9273 States= 5.2e+07 Transitions= 6.9e+08 Memory= 5483.955 t= 1.93e+03 R= 3e+04
+Depth= 9273 States= 5.3e+07 Transitions= 7.01e+08 Memory= 5567.940 t= 1.96e+03 R= 3e+04
+Depth= 9273 States= 5.4e+07 Transitions= 7.14e+08 Memory= 5651.826 t= 1.99e+03 R= 3e+04
+Depth= 9273 States= 5.5e+07 Transitions= 7.26e+08 Memory= 5735.811 t= 2.02e+03 R= 3e+04
+Depth= 9273 States= 5.6e+07 Transitions= 7.44e+08 Memory= 5819.795 t= 2.07e+03 R= 3e+04
+Depth= 9273 States= 5.7e+07 Transitions= 7.57e+08 Memory= 5903.779 t= 2.11e+03 R= 3e+04
+Depth= 9273 States= 5.8e+07 Transitions= 7.72e+08 Memory= 5987.764 t= 2.15e+03 R= 3e+04
+Depth= 9273 States= 5.9e+07 Transitions= 7.87e+08 Memory= 6071.748 t= 2.19e+03 R= 3e+04
+Depth= 9273 States= 6e+07 Transitions= 8.03e+08 Memory= 6155.733 t= 2.24e+03 R= 3e+04
+Depth= 9273 States= 6.1e+07 Transitions= 8.18e+08 Memory= 6239.619 t= 2.28e+03 R= 3e+04
+Depth= 9273 States= 6.2e+07 Transitions= 8.31e+08 Memory= 6323.604 t= 2.31e+03 R= 3e+04
+Depth= 9273 States= 6.3e+07 Transitions= 8.38e+08 Memory= 6407.588 t= 2.33e+03 R= 3e+04
+Depth= 9273 States= 6.4e+07 Transitions= 8.46e+08 Memory= 6491.572 t= 2.35e+03 R= 3e+04
+Depth= 9273 States= 6.5e+07 Transitions= 8.56e+08 Memory= 6575.557 t= 2.38e+03 R= 3e+04
+Depth= 9273 States= 6.6e+07 Transitions= 8.63e+08 Memory= 6659.541 t= 2.4e+03 R= 3e+04
+Depth= 9273 States= 6.7e+07 Transitions= 8.7e+08 Memory= 6743.428 t= 2.42e+03 R= 3e+04
+Depth= 9273 States= 6.8e+07 Transitions= 8.88e+08 Memory= 6827.412 t= 2.47e+03 R= 3e+04
+Depth= 9273 States= 6.9e+07 Transitions= 9e+08 Memory= 6911.397 t= 2.5e+03 R= 3e+04
+pan: claim violated! (at depth 1431)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 9273, errors: 1
+ 69874699 states, stored
+8.4222224e+08 states, matched
+9.1209694e+08 transitions (= stored+matched)
+1.3919028e+10 atomic steps
+hash conflicts: 5.0632776e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7729.974 equivalent memory usage for states (stored*(State-vector + overhead))
+ 6018.458 actual memory usage for states (compression: 77.86%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 3.388 memory lost to fragmentation
+ 6984.834 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 272, "pan.___", state 30, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 61, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 77, "(1)"
+ line 253, "pan.___", state 85, "(1)"
+ line 257, "pan.___", state 97, "(1)"
+ line 261, "pan.___", state 105, "(1)"
+ line 411, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 163, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 177, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 195, "(1)"
+ line 257, "pan.___", state 215, "(1)"
+ line 261, "pan.___", state 223, "(1)"
+ line 691, "pan.___", state 242, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 249, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 281, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 295, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 313, "(1)"
+ line 257, "pan.___", state 333, "(1)"
+ line 261, "pan.___", state 341, "(1)"
+ line 411, "pan.___", state 360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 392, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 406, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 424, "(1)"
+ line 257, "pan.___", state 444, "(1)"
+ line 261, "pan.___", state 452, "(1)"
+ line 411, "pan.___", state 473, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 475, "(1)"
+ line 411, "pan.___", state 476, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 476, "else"
+ line 411, "pan.___", state 479, "(1)"
+ line 415, "pan.___", state 487, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 489, "(1)"
+ line 415, "pan.___", state 490, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 490, "else"
+ line 415, "pan.___", state 493, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 413, "pan.___", state 499, "((i<1))"
+ line 413, "pan.___", state 499, "((i>=1))"
+ line 420, "pan.___", state 505, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 507, "(1)"
+ line 420, "pan.___", state 508, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 508, "else"
+ line 420, "pan.___", state 511, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 424, "pan.___", state 519, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 521, "(1)"
+ line 424, "pan.___", state 522, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 522, "else"
+ line 424, "pan.___", state 525, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 422, "pan.___", state 531, "((i<2))"
+ line 422, "pan.___", state 531, "((i>=2))"
+ line 249, "pan.___", state 537, "(1)"
+ line 253, "pan.___", state 545, "(1)"
+ line 253, "pan.___", state 546, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 546, "else"
+ line 251, "pan.___", state 551, "((i<1))"
+ line 251, "pan.___", state 551, "((i>=1))"
+ line 257, "pan.___", state 557, "(1)"
+ line 257, "pan.___", state 558, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 558, "else"
+ line 261, "pan.___", state 565, "(1)"
+ line 261, "pan.___", state 566, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 566, "else"
+ line 259, "pan.___", state 571, "((i<2))"
+ line 259, "pan.___", state 571, "((i>=2))"
+ line 266, "pan.___", state 575, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 575, "else"
+ line 431, "pan.___", state 577, "(1)"
+ line 431, "pan.___", state 577, "(1)"
+ line 691, "pan.___", state 580, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 691, "pan.___", state 581, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 691, "pan.___", state 582, "(1)"
+ line 411, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 621, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 635, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 653, "(1)"
+ line 257, "pan.___", state 673, "(1)"
+ line 261, "pan.___", state 681, "(1)"
+ line 411, "pan.___", state 707, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 739, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 753, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 771, "(1)"
+ line 257, "pan.___", state 791, "(1)"
+ line 261, "pan.___", state 799, "(1)"
+ line 411, "pan.___", state 818, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 820, "(1)"
+ line 411, "pan.___", state 821, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 821, "else"
+ line 411, "pan.___", state 824, "(1)"
+ line 415, "pan.___", state 832, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 834, "(1)"
+ line 415, "pan.___", state 835, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 835, "else"
+ line 415, "pan.___", state 838, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 413, "pan.___", state 844, "((i<1))"
+ line 413, "pan.___", state 844, "((i>=1))"
+ line 420, "pan.___", state 850, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 852, "(1)"
+ line 420, "pan.___", state 853, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 853, "else"
+ line 420, "pan.___", state 856, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 424, "pan.___", state 864, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 866, "(1)"
+ line 424, "pan.___", state 867, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 867, "else"
+ line 424, "pan.___", state 870, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 422, "pan.___", state 876, "((i<2))"
+ line 422, "pan.___", state 876, "((i>=2))"
+ line 249, "pan.___", state 882, "(1)"
+ line 253, "pan.___", state 890, "(1)"
+ line 253, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 891, "else"
+ line 251, "pan.___", state 896, "((i<1))"
+ line 251, "pan.___", state 896, "((i>=1))"
+ line 257, "pan.___", state 902, "(1)"
+ line 257, "pan.___", state 903, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 903, "else"
+ line 261, "pan.___", state 910, "(1)"
+ line 261, "pan.___", state 911, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 911, "else"
+ line 259, "pan.___", state 916, "((i<2))"
+ line 259, "pan.___", state 916, "((i>=2))"
+ line 266, "pan.___", state 920, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 920, "else"
+ line 431, "pan.___", state 922, "(1)"
+ line 431, "pan.___", state 922, "(1)"
+ line 699, "pan.___", state 926, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 963, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 977, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 995, "(1)"
+ line 257, "pan.___", state 1015, "(1)"
+ line 261, "pan.___", state 1023, "(1)"
+ line 411, "pan.___", state 1045, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1077, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1091, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1109, "(1)"
+ line 257, "pan.___", state 1129, "(1)"
+ line 261, "pan.___", state 1137, "(1)"
+ line 411, "pan.___", state 1160, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1192, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1206, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1224, "(1)"
+ line 257, "pan.___", state 1244, "(1)"
+ line 261, "pan.___", state 1252, "(1)"
+ line 411, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1303, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1317, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1335, "(1)"
+ line 257, "pan.___", state 1355, "(1)"
+ line 261, "pan.___", state 1363, "(1)"
+ line 411, "pan.___", state 1387, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1419, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1433, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1451, "(1)"
+ line 257, "pan.___", state 1471, "(1)"
+ line 261, "pan.___", state 1479, "(1)"
+ line 411, "pan.___", state 1498, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1530, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1544, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1562, "(1)"
+ line 257, "pan.___", state 1582, "(1)"
+ line 261, "pan.___", state 1590, "(1)"
+ line 411, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1644, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1658, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1676, "(1)"
+ line 257, "pan.___", state 1696, "(1)"
+ line 261, "pan.___", state 1704, "(1)"
+ line 738, "pan.___", state 1723, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1730, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1762, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1776, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1794, "(1)"
+ line 257, "pan.___", state 1814, "(1)"
+ line 261, "pan.___", state 1822, "(1)"
+ line 411, "pan.___", state 1841, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1873, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1887, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1905, "(1)"
+ line 257, "pan.___", state 1925, "(1)"
+ line 261, "pan.___", state 1933, "(1)"
+ line 411, "pan.___", state 1954, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 1956, "(1)"
+ line 411, "pan.___", state 1957, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 1957, "else"
+ line 411, "pan.___", state 1960, "(1)"
+ line 415, "pan.___", state 1968, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1970, "(1)"
+ line 415, "pan.___", state 1971, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 1971, "else"
+ line 415, "pan.___", state 1974, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 413, "pan.___", state 1980, "((i<1))"
+ line 413, "pan.___", state 1980, "((i>=1))"
+ line 420, "pan.___", state 1986, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1988, "(1)"
+ line 420, "pan.___", state 1989, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 1989, "else"
+ line 420, "pan.___", state 1992, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 424, "pan.___", state 2000, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2002, "(1)"
+ line 424, "pan.___", state 2003, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2003, "else"
+ line 424, "pan.___", state 2006, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 422, "pan.___", state 2012, "((i<2))"
+ line 422, "pan.___", state 2012, "((i>=2))"
+ line 249, "pan.___", state 2018, "(1)"
+ line 253, "pan.___", state 2026, "(1)"
+ line 253, "pan.___", state 2027, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2027, "else"
+ line 251, "pan.___", state 2032, "((i<1))"
+ line 251, "pan.___", state 2032, "((i>=1))"
+ line 257, "pan.___", state 2038, "(1)"
+ line 257, "pan.___", state 2039, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2039, "else"
+ line 261, "pan.___", state 2046, "(1)"
+ line 261, "pan.___", state 2047, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2047, "else"
+ line 259, "pan.___", state 2052, "((i<2))"
+ line 259, "pan.___", state 2052, "((i>=2))"
+ line 266, "pan.___", state 2056, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2056, "else"
+ line 431, "pan.___", state 2058, "(1)"
+ line 431, "pan.___", state 2058, "(1)"
+ line 738, "pan.___", state 2061, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 738, "pan.___", state 2062, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 738, "pan.___", state 2063, "(1)"
+ line 411, "pan.___", state 2070, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2102, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2116, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2134, "(1)"
+ line 257, "pan.___", state 2154, "(1)"
+ line 261, "pan.___", state 2162, "(1)"
+ line 411, "pan.___", state 2187, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2219, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2233, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2251, "(1)"
+ line 257, "pan.___", state 2271, "(1)"
+ line 261, "pan.___", state 2279, "(1)"
+ line 411, "pan.___", state 2298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2362, "(1)"
+ line 257, "pan.___", state 2382, "(1)"
+ line 261, "pan.___", state 2390, "(1)"
+ line 249, "pan.___", state 2421, "(1)"
+ line 257, "pan.___", state 2441, "(1)"
+ line 261, "pan.___", state 2449, "(1)"
+ line 249, "pan.___", state 2464, "(1)"
+ line 257, "pan.___", state 2484, "(1)"
+ line 261, "pan.___", state 2492, "(1)"
+ line 898, "pan.___", state 2509, "-end-"
+ (221 of 2509 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 19, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 33, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 83, "(1)"
+ line 253, "pan.___", state 91, "(1)"
+ line 272, "pan.___", state 132, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 134, "(1)"
+ line 276, "pan.___", state 141, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 143, "(1)"
+ line 276, "pan.___", state 144, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 144, "else"
+ line 274, "pan.___", state 149, "((i<1))"
+ line 274, "pan.___", state 149, "((i>=1))"
+ line 280, "pan.___", state 154, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 156, "(1)"
+ line 280, "pan.___", state 157, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 157, "else"
+ line 284, "pan.___", state 163, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 165, "(1)"
+ line 284, "pan.___", state 166, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 166, "else"
+ line 289, "pan.___", state 175, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 289, "pan.___", state 175, "else"
+ line 411, "pan.___", state 194, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 208, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 226, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 240, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 258, "(1)"
+ line 253, "pan.___", state 266, "(1)"
+ line 257, "pan.___", state 278, "(1)"
+ line 261, "pan.___", state 286, "(1)"
+ line 415, "pan.___", state 321, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 339, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 353, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 379, "(1)"
+ line 257, "pan.___", state 391, "(1)"
+ line 261, "pan.___", state 399, "(1)"
+ line 415, "pan.___", state 442, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 460, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 474, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 500, "(1)"
+ line 257, "pan.___", state 512, "(1)"
+ line 261, "pan.___", state 520, "(1)"
+ line 415, "pan.___", state 553, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 571, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 585, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 611, "(1)"
+ line 257, "pan.___", state 623, "(1)"
+ line 261, "pan.___", state 631, "(1)"
+ line 415, "pan.___", state 666, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 684, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 698, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 724, "(1)"
+ line 257, "pan.___", state 736, "(1)"
+ line 261, "pan.___", state 744, "(1)"
+ line 272, "pan.___", state 797, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 806, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 844, "(1)"
+ line 253, "pan.___", state 852, "(1)"
+ line 257, "pan.___", state 864, "(1)"
+ line 261, "pan.___", state 872, "(1)"
+ line 272, "pan.___", state 903, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 912, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 925, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 934, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 950, "(1)"
+ line 253, "pan.___", state 958, "(1)"
+ line 257, "pan.___", state 970, "(1)"
+ line 261, "pan.___", state 978, "(1)"
+ line 276, "pan.___", state 1004, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1017, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1026, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1042, "(1)"
+ line 253, "pan.___", state 1050, "(1)"
+ line 257, "pan.___", state 1062, "(1)"
+ line 261, "pan.___", state 1070, "(1)"
+ line 272, "pan.___", state 1101, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1110, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1123, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1132, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1148, "(1)"
+ line 253, "pan.___", state 1156, "(1)"
+ line 257, "pan.___", state 1168, "(1)"
+ line 261, "pan.___", state 1176, "(1)"
+ line 276, "pan.___", state 1202, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1215, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1224, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1240, "(1)"
+ line 253, "pan.___", state 1248, "(1)"
+ line 257, "pan.___", state 1260, "(1)"
+ line 261, "pan.___", state 1268, "(1)"
+ line 272, "pan.___", state 1299, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1308, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1321, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1330, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1346, "(1)"
+ line 253, "pan.___", state 1354, "(1)"
+ line 257, "pan.___", state 1366, "(1)"
+ line 261, "pan.___", state 1374, "(1)"
+ line 276, "pan.___", state 1400, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1413, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1422, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1438, "(1)"
+ line 253, "pan.___", state 1446, "(1)"
+ line 257, "pan.___", state 1458, "(1)"
+ line 261, "pan.___", state 1466, "(1)"
+ line 272, "pan.___", state 1497, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1506, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1519, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1528, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1544, "(1)"
+ line 253, "pan.___", state 1552, "(1)"
+ line 257, "pan.___", state 1564, "(1)"
+ line 261, "pan.___", state 1572, "(1)"
+ line 1237, "pan.___", state 1588, "-end-"
+ (109 of 1588 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 2.53e+03 seconds
+pan: rate 27617.257 states/second
+pan: avg transition delay 2.7739e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
--- /dev/null
+#define NO_WMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 9112 States= 1e+06 Transitions= 7.1e+06 Memory= 550.432 t= 17.4 R= 6e+04
+Depth= 9112 States= 2e+06 Transitions= 1.64e+07 Memory= 634.318 t= 41.8 R= 5e+04
+Depth= 9112 States= 3e+06 Transitions= 2.63e+07 Memory= 718.303 t= 68.2 R= 4e+04
+pan: resizing hashtable to -w22.. done
+Depth= 9112 States= 4e+06 Transitions= 3.56e+07 Memory= 833.311 t= 93.2 R= 4e+04
+Depth= 9112 States= 5e+06 Transitions= 4.66e+07 Memory= 917.295 t= 122 R= 4e+04
+Depth= 9112 States= 6e+06 Transitions= 5.77e+07 Memory= 1001.279 t= 152 R= 4e+04
+Depth= 9112 States= 7e+06 Transitions= 6.72e+07 Memory= 1085.264 t= 177 R= 4e+04
+Depth= 9112 States= 8e+06 Transitions= 7.41e+07 Memory= 1169.151 t= 194 R= 4e+04
+Depth= 9112 States= 9e+06 Transitions= 8.11e+07 Memory= 1253.135 t= 212 R= 4e+04
+pan: resizing hashtable to -w24.. done
+Depth= 9112 States= 1e+07 Transitions= 8.81e+07 Memory= 1461.115 t= 231 R= 4e+04
+Depth= 9112 States= 1.1e+07 Transitions= 9.84e+07 Memory= 1545.100 t= 259 R= 4e+04
+Depth= 9112 States= 1.2e+07 Transitions= 1.08e+08 Memory= 1629.084 t= 282 R= 4e+04
+Depth= 9112 States= 1.3e+07 Transitions= 1.16e+08 Memory= 1713.068 t= 304 R= 4e+04
+Depth= 9112 States= 1.4e+07 Transitions= 1.25e+08 Memory= 1797.053 t= 329 R= 4e+04
+Depth= 9112 States= 1.5e+07 Transitions= 1.35e+08 Memory= 1881.037 t= 352 R= 4e+04
+Depth= 9278 States= 1.6e+07 Transitions= 1.45e+08 Memory= 1964.924 t= 382 R= 4e+04
+Depth= 9283 States= 1.7e+07 Transitions= 1.56e+08 Memory= 2048.908 t= 409 R= 4e+04
+Depth= 9283 States= 1.8e+07 Transitions= 1.66e+08 Memory= 2132.893 t= 437 R= 4e+04
+Depth= 9283 States= 1.9e+07 Transitions= 1.76e+08 Memory= 2216.877 t= 464 R= 4e+04
+Depth= 9283 States= 2e+07 Transitions= 1.87e+08 Memory= 2300.861 t= 493 R= 4e+04
+Depth= 9283 States= 2.1e+07 Transitions= 1.97e+08 Memory= 2384.846 t= 521 R= 4e+04
+Depth= 9283 States= 2.2e+07 Transitions= 2.08e+08 Memory= 2468.830 t= 549 R= 4e+04
+Depth= 9283 States= 2.3e+07 Transitions= 2.17e+08 Memory= 2552.717 t= 572 R= 4e+04
+Depth= 9283 States= 2.4e+07 Transitions= 2.26e+08 Memory= 2636.701 t= 596 R= 4e+04
+Depth= 9283 States= 2.5e+07 Transitions= 2.37e+08 Memory= 2720.686 t= 627 R= 4e+04
+Depth= 9283 States= 2.6e+07 Transitions= 2.49e+08 Memory= 2804.670 t= 659 R= 4e+04
+Depth= 9283 States= 2.7e+07 Transitions= 2.6e+08 Memory= 2888.654 t= 689 R= 4e+04
+Depth= 9283 States= 2.8e+07 Transitions= 2.71e+08 Memory= 2972.639 t= 718 R= 4e+04
+Depth= 9283 States= 2.9e+07 Transitions= 2.8e+08 Memory= 3056.526 t= 741 R= 4e+04
+Depth= 9283 States= 3e+07 Transitions= 2.89e+08 Memory= 3140.510 t= 764 R= 4e+04
+Depth= 9283 States= 3.1e+07 Transitions= 2.99e+08 Memory= 3224.494 t= 791 R= 4e+04
+Depth= 9283 States= 3.2e+07 Transitions= 3.09e+08 Memory= 3308.479 t= 818 R= 4e+04
+Depth= 9283 States= 3.3e+07 Transitions= 3.19e+08 Memory= 3392.463 t= 846 R= 4e+04
+Depth= 9283 States= 3.4e+07 Transitions= 3.29e+08 Memory= 3476.447 t= 873 R= 4e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9283 States= 3.5e+07 Transitions= 3.39e+08 Memory= 4056.416 t= 908 R= 4e+04
+Depth= 9283 States= 3.6e+07 Transitions= 3.49e+08 Memory= 4140.401 t= 934 R= 4e+04
+Depth= 9283 States= 3.7e+07 Transitions= 3.59e+08 Memory= 4224.385 t= 959 R= 4e+04
+pan: claim violated! (at depth 1298)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 9283, errors: 1
+ 37684654 states, stored
+3.2905753e+08 states, matched
+3.6674218e+08 transitions (= stored+matched)
+5.3145922e+09 atomic steps
+hash conflicts: 2.6456917e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 4168.911 equivalent memory usage for states (stored*(State-vector + overhead))
+ 3314.050 actual memory usage for states (compression: 79.49%)
+ state-vector as stored = 64 byte + 28 byte overhead
+ 512.000 memory used for hash table (-w26)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1.910 memory lost to fragmentation
+ 4281.904 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 272, "pan.___", state 30, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 61, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 77, "(1)"
+ line 253, "pan.___", state 85, "(1)"
+ line 257, "pan.___", state 97, "(1)"
+ line 261, "pan.___", state 105, "(1)"
+ line 411, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 163, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 177, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 195, "(1)"
+ line 257, "pan.___", state 215, "(1)"
+ line 261, "pan.___", state 223, "(1)"
+ line 691, "pan.___", state 242, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 249, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 281, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 295, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 313, "(1)"
+ line 257, "pan.___", state 333, "(1)"
+ line 261, "pan.___", state 341, "(1)"
+ line 411, "pan.___", state 360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 392, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 406, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 424, "(1)"
+ line 257, "pan.___", state 444, "(1)"
+ line 261, "pan.___", state 452, "(1)"
+ line 411, "pan.___", state 473, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 475, "(1)"
+ line 411, "pan.___", state 476, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 476, "else"
+ line 411, "pan.___", state 479, "(1)"
+ line 415, "pan.___", state 487, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 489, "(1)"
+ line 415, "pan.___", state 490, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 490, "else"
+ line 415, "pan.___", state 493, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 415, "pan.___", state 494, "(1)"
+ line 413, "pan.___", state 499, "((i<1))"
+ line 413, "pan.___", state 499, "((i>=1))"
+ line 420, "pan.___", state 505, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 507, "(1)"
+ line 420, "pan.___", state 508, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 508, "else"
+ line 420, "pan.___", state 511, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 420, "pan.___", state 512, "(1)"
+ line 424, "pan.___", state 519, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 521, "(1)"
+ line 424, "pan.___", state 522, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 522, "else"
+ line 424, "pan.___", state 525, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 424, "pan.___", state 526, "(1)"
+ line 422, "pan.___", state 531, "((i<2))"
+ line 422, "pan.___", state 531, "((i>=2))"
+ line 249, "pan.___", state 537, "(1)"
+ line 253, "pan.___", state 545, "(1)"
+ line 253, "pan.___", state 546, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 546, "else"
+ line 251, "pan.___", state 551, "((i<1))"
+ line 251, "pan.___", state 551, "((i>=1))"
+ line 257, "pan.___", state 557, "(1)"
+ line 257, "pan.___", state 558, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 558, "else"
+ line 261, "pan.___", state 565, "(1)"
+ line 261, "pan.___", state 566, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 566, "else"
+ line 259, "pan.___", state 571, "((i<2))"
+ line 259, "pan.___", state 571, "((i>=2))"
+ line 266, "pan.___", state 575, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 575, "else"
+ line 431, "pan.___", state 577, "(1)"
+ line 431, "pan.___", state 577, "(1)"
+ line 691, "pan.___", state 580, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 691, "pan.___", state 581, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 691, "pan.___", state 582, "(1)"
+ line 411, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 621, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 635, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 653, "(1)"
+ line 257, "pan.___", state 673, "(1)"
+ line 261, "pan.___", state 681, "(1)"
+ line 411, "pan.___", state 707, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 739, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 753, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 771, "(1)"
+ line 257, "pan.___", state 791, "(1)"
+ line 261, "pan.___", state 799, "(1)"
+ line 411, "pan.___", state 818, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 820, "(1)"
+ line 411, "pan.___", state 821, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 821, "else"
+ line 411, "pan.___", state 824, "(1)"
+ line 415, "pan.___", state 832, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 834, "(1)"
+ line 415, "pan.___", state 835, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 835, "else"
+ line 415, "pan.___", state 838, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 415, "pan.___", state 839, "(1)"
+ line 413, "pan.___", state 844, "((i<1))"
+ line 413, "pan.___", state 844, "((i>=1))"
+ line 420, "pan.___", state 850, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 852, "(1)"
+ line 420, "pan.___", state 853, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 853, "else"
+ line 420, "pan.___", state 856, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 420, "pan.___", state 857, "(1)"
+ line 424, "pan.___", state 864, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 866, "(1)"
+ line 424, "pan.___", state 867, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 867, "else"
+ line 424, "pan.___", state 870, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 424, "pan.___", state 871, "(1)"
+ line 422, "pan.___", state 876, "((i<2))"
+ line 422, "pan.___", state 876, "((i>=2))"
+ line 249, "pan.___", state 882, "(1)"
+ line 253, "pan.___", state 890, "(1)"
+ line 253, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 891, "else"
+ line 251, "pan.___", state 896, "((i<1))"
+ line 251, "pan.___", state 896, "((i>=1))"
+ line 257, "pan.___", state 902, "(1)"
+ line 257, "pan.___", state 903, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 903, "else"
+ line 261, "pan.___", state 910, "(1)"
+ line 261, "pan.___", state 911, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 911, "else"
+ line 259, "pan.___", state 916, "((i<2))"
+ line 259, "pan.___", state 916, "((i>=2))"
+ line 266, "pan.___", state 920, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 920, "else"
+ line 431, "pan.___", state 922, "(1)"
+ line 431, "pan.___", state 922, "(1)"
+ line 699, "pan.___", state 926, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 963, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 977, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 995, "(1)"
+ line 257, "pan.___", state 1015, "(1)"
+ line 261, "pan.___", state 1023, "(1)"
+ line 411, "pan.___", state 1045, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1077, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1091, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1109, "(1)"
+ line 257, "pan.___", state 1129, "(1)"
+ line 261, "pan.___", state 1137, "(1)"
+ line 411, "pan.___", state 1160, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1192, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1206, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1224, "(1)"
+ line 257, "pan.___", state 1244, "(1)"
+ line 261, "pan.___", state 1252, "(1)"
+ line 411, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1303, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1317, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1335, "(1)"
+ line 257, "pan.___", state 1355, "(1)"
+ line 261, "pan.___", state 1363, "(1)"
+ line 411, "pan.___", state 1387, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1419, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1433, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1451, "(1)"
+ line 257, "pan.___", state 1471, "(1)"
+ line 261, "pan.___", state 1479, "(1)"
+ line 411, "pan.___", state 1498, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1530, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1544, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1562, "(1)"
+ line 257, "pan.___", state 1582, "(1)"
+ line 261, "pan.___", state 1590, "(1)"
+ line 411, "pan.___", state 1612, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1644, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1658, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1676, "(1)"
+ line 257, "pan.___", state 1696, "(1)"
+ line 261, "pan.___", state 1704, "(1)"
+ line 738, "pan.___", state 1723, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1730, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1762, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1776, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1794, "(1)"
+ line 257, "pan.___", state 1814, "(1)"
+ line 261, "pan.___", state 1822, "(1)"
+ line 411, "pan.___", state 1841, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1873, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1887, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1905, "(1)"
+ line 257, "pan.___", state 1925, "(1)"
+ line 261, "pan.___", state 1933, "(1)"
+ line 411, "pan.___", state 1954, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 1956, "(1)"
+ line 411, "pan.___", state 1957, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 1957, "else"
+ line 411, "pan.___", state 1960, "(1)"
+ line 415, "pan.___", state 1968, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1970, "(1)"
+ line 415, "pan.___", state 1971, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 1971, "else"
+ line 415, "pan.___", state 1974, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 415, "pan.___", state 1975, "(1)"
+ line 413, "pan.___", state 1980, "((i<1))"
+ line 413, "pan.___", state 1980, "((i>=1))"
+ line 420, "pan.___", state 1986, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1988, "(1)"
+ line 420, "pan.___", state 1989, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 1989, "else"
+ line 420, "pan.___", state 1992, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 420, "pan.___", state 1993, "(1)"
+ line 424, "pan.___", state 2000, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2002, "(1)"
+ line 424, "pan.___", state 2003, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2003, "else"
+ line 424, "pan.___", state 2006, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 424, "pan.___", state 2007, "(1)"
+ line 422, "pan.___", state 2012, "((i<2))"
+ line 422, "pan.___", state 2012, "((i>=2))"
+ line 249, "pan.___", state 2018, "(1)"
+ line 253, "pan.___", state 2026, "(1)"
+ line 253, "pan.___", state 2027, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2027, "else"
+ line 251, "pan.___", state 2032, "((i<1))"
+ line 251, "pan.___", state 2032, "((i>=1))"
+ line 257, "pan.___", state 2038, "(1)"
+ line 257, "pan.___", state 2039, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2039, "else"
+ line 261, "pan.___", state 2046, "(1)"
+ line 261, "pan.___", state 2047, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2047, "else"
+ line 259, "pan.___", state 2052, "((i<2))"
+ line 259, "pan.___", state 2052, "((i>=2))"
+ line 266, "pan.___", state 2056, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2056, "else"
+ line 431, "pan.___", state 2058, "(1)"
+ line 431, "pan.___", state 2058, "(1)"
+ line 738, "pan.___", state 2061, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 738, "pan.___", state 2062, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 738, "pan.___", state 2063, "(1)"
+ line 411, "pan.___", state 2070, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2102, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2116, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2134, "(1)"
+ line 257, "pan.___", state 2154, "(1)"
+ line 261, "pan.___", state 2162, "(1)"
+ line 411, "pan.___", state 2187, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2219, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2233, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2251, "(1)"
+ line 257, "pan.___", state 2271, "(1)"
+ line 261, "pan.___", state 2279, "(1)"
+ line 411, "pan.___", state 2298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2330, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2344, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2362, "(1)"
+ line 257, "pan.___", state 2382, "(1)"
+ line 261, "pan.___", state 2390, "(1)"
+ line 249, "pan.___", state 2421, "(1)"
+ line 257, "pan.___", state 2441, "(1)"
+ line 261, "pan.___", state 2449, "(1)"
+ line 249, "pan.___", state 2464, "(1)"
+ line 257, "pan.___", state 2484, "(1)"
+ line 261, "pan.___", state 2492, "(1)"
+ line 898, "pan.___", state 2509, "-end-"
+ (221 of 2509 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 22, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 36, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 54, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 86, "(1)"
+ line 253, "pan.___", state 94, "(1)"
+ line 257, "pan.___", state 106, "(1)"
+ line 272, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 144, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 157, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 211, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 229, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 243, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 261, "(1)"
+ line 253, "pan.___", state 269, "(1)"
+ line 257, "pan.___", state 281, "(1)"
+ line 261, "pan.___", state 289, "(1)"
+ line 415, "pan.___", state 324, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 342, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 356, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 382, "(1)"
+ line 257, "pan.___", state 394, "(1)"
+ line 261, "pan.___", state 402, "(1)"
+ line 411, "pan.___", state 430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 444, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 462, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 476, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 494, "(1)"
+ line 253, "pan.___", state 502, "(1)"
+ line 257, "pan.___", state 514, "(1)"
+ line 261, "pan.___", state 522, "(1)"
+ line 411, "pan.___", state 541, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 543, "(1)"
+ line 411, "pan.___", state 544, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 544, "else"
+ line 411, "pan.___", state 547, "(1)"
+ line 415, "pan.___", state 555, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 557, "(1)"
+ line 415, "pan.___", state 558, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 558, "else"
+ line 415, "pan.___", state 561, "(1)"
+ line 415, "pan.___", state 562, "(1)"
+ line 415, "pan.___", state 562, "(1)"
+ line 413, "pan.___", state 567, "((i<1))"
+ line 413, "pan.___", state 567, "((i>=1))"
+ line 420, "pan.___", state 573, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 575, "(1)"
+ line 420, "pan.___", state 576, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 576, "else"
+ line 420, "pan.___", state 579, "(1)"
+ line 420, "pan.___", state 580, "(1)"
+ line 420, "pan.___", state 580, "(1)"
+ line 424, "pan.___", state 587, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 589, "(1)"
+ line 424, "pan.___", state 590, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 590, "else"
+ line 424, "pan.___", state 593, "(1)"
+ line 424, "pan.___", state 594, "(1)"
+ line 424, "pan.___", state 594, "(1)"
+ line 422, "pan.___", state 599, "((i<2))"
+ line 422, "pan.___", state 599, "((i>=2))"
+ line 249, "pan.___", state 605, "(1)"
+ line 253, "pan.___", state 613, "(1)"
+ line 253, "pan.___", state 614, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 614, "else"
+ line 251, "pan.___", state 619, "((i<1))"
+ line 251, "pan.___", state 619, "((i>=1))"
+ line 257, "pan.___", state 625, "(1)"
+ line 257, "pan.___", state 626, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 626, "else"
+ line 261, "pan.___", state 633, "(1)"
+ line 261, "pan.___", state 634, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 634, "else"
+ line 259, "pan.___", state 639, "((i<2))"
+ line 259, "pan.___", state 639, "((i>=2))"
+ line 266, "pan.___", state 643, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 643, "else"
+ line 431, "pan.___", state 645, "(1)"
+ line 431, "pan.___", state 645, "(1)"
+ line 1117, "pan.___", state 649, "_proc_urcu_writer = (_proc_urcu_writer|(1<<10))"
+ line 411, "pan.___", state 654, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 656, "(1)"
+ line 411, "pan.___", state 657, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 657, "else"
+ line 411, "pan.___", state 660, "(1)"
+ line 415, "pan.___", state 668, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 670, "(1)"
+ line 415, "pan.___", state 671, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 671, "else"
+ line 415, "pan.___", state 674, "(1)"
+ line 415, "pan.___", state 675, "(1)"
+ line 415, "pan.___", state 675, "(1)"
+ line 413, "pan.___", state 680, "((i<1))"
+ line 413, "pan.___", state 680, "((i>=1))"
+ line 420, "pan.___", state 686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 688, "(1)"
+ line 420, "pan.___", state 689, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 689, "else"
+ line 420, "pan.___", state 692, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 424, "pan.___", state 700, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 702, "(1)"
+ line 424, "pan.___", state 703, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 703, "else"
+ line 424, "pan.___", state 706, "(1)"
+ line 424, "pan.___", state 707, "(1)"
+ line 424, "pan.___", state 707, "(1)"
+ line 422, "pan.___", state 712, "((i<2))"
+ line 422, "pan.___", state 712, "((i>=2))"
+ line 249, "pan.___", state 718, "(1)"
+ line 253, "pan.___", state 726, "(1)"
+ line 253, "pan.___", state 727, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 727, "else"
+ line 251, "pan.___", state 732, "((i<1))"
+ line 251, "pan.___", state 732, "((i>=1))"
+ line 257, "pan.___", state 738, "(1)"
+ line 257, "pan.___", state 739, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 739, "else"
+ line 261, "pan.___", state 746, "(1)"
+ line 261, "pan.___", state 747, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 747, "else"
+ line 259, "pan.___", state 752, "((i<2))"
+ line 259, "pan.___", state 752, "((i>=2))"
+ line 266, "pan.___", state 756, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 756, "else"
+ line 431, "pan.___", state 758, "(1)"
+ line 431, "pan.___", state 758, "(1)"
+ line 1133, "pan.___", state 763, "_proc_urcu_writer = (_proc_urcu_writer|(1<<11))"
+ line 1128, "pan.___", state 764, "(((tmp2&((1<<7)-1))&&((tmp2^0)&(1<<7))))"
+ line 1128, "pan.___", state 764, "else"
+ line 1153, "pan.___", state 768, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<12)|(1<<11))))"
+ line 272, "pan.___", state 799, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 823, "(1)"
+ line 284, "pan.___", state 830, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 846, "(1)"
+ line 253, "pan.___", state 854, "(1)"
+ line 257, "pan.___", state 866, "(1)"
+ line 261, "pan.___", state 874, "(1)"
+ line 272, "pan.___", state 905, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 914, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 927, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 936, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 952, "(1)"
+ line 253, "pan.___", state 960, "(1)"
+ line 257, "pan.___", state 972, "(1)"
+ line 261, "pan.___", state 980, "(1)"
+ line 276, "pan.___", state 1006, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1019, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1028, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1044, "(1)"
+ line 253, "pan.___", state 1052, "(1)"
+ line 257, "pan.___", state 1064, "(1)"
+ line 261, "pan.___", state 1072, "(1)"
+ line 272, "pan.___", state 1103, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1112, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1125, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1134, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1150, "(1)"
+ line 253, "pan.___", state 1158, "(1)"
+ line 257, "pan.___", state 1170, "(1)"
+ line 261, "pan.___", state 1178, "(1)"
+ line 272, "pan.___", state 1195, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1197, "(1)"
+ line 276, "pan.___", state 1204, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1206, "(1)"
+ line 276, "pan.___", state 1207, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1207, "else"
+ line 274, "pan.___", state 1212, "((i<1))"
+ line 274, "pan.___", state 1212, "((i>=1))"
+ line 280, "pan.___", state 1217, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1219, "(1)"
+ line 280, "pan.___", state 1220, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1220, "else"
+ line 284, "pan.___", state 1226, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1228, "(1)"
+ line 284, "pan.___", state 1229, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1229, "else"
+ line 282, "pan.___", state 1234, "((i<2))"
+ line 282, "pan.___", state 1234, "((i>=2))"
+ line 249, "pan.___", state 1242, "(1)"
+ line 253, "pan.___", state 1250, "(1)"
+ line 253, "pan.___", state 1251, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1251, "else"
+ line 251, "pan.___", state 1256, "((i<1))"
+ line 251, "pan.___", state 1256, "((i>=1))"
+ line 257, "pan.___", state 1262, "(1)"
+ line 257, "pan.___", state 1263, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1263, "else"
+ line 261, "pan.___", state 1270, "(1)"
+ line 261, "pan.___", state 1271, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1271, "else"
+ line 266, "pan.___", state 1280, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1280, "else"
+ line 1229, "pan.___", state 1283, "i = 0"
+ line 1229, "pan.___", state 1285, "reader_barrier = 1"
+ line 1229, "pan.___", state 1296, "((i<1))"
+ line 1229, "pan.___", state 1296, "((i>=1))"
+ line 272, "pan.___", state 1301, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1303, "(1)"
+ line 276, "pan.___", state 1310, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1312, "(1)"
+ line 276, "pan.___", state 1313, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1313, "else"
+ line 274, "pan.___", state 1318, "((i<1))"
+ line 274, "pan.___", state 1318, "((i>=1))"
+ line 280, "pan.___", state 1323, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1325, "(1)"
+ line 280, "pan.___", state 1326, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1326, "else"
+ line 284, "pan.___", state 1332, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1334, "(1)"
+ line 284, "pan.___", state 1335, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1335, "else"
+ line 282, "pan.___", state 1340, "((i<2))"
+ line 282, "pan.___", state 1340, "((i>=2))"
+ line 249, "pan.___", state 1348, "(1)"
+ line 253, "pan.___", state 1356, "(1)"
+ line 253, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1357, "else"
+ line 251, "pan.___", state 1362, "((i<1))"
+ line 251, "pan.___", state 1362, "((i>=1))"
+ line 257, "pan.___", state 1368, "(1)"
+ line 257, "pan.___", state 1369, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1369, "else"
+ line 261, "pan.___", state 1376, "(1)"
+ line 261, "pan.___", state 1377, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1377, "else"
+ line 266, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1386, "else"
+ line 299, "pan.___", state 1388, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1388, "else"
+ line 1229, "pan.___", state 1389, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 1229, "pan.___", state 1389, "else"
+ line 276, "pan.___", state 1402, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1415, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1424, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1440, "(1)"
+ line 253, "pan.___", state 1448, "(1)"
+ line 257, "pan.___", state 1460, "(1)"
+ line 261, "pan.___", state 1468, "(1)"
+ line 272, "pan.___", state 1499, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1508, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1521, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1530, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1546, "(1)"
+ line 253, "pan.___", state 1554, "(1)"
+ line 257, "pan.___", state 1566, "(1)"
+ line 261, "pan.___", state 1574, "(1)"
+ line 1237, "pan.___", state 1590, "-end-"
+ (195 of 1590 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 982 seconds
+pan: rate 38391.44 states/second
+pan: avg transition delay 2.6765e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
--- /dev/null
+#define SINGLE_FLIP
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+-2:3:-2
+-4:-4:-4
+1:0:4179
+2:3:4099
+3:3:4102
+4:3:4102
+5:3:4105
+6:3:4113
+7:3:4113
+8:3:4116
+9:3:4122
+10:3:4126
+11:3:4126
+12:3:4129
+13:3:4139
+14:3:4147
+15:3:4147
+16:3:4150
+17:3:4156
+18:3:4160
+19:3:4160
+20:3:4163
+21:3:4169
+22:3:4173
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--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+depth 23: Claim reached state 9 (line 1300)
+depth 51: Claim reached state 9 (line 1299)
+Depth= 7071 States= 1e+06 Transitions= 1.16e+07 Memory= 514.397 t= 30.7 R= 3e+04
+Depth= 7071 States= 2e+06 Transitions= 2.31e+07 Memory= 566.252 t= 61.5 R= 3e+04
+Depth= 7071 States= 3e+06 Transitions= 3.43e+07 Memory= 617.326 t= 91.6 R= 3e+04
+pan: resizing hashtable to -w22.. done
+Depth= 8815 States= 4e+06 Transitions= 4.57e+07 Memory= 696.592 t= 122 R= 3e+04
+Depth= 8815 States= 5e+06 Transitions= 5.73e+07 Memory= 743.955 t= 153 R= 3e+04
+Depth= 8815 States= 6e+06 Transitions= 7.04e+07 Memory= 797.373 t= 190 R= 3e+04
+Depth= 8815 States= 7e+06 Transitions= 8.38e+07 Memory= 847.861 t= 226 R= 3e+04
+Depth= 8815 States= 8e+06 Transitions= 9.59e+07 Memory= 898.057 t= 259 R= 3e+04
+Depth= 8815 States= 9e+06 Transitions= 1.08e+08 Memory= 948.350 t= 293 R= 3e+04
+pan: resizing hashtable to -w24.. done
+Depth= 8815 States= 1e+07 Transitions= 1.29e+08 Memory= 1123.615 t= 352 R= 3e+04
+Depth= 8815 States= 1.1e+07 Transitions= 1.41e+08 Memory= 1175.764 t= 385 R= 3e+04
+Depth= 8815 States= 1.2e+07 Transitions= 1.53e+08 Memory= 1225.471 t= 417 R= 3e+04
+Depth= 8815 States= 1.3e+07 Transitions= 1.64e+08 Memory= 1276.057 t= 447 R= 3e+04
+Depth= 8815 States= 1.4e+07 Transitions= 1.75e+08 Memory= 1330.451 t= 477 R= 3e+04
+Depth= 8815 States= 1.5e+07 Transitions= 1.87e+08 Memory= 1379.670 t= 508 R= 3e+04
+Depth= 8815 States= 1.6e+07 Transitions= 1.98e+08 Memory= 1429.865 t= 538 R= 3e+04
+Depth= 8815 States= 1.7e+07 Transitions= 2.09e+08 Memory= 1484.748 t= 568 R= 3e+04
+Depth= 8815 States= 1.8e+07 Transitions= 2.23e+08 Memory= 1529.670 t= 606 R= 3e+04
+Depth= 8815 States= 1.9e+07 Transitions= 2.36e+08 Memory= 1579.377 t= 643 R= 3e+04
+Depth= 8815 States= 2e+07 Transitions= 2.57e+08 Memory= 1629.279 t= 701 R= 3e+04
+Depth= 8815 States= 2.1e+07 Transitions= 2.93e+08 Memory= 1686.115 t= 807 R= 3e+04
+Depth= 9016 States= 2.2e+07 Transitions= 3.11e+08 Memory= 1741.193 t= 858 R= 3e+04
+Depth= 9016 States= 2.3e+07 Transitions= 3.25e+08 Memory= 1793.733 t= 897 R= 3e+04
+Depth= 9016 States= 2.4e+07 Transitions= 3.45e+08 Memory= 1846.272 t= 954 R= 3e+04
+Depth= 9016 States= 2.5e+07 Transitions= 3.67e+08 Memory= 1897.639 t= 1.02e+03 R= 2e+04
+Depth= 9016 States= 2.6e+07 Transitions= 3.84e+08 Memory= 1951.447 t= 1.06e+03 R= 2e+04
+Depth= 9016 States= 2.7e+07 Transitions= 4.07e+08 Memory= 2004.670 t= 1.13e+03 R= 2e+04
+Depth= 9016 States= 2.8e+07 Transitions= 4.29e+08 Memory= 2050.764 t= 1.19e+03 R= 2e+04
+Depth= 9016 States= 2.9e+07 Transitions= 4.48e+08 Memory= 2100.373 t= 1.25e+03 R= 2e+04
+Depth= 9016 States= 3e+07 Transitions= 4.66e+08 Memory= 2151.545 t= 1.3e+03 R= 2e+04
+Depth= 9016 States= 3.1e+07 Transitions= 4.86e+08 Memory= 2201.838 t= 1.36e+03 R= 2e+04
+Depth= 9016 States= 3.2e+07 Transitions= 5.1e+08 Memory= 2250.861 t= 1.43e+03 R= 2e+04
+Depth= 9016 States= 3.3e+07 Transitions= 5.29e+08 Memory= 2299.983 t= 1.48e+03 R= 2e+04
+Depth= 9016 States= 3.4e+07 Transitions= 5.47e+08 Memory= 2351.057 t= 1.53e+03 R= 2e+04
+pan: resizing hashtable to -w26.. done
+Depth= 9016 States= 3.5e+07 Transitions= 5.69e+08 Memory= 2896.943 t= 1.6e+03 R= 2e+04
+Depth= 9016 States= 3.6e+07 Transitions= 5.95e+08 Memory= 2945.186 t= 1.67e+03 R= 2e+04
+Depth= 9016 States= 3.7e+07 Transitions= 6.12e+08 Memory= 2995.576 t= 1.72e+03 R= 2e+04
+Depth= 9016 States= 3.8e+07 Transitions= 6.29e+08 Memory= 3042.256 t= 1.77e+03 R= 2e+04
+Depth= 9016 States= 3.9e+07 Transitions= 6.42e+08 Memory= 3093.135 t= 1.8e+03 R= 2e+04
+Depth= 9016 States= 4e+07 Transitions= 6.56e+08 Memory= 3146.651 t= 1.84e+03 R= 2e+04
+Depth= 9016 States= 4.1e+07 Transitions= 6.69e+08 Memory= 3202.901 t= 1.88e+03 R= 2e+04
+Depth= 9016 States= 4.2e+07 Transitions= 6.82e+08 Memory= 3254.951 t= 1.91e+03 R= 2e+04
+Depth= 9016 States= 4.3e+07 Transitions= 6.95e+08 Memory= 3309.053 t= 1.95e+03 R= 2e+04
+Depth= 9016 States= 4.4e+07 Transitions= 7.07e+08 Memory= 3360.615 t= 1.98e+03 R= 2e+04
+Depth= 9016 States= 4.5e+07 Transitions= 7.28e+08 Memory= 3410.713 t= 2.04e+03 R= 2e+04
+Depth= 9016 States= 4.6e+07 Transitions= 7.63e+08 Memory= 3466.963 t= 2.14e+03 R= 2e+04
+Depth= 9016 States= 4.7e+07 Transitions= 7.99e+08 Memory= 3532.295 t= 2.25e+03 R= 2e+04
+Depth= 9016 States= 4.8e+07 Transitions= 8.49e+08 Memory= 3594.307 t= 2.4e+03 R= 2e+04
+Depth= 9016 States= 4.9e+07 Transitions= 8.91e+08 Memory= 3646.455 t= 2.52e+03 R= 2e+04
+Depth= 9016 States= 5e+07 Transitions= 9.24e+08 Memory= 3689.912 t= 2.62e+03 R= 2e+04
+Depth= 9016 States= 5.1e+07 Transitions= 9.39e+08 Memory= 3742.940 t= 2.66e+03 R= 2e+04
+Depth= 9016 States= 5.2e+07 Transitions= 9.6e+08 Memory= 3793.721 t= 2.72e+03 R= 2e+04
+Depth= 9016 States= 5.3e+07 Transitions= 9.99e+08 Memory= 3843.721 t= 2.84e+03 R= 2e+04
+Depth= 9016 States= 5.4e+07 Transitions= 1.01e+09 Memory= 3899.287 t= 2.88e+03 R= 2e+04
+Depth= 9016 States= 5.5e+07 Transitions= 1.03e+09 Memory= 3947.627 t= 2.93e+03 R= 2e+04
+Depth= 9016 States= 5.6e+07 Transitions= 1.05e+09 Memory= 3995.479 t= 2.97e+03 R= 2e+04
+Depth= 9016 States= 5.7e+07 Transitions= 1.06e+09 Memory= 4049.776 t= 3.01e+03 R= 2e+04
+Depth= 9016 States= 5.8e+07 Transitions= 1.09e+09 Memory= 4100.947 t= 3.09e+03 R= 2e+04
+Depth= 9016 States= 5.9e+07 Transitions= 1.1e+09 Memory= 4151.533 t= 3.13e+03 R= 2e+04
+Depth= 9016 States= 6e+07 Transitions= 1.13e+09 Memory= 4201.924 t= 3.22e+03 R= 2e+04
+Depth= 9016 States= 6.1e+07 Transitions= 1.15e+09 Memory= 4251.240 t= 3.28e+03 R= 2e+04
+Depth= 9016 States= 6.2e+07 Transitions= 1.19e+09 Memory= 4303.779 t= 3.38e+03 R= 2e+04
+Depth= 9016 States= 6.3e+07 Transitions= 1.21e+09 Memory= 4352.998 t= 3.43e+03 R= 2e+04
+Depth= 9016 States= 6.4e+07 Transitions= 1.24e+09 Memory= 4403.096 t= 3.53e+03 R= 2e+04
+Depth= 9016 States= 6.5e+07 Transitions= 1.26e+09 Memory= 4453.682 t= 3.59e+03 R= 2e+04
+Depth= 9016 States= 6.6e+07 Transitions= 1.28e+09 Memory= 4503.096 t= 3.66e+03 R= 2e+04
+Depth= 9016 States= 6.7e+07 Transitions= 1.3e+09 Memory= 4554.072 t= 3.71e+03 R= 2e+04
+Depth= 9016 States= 6.8e+07 Transitions= 1.33e+09 Memory= 4604.951 t= 3.79e+03 R= 2e+04
+Depth= 9016 States= 6.9e+07 Transitions= 1.36e+09 Memory= 4656.221 t= 3.87e+03 R= 2e+04
+Depth= 9523 States= 7e+07 Transitions= 1.38e+09 Memory= 4712.959 t= 3.93e+03 R= 2e+04
+Depth= 9523 States= 7.1e+07 Transitions= 1.39e+09 Memory= 4759.443 t= 3.97e+03 R= 2e+04
+Depth= 9523 States= 7.2e+07 Transitions= 1.41e+09 Memory= 4814.033 t= 4.03e+03 R= 2e+04
+Depth= 9554 States= 7.3e+07 Transitions= 1.44e+09 Memory= 4868.037 t= 4.09e+03 R= 2e+04
+Depth= 9554 States= 7.4e+07 Transitions= 1.45e+09 Memory= 4915.401 t= 4.13e+03 R= 2e+04
+Depth= 9554 States= 7.5e+07 Transitions= 1.47e+09 Memory= 4970.479 t= 4.2e+03 R= 2e+04
+Depth= 9554 States= 7.6e+07 Transitions= 1.49e+09 Memory= 5022.334 t= 4.26e+03 R= 2e+04
+Depth= 9554 States= 7.7e+07 Transitions= 1.51e+09 Memory= 5071.358 t= 4.3e+03 R= 2e+04
+Depth= 9554 States= 7.8e+07 Transitions= 1.52e+09 Memory= 5124.971 t= 4.33e+03 R= 2e+04
+Depth= 9554 States= 7.9e+07 Transitions= 1.54e+09 Memory= 5178.779 t= 4.4e+03 R= 2e+04
+Depth= 9554 States= 8e+07 Transitions= 1.56e+09 Memory= 5231.221 t= 4.46e+03 R= 2e+04
+Depth= 9554 States= 8.1e+07 Transitions= 1.58e+09 Memory= 5284.541 t= 4.51e+03 R= 2e+04
+Depth= 9554 States= 8.2e+07 Transitions= 1.6e+09 Memory= 5335.029 t= 4.55e+03 R= 2e+04
+Depth= 9554 States= 8.3e+07 Transitions= 1.61e+09 Memory= 5385.908 t= 4.6e+03 R= 2e+04
+Depth= 9554 States= 8.4e+07 Transitions= 1.63e+09 Memory= 5437.276 t= 4.64e+03 R= 2e+04
+Depth= 9554 States= 8.5e+07 Transitions= 1.65e+09 Memory= 5486.787 t= 4.69e+03 R= 2e+04
+Depth= 9554 States= 8.6e+07 Transitions= 1.67e+09 Memory= 5535.615 t= 4.76e+03 R= 2e+04
+Depth= 9554 States= 8.7e+07 Transitions= 1.69e+09 Memory= 5589.522 t= 4.81e+03 R= 2e+04
+Depth= 9554 States= 8.8e+07 Transitions= 1.7e+09 Memory= 5647.627 t= 4.86e+03 R= 2e+04
+Depth= 9554 States= 8.9e+07 Transitions= 1.72e+09 Memory= 5695.967 t= 4.9e+03 R= 2e+04
+Depth= 9554 States= 9e+07 Transitions= 1.74e+09 Memory= 5749.971 t= 4.95e+03 R= 2e+04
+Depth= 9554 States= 9.1e+07 Transitions= 1.76e+09 Memory= 5799.483 t= 5.01e+03 R= 2e+04
+Depth= 9554 States= 9.2e+07 Transitions= 1.78e+09 Memory= 5849.092 t= 5.06e+03 R= 2e+04
+Depth= 9554 States= 9.3e+07 Transitions= 1.8e+09 Memory= 5897.529 t= 5.12e+03 R= 2e+04
+Depth= 9554 States= 9.4e+07 Transitions= 1.82e+09 Memory= 5949.287 t= 5.19e+03 R= 2e+04
+Depth= 9554 States= 9.5e+07 Transitions= 1.84e+09 Memory= 6004.072 t= 5.25e+03 R= 2e+04
+Depth= 9554 States= 9.6e+07 Transitions= 1.86e+09 Memory= 6052.412 t= 5.29e+03 R= 2e+04
+Depth= 9554 States= 9.7e+07 Transitions= 1.88e+09 Memory= 6107.588 t= 5.36e+03 R= 2e+04
+Depth= 9554 States= 9.8e+07 Transitions= 1.9e+09 Memory= 6160.029 t= 5.4e+03 R= 2e+04
+Depth= 9554 States= 9.9e+07 Transitions= 1.91e+09 Memory= 6211.006 t= 5.44e+03 R= 2e+04
+Depth= 9554 States= 1e+08 Transitions= 1.93e+09 Memory= 6262.861 t= 5.49e+03 R= 2e+04
+Depth= 9554 States= 1.01e+08 Transitions= 1.94e+09 Memory= 6317.256 t= 5.54e+03 R= 2e+04
+Depth= 9554 States= 1.02e+08 Transitions= 1.96e+09 Memory= 6371.455 t= 5.58e+03 R= 2e+04
+Depth= 9554 States= 1.03e+08 Transitions= 1.98e+09 Memory= 6423.311 t= 5.64e+03 R= 2e+04
+Depth= 9554 States= 1.04e+08 Transitions= 2e+09 Memory= 6477.608 t= 5.71e+03 R= 2e+04
+Depth= 9554 States= 1.05e+08 Transitions= 2.02e+09 Memory= 6526.045 t= 5.75e+03 R= 2e+04
+Depth= 9554 States= 1.06e+08 Transitions= 2.04e+09 Memory= 6580.733 t= 5.81e+03 R= 2e+04
+Depth= 9554 States= 1.07e+08 Transitions= 2.06e+09 Memory= 6634.053 t= 5.87e+03 R= 2e+04
+Depth= 9554 States= 1.08e+08 Transitions= 2.07e+09 Memory= 6685.127 t= 5.9e+03 R= 2e+04
+Depth= 9554 States= 1.09e+08 Transitions= 2.09e+09 Memory= 6736.299 t= 5.96e+03 R= 2e+04
+Depth= 9554 States= 1.1e+08 Transitions= 2.11e+09 Memory= 6790.401 t= 6e+03 R= 2e+04
+Depth= 9554 States= 1.11e+08 Transitions= 2.12e+09 Memory= 6844.990 t= 6.05e+03 R= 2e+04
+Depth= 9554 States= 1.12e+08 Transitions= 2.14e+09 Memory= 6890.010 t= 6.09e+03 R= 2e+04
+Depth= 9554 States= 1.13e+08 Transitions= 2.16e+09 Memory= 6940.889 t= 6.14e+03 R= 2e+04
+Depth= 9554 States= 1.14e+08 Transitions= 2.17e+09 Memory= 6992.061 t= 6.19e+03 R= 2e+04
+Depth= 9554 States= 1.15e+08 Transitions= 2.19e+09 Memory= 7043.623 t= 6.24e+03 R= 2e+04
+Depth= 9554 States= 1.16e+08 Transitions= 2.21e+09 Memory= 7095.186 t= 6.28e+03 R= 2e+04
+Depth= 9554 States= 1.17e+08 Transitions= 2.23e+09 Memory= 7144.600 t= 6.36e+03 R= 2e+04
+Depth= 9554 States= 1.18e+08 Transitions= 2.27e+09 Memory= 7198.897 t= 6.46e+03 R= 2e+04
+Depth= 9554 States= 1.19e+08 Transitions= 2.29e+09 Memory= 7253.779 t= 6.52e+03 R= 2e+04
+Depth= 9554 States= 1.2e+08 Transitions= 2.3e+09 Memory= 7307.783 t= 6.56e+03 R= 2e+04
+Depth= 9554 States= 1.21e+08 Transitions= 2.32e+09 Memory= 7358.467 t= 6.62e+03 R= 2e+04
+Depth= 9554 States= 1.22e+08 Transitions= 2.34e+09 Memory= 7410.811 t= 6.67e+03 R= 2e+04
+Depth= 9554 States= 1.23e+08 Transitions= 2.36e+09 Memory= 7465.010 t= 6.72e+03 R= 2e+04
+Depth= 9554 States= 1.24e+08 Transitions= 2.38e+09 Memory= 7516.670 t= 6.78e+03 R= 2e+04
+Depth= 9554 States= 1.25e+08 Transitions= 2.41e+09 Memory= 7565.205 t= 6.87e+03 R= 2e+04
+Depth= 9554 States= 1.26e+08 Transitions= 2.43e+09 Memory= 7613.936 t= 6.93e+03 R= 2e+04
+Depth= 9554 States= 1.27e+08 Transitions= 2.45e+09 Memory= 7662.471 t= 7e+03 R= 2e+04
+Depth= 9554 States= 1.28e+08 Transitions= 2.48e+09 Memory= 7710.713 t= 7.08e+03 R= 2e+04
+Depth= 9554 States= 1.29e+08 Transitions= 2.5e+09 Memory= 7759.346 t= 7.14e+03 R= 2e+04
+Depth= 9554 States= 1.3e+08 Transitions= 2.52e+09 Memory= 7810.322 t= 7.2e+03 R= 2e+04
+Depth= 9554 States= 1.31e+08 Transitions= 2.55e+09 Memory= 7859.834 t= 7.26e+03 R= 2e+04
+Depth= 9554 States= 1.32e+08 Transitions= 2.57e+09 Memory= 7910.615 t= 7.33e+03 R= 2e+04
+Depth= 9554 States= 1.33e+08 Transitions= 2.59e+09 Memory= 7959.248 t= 7.4e+03 R= 2e+04
+Depth= 9554 States= 1.34e+08 Transitions= 2.61e+09 Memory= 8011.787 t= 7.46e+03 R= 2e+04
+Depth= 9554 States= 1.35e+08 Transitions= 2.63e+09 Memory= 8060.713 t= 7.51e+03 R= 2e+04
+pan: resizing hashtable to -w28.. done
+Depth= 9554 States= 1.36e+08 Transitions= 2.65e+09 Memory= 10108.713 t= 7.58e+03 R= 2e+04
+Depth= 9554 States= 1.37e+08 Transitions= 2.66e+09 Memory= 10144.455 t= 7.62e+03 R= 2e+04
+Depth= 9554 States= 1.38e+08 Transitions= 2.67e+09 Memory= 10199.143 t= 7.65e+03 R= 2e+04
+Depth= 9554 States= 1.39e+08 Transitions= 2.69e+09 Memory= 10253.830 t= 7.69e+03 R= 2e+04
+Depth= 9554 States= 1.4e+08 Transitions= 2.7e+09 Memory= 10308.127 t= 7.74e+03 R= 2e+04
+Depth= 9554 States= 1.41e+08 Transitions= 2.72e+09 Memory= 10360.178 t= 7.78e+03 R= 2e+04
+Depth= 9554 States= 1.42e+08 Transitions= 2.74e+09 Memory= 10413.889 t= 7.83e+03 R= 2e+04
+Depth= 9554 States= 1.43e+08 Transitions= 2.75e+09 Memory= 10467.111 t= 7.87e+03 R= 2e+04
+Depth= 9554 States= 1.44e+08 Transitions= 2.77e+09 Memory= 10518.088 t= 7.92e+03 R= 2e+04
+Depth= 9554 States= 1.45e+08 Transitions= 2.79e+09 Memory= 10567.795 t= 7.98e+03 R= 2e+04
+Depth= 9554 States= 1.46e+08 Transitions= 2.82e+09 Memory= 10624.631 t= 8.08e+03 R= 2e+04
+Depth= 9554 States= 1.47e+08 Transitions= 2.86e+09 Memory= 10689.963 t= 8.19e+03 R= 2e+04
+Depth= 9554 States= 1.48e+08 Transitions= 2.91e+09 Memory= 10752.072 t= 8.34e+03 R= 2e+04
+Depth= 9554 States= 1.49e+08 Transitions= 2.95e+09 Memory= 10802.658 t= 8.46e+03 R= 2e+04
+Depth= 9554 States= 1.5e+08 Transitions= 2.99e+09 Memory= 10848.361 t= 8.56e+03 R= 2e+04
+Depth= 9554 States= 1.51e+08 Transitions= 3e+09 Memory= 10900.022 t= 8.61e+03 R= 2e+04
+Depth= 9554 States= 1.52e+08 Transitions= 3.02e+09 Memory= 10951.096 t= 8.66e+03 R= 2e+04
+Depth= 9554 States= 1.53e+08 Transitions= 3.05e+09 Memory= 11002.365 t= 8.75e+03 R= 2e+04
+Depth= 9554 States= 1.54e+08 Transitions= 3.08e+09 Memory= 11054.611 t= 8.83e+03 R= 2e+04
+Depth= 9554 States= 1.55e+08 Transitions= 3.1e+09 Memory= 11105.783 t= 8.88e+03 R= 2e+04
+Depth= 9554 States= 1.56e+08 Transitions= 3.11e+09 Memory= 11153.830 t= 8.92e+03 R= 2e+04
+Depth= 9554 States= 1.57e+08 Transitions= 3.13e+09 Memory= 11202.365 t= 8.96e+03 R= 2e+04
+Depth= 9554 States= 1.58e+08 Transitions= 3.14e+09 Memory= 11257.443 t= 9e+03 R= 2e+04
+Depth= 9554 States= 1.59e+08 Transitions= 3.17e+09 Memory= 11307.639 t= 9.08e+03 R= 2e+04
+Depth= 9554 States= 1.6e+08 Transitions= 3.19e+09 Memory= 11357.541 t= 9.15e+03 R= 2e+04
+Depth= 9554 States= 1.61e+08 Transitions= 3.21e+09 Memory= 11407.541 t= 9.21e+03 R= 2e+04
+Depth= 9554 States= 1.62e+08 Transitions= 3.24e+09 Memory= 11457.736 t= 9.28e+03 R= 2e+04
+Depth= 9554 States= 1.63e+08 Transitions= 3.27e+09 Memory= 11507.053 t= 9.36e+03 R= 2e+04
+Depth= 9554 States= 1.64e+08 Transitions= 3.29e+09 Memory= 11560.959 t= 9.44e+03 R= 2e+04
+Depth= 9554 States= 1.65e+08 Transitions= 3.31e+09 Memory= 11613.108 t= 9.5e+03 R= 2e+04
+Depth= 9554 States= 1.66e+08 Transitions= 3.34e+09 Memory= 11661.252 t= 9.58e+03 R= 2e+04
+Depth= 9554 States= 1.67e+08 Transitions= 3.37e+09 Memory= 11711.154 t= 9.66e+03 R= 2e+04
+Depth= 9554 States= 1.68e+08 Transitions= 3.39e+09 Memory= 11763.596 t= 9.72e+03 R= 2e+04
+Depth= 9554 States= 1.69e+08 Transitions= 3.41e+09 Memory= 11812.912 t= 9.78e+03 R= 2e+04
+Depth= 9554 States= 1.7e+08 Transitions= 3.44e+09 Memory= 11866.135 t= 9.87e+03 R= 2e+04
+Depth= 9554 States= 1.71e+08 Transitions= 3.46e+09 Memory= 11920.139 t= 9.91e+03 R= 2e+04
+Depth= 9554 States= 1.72e+08 Transitions= 3.47e+09 Memory= 11967.014 t= 9.95e+03 R= 2e+04
+Depth= 9554 States= 1.73e+08 Transitions= 3.5e+09 Memory= 12021.115 t= 1e+04 R= 2e+04
+Depth= 9554 States= 1.74e+08 Transitions= 3.52e+09 Memory= 12075.315 t= 1.01e+04 R= 2e+04
+Depth= 9554 States= 1.75e+08 Transitions= 3.53e+09 Memory= 12126.779 t= 1.01e+04 R= 2e+04
+Depth= 9554 States= 1.76e+08 Transitions= 3.56e+09 Memory= 12180.002 t= 1.02e+04 R= 2e+04
+Depth= 9554 States= 1.77e+08 Transitions= 3.57e+09 Memory= 12229.416 t= 1.02e+04 R= 2e+04
+Depth= 9554 States= 1.78e+08 Transitions= 3.59e+09 Memory= 12282.834 t= 1.03e+04 R= 2e+04
+Depth= 9554 States= 1.79e+08 Transitions= 3.61e+09 Memory= 12334.494 t= 1.03e+04 R= 2e+04
+Depth= 9554 States= 1.8e+08 Transitions= 3.63e+09 Memory= 12387.522 t= 1.04e+04 R= 2e+04
+Depth= 9554 States= 1.81e+08 Transitions= 3.65e+09 Memory= 12440.451 t= 1.05e+04 R= 2e+04
+Depth= 9554 States= 1.82e+08 Transitions= 3.66e+09 Memory= 12492.111 t= 1.05e+04 R= 2e+04
+Depth= 9554 States= 1.83e+08 Transitions= 3.68e+09 Memory= 12544.162 t= 1.05e+04 R= 2e+04
+Depth= 9554 States= 1.84e+08 Transitions= 3.69e+09 Memory= 12594.943 t= 1.06e+04 R= 2e+04
+Depth= 9554 States= 1.85e+08 Transitions= 3.71e+09 Memory= 12645.627 t= 1.06e+04 R= 2e+04
+Depth= 9554 States= 1.86e+08 Transitions= 3.73e+09 Memory= 12695.236 t= 1.07e+04 R= 2e+04
+Depth= 9554 States= 1.87e+08 Transitions= 3.75e+09 Memory= 12750.705 t= 1.07e+04 R= 2e+04
+Depth= 9554 States= 1.88e+08 Transitions= 3.77e+09 Memory= 12807.639 t= 1.08e+04 R= 2e+04
+Depth= 9554 States= 1.89e+08 Transitions= 3.78e+09 Memory= 12855.979 t= 1.08e+04 R= 2e+04
+Depth= 9554 States= 1.9e+08 Transitions= 3.8e+09 Memory= 12909.592 t= 1.09e+04 R= 2e+04
+Depth= 9554 States= 1.91e+08 Transitions= 3.82e+09 Memory= 12959.104 t= 1.09e+04 R= 2e+04
+Depth= 9554 States= 1.92e+08 Transitions= 3.84e+09 Memory= 13008.615 t= 1.1e+04 R= 2e+04
+Depth= 9554 States= 1.93e+08 Transitions= 3.86e+09 Memory= 13065.061 t= 1.11e+04 R= 2e+04
+Depth= 9554 States= 1.94e+08 Transitions= 3.88e+09 Memory= 13114.377 t= 1.11e+04 R= 2e+04
+Depth= 9554 States= 1.95e+08 Transitions= 3.9e+09 Memory= 13168.674 t= 1.12e+04 R= 2e+04
+Depth= 9554 States= 1.96e+08 Transitions= 3.92e+09 Memory= 13222.678 t= 1.12e+04 R= 2e+04
+Depth= 9554 States= 1.97e+08 Transitions= 3.93e+09 Memory= 13271.701 t= 1.13e+04 R= 2e+04
+Depth= 9554 States= 1.98e+08 Transitions= 3.95e+09 Memory= 13324.338 t= 1.13e+04 R= 2e+04
+Depth= 9554 States= 1.99e+08 Transitions= 3.96e+09 Memory= 13377.170 t= 1.13e+04 R= 2e+04
+Depth= 9554 States= 2e+08 Transitions= 3.98e+09 Memory= 13432.639 t= 1.14e+04 R= 2e+04
+Depth= 9554 States= 2.01e+08 Transitions= 4e+09 Memory= 13483.811 t= 1.14e+04 R= 2e+04
+Depth= 9554 States= 2.02e+08 Transitions= 4.03e+09 Memory= 13537.522 t= 1.15e+04 R= 2e+04
+Depth= 9554 States= 2.03e+08 Transitions= 4.04e+09 Memory= 13588.693 t= 1.16e+04 R= 2e+04
+Depth= 9554 States= 2.04e+08 Transitions= 4.06e+09 Memory= 13642.600 t= 1.16e+04 R= 2e+04
+Depth= 9554 States= 2.05e+08 Transitions= 4.08e+09 Memory= 13696.799 t= 1.17e+04 R= 2e+04
+Depth= 9554 States= 2.06e+08 Transitions= 4.09e+09 Memory= 13744.748 t= 1.17e+04 R= 2e+04
+Depth= 9554 States= 2.07e+08 Transitions= 4.11e+09 Memory= 13798.068 t= 1.18e+04 R= 2e+04
+Depth= 9554 States= 2.08e+08 Transitions= 4.13e+09 Memory= 13850.022 t= 1.18e+04 R= 2e+04
+Depth= 9554 States= 2.09e+08 Transitions= 4.14e+09 Memory= 13905.783 t= 1.18e+04 R= 2e+04
+Depth= 9554 States= 2.1e+08 Transitions= 4.16e+09 Memory= 13952.365 t= 1.19e+04 R= 2e+04
+Depth= 9554 States= 2.11e+08 Transitions= 4.18e+09 Memory= 14003.244 t= 1.19e+04 R= 2e+04
+Depth= 9554 States= 2.12e+08 Transitions= 4.19e+09 Memory= 14054.318 t= 1.2e+04 R= 2e+04
+Depth= 9554 States= 2.13e+08 Transitions= 4.21e+09 Memory= 14106.076 t= 1.2e+04 R= 2e+04
+Depth= 9554 States= 2.14e+08 Transitions= 4.22e+09 Memory= 14156.662 t= 1.21e+04 R= 2e+04
+Depth= 9554 States= 2.15e+08 Transitions= 4.26e+09 Memory= 14209.690 t= 1.22e+04 R= 2e+04
+Depth= 9554 States= 2.16e+08 Transitions= 4.29e+09 Memory= 14265.256 t= 1.23e+04 R= 2e+04
+Depth= 9554 States= 2.17e+08 Transitions= 4.3e+09 Memory= 14317.697 t= 1.23e+04 R= 2e+04
+Depth= 9554 States= 2.18e+08 Transitions= 4.32e+09 Memory= 14371.311 t= 1.23e+04 R= 2e+04
+Depth= 9554 States= 2.19e+08 Transitions= 4.33e+09 Memory= 14424.045 t= 1.24e+04 R= 2e+04
+Depth= 9554 States= 2.2e+08 Transitions= 4.35e+09 Memory= 14477.854 t= 1.24e+04 R= 2e+04
+Depth= 9554 States= 2.21e+08 Transitions= 4.37e+09 Memory= 14529.611 t= 1.25e+04 R= 2e+04
+Depth= 9554 States= 2.22e+08 Transitions= 4.4e+09 Memory= 14576.291 t= 1.26e+04 R= 2e+04
+Depth= 9554 States= 2.23e+08 Transitions= 4.43e+09 Memory= 14625.608 t= 1.27e+04 R= 2e+04
+Depth= 9554 States= 2.24e+08 Transitions= 4.45e+09 Memory= 14674.045 t= 1.27e+04 R= 2e+04
+Depth= 9554 States= 2.25e+08 Transitions= 4.48e+09 Memory= 14722.776 t= 1.28e+04 R= 2e+04
+Depth= 9554 States= 2.26e+08 Transitions= 4.5e+09 Memory= 14770.529 t= 1.29e+04 R= 2e+04
+Depth= 9554 States= 2.27e+08 Transitions= 4.52e+09 Memory= 14821.018 t= 1.29e+04 R= 2e+04
+Depth= 9554 States= 2.28e+08 Transitions= 4.54e+09 Memory= 14870.529 t= 1.3e+04 R= 2e+04
+Depth= 9554 States= 2.29e+08 Transitions= 4.56e+09 Memory= 14918.967 t= 1.3e+04 R= 2e+04
+Depth= 9554 States= 2.3e+08 Transitions= 4.59e+09 Memory= 14966.916 t= 1.31e+04 R= 2e+04
+Depth= 9554 States= 2.31e+08 Transitions= 4.6e+09 Memory= 15017.600 t= 1.32e+04 R= 2e+04
+Depth= 9554 States= 2.32e+08 Transitions= 4.63e+09 Memory= 15066.330 t= 1.32e+04 R= 2e+04
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
--- /dev/null
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+ make urcu_free | tee urcu_free.log
+ make urcu_free_no_mb | tee urcu_free_no_mb.log
+ make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+ make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+ make urcu_free_single_flip | tee urcu_free_single_flip.log
+ make urcu_progress_writer | tee urcu_progress_writer.log
+ make urcu_progress_reader | tee urcu_progress_reader.log
+ make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+ make asserts | tee asserts.log
+ make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+ @echo
+ @echo "Verification summary"
+ @grep errors: *.log
+
+asserts: clean
+ cat DEFINES > .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X .input.spin
+ gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+ ./pan -v -c1 -X -m10000000 -w20
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+ cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+ cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+ cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+ cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+ cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+ touch .input.define
+ cat .input.define >> pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+ urcu_progress_writer_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+ cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+ urcu_progress_reader_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+ cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+ urcu_progress_writer_error_define run_weak_fair
+ cp .input.spin $@.spin.input
+ -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+ cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+ touch .input.define
+ cat .input.define > pan.ltl
+ cat DEFINES >> pan.ltl
+ spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+ ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+ ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+ gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+ cat .input.define > .input.spin
+ cat DEFINES >> .input.spin
+ cat ${SPINFILE} >> .input.spin
+ rm -f .input.spin.trail
+ spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+ rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+ rm -f *.trail *.input *.log
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth= 4473 States= 1e+06 Transitions= 2.37e+07 Memory= 542.619 t= 57.3 R= 2e+04
+Depth= 4540 States= 2e+06 Transitions= 4.8e+07 Memory= 618.889 t= 117 R= 2e+04
+Depth= 4540 States= 3e+06 Transitions= 7.25e+07 Memory= 695.158 t= 178 R= 2e+04
+pan: resizing hashtable to -w22.. done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim - (none specified)
+ assertion violations +
+ cycle checks - (disabled by -DSAFETY)
+ invalid end states +
+
+State-vector 72 byte, depth reached 4540, errors: 0
+ 3841511 states, stored
+ 90242688 states, matched
+ 94084199 transitions (= stored+matched)
+1.5073578e+09 atomic steps
+hash conflicts: 63759942 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 366.355 equivalent memory usage for states (stored*(State-vector + overhead))
+ 300.680 actual memory usage for states (compression: 82.07%)
+ state-vector as stored = 54 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 790.440 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 410, ".input.spin", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 81, "(1)"
+ line 256, ".input.spin", state 101, "(1)"
+ line 260, ".input.spin", state 109, "(1)"
+ line 596, ".input.spin", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 410, ".input.spin", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 199, "(1)"
+ line 256, ".input.spin", state 219, "(1)"
+ line 260, ".input.spin", state 227, "(1)"
+ line 410, ".input.spin", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 310, "(1)"
+ line 256, ".input.spin", state 330, "(1)"
+ line 260, ".input.spin", state 338, "(1)"
+ line 410, ".input.spin", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 361, "(1)"
+ line 410, ".input.spin", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 362, "else"
+ line 410, ".input.spin", state 365, "(1)"
+ line 414, ".input.spin", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 375, "(1)"
+ line 414, ".input.spin", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 376, "else"
+ line 414, ".input.spin", state 379, "(1)"
+ line 414, ".input.spin", state 380, "(1)"
+ line 414, ".input.spin", state 380, "(1)"
+ line 412, ".input.spin", state 385, "((i<1))"
+ line 412, ".input.spin", state 385, "((i>=1))"
+ line 419, ".input.spin", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 393, "(1)"
+ line 419, ".input.spin", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 394, "else"
+ line 419, ".input.spin", state 397, "(1)"
+ line 419, ".input.spin", state 398, "(1)"
+ line 419, ".input.spin", state 398, "(1)"
+ line 423, ".input.spin", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 407, "(1)"
+ line 423, ".input.spin", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 408, "else"
+ line 423, ".input.spin", state 411, "(1)"
+ line 423, ".input.spin", state 412, "(1)"
+ line 423, ".input.spin", state 412, "(1)"
+ line 421, ".input.spin", state 417, "((i<2))"
+ line 421, ".input.spin", state 417, "((i>=2))"
+ line 248, ".input.spin", state 423, "(1)"
+ line 252, ".input.spin", state 431, "(1)"
+ line 252, ".input.spin", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, ".input.spin", state 432, "else"
+ line 250, ".input.spin", state 437, "((i<1))"
+ line 250, ".input.spin", state 437, "((i>=1))"
+ line 256, ".input.spin", state 443, "(1)"
+ line 256, ".input.spin", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, ".input.spin", state 444, "else"
+ line 260, ".input.spin", state 451, "(1)"
+ line 260, ".input.spin", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, ".input.spin", state 452, "else"
+ line 258, ".input.spin", state 457, "((i<2))"
+ line 258, ".input.spin", state 457, "((i>=2))"
+ line 265, ".input.spin", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, ".input.spin", state 461, "else"
+ line 430, ".input.spin", state 463, "(1)"
+ line 430, ".input.spin", state 463, "(1)"
+ line 596, ".input.spin", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 596, ".input.spin", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 596, ".input.spin", state 468, "(1)"
+ line 271, ".input.spin", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 483, "(1)"
+ line 279, ".input.spin", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 519, "(1)"
+ line 252, ".input.spin", state 527, "(1)"
+ line 256, ".input.spin", state 539, "(1)"
+ line 260, ".input.spin", state 547, "(1)"
+ line 410, ".input.spin", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 629, "(1)"
+ line 252, ".input.spin", state 637, "(1)"
+ line 256, ".input.spin", state 649, "(1)"
+ line 260, ".input.spin", state 657, "(1)"
+ line 410, ".input.spin", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 747, "(1)"
+ line 256, ".input.spin", state 767, "(1)"
+ line 260, ".input.spin", state 775, "(1)"
+ line 410, ".input.spin", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 796, "(1)"
+ line 410, ".input.spin", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 797, "else"
+ line 410, ".input.spin", state 800, "(1)"
+ line 414, ".input.spin", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 810, "(1)"
+ line 414, ".input.spin", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 811, "else"
+ line 414, ".input.spin", state 814, "(1)"
+ line 414, ".input.spin", state 815, "(1)"
+ line 414, ".input.spin", state 815, "(1)"
+ line 412, ".input.spin", state 820, "((i<1))"
+ line 412, ".input.spin", state 820, "((i>=1))"
+ line 419, ".input.spin", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 828, "(1)"
+ line 419, ".input.spin", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 829, "else"
+ line 419, ".input.spin", state 832, "(1)"
+ line 419, ".input.spin", state 833, "(1)"
+ line 419, ".input.spin", state 833, "(1)"
+ line 423, ".input.spin", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 842, "(1)"
+ line 423, ".input.spin", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 843, "else"
+ line 423, ".input.spin", state 846, "(1)"
+ line 423, ".input.spin", state 847, "(1)"
+ line 423, ".input.spin", state 847, "(1)"
+ line 421, ".input.spin", state 852, "((i<2))"
+ line 421, ".input.spin", state 852, "((i>=2))"
+ line 248, ".input.spin", state 858, "(1)"
+ line 252, ".input.spin", state 866, "(1)"
+ line 252, ".input.spin", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, ".input.spin", state 867, "else"
+ line 250, ".input.spin", state 872, "((i<1))"
+ line 250, ".input.spin", state 872, "((i>=1))"
+ line 256, ".input.spin", state 878, "(1)"
+ line 256, ".input.spin", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, ".input.spin", state 879, "else"
+ line 260, ".input.spin", state 886, "(1)"
+ line 260, ".input.spin", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, ".input.spin", state 887, "else"
+ line 258, ".input.spin", state 892, "((i<2))"
+ line 258, ".input.spin", state 892, "((i>=2))"
+ line 265, ".input.spin", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, ".input.spin", state 896, "else"
+ line 430, ".input.spin", state 898, "(1)"
+ line 430, ".input.spin", state 898, "(1)"
+ line 604, ".input.spin", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 410, ".input.spin", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 971, "(1)"
+ line 252, ".input.spin", state 979, "(1)"
+ line 256, ".input.spin", state 991, "(1)"
+ line 260, ".input.spin", state 999, "(1)"
+ line 410, ".input.spin", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1085, "(1)"
+ line 256, ".input.spin", state 1105, "(1)"
+ line 260, ".input.spin", state 1113, "(1)"
+ line 410, ".input.spin", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1200, "(1)"
+ line 256, ".input.spin", state 1220, "(1)"
+ line 260, ".input.spin", state 1228, "(1)"
+ line 410, ".input.spin", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1311, "(1)"
+ line 256, ".input.spin", state 1331, "(1)"
+ line 260, ".input.spin", state 1339, "(1)"
+ line 271, ".input.spin", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1407, "(1)"
+ line 252, ".input.spin", state 1415, "(1)"
+ line 256, ".input.spin", state 1427, "(1)"
+ line 260, ".input.spin", state 1435, "(1)"
+ line 410, ".input.spin", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1517, "(1)"
+ line 252, ".input.spin", state 1525, "(1)"
+ line 256, ".input.spin", state 1537, "(1)"
+ line 260, ".input.spin", state 1545, "(1)"
+ line 410, ".input.spin", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1628, "(1)"
+ line 252, ".input.spin", state 1636, "(1)"
+ line 256, ".input.spin", state 1648, "(1)"
+ line 260, ".input.spin", state 1656, "(1)"
+ line 410, ".input.spin", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1742, "(1)"
+ line 256, ".input.spin", state 1762, "(1)"
+ line 260, ".input.spin", state 1770, "(1)"
+ line 643, ".input.spin", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 410, ".input.spin", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1860, "(1)"
+ line 256, ".input.spin", state 1880, "(1)"
+ line 260, ".input.spin", state 1888, "(1)"
+ line 410, ".input.spin", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1971, "(1)"
+ line 256, ".input.spin", state 1991, "(1)"
+ line 260, ".input.spin", state 1999, "(1)"
+ line 410, ".input.spin", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 2022, "(1)"
+ line 410, ".input.spin", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, ".input.spin", state 2023, "else"
+ line 410, ".input.spin", state 2026, "(1)"
+ line 414, ".input.spin", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2036, "(1)"
+ line 414, ".input.spin", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, ".input.spin", state 2037, "else"
+ line 414, ".input.spin", state 2040, "(1)"
+ line 414, ".input.spin", state 2041, "(1)"
+ line 414, ".input.spin", state 2041, "(1)"
+ line 412, ".input.spin", state 2046, "((i<1))"
+ line 412, ".input.spin", state 2046, "((i>=1))"
+ line 419, ".input.spin", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2054, "(1)"
+ line 419, ".input.spin", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, ".input.spin", state 2055, "else"
+ line 419, ".input.spin", state 2058, "(1)"
+ line 419, ".input.spin", state 2059, "(1)"
+ line 419, ".input.spin", state 2059, "(1)"
+ line 423, ".input.spin", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2068, "(1)"
+ line 423, ".input.spin", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, ".input.spin", state 2069, "else"
+ line 423, ".input.spin", state 2072, "(1)"
+ line 423, ".input.spin", state 2073, "(1)"
+ line 423, ".input.spin", state 2073, "(1)"
+ line 421, ".input.spin", state 2078, "((i<2))"
+ line 421, ".input.spin", state 2078, "((i>=2))"
+ line 248, ".input.spin", state 2084, "(1)"
+ line 252, ".input.spin", state 2092, "(1)"
+ line 252, ".input.spin", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, ".input.spin", state 2093, "else"
+ line 250, ".input.spin", state 2098, "((i<1))"
+ line 250, ".input.spin", state 2098, "((i>=1))"
+ line 256, ".input.spin", state 2104, "(1)"
+ line 256, ".input.spin", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, ".input.spin", state 2105, "else"
+ line 260, ".input.spin", state 2112, "(1)"
+ line 260, ".input.spin", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, ".input.spin", state 2113, "else"
+ line 258, ".input.spin", state 2118, "((i<2))"
+ line 258, ".input.spin", state 2118, "((i>=2))"
+ line 265, ".input.spin", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, ".input.spin", state 2122, "else"
+ line 430, ".input.spin", state 2124, "(1)"
+ line 430, ".input.spin", state 2124, "(1)"
+ line 643, ".input.spin", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 643, ".input.spin", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 643, ".input.spin", state 2129, "(1)"
+ line 271, ".input.spin", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2180, "(1)"
+ line 252, ".input.spin", state 2188, "(1)"
+ line 256, ".input.spin", state 2200, "(1)"
+ line 260, ".input.spin", state 2208, "(1)"
+ line 410, ".input.spin", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2290, "(1)"
+ line 252, ".input.spin", state 2298, "(1)"
+ line 256, ".input.spin", state 2310, "(1)"
+ line 260, ".input.spin", state 2318, "(1)"
+ line 271, ".input.spin", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2387, "(1)"
+ line 252, ".input.spin", state 2395, "(1)"
+ line 256, ".input.spin", state 2407, "(1)"
+ line 260, ".input.spin", state 2415, "(1)"
+ line 410, ".input.spin", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2497, "(1)"
+ line 252, ".input.spin", state 2505, "(1)"
+ line 256, ".input.spin", state 2517, "(1)"
+ line 260, ".input.spin", state 2525, "(1)"
+ line 410, ".input.spin", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 2608, "(1)"
+ line 252, ".input.spin", state 2616, "(1)"
+ line 256, ".input.spin", state 2628, "(1)"
+ line 260, ".input.spin", state 2636, "(1)"
+ line 248, ".input.spin", state 2667, "(1)"
+ line 256, ".input.spin", state 2687, "(1)"
+ line 260, ".input.spin", state 2695, "(1)"
+ line 248, ".input.spin", state 2710, "(1)"
+ line 252, ".input.spin", state 2718, "(1)"
+ line 256, ".input.spin", state 2730, "(1)"
+ line 260, ".input.spin", state 2738, "(1)"
+ line 897, ".input.spin", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 410, ".input.spin", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 82, "(1)"
+ line 252, ".input.spin", state 90, "(1)"
+ line 256, ".input.spin", state 102, "(1)"
+ line 271, ".input.spin", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 410, ".input.spin", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, ".input.spin", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 257, "(1)"
+ line 252, ".input.spin", state 265, "(1)"
+ line 256, ".input.spin", state 277, "(1)"
+ line 260, ".input.spin", state 285, "(1)"
+ line 414, ".input.spin", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, ".input.spin", state 378, "(1)"
+ line 256, ".input.spin", state 390, "(1)"
+ line 260, ".input.spin", state 398, "(1)"
+ line 414, ".input.spin", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, ".input.spin", state 499, "(1)"
+ line 256, ".input.spin", state 511, "(1)"
+ line 260, ".input.spin", state 519, "(1)"
+ line 414, ".input.spin", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, ".input.spin", state 610, "(1)"
+ line 256, ".input.spin", state 622, "(1)"
+ line 260, ".input.spin", state 630, "(1)"
+ line 414, ".input.spin", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, ".input.spin", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, ".input.spin", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, ".input.spin", state 723, "(1)"
+ line 256, ".input.spin", state 735, "(1)"
+ line 260, ".input.spin", state 743, "(1)"
+ line 271, ".input.spin", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, ".input.spin", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 820, "(1)"
+ line 283, ".input.spin", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 843, "(1)"
+ line 252, ".input.spin", state 851, "(1)"
+ line 256, ".input.spin", state 863, "(1)"
+ line 260, ".input.spin", state 871, "(1)"
+ line 275, ".input.spin", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 909, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 918, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 934, "(1)"
+ line 252, ".input.spin", state 942, "(1)"
+ line 256, ".input.spin", state 954, "(1)"
+ line 260, ".input.spin", state 962, "(1)"
+ line 275, ".input.spin", state 987, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1000, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1009, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1025, "(1)"
+ line 252, ".input.spin", state 1033, "(1)"
+ line 256, ".input.spin", state 1045, "(1)"
+ line 260, ".input.spin", state 1053, "(1)"
+ line 275, ".input.spin", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, ".input.spin", state 1091, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, ".input.spin", state 1100, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, ".input.spin", state 1116, "(1)"
+ line 252, ".input.spin", state 1124, "(1)"
+ line 256, ".input.spin", state 1136, "(1)"
+ line 260, ".input.spin", state 1144, "(1)"
+ line 1236, ".input.spin", state 1159, "-end-"
+ (71 of 1159 states)
+unreached in proctype :init:
+ (0 of 78 states)
+
+pan: elapsed time 231 seconds
+pan: rate 16628.478 states/second
+pan: avg transition delay 2.4555e-06 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+ (downloaded)
--- /dev/null
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+# Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+# Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
--- /dev/null
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1294)
+Depth= 4900 States= 1e+06 Transitions= 2.37e+07 Memory= 550.334 t= 65.5 R= 2e+04
+Depth= 4973 States= 2e+06 Transitions= 4.8e+07 Memory= 634.221 t= 134 R= 1e+04
+Depth= 4973 States= 3e+06 Transitions= 7.25e+07 Memory= 718.205 t= 204 R= 1e+04
+pan: resizing hashtable to -w22.. done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 4973, errors: 0
+ 3841511 states, stored
+ 90254094 states, matched
+ 94095605 transitions (= stored+matched)
+1.5073578e+09 atomic steps
+hash conflicts: 63765708 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 424.972 equivalent memory usage for states (stored*(State-vector + overhead))
+ 330.368 actual memory usage for states (compression: 77.74%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 819.932 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 410, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 81, "(1)"
+ line 256, "pan.___", state 101, "(1)"
+ line 260, "pan.___", state 109, "(1)"
+ line 596, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 410, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 199, "(1)"
+ line 256, "pan.___", state 219, "(1)"
+ line 260, "pan.___", state 227, "(1)"
+ line 410, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 310, "(1)"
+ line 256, "pan.___", state 330, "(1)"
+ line 260, "pan.___", state 338, "(1)"
+ line 410, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 361, "(1)"
+ line 410, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 362, "else"
+ line 410, "pan.___", state 365, "(1)"
+ line 414, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 375, "(1)"
+ line 414, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 376, "else"
+ line 414, "pan.___", state 379, "(1)"
+ line 414, "pan.___", state 380, "(1)"
+ line 414, "pan.___", state 380, "(1)"
+ line 412, "pan.___", state 385, "((i<1))"
+ line 412, "pan.___", state 385, "((i>=1))"
+ line 419, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 393, "(1)"
+ line 419, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 394, "else"
+ line 419, "pan.___", state 397, "(1)"
+ line 419, "pan.___", state 398, "(1)"
+ line 419, "pan.___", state 398, "(1)"
+ line 423, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 407, "(1)"
+ line 423, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 408, "else"
+ line 423, "pan.___", state 411, "(1)"
+ line 423, "pan.___", state 412, "(1)"
+ line 423, "pan.___", state 412, "(1)"
+ line 421, "pan.___", state 417, "((i<2))"
+ line 421, "pan.___", state 417, "((i>=2))"
+ line 248, "pan.___", state 423, "(1)"
+ line 252, "pan.___", state 431, "(1)"
+ line 252, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 432, "else"
+ line 250, "pan.___", state 437, "((i<1))"
+ line 250, "pan.___", state 437, "((i>=1))"
+ line 256, "pan.___", state 443, "(1)"
+ line 256, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 444, "else"
+ line 260, "pan.___", state 451, "(1)"
+ line 260, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 452, "else"
+ line 258, "pan.___", state 457, "((i<2))"
+ line 258, "pan.___", state 457, "((i>=2))"
+ line 265, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 461, "else"
+ line 430, "pan.___", state 463, "(1)"
+ line 430, "pan.___", state 463, "(1)"
+ line 596, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 596, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 596, "pan.___", state 468, "(1)"
+ line 271, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 483, "(1)"
+ line 279, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 519, "(1)"
+ line 252, "pan.___", state 527, "(1)"
+ line 256, "pan.___", state 539, "(1)"
+ line 260, "pan.___", state 547, "(1)"
+ line 410, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 629, "(1)"
+ line 252, "pan.___", state 637, "(1)"
+ line 256, "pan.___", state 649, "(1)"
+ line 260, "pan.___", state 657, "(1)"
+ line 410, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 747, "(1)"
+ line 256, "pan.___", state 767, "(1)"
+ line 260, "pan.___", state 775, "(1)"
+ line 410, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 796, "(1)"
+ line 410, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 797, "else"
+ line 410, "pan.___", state 800, "(1)"
+ line 414, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 810, "(1)"
+ line 414, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 811, "else"
+ line 414, "pan.___", state 814, "(1)"
+ line 414, "pan.___", state 815, "(1)"
+ line 414, "pan.___", state 815, "(1)"
+ line 412, "pan.___", state 820, "((i<1))"
+ line 412, "pan.___", state 820, "((i>=1))"
+ line 419, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 828, "(1)"
+ line 419, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 829, "else"
+ line 419, "pan.___", state 832, "(1)"
+ line 419, "pan.___", state 833, "(1)"
+ line 419, "pan.___", state 833, "(1)"
+ line 423, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 842, "(1)"
+ line 423, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 843, "else"
+ line 423, "pan.___", state 846, "(1)"
+ line 423, "pan.___", state 847, "(1)"
+ line 423, "pan.___", state 847, "(1)"
+ line 421, "pan.___", state 852, "((i<2))"
+ line 421, "pan.___", state 852, "((i>=2))"
+ line 248, "pan.___", state 858, "(1)"
+ line 252, "pan.___", state 866, "(1)"
+ line 252, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 867, "else"
+ line 250, "pan.___", state 872, "((i<1))"
+ line 250, "pan.___", state 872, "((i>=1))"
+ line 256, "pan.___", state 878, "(1)"
+ line 256, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 879, "else"
+ line 260, "pan.___", state 886, "(1)"
+ line 260, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 887, "else"
+ line 258, "pan.___", state 892, "((i<2))"
+ line 258, "pan.___", state 892, "((i>=2))"
+ line 265, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 896, "else"
+ line 430, "pan.___", state 898, "(1)"
+ line 430, "pan.___", state 898, "(1)"
+ line 604, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 410, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 971, "(1)"
+ line 252, "pan.___", state 979, "(1)"
+ line 256, "pan.___", state 991, "(1)"
+ line 260, "pan.___", state 999, "(1)"
+ line 410, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1085, "(1)"
+ line 256, "pan.___", state 1105, "(1)"
+ line 260, "pan.___", state 1113, "(1)"
+ line 410, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1200, "(1)"
+ line 256, "pan.___", state 1220, "(1)"
+ line 260, "pan.___", state 1228, "(1)"
+ line 410, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1311, "(1)"
+ line 256, "pan.___", state 1331, "(1)"
+ line 260, "pan.___", state 1339, "(1)"
+ line 271, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1407, "(1)"
+ line 252, "pan.___", state 1415, "(1)"
+ line 256, "pan.___", state 1427, "(1)"
+ line 260, "pan.___", state 1435, "(1)"
+ line 410, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1517, "(1)"
+ line 252, "pan.___", state 1525, "(1)"
+ line 256, "pan.___", state 1537, "(1)"
+ line 260, "pan.___", state 1545, "(1)"
+ line 410, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1628, "(1)"
+ line 252, "pan.___", state 1636, "(1)"
+ line 256, "pan.___", state 1648, "(1)"
+ line 260, "pan.___", state 1656, "(1)"
+ line 410, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1742, "(1)"
+ line 256, "pan.___", state 1762, "(1)"
+ line 260, "pan.___", state 1770, "(1)"
+ line 643, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 410, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1860, "(1)"
+ line 256, "pan.___", state 1880, "(1)"
+ line 260, "pan.___", state 1888, "(1)"
+ line 410, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1971, "(1)"
+ line 256, "pan.___", state 1991, "(1)"
+ line 260, "pan.___", state 1999, "(1)"
+ line 410, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 2022, "(1)"
+ line 410, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 410, "pan.___", state 2023, "else"
+ line 410, "pan.___", state 2026, "(1)"
+ line 414, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2036, "(1)"
+ line 414, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 414, "pan.___", state 2037, "else"
+ line 414, "pan.___", state 2040, "(1)"
+ line 414, "pan.___", state 2041, "(1)"
+ line 414, "pan.___", state 2041, "(1)"
+ line 412, "pan.___", state 2046, "((i<1))"
+ line 412, "pan.___", state 2046, "((i>=1))"
+ line 419, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2054, "(1)"
+ line 419, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 419, "pan.___", state 2055, "else"
+ line 419, "pan.___", state 2058, "(1)"
+ line 419, "pan.___", state 2059, "(1)"
+ line 419, "pan.___", state 2059, "(1)"
+ line 423, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2068, "(1)"
+ line 423, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 423, "pan.___", state 2069, "else"
+ line 423, "pan.___", state 2072, "(1)"
+ line 423, "pan.___", state 2073, "(1)"
+ line 423, "pan.___", state 2073, "(1)"
+ line 421, "pan.___", state 2078, "((i<2))"
+ line 421, "pan.___", state 2078, "((i>=2))"
+ line 248, "pan.___", state 2084, "(1)"
+ line 252, "pan.___", state 2092, "(1)"
+ line 252, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 252, "pan.___", state 2093, "else"
+ line 250, "pan.___", state 2098, "((i<1))"
+ line 250, "pan.___", state 2098, "((i>=1))"
+ line 256, "pan.___", state 2104, "(1)"
+ line 256, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 256, "pan.___", state 2105, "else"
+ line 260, "pan.___", state 2112, "(1)"
+ line 260, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 260, "pan.___", state 2113, "else"
+ line 258, "pan.___", state 2118, "((i<2))"
+ line 258, "pan.___", state 2118, "((i>=2))"
+ line 265, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 265, "pan.___", state 2122, "else"
+ line 430, "pan.___", state 2124, "(1)"
+ line 430, "pan.___", state 2124, "(1)"
+ line 643, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 643, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 643, "pan.___", state 2129, "(1)"
+ line 271, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2180, "(1)"
+ line 252, "pan.___", state 2188, "(1)"
+ line 256, "pan.___", state 2200, "(1)"
+ line 260, "pan.___", state 2208, "(1)"
+ line 410, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2290, "(1)"
+ line 252, "pan.___", state 2298, "(1)"
+ line 256, "pan.___", state 2310, "(1)"
+ line 260, "pan.___", state 2318, "(1)"
+ line 271, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2387, "(1)"
+ line 252, "pan.___", state 2395, "(1)"
+ line 256, "pan.___", state 2407, "(1)"
+ line 260, "pan.___", state 2415, "(1)"
+ line 410, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2497, "(1)"
+ line 252, "pan.___", state 2505, "(1)"
+ line 256, "pan.___", state 2517, "(1)"
+ line 260, "pan.___", state 2525, "(1)"
+ line 410, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 2608, "(1)"
+ line 252, "pan.___", state 2616, "(1)"
+ line 256, "pan.___", state 2628, "(1)"
+ line 260, "pan.___", state 2636, "(1)"
+ line 248, "pan.___", state 2667, "(1)"
+ line 256, "pan.___", state 2687, "(1)"
+ line 260, "pan.___", state 2695, "(1)"
+ line 248, "pan.___", state 2710, "(1)"
+ line 252, "pan.___", state 2718, "(1)"
+ line 256, "pan.___", state 2730, "(1)"
+ line 260, "pan.___", state 2738, "(1)"
+ line 897, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 410, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 82, "(1)"
+ line 252, "pan.___", state 90, "(1)"
+ line 256, "pan.___", state 102, "(1)"
+ line 271, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 410, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 414, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 257, "(1)"
+ line 252, "pan.___", state 265, "(1)"
+ line 256, "pan.___", state 277, "(1)"
+ line 260, "pan.___", state 285, "(1)"
+ line 414, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 378, "(1)"
+ line 256, "pan.___", state 390, "(1)"
+ line 260, "pan.___", state 398, "(1)"
+ line 414, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 499, "(1)"
+ line 256, "pan.___", state 511, "(1)"
+ line 260, "pan.___", state 519, "(1)"
+ line 414, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 610, "(1)"
+ line 256, "pan.___", state 622, "(1)"
+ line 260, "pan.___", state 630, "(1)"
+ line 414, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 419, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 423, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 252, "pan.___", state 723, "(1)"
+ line 256, "pan.___", state 735, "(1)"
+ line 260, "pan.___", state 743, "(1)"
+ line 271, "pan.___", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 820, "(1)"
+ line 283, "pan.___", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 843, "(1)"
+ line 252, "pan.___", state 851, "(1)"
+ line 256, "pan.___", state 863, "(1)"
+ line 260, "pan.___", state 871, "(1)"
+ line 275, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 909, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 918, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 934, "(1)"
+ line 252, "pan.___", state 942, "(1)"
+ line 256, "pan.___", state 954, "(1)"
+ line 260, "pan.___", state 962, "(1)"
+ line 275, "pan.___", state 987, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1000, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1009, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1025, "(1)"
+ line 252, "pan.___", state 1033, "(1)"
+ line 256, "pan.___", state 1045, "(1)"
+ line 260, "pan.___", state 1053, "(1)"
+ line 275, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 279, "pan.___", state 1091, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1100, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 248, "pan.___", state 1116, "(1)"
+ line 252, "pan.___", state 1124, "(1)"
+ line 256, "pan.___", state 1136, "(1)"
+ line 260, "pan.___", state 1144, "(1)"
+ line 1236, "pan.___", state 1159, "-end-"
+ (71 of 1159 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1299, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 265 seconds
+pan: rate 14518.182 states/second
+pan: avg transition delay 2.812e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+[] (!read_poison)
--- /dev/null
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define READER_NEST_LEVEL 2
--- /dev/null
+#define NO_MB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 8086 States= 1e+06 Transitions= 1.91e+07 Memory= 550.334 t= 51.2 R= 2e+04
+Depth= 8086 States= 2e+06 Transitions= 3.68e+07 Memory= 634.318 t= 98.4 R= 2e+04
+Depth= 8086 States= 3e+06 Transitions= 5.68e+07 Memory= 718.205 t= 153 R= 2e+04
+pan: resizing hashtable to -w22.. done
+Depth= 8086 States= 4e+06 Transitions= 7.01e+07 Memory= 833.213 t= 188 R= 2e+04
+Depth= 8086 States= 5e+06 Transitions= 8.42e+07 Memory= 917.197 t= 225 R= 2e+04
+Depth= 8086 States= 6e+06 Transitions= 9.87e+07 Memory= 1001.182 t= 263 R= 2e+04
+Depth= 8086 States= 7e+06 Transitions= 1.12e+08 Memory= 1085.166 t= 298 R= 2e+04
+Depth= 8086 States= 8e+06 Transitions= 1.28e+08 Memory= 1169.053 t= 342 R= 2e+04
+Depth= 8086 States= 9e+06 Transitions= 1.62e+08 Memory= 1253.037 t= 436 R= 2e+04
+pan: resizing hashtable to -w24.. done
+Depth= 8086 States= 1e+07 Transitions= 1.95e+08 Memory= 1461.018 t= 530 R= 2e+04
+Depth= 13700 States= 1.1e+07 Transitions= 2.31e+08 Memory= 1545.002 t= 629 R= 2e+04
+Depth= 13700 States= 1.2e+07 Transitions= 2.64e+08 Memory= 1628.986 t= 721 R= 2e+04
+Depth= 13700 States= 1.3e+07 Transitions= 2.89e+08 Memory= 1712.971 t= 789 R= 2e+04
+Depth= 13700 States= 1.4e+07 Transitions= 3.09e+08 Memory= 1796.955 t= 844 R= 2e+04
+Depth= 13700 States= 1.5e+07 Transitions= 3.29e+08 Memory= 1880.940 t= 897 R= 2e+04
+pan: claim violated! (at depth 1143)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 13700, errors: 1
+ 15925114 states, stored
+3.2589318e+08 states, matched
+3.418183e+08 transitions (= stored+matched)
+5.3108495e+09 atomic steps
+hash conflicts: 1.8673119e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1761.735 equivalent memory usage for states (stored*(State-vector + overhead))
+ 1373.571 actual memory usage for states (compression: 77.97%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1958.576 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 21, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 53, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 67, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 85, "(1)"
+ line 257, "pan.___", state 105, "(1)"
+ line 261, "pan.___", state 113, "(1)"
+ line 603, "pan.___", state 132, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 139, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 171, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 185, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 203, "(1)"
+ line 257, "pan.___", state 223, "(1)"
+ line 261, "pan.___", state 231, "(1)"
+ line 411, "pan.___", state 250, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 282, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 296, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 314, "(1)"
+ line 257, "pan.___", state 334, "(1)"
+ line 261, "pan.___", state 342, "(1)"
+ line 411, "pan.___", state 363, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 365, "(1)"
+ line 411, "pan.___", state 366, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 366, "else"
+ line 411, "pan.___", state 369, "(1)"
+ line 415, "pan.___", state 377, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 380, "else"
+ line 415, "pan.___", state 383, "(1)"
+ line 415, "pan.___", state 384, "(1)"
+ line 415, "pan.___", state 384, "(1)"
+ line 413, "pan.___", state 389, "((i<1))"
+ line 413, "pan.___", state 389, "((i>=1))"
+ line 420, "pan.___", state 395, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 398, "else"
+ line 420, "pan.___", state 401, "(1)"
+ line 420, "pan.___", state 402, "(1)"
+ line 420, "pan.___", state 402, "(1)"
+ line 424, "pan.___", state 409, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 412, "else"
+ line 424, "pan.___", state 415, "(1)"
+ line 424, "pan.___", state 416, "(1)"
+ line 424, "pan.___", state 416, "(1)"
+ line 422, "pan.___", state 421, "((i<2))"
+ line 422, "pan.___", state 421, "((i>=2))"
+ line 249, "pan.___", state 427, "(1)"
+ line 253, "pan.___", state 435, "(1)"
+ line 253, "pan.___", state 436, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 436, "else"
+ line 251, "pan.___", state 441, "((i<1))"
+ line 251, "pan.___", state 441, "((i>=1))"
+ line 257, "pan.___", state 447, "(1)"
+ line 257, "pan.___", state 448, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 448, "else"
+ line 261, "pan.___", state 455, "(1)"
+ line 261, "pan.___", state 456, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 456, "else"
+ line 259, "pan.___", state 461, "((i<2))"
+ line 259, "pan.___", state 461, "((i>=2))"
+ line 266, "pan.___", state 465, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 465, "else"
+ line 431, "pan.___", state 467, "(1)"
+ line 431, "pan.___", state 467, "(1)"
+ line 603, "pan.___", state 470, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 603, "pan.___", state 471, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 603, "pan.___", state 472, "(1)"
+ line 272, "pan.___", state 476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 478, "(1)"
+ line 276, "pan.___", state 485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 487, "(1)"
+ line 276, "pan.___", state 488, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 488, "else"
+ line 274, "pan.___", state 493, "((i<1))"
+ line 274, "pan.___", state 493, "((i>=1))"
+ line 280, "pan.___", state 498, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 500, "(1)"
+ line 280, "pan.___", state 501, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 501, "else"
+ line 284, "pan.___", state 507, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 509, "(1)"
+ line 284, "pan.___", state 510, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 510, "else"
+ line 282, "pan.___", state 515, "((i<2))"
+ line 282, "pan.___", state 515, "((i>=2))"
+ line 249, "pan.___", state 523, "(1)"
+ line 253, "pan.___", state 531, "(1)"
+ line 253, "pan.___", state 532, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 532, "else"
+ line 251, "pan.___", state 537, "((i<1))"
+ line 251, "pan.___", state 537, "((i>=1))"
+ line 257, "pan.___", state 543, "(1)"
+ line 257, "pan.___", state 544, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 544, "else"
+ line 261, "pan.___", state 551, "(1)"
+ line 261, "pan.___", state 552, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 552, "else"
+ line 266, "pan.___", state 561, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 561, "else"
+ line 299, "pan.___", state 563, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 563, "else"
+ line 411, "pan.___", state 569, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 601, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 615, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 633, "(1)"
+ line 257, "pan.___", state 653, "(1)"
+ line 261, "pan.___", state 661, "(1)"
+ line 411, "pan.___", state 687, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 719, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 733, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 751, "(1)"
+ line 257, "pan.___", state 771, "(1)"
+ line 261, "pan.___", state 779, "(1)"
+ line 411, "pan.___", state 798, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 800, "(1)"
+ line 411, "pan.___", state 801, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 801, "else"
+ line 411, "pan.___", state 804, "(1)"
+ line 415, "pan.___", state 812, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 815, "else"
+ line 415, "pan.___", state 818, "(1)"
+ line 415, "pan.___", state 819, "(1)"
+ line 415, "pan.___", state 819, "(1)"
+ line 413, "pan.___", state 824, "((i<1))"
+ line 413, "pan.___", state 824, "((i>=1))"
+ line 420, "pan.___", state 830, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 833, "else"
+ line 420, "pan.___", state 836, "(1)"
+ line 420, "pan.___", state 837, "(1)"
+ line 420, "pan.___", state 837, "(1)"
+ line 424, "pan.___", state 844, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 847, "else"
+ line 424, "pan.___", state 850, "(1)"
+ line 424, "pan.___", state 851, "(1)"
+ line 424, "pan.___", state 851, "(1)"
+ line 422, "pan.___", state 856, "((i<2))"
+ line 422, "pan.___", state 856, "((i>=2))"
+ line 249, "pan.___", state 862, "(1)"
+ line 253, "pan.___", state 870, "(1)"
+ line 253, "pan.___", state 871, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 871, "else"
+ line 251, "pan.___", state 876, "((i<1))"
+ line 251, "pan.___", state 876, "((i>=1))"
+ line 257, "pan.___", state 882, "(1)"
+ line 257, "pan.___", state 883, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 883, "else"
+ line 261, "pan.___", state 890, "(1)"
+ line 261, "pan.___", state 891, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 891, "else"
+ line 259, "pan.___", state 896, "((i<2))"
+ line 259, "pan.___", state 896, "((i>=2))"
+ line 266, "pan.___", state 900, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 900, "else"
+ line 431, "pan.___", state 902, "(1)"
+ line 431, "pan.___", state 902, "(1)"
+ line 611, "pan.___", state 906, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 911, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 943, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 957, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 975, "(1)"
+ line 257, "pan.___", state 995, "(1)"
+ line 261, "pan.___", state 1003, "(1)"
+ line 411, "pan.___", state 1025, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1057, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1071, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1089, "(1)"
+ line 257, "pan.___", state 1109, "(1)"
+ line 261, "pan.___", state 1117, "(1)"
+ line 411, "pan.___", state 1140, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1172, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1186, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1204, "(1)"
+ line 257, "pan.___", state 1224, "(1)"
+ line 261, "pan.___", state 1232, "(1)"
+ line 411, "pan.___", state 1251, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1283, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1297, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1315, "(1)"
+ line 257, "pan.___", state 1335, "(1)"
+ line 261, "pan.___", state 1343, "(1)"
+ line 272, "pan.___", state 1364, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1366, "(1)"
+ line 276, "pan.___", state 1373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1375, "(1)"
+ line 276, "pan.___", state 1376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1376, "else"
+ line 274, "pan.___", state 1381, "((i<1))"
+ line 274, "pan.___", state 1381, "((i>=1))"
+ line 280, "pan.___", state 1386, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1388, "(1)"
+ line 280, "pan.___", state 1389, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1389, "else"
+ line 284, "pan.___", state 1395, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1397, "(1)"
+ line 284, "pan.___", state 1398, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1398, "else"
+ line 282, "pan.___", state 1403, "((i<2))"
+ line 282, "pan.___", state 1403, "((i>=2))"
+ line 249, "pan.___", state 1411, "(1)"
+ line 253, "pan.___", state 1419, "(1)"
+ line 253, "pan.___", state 1420, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1420, "else"
+ line 251, "pan.___", state 1425, "((i<1))"
+ line 251, "pan.___", state 1425, "((i>=1))"
+ line 257, "pan.___", state 1431, "(1)"
+ line 257, "pan.___", state 1432, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1432, "else"
+ line 261, "pan.___", state 1439, "(1)"
+ line 261, "pan.___", state 1440, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1440, "else"
+ line 266, "pan.___", state 1449, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1449, "else"
+ line 299, "pan.___", state 1451, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1451, "else"
+ line 411, "pan.___", state 1457, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1489, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1521, "(1)"
+ line 257, "pan.___", state 1541, "(1)"
+ line 261, "pan.___", state 1549, "(1)"
+ line 411, "pan.___", state 1568, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1600, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1614, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1632, "(1)"
+ line 257, "pan.___", state 1652, "(1)"
+ line 261, "pan.___", state 1660, "(1)"
+ line 411, "pan.___", state 1682, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1714, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1728, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1746, "(1)"
+ line 257, "pan.___", state 1766, "(1)"
+ line 261, "pan.___", state 1774, "(1)"
+ line 650, "pan.___", state 1793, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1800, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1832, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1846, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1864, "(1)"
+ line 257, "pan.___", state 1884, "(1)"
+ line 261, "pan.___", state 1892, "(1)"
+ line 411, "pan.___", state 1911, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1943, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1957, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1975, "(1)"
+ line 257, "pan.___", state 1995, "(1)"
+ line 261, "pan.___", state 2003, "(1)"
+ line 411, "pan.___", state 2024, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2026, "(1)"
+ line 411, "pan.___", state 2027, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2027, "else"
+ line 411, "pan.___", state 2030, "(1)"
+ line 415, "pan.___", state 2038, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2041, "else"
+ line 415, "pan.___", state 2044, "(1)"
+ line 415, "pan.___", state 2045, "(1)"
+ line 415, "pan.___", state 2045, "(1)"
+ line 413, "pan.___", state 2050, "((i<1))"
+ line 413, "pan.___", state 2050, "((i>=1))"
+ line 420, "pan.___", state 2056, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2059, "else"
+ line 420, "pan.___", state 2062, "(1)"
+ line 420, "pan.___", state 2063, "(1)"
+ line 420, "pan.___", state 2063, "(1)"
+ line 424, "pan.___", state 2070, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2073, "else"
+ line 424, "pan.___", state 2076, "(1)"
+ line 424, "pan.___", state 2077, "(1)"
+ line 424, "pan.___", state 2077, "(1)"
+ line 422, "pan.___", state 2082, "((i<2))"
+ line 422, "pan.___", state 2082, "((i>=2))"
+ line 249, "pan.___", state 2088, "(1)"
+ line 253, "pan.___", state 2096, "(1)"
+ line 253, "pan.___", state 2097, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2097, "else"
+ line 251, "pan.___", state 2102, "((i<1))"
+ line 251, "pan.___", state 2102, "((i>=1))"
+ line 257, "pan.___", state 2108, "(1)"
+ line 257, "pan.___", state 2109, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2109, "else"
+ line 261, "pan.___", state 2116, "(1)"
+ line 261, "pan.___", state 2117, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2117, "else"
+ line 259, "pan.___", state 2122, "((i<2))"
+ line 259, "pan.___", state 2122, "((i>=2))"
+ line 266, "pan.___", state 2126, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2126, "else"
+ line 431, "pan.___", state 2128, "(1)"
+ line 431, "pan.___", state 2128, "(1)"
+ line 650, "pan.___", state 2131, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 650, "pan.___", state 2132, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 650, "pan.___", state 2133, "(1)"
+ line 272, "pan.___", state 2137, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 2139, "(1)"
+ line 276, "pan.___", state 2146, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2148, "(1)"
+ line 276, "pan.___", state 2149, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 2149, "else"
+ line 274, "pan.___", state 2154, "((i<1))"
+ line 274, "pan.___", state 2154, "((i>=1))"
+ line 280, "pan.___", state 2159, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2161, "(1)"
+ line 280, "pan.___", state 2162, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 2162, "else"
+ line 284, "pan.___", state 2168, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2170, "(1)"
+ line 284, "pan.___", state 2171, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 2171, "else"
+ line 282, "pan.___", state 2176, "((i<2))"
+ line 282, "pan.___", state 2176, "((i>=2))"
+ line 249, "pan.___", state 2184, "(1)"
+ line 253, "pan.___", state 2192, "(1)"
+ line 253, "pan.___", state 2193, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2193, "else"
+ line 251, "pan.___", state 2198, "((i<1))"
+ line 251, "pan.___", state 2198, "((i>=1))"
+ line 257, "pan.___", state 2204, "(1)"
+ line 257, "pan.___", state 2205, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2205, "else"
+ line 261, "pan.___", state 2212, "(1)"
+ line 261, "pan.___", state 2213, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2213, "else"
+ line 266, "pan.___", state 2222, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2222, "else"
+ line 299, "pan.___", state 2224, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 2224, "else"
+ line 411, "pan.___", state 2230, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2262, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2276, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2294, "(1)"
+ line 257, "pan.___", state 2314, "(1)"
+ line 261, "pan.___", state 2322, "(1)"
+ line 272, "pan.___", state 2344, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 2346, "(1)"
+ line 276, "pan.___", state 2353, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2355, "(1)"
+ line 276, "pan.___", state 2356, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 2356, "else"
+ line 274, "pan.___", state 2361, "((i<1))"
+ line 274, "pan.___", state 2361, "((i>=1))"
+ line 280, "pan.___", state 2366, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2368, "(1)"
+ line 280, "pan.___", state 2369, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 2369, "else"
+ line 284, "pan.___", state 2375, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2377, "(1)"
+ line 284, "pan.___", state 2378, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 2378, "else"
+ line 282, "pan.___", state 2383, "((i<2))"
+ line 282, "pan.___", state 2383, "((i>=2))"
+ line 249, "pan.___", state 2391, "(1)"
+ line 253, "pan.___", state 2399, "(1)"
+ line 253, "pan.___", state 2400, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2400, "else"
+ line 251, "pan.___", state 2405, "((i<1))"
+ line 251, "pan.___", state 2405, "((i>=1))"
+ line 257, "pan.___", state 2411, "(1)"
+ line 257, "pan.___", state 2412, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2412, "else"
+ line 261, "pan.___", state 2419, "(1)"
+ line 261, "pan.___", state 2420, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2420, "else"
+ line 266, "pan.___", state 2429, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2429, "else"
+ line 299, "pan.___", state 2431, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 2431, "else"
+ line 411, "pan.___", state 2437, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2469, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2483, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2501, "(1)"
+ line 257, "pan.___", state 2521, "(1)"
+ line 261, "pan.___", state 2529, "(1)"
+ line 411, "pan.___", state 2548, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2580, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2594, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2612, "(1)"
+ line 257, "pan.___", state 2632, "(1)"
+ line 261, "pan.___", state 2640, "(1)"
+ line 249, "pan.___", state 2671, "(1)"
+ line 257, "pan.___", state 2691, "(1)"
+ line 261, "pan.___", state 2699, "(1)"
+ line 249, "pan.___", state 2714, "(1)"
+ line 257, "pan.___", state 2734, "(1)"
+ line 261, "pan.___", state 2742, "(1)"
+ line 898, "pan.___", state 2759, "-end-"
+ (306 of 2759 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 20, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 26, "(1)"
+ line 415, "pan.___", state 34, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 40, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 415, "pan.___", state 41, "(1)"
+ line 413, "pan.___", state 46, "((i<1))"
+ line 413, "pan.___", state 46, "((i>=1))"
+ line 420, "pan.___", state 52, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 58, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 420, "pan.___", state 59, "(1)"
+ line 424, "pan.___", state 72, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 424, "pan.___", state 73, "(1)"
+ line 422, "pan.___", state 78, "((i<2))"
+ line 422, "pan.___", state 78, "((i>=2))"
+ line 249, "pan.___", state 84, "(1)"
+ line 253, "pan.___", state 92, "(1)"
+ line 253, "pan.___", state 93, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 93, "else"
+ line 251, "pan.___", state 98, "((i<1))"
+ line 251, "pan.___", state 98, "((i>=1))"
+ line 257, "pan.___", state 104, "(1)"
+ line 257, "pan.___", state 105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 105, "else"
+ line 261, "pan.___", state 112, "(1)"
+ line 261, "pan.___", state 113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 113, "else"
+ line 259, "pan.___", state 118, "((i<2))"
+ line 259, "pan.___", state 118, "((i>=2))"
+ line 266, "pan.___", state 122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 122, "else"
+ line 431, "pan.___", state 124, "(1)"
+ line 431, "pan.___", state 124, "(1)"
+ line 272, "pan.___", state 133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 142, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 274, "pan.___", state 150, "((i<1))"
+ line 274, "pan.___", state 150, "((i>=1))"
+ line 280, "pan.___", state 155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 1021, "pan.___", state 183, "old_data = cached_rcu_ptr.val[_pid]"
+ line 1032, "pan.___", state 187, "_proc_urcu_writer = (_proc_urcu_writer|(1<<4))"
+ line 411, "pan.___", state 195, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 201, "(1)"
+ line 415, "pan.___", state 209, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 215, "(1)"
+ line 415, "pan.___", state 216, "(1)"
+ line 415, "pan.___", state 216, "(1)"
+ line 420, "pan.___", state 229, "(1)"
+ line 424, "pan.___", state 241, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 259, "(1)"
+ line 253, "pan.___", state 267, "(1)"
+ line 261, "pan.___", state 287, "(1)"
+ line 431, "pan.___", state 299, "(1)"
+ line 431, "pan.___", state 299, "(1)"
+ line 415, "pan.___", state 322, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 354, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 380, "(1)"
+ line 261, "pan.___", state 400, "(1)"
+ line 415, "pan.___", state 443, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 501, "(1)"
+ line 415, "pan.___", state 554, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 612, "(1)"
+ line 415, "pan.___", state 667, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 699, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 725, "(1)"
+ line 261, "pan.___", state 745, "(1)"
+ line 1168, "pan.___", state 770, "_proc_urcu_writer = (_proc_urcu_writer|(1<<13))"
+ line 272, "pan.___", state 798, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 800, "(1)"
+ line 276, "pan.___", state 807, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 809, "(1)"
+ line 276, "pan.___", state 810, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 810, "else"
+ line 274, "pan.___", state 815, "((i<1))"
+ line 274, "pan.___", state 815, "((i>=1))"
+ line 280, "pan.___", state 820, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 822, "(1)"
+ line 280, "pan.___", state 823, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 823, "else"
+ line 284, "pan.___", state 829, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 831, "(1)"
+ line 284, "pan.___", state 832, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 832, "else"
+ line 282, "pan.___", state 837, "((i<2))"
+ line 282, "pan.___", state 837, "((i>=2))"
+ line 249, "pan.___", state 845, "(1)"
+ line 253, "pan.___", state 853, "(1)"
+ line 253, "pan.___", state 854, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 854, "else"
+ line 251, "pan.___", state 859, "((i<1))"
+ line 251, "pan.___", state 859, "((i>=1))"
+ line 257, "pan.___", state 865, "(1)"
+ line 257, "pan.___", state 866, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 866, "else"
+ line 261, "pan.___", state 873, "(1)"
+ line 261, "pan.___", state 874, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 874, "else"
+ line 266, "pan.___", state 883, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 883, "else"
+ line 299, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 885, "else"
+ line 276, "pan.___", state 898, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 911, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 920, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 936, "(1)"
+ line 253, "pan.___", state 944, "(1)"
+ line 257, "pan.___", state 956, "(1)"
+ line 261, "pan.___", state 964, "(1)"
+ line 276, "pan.___", state 989, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1011, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1027, "(1)"
+ line 253, "pan.___", state 1035, "(1)"
+ line 257, "pan.___", state 1047, "(1)"
+ line 261, "pan.___", state 1055, "(1)"
+ line 272, "pan.___", state 1071, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 1073, "(1)"
+ line 276, "pan.___", state 1080, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 1082, "(1)"
+ line 276, "pan.___", state 1083, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 1083, "else"
+ line 274, "pan.___", state 1088, "((i<1))"
+ line 274, "pan.___", state 1088, "((i>=1))"
+ line 280, "pan.___", state 1093, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1095, "(1)"
+ line 280, "pan.___", state 1096, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1096, "else"
+ line 284, "pan.___", state 1102, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1104, "(1)"
+ line 284, "pan.___", state 1105, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1105, "else"
+ line 282, "pan.___", state 1110, "((i<2))"
+ line 282, "pan.___", state 1110, "((i>=2))"
+ line 249, "pan.___", state 1118, "(1)"
+ line 253, "pan.___", state 1126, "(1)"
+ line 253, "pan.___", state 1127, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1127, "else"
+ line 251, "pan.___", state 1132, "((i<1))"
+ line 251, "pan.___", state 1132, "((i>=1))"
+ line 257, "pan.___", state 1138, "(1)"
+ line 257, "pan.___", state 1139, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1139, "else"
+ line 261, "pan.___", state 1146, "(1)"
+ line 261, "pan.___", state 1147, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1147, "else"
+ line 266, "pan.___", state 1156, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1156, "else"
+ line 299, "pan.___", state 1158, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1158, "else"
+ line 1237, "pan.___", state 1161, "-end-"
+ (113 of 1161 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 933 seconds
+pan: rate 17076.039 states/second
+pan: avg transition delay 2.7284e-06 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define NO_MB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+#define NO_RMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 4907 States= 1e+06 Transitions= 2.54e+07 Memory= 550.432 t= 71.2 R= 1e+04
+Depth= 5133 States= 2e+06 Transitions= 5.13e+07 Memory= 634.318 t= 145 R= 1e+04
+Depth= 5133 States= 3e+06 Transitions= 7.76e+07 Memory= 718.303 t= 220 R= 1e+04
+pan: resizing hashtable to -w22.. done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5133, errors: 0
+ 3846927 states, stored
+ 96650452 states, matched
+1.0049738e+08 transitions (= stored+matched)
+1.6169296e+09 atomic steps
+hash conflicts: 68306904 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 425.571 equivalent memory usage for states (stored*(State-vector + overhead))
+ 330.939 actual memory usage for states (compression: 77.76%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 820.420 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 597, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 411, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 310, "(1)"
+ line 257, "pan.___", state 330, "(1)"
+ line 261, "pan.___", state 338, "(1)"
+ line 411, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 361, "(1)"
+ line 411, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 362, "else"
+ line 411, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 375, "(1)"
+ line 415, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 376, "else"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 413, "pan.___", state 385, "((i<1))"
+ line 413, "pan.___", state 385, "((i>=1))"
+ line 420, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 393, "(1)"
+ line 420, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 394, "else"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 424, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 407, "(1)"
+ line 424, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 408, "else"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 422, "pan.___", state 417, "((i<2))"
+ line 422, "pan.___", state 417, "((i>=2))"
+ line 249, "pan.___", state 423, "(1)"
+ line 253, "pan.___", state 431, "(1)"
+ line 253, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 432, "else"
+ line 251, "pan.___", state 437, "((i<1))"
+ line 251, "pan.___", state 437, "((i>=1))"
+ line 257, "pan.___", state 443, "(1)"
+ line 257, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 444, "else"
+ line 261, "pan.___", state 451, "(1)"
+ line 261, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 452, "else"
+ line 259, "pan.___", state 457, "((i<2))"
+ line 259, "pan.___", state 457, "((i>=2))"
+ line 266, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 461, "else"
+ line 431, "pan.___", state 463, "(1)"
+ line 431, "pan.___", state 463, "(1)"
+ line 597, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 468, "(1)"
+ line 272, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 483, "(1)"
+ line 280, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 519, "(1)"
+ line 253, "pan.___", state 527, "(1)"
+ line 257, "pan.___", state 539, "(1)"
+ line 261, "pan.___", state 547, "(1)"
+ line 411, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 629, "(1)"
+ line 253, "pan.___", state 637, "(1)"
+ line 257, "pan.___", state 649, "(1)"
+ line 261, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 747, "(1)"
+ line 257, "pan.___", state 767, "(1)"
+ line 261, "pan.___", state 775, "(1)"
+ line 411, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 796, "(1)"
+ line 411, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 797, "else"
+ line 411, "pan.___", state 800, "(1)"
+ line 415, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 810, "(1)"
+ line 415, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 811, "else"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 413, "pan.___", state 820, "((i<1))"
+ line 413, "pan.___", state 820, "((i>=1))"
+ line 420, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 828, "(1)"
+ line 420, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 829, "else"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 424, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 842, "(1)"
+ line 424, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 843, "else"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 422, "pan.___", state 852, "((i<2))"
+ line 422, "pan.___", state 852, "((i>=2))"
+ line 249, "pan.___", state 858, "(1)"
+ line 253, "pan.___", state 866, "(1)"
+ line 253, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 867, "else"
+ line 251, "pan.___", state 872, "((i<1))"
+ line 251, "pan.___", state 872, "((i>=1))"
+ line 257, "pan.___", state 878, "(1)"
+ line 257, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 879, "else"
+ line 261, "pan.___", state 886, "(1)"
+ line 261, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 887, "else"
+ line 259, "pan.___", state 892, "((i<2))"
+ line 259, "pan.___", state 892, "((i>=2))"
+ line 266, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 896, "else"
+ line 431, "pan.___", state 898, "(1)"
+ line 431, "pan.___", state 898, "(1)"
+ line 605, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 971, "(1)"
+ line 253, "pan.___", state 979, "(1)"
+ line 257, "pan.___", state 991, "(1)"
+ line 261, "pan.___", state 999, "(1)"
+ line 411, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1085, "(1)"
+ line 257, "pan.___", state 1105, "(1)"
+ line 261, "pan.___", state 1113, "(1)"
+ line 411, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1200, "(1)"
+ line 257, "pan.___", state 1220, "(1)"
+ line 261, "pan.___", state 1228, "(1)"
+ line 411, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1311, "(1)"
+ line 257, "pan.___", state 1331, "(1)"
+ line 261, "pan.___", state 1339, "(1)"
+ line 272, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1407, "(1)"
+ line 253, "pan.___", state 1415, "(1)"
+ line 257, "pan.___", state 1427, "(1)"
+ line 261, "pan.___", state 1435, "(1)"
+ line 411, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1517, "(1)"
+ line 253, "pan.___", state 1525, "(1)"
+ line 257, "pan.___", state 1537, "(1)"
+ line 261, "pan.___", state 1545, "(1)"
+ line 411, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1628, "(1)"
+ line 253, "pan.___", state 1636, "(1)"
+ line 257, "pan.___", state 1648, "(1)"
+ line 261, "pan.___", state 1656, "(1)"
+ line 411, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1742, "(1)"
+ line 257, "pan.___", state 1762, "(1)"
+ line 261, "pan.___", state 1770, "(1)"
+ line 644, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1860, "(1)"
+ line 257, "pan.___", state 1880, "(1)"
+ line 261, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1971, "(1)"
+ line 257, "pan.___", state 1991, "(1)"
+ line 261, "pan.___", state 1999, "(1)"
+ line 411, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2022, "(1)"
+ line 411, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2023, "else"
+ line 411, "pan.___", state 2026, "(1)"
+ line 415, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2036, "(1)"
+ line 415, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2037, "else"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 413, "pan.___", state 2046, "((i<1))"
+ line 413, "pan.___", state 2046, "((i>=1))"
+ line 420, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2054, "(1)"
+ line 420, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2055, "else"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 424, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2068, "(1)"
+ line 424, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2069, "else"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 422, "pan.___", state 2078, "((i<2))"
+ line 422, "pan.___", state 2078, "((i>=2))"
+ line 249, "pan.___", state 2084, "(1)"
+ line 253, "pan.___", state 2092, "(1)"
+ line 253, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2093, "else"
+ line 251, "pan.___", state 2098, "((i<1))"
+ line 251, "pan.___", state 2098, "((i>=1))"
+ line 257, "pan.___", state 2104, "(1)"
+ line 257, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2105, "else"
+ line 261, "pan.___", state 2112, "(1)"
+ line 261, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2113, "else"
+ line 259, "pan.___", state 2118, "((i<2))"
+ line 259, "pan.___", state 2118, "((i>=2))"
+ line 266, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2122, "else"
+ line 431, "pan.___", state 2124, "(1)"
+ line 431, "pan.___", state 2124, "(1)"
+ line 644, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2129, "(1)"
+ line 272, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2180, "(1)"
+ line 253, "pan.___", state 2188, "(1)"
+ line 257, "pan.___", state 2200, "(1)"
+ line 261, "pan.___", state 2208, "(1)"
+ line 411, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2290, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2310, "(1)"
+ line 261, "pan.___", state 2318, "(1)"
+ line 272, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2387, "(1)"
+ line 253, "pan.___", state 2395, "(1)"
+ line 257, "pan.___", state 2407, "(1)"
+ line 261, "pan.___", state 2415, "(1)"
+ line 411, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2497, "(1)"
+ line 253, "pan.___", state 2505, "(1)"
+ line 257, "pan.___", state 2517, "(1)"
+ line 261, "pan.___", state 2525, "(1)"
+ line 411, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2608, "(1)"
+ line 253, "pan.___", state 2616, "(1)"
+ line 257, "pan.___", state 2628, "(1)"
+ line 261, "pan.___", state 2636, "(1)"
+ line 411, "pan.___", state 2667, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2699, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2713, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2731, "(1)"
+ line 257, "pan.___", state 2751, "(1)"
+ line 261, "pan.___", state 2759, "(1)"
+ line 411, "pan.___", state 2776, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2790, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2808, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2822, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2840, "(1)"
+ line 253, "pan.___", state 2848, "(1)"
+ line 257, "pan.___", state 2860, "(1)"
+ line 261, "pan.___", state 2868, "(1)"
+ line 898, "pan.___", state 2887, "-end-"
+ (266 of 2887 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 82, "(1)"
+ line 253, "pan.___", state 90, "(1)"
+ line 257, "pan.___", state 102, "(1)"
+ line 272, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 257, "(1)"
+ line 253, "pan.___", state 265, "(1)"
+ line 257, "pan.___", state 277, "(1)"
+ line 261, "pan.___", state 285, "(1)"
+ line 415, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 378, "(1)"
+ line 257, "pan.___", state 390, "(1)"
+ line 261, "pan.___", state 398, "(1)"
+ line 415, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 499, "(1)"
+ line 257, "pan.___", state 511, "(1)"
+ line 261, "pan.___", state 519, "(1)"
+ line 415, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 610, "(1)"
+ line 257, "pan.___", state 622, "(1)"
+ line 261, "pan.___", state 630, "(1)"
+ line 415, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 723, "(1)"
+ line 257, "pan.___", state 735, "(1)"
+ line 261, "pan.___", state 743, "(1)"
+ line 272, "pan.___", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 820, "(1)"
+ line 284, "pan.___", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 843, "(1)"
+ line 253, "pan.___", state 851, "(1)"
+ line 257, "pan.___", state 863, "(1)"
+ line 261, "pan.___", state 871, "(1)"
+ line 276, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 909, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 918, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 934, "(1)"
+ line 253, "pan.___", state 942, "(1)"
+ line 257, "pan.___", state 954, "(1)"
+ line 261, "pan.___", state 962, "(1)"
+ line 276, "pan.___", state 987, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1000, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1009, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1025, "(1)"
+ line 253, "pan.___", state 1033, "(1)"
+ line 257, "pan.___", state 1045, "(1)"
+ line 261, "pan.___", state 1053, "(1)"
+ line 276, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1091, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1100, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1116, "(1)"
+ line 253, "pan.___", state 1124, "(1)"
+ line 257, "pan.___", state 1136, "(1)"
+ line 261, "pan.___", state 1144, "(1)"
+ line 1237, "pan.___", state 1159, "-end-"
+ (71 of 1159 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 285 seconds
+pan: rate 13484.269 states/second
+pan: avg transition delay 2.8388e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define NO_RMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define NO_WMB
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 4736 States= 1e+06 Transitions= 2.14e+07 Memory= 550.334 t= 59.2 R= 2e+04
+Depth= 4922 States= 2e+06 Transitions= 4.72e+07 Memory= 634.221 t= 132 R= 2e+04
+Depth= 4922 States= 3e+06 Transitions= 7.19e+07 Memory= 718.205 t= 203 R= 1e+04
+pan: resizing hashtable to -w22.. done
+pan: claim violated! (at depth 1295)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 4922, errors: 1
+ 3435201 states, stored
+ 77730101 states, matched
+ 81165302 transitions (= stored+matched)
+1.2953753e+09 atomic steps
+hash conflicts: 60833788 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 380.023 equivalent memory usage for states (stored*(State-vector + overhead))
+ 296.169 actual memory usage for states (compression: 77.93%)
+ state-vector as stored = 62 byte + 28 byte overhead
+ 32.000 memory used for hash table (-w22)
+ 457.764 memory used for DFS stack (-m10000000)
+ 785.752 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 597, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 411, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 310, "(1)"
+ line 257, "pan.___", state 330, "(1)"
+ line 261, "pan.___", state 338, "(1)"
+ line 411, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 361, "(1)"
+ line 411, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 362, "else"
+ line 411, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 375, "(1)"
+ line 415, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 376, "else"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 413, "pan.___", state 385, "((i<1))"
+ line 413, "pan.___", state 385, "((i>=1))"
+ line 420, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 393, "(1)"
+ line 420, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 394, "else"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 424, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 407, "(1)"
+ line 424, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 408, "else"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 422, "pan.___", state 417, "((i<2))"
+ line 422, "pan.___", state 417, "((i>=2))"
+ line 249, "pan.___", state 423, "(1)"
+ line 253, "pan.___", state 431, "(1)"
+ line 253, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 432, "else"
+ line 251, "pan.___", state 437, "((i<1))"
+ line 251, "pan.___", state 437, "((i>=1))"
+ line 257, "pan.___", state 443, "(1)"
+ line 257, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 444, "else"
+ line 261, "pan.___", state 451, "(1)"
+ line 261, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 452, "else"
+ line 259, "pan.___", state 457, "((i<2))"
+ line 259, "pan.___", state 457, "((i>=2))"
+ line 266, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 461, "else"
+ line 431, "pan.___", state 463, "(1)"
+ line 431, "pan.___", state 463, "(1)"
+ line 597, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 468, "(1)"
+ line 272, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 483, "(1)"
+ line 280, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 519, "(1)"
+ line 253, "pan.___", state 527, "(1)"
+ line 257, "pan.___", state 539, "(1)"
+ line 261, "pan.___", state 547, "(1)"
+ line 411, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 629, "(1)"
+ line 253, "pan.___", state 637, "(1)"
+ line 257, "pan.___", state 649, "(1)"
+ line 261, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 747, "(1)"
+ line 257, "pan.___", state 767, "(1)"
+ line 261, "pan.___", state 775, "(1)"
+ line 411, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 796, "(1)"
+ line 411, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 797, "else"
+ line 411, "pan.___", state 800, "(1)"
+ line 415, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 810, "(1)"
+ line 415, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 811, "else"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 413, "pan.___", state 820, "((i<1))"
+ line 413, "pan.___", state 820, "((i>=1))"
+ line 420, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 828, "(1)"
+ line 420, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 829, "else"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 424, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 842, "(1)"
+ line 424, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 843, "else"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 422, "pan.___", state 852, "((i<2))"
+ line 422, "pan.___", state 852, "((i>=2))"
+ line 249, "pan.___", state 858, "(1)"
+ line 253, "pan.___", state 866, "(1)"
+ line 253, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 867, "else"
+ line 251, "pan.___", state 872, "((i<1))"
+ line 251, "pan.___", state 872, "((i>=1))"
+ line 257, "pan.___", state 878, "(1)"
+ line 257, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 879, "else"
+ line 261, "pan.___", state 886, "(1)"
+ line 261, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 887, "else"
+ line 259, "pan.___", state 892, "((i<2))"
+ line 259, "pan.___", state 892, "((i>=2))"
+ line 266, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 896, "else"
+ line 431, "pan.___", state 898, "(1)"
+ line 431, "pan.___", state 898, "(1)"
+ line 605, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 971, "(1)"
+ line 253, "pan.___", state 979, "(1)"
+ line 257, "pan.___", state 991, "(1)"
+ line 261, "pan.___", state 999, "(1)"
+ line 411, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1085, "(1)"
+ line 257, "pan.___", state 1105, "(1)"
+ line 261, "pan.___", state 1113, "(1)"
+ line 411, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1200, "(1)"
+ line 257, "pan.___", state 1220, "(1)"
+ line 261, "pan.___", state 1228, "(1)"
+ line 411, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1311, "(1)"
+ line 257, "pan.___", state 1331, "(1)"
+ line 261, "pan.___", state 1339, "(1)"
+ line 272, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1407, "(1)"
+ line 253, "pan.___", state 1415, "(1)"
+ line 257, "pan.___", state 1427, "(1)"
+ line 261, "pan.___", state 1435, "(1)"
+ line 411, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1517, "(1)"
+ line 253, "pan.___", state 1525, "(1)"
+ line 257, "pan.___", state 1537, "(1)"
+ line 261, "pan.___", state 1545, "(1)"
+ line 411, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1628, "(1)"
+ line 253, "pan.___", state 1636, "(1)"
+ line 257, "pan.___", state 1648, "(1)"
+ line 261, "pan.___", state 1656, "(1)"
+ line 411, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1742, "(1)"
+ line 257, "pan.___", state 1762, "(1)"
+ line 261, "pan.___", state 1770, "(1)"
+ line 644, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1860, "(1)"
+ line 257, "pan.___", state 1880, "(1)"
+ line 261, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1971, "(1)"
+ line 257, "pan.___", state 1991, "(1)"
+ line 261, "pan.___", state 1999, "(1)"
+ line 411, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2022, "(1)"
+ line 411, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2023, "else"
+ line 411, "pan.___", state 2026, "(1)"
+ line 415, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2036, "(1)"
+ line 415, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2037, "else"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 413, "pan.___", state 2046, "((i<1))"
+ line 413, "pan.___", state 2046, "((i>=1))"
+ line 420, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2054, "(1)"
+ line 420, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2055, "else"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 424, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2068, "(1)"
+ line 424, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2069, "else"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 422, "pan.___", state 2078, "((i<2))"
+ line 422, "pan.___", state 2078, "((i>=2))"
+ line 249, "pan.___", state 2084, "(1)"
+ line 253, "pan.___", state 2092, "(1)"
+ line 253, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2093, "else"
+ line 251, "pan.___", state 2098, "((i<1))"
+ line 251, "pan.___", state 2098, "((i>=1))"
+ line 257, "pan.___", state 2104, "(1)"
+ line 257, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2105, "else"
+ line 261, "pan.___", state 2112, "(1)"
+ line 261, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2113, "else"
+ line 259, "pan.___", state 2118, "((i<2))"
+ line 259, "pan.___", state 2118, "((i>=2))"
+ line 266, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2122, "else"
+ line 431, "pan.___", state 2124, "(1)"
+ line 431, "pan.___", state 2124, "(1)"
+ line 644, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2129, "(1)"
+ line 272, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2180, "(1)"
+ line 253, "pan.___", state 2188, "(1)"
+ line 257, "pan.___", state 2200, "(1)"
+ line 261, "pan.___", state 2208, "(1)"
+ line 411, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2290, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2310, "(1)"
+ line 261, "pan.___", state 2318, "(1)"
+ line 272, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2387, "(1)"
+ line 253, "pan.___", state 2395, "(1)"
+ line 257, "pan.___", state 2407, "(1)"
+ line 261, "pan.___", state 2415, "(1)"
+ line 411, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2497, "(1)"
+ line 253, "pan.___", state 2505, "(1)"
+ line 257, "pan.___", state 2517, "(1)"
+ line 261, "pan.___", state 2525, "(1)"
+ line 411, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2608, "(1)"
+ line 253, "pan.___", state 2616, "(1)"
+ line 257, "pan.___", state 2628, "(1)"
+ line 261, "pan.___", state 2636, "(1)"
+ line 249, "pan.___", state 2667, "(1)"
+ line 257, "pan.___", state 2687, "(1)"
+ line 261, "pan.___", state 2695, "(1)"
+ line 249, "pan.___", state 2710, "(1)"
+ line 253, "pan.___", state 2718, "(1)"
+ line 257, "pan.___", state 2730, "(1)"
+ line 261, "pan.___", state 2738, "(1)"
+ line 898, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 19, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 33, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 83, "(1)"
+ line 253, "pan.___", state 91, "(1)"
+ line 272, "pan.___", state 132, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 134, "(1)"
+ line 276, "pan.___", state 141, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 143, "(1)"
+ line 276, "pan.___", state 144, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 144, "else"
+ line 274, "pan.___", state 149, "((i<1))"
+ line 274, "pan.___", state 149, "((i>=1))"
+ line 280, "pan.___", state 154, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 156, "(1)"
+ line 280, "pan.___", state 157, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 157, "else"
+ line 284, "pan.___", state 163, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 165, "(1)"
+ line 284, "pan.___", state 166, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 166, "else"
+ line 289, "pan.___", state 175, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 289, "pan.___", state 175, "else"
+ line 411, "pan.___", state 194, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 208, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 226, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 240, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 258, "(1)"
+ line 253, "pan.___", state 266, "(1)"
+ line 257, "pan.___", state 278, "(1)"
+ line 261, "pan.___", state 286, "(1)"
+ line 415, "pan.___", state 321, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 339, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 353, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 379, "(1)"
+ line 257, "pan.___", state 391, "(1)"
+ line 261, "pan.___", state 399, "(1)"
+ line 415, "pan.___", state 442, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 460, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 474, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 500, "(1)"
+ line 257, "pan.___", state 512, "(1)"
+ line 261, "pan.___", state 520, "(1)"
+ line 415, "pan.___", state 553, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 571, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 585, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 611, "(1)"
+ line 257, "pan.___", state 623, "(1)"
+ line 261, "pan.___", state 631, "(1)"
+ line 415, "pan.___", state 666, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 684, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 698, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 724, "(1)"
+ line 257, "pan.___", state 736, "(1)"
+ line 261, "pan.___", state 744, "(1)"
+ line 272, "pan.___", state 797, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 806, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 844, "(1)"
+ line 253, "pan.___", state 852, "(1)"
+ line 257, "pan.___", state 864, "(1)"
+ line 261, "pan.___", state 872, "(1)"
+ line 276, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 910, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 919, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 935, "(1)"
+ line 253, "pan.___", state 943, "(1)"
+ line 257, "pan.___", state 955, "(1)"
+ line 261, "pan.___", state 963, "(1)"
+ line 276, "pan.___", state 988, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1001, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1010, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1026, "(1)"
+ line 253, "pan.___", state 1034, "(1)"
+ line 257, "pan.___", state 1046, "(1)"
+ line 261, "pan.___", state 1054, "(1)"
+ line 276, "pan.___", state 1079, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1092, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1101, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1117, "(1)"
+ line 253, "pan.___", state 1125, "(1)"
+ line 257, "pan.___", state 1137, "(1)"
+ line 261, "pan.___", state 1145, "(1)"
+ line 1237, "pan.___", state 1160, "-end-"
+ (77 of 1160 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 229 seconds
+pan: rate 14976.68 states/second
+pan: avg transition delay 2.826e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define NO_WMB
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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+1291:1:1129
+1292:1:1130
+1293:0:3993
+1294:1:11
+1295:0:3999
+1296:1:2142
--- /dev/null
+#define SINGLE_FLIP
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+Depth= 5162 States= 1e+06 Transitions= 1.79e+07 Memory= 550.334 t= 49 R= 2e+04
+pan: claim violated! (at depth 1059)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness disabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 5162, errors: 1
+ 1708535 states, stored
+ 29763099 states, matched
+ 31471634 transitions (= stored+matched)
+4.8935629e+08 atomic steps
+hash conflicts: 14510834 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 189.009 equivalent memory usage for states (stored*(State-vector + overhead))
+ 144.122 actual memory usage for states (compression: 76.25%)
+ state-vector as stored = 60 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 609.807 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 597, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 411, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 310, "(1)"
+ line 257, "pan.___", state 330, "(1)"
+ line 261, "pan.___", state 338, "(1)"
+ line 411, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 361, "(1)"
+ line 411, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 362, "else"
+ line 411, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 375, "(1)"
+ line 415, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 376, "else"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 413, "pan.___", state 385, "((i<1))"
+ line 413, "pan.___", state 385, "((i>=1))"
+ line 420, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 393, "(1)"
+ line 420, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 394, "else"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 424, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 407, "(1)"
+ line 424, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 408, "else"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 422, "pan.___", state 417, "((i<2))"
+ line 422, "pan.___", state 417, "((i>=2))"
+ line 249, "pan.___", state 423, "(1)"
+ line 253, "pan.___", state 431, "(1)"
+ line 253, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 432, "else"
+ line 251, "pan.___", state 437, "((i<1))"
+ line 251, "pan.___", state 437, "((i>=1))"
+ line 257, "pan.___", state 443, "(1)"
+ line 257, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 444, "else"
+ line 261, "pan.___", state 451, "(1)"
+ line 261, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 452, "else"
+ line 259, "pan.___", state 457, "((i<2))"
+ line 259, "pan.___", state 457, "((i>=2))"
+ line 266, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 461, "else"
+ line 431, "pan.___", state 463, "(1)"
+ line 431, "pan.___", state 463, "(1)"
+ line 597, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 468, "(1)"
+ line 272, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 483, "(1)"
+ line 280, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 519, "(1)"
+ line 253, "pan.___", state 527, "(1)"
+ line 257, "pan.___", state 539, "(1)"
+ line 261, "pan.___", state 547, "(1)"
+ line 411, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 629, "(1)"
+ line 253, "pan.___", state 637, "(1)"
+ line 257, "pan.___", state 649, "(1)"
+ line 261, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 747, "(1)"
+ line 257, "pan.___", state 767, "(1)"
+ line 261, "pan.___", state 775, "(1)"
+ line 411, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 796, "(1)"
+ line 411, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 797, "else"
+ line 411, "pan.___", state 800, "(1)"
+ line 415, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 810, "(1)"
+ line 415, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 811, "else"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 413, "pan.___", state 820, "((i<1))"
+ line 413, "pan.___", state 820, "((i>=1))"
+ line 420, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 828, "(1)"
+ line 420, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 829, "else"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 424, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 842, "(1)"
+ line 424, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 843, "else"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 422, "pan.___", state 852, "((i<2))"
+ line 422, "pan.___", state 852, "((i>=2))"
+ line 249, "pan.___", state 858, "(1)"
+ line 253, "pan.___", state 866, "(1)"
+ line 253, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 867, "else"
+ line 251, "pan.___", state 872, "((i<1))"
+ line 251, "pan.___", state 872, "((i>=1))"
+ line 257, "pan.___", state 878, "(1)"
+ line 257, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 879, "else"
+ line 261, "pan.___", state 886, "(1)"
+ line 261, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 887, "else"
+ line 259, "pan.___", state 892, "((i<2))"
+ line 259, "pan.___", state 892, "((i>=2))"
+ line 266, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 896, "else"
+ line 431, "pan.___", state 898, "(1)"
+ line 431, "pan.___", state 898, "(1)"
+ line 605, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 971, "(1)"
+ line 253, "pan.___", state 979, "(1)"
+ line 257, "pan.___", state 991, "(1)"
+ line 261, "pan.___", state 999, "(1)"
+ line 411, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1085, "(1)"
+ line 257, "pan.___", state 1105, "(1)"
+ line 261, "pan.___", state 1113, "(1)"
+ line 411, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1200, "(1)"
+ line 257, "pan.___", state 1220, "(1)"
+ line 261, "pan.___", state 1228, "(1)"
+ line 411, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1311, "(1)"
+ line 257, "pan.___", state 1331, "(1)"
+ line 261, "pan.___", state 1339, "(1)"
+ line 272, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1407, "(1)"
+ line 253, "pan.___", state 1415, "(1)"
+ line 257, "pan.___", state 1427, "(1)"
+ line 261, "pan.___", state 1435, "(1)"
+ line 411, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1517, "(1)"
+ line 253, "pan.___", state 1525, "(1)"
+ line 257, "pan.___", state 1537, "(1)"
+ line 261, "pan.___", state 1545, "(1)"
+ line 411, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1628, "(1)"
+ line 253, "pan.___", state 1636, "(1)"
+ line 257, "pan.___", state 1648, "(1)"
+ line 261, "pan.___", state 1656, "(1)"
+ line 411, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1742, "(1)"
+ line 257, "pan.___", state 1762, "(1)"
+ line 261, "pan.___", state 1770, "(1)"
+ line 644, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1860, "(1)"
+ line 257, "pan.___", state 1880, "(1)"
+ line 261, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1971, "(1)"
+ line 257, "pan.___", state 1991, "(1)"
+ line 261, "pan.___", state 1999, "(1)"
+ line 411, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2022, "(1)"
+ line 411, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2023, "else"
+ line 411, "pan.___", state 2026, "(1)"
+ line 415, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2036, "(1)"
+ line 415, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2037, "else"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 413, "pan.___", state 2046, "((i<1))"
+ line 413, "pan.___", state 2046, "((i>=1))"
+ line 420, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2054, "(1)"
+ line 420, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2055, "else"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 424, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2068, "(1)"
+ line 424, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2069, "else"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 422, "pan.___", state 2078, "((i<2))"
+ line 422, "pan.___", state 2078, "((i>=2))"
+ line 249, "pan.___", state 2084, "(1)"
+ line 253, "pan.___", state 2092, "(1)"
+ line 253, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2093, "else"
+ line 251, "pan.___", state 2098, "((i<1))"
+ line 251, "pan.___", state 2098, "((i>=1))"
+ line 257, "pan.___", state 2104, "(1)"
+ line 257, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2105, "else"
+ line 261, "pan.___", state 2112, "(1)"
+ line 261, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2113, "else"
+ line 259, "pan.___", state 2118, "((i<2))"
+ line 259, "pan.___", state 2118, "((i>=2))"
+ line 266, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2122, "else"
+ line 431, "pan.___", state 2124, "(1)"
+ line 431, "pan.___", state 2124, "(1)"
+ line 644, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2129, "(1)"
+ line 272, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2180, "(1)"
+ line 253, "pan.___", state 2188, "(1)"
+ line 257, "pan.___", state 2200, "(1)"
+ line 261, "pan.___", state 2208, "(1)"
+ line 411, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2290, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2310, "(1)"
+ line 261, "pan.___", state 2318, "(1)"
+ line 272, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2387, "(1)"
+ line 253, "pan.___", state 2395, "(1)"
+ line 257, "pan.___", state 2407, "(1)"
+ line 261, "pan.___", state 2415, "(1)"
+ line 411, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2497, "(1)"
+ line 253, "pan.___", state 2505, "(1)"
+ line 257, "pan.___", state 2517, "(1)"
+ line 261, "pan.___", state 2525, "(1)"
+ line 411, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2608, "(1)"
+ line 253, "pan.___", state 2616, "(1)"
+ line 257, "pan.___", state 2628, "(1)"
+ line 261, "pan.___", state 2636, "(1)"
+ line 249, "pan.___", state 2667, "(1)"
+ line 257, "pan.___", state 2687, "(1)"
+ line 261, "pan.___", state 2695, "(1)"
+ line 249, "pan.___", state 2710, "(1)"
+ line 253, "pan.___", state 2718, "(1)"
+ line 257, "pan.___", state 2730, "(1)"
+ line 261, "pan.___", state 2738, "(1)"
+ line 898, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 22, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 36, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 54, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 86, "(1)"
+ line 253, "pan.___", state 94, "(1)"
+ line 257, "pan.___", state 106, "(1)"
+ line 272, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 144, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 157, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 211, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 229, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 243, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 261, "(1)"
+ line 253, "pan.___", state 269, "(1)"
+ line 257, "pan.___", state 281, "(1)"
+ line 261, "pan.___", state 289, "(1)"
+ line 415, "pan.___", state 324, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 342, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 356, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 382, "(1)"
+ line 257, "pan.___", state 394, "(1)"
+ line 261, "pan.___", state 402, "(1)"
+ line 411, "pan.___", state 430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 444, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 462, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 476, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 494, "(1)"
+ line 253, "pan.___", state 502, "(1)"
+ line 257, "pan.___", state 514, "(1)"
+ line 261, "pan.___", state 522, "(1)"
+ line 411, "pan.___", state 541, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 543, "(1)"
+ line 411, "pan.___", state 544, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 544, "else"
+ line 411, "pan.___", state 547, "(1)"
+ line 415, "pan.___", state 555, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 557, "(1)"
+ line 415, "pan.___", state 558, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 558, "else"
+ line 415, "pan.___", state 561, "(1)"
+ line 415, "pan.___", state 562, "(1)"
+ line 415, "pan.___", state 562, "(1)"
+ line 413, "pan.___", state 567, "((i<1))"
+ line 413, "pan.___", state 567, "((i>=1))"
+ line 420, "pan.___", state 573, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 575, "(1)"
+ line 420, "pan.___", state 576, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 576, "else"
+ line 420, "pan.___", state 579, "(1)"
+ line 420, "pan.___", state 580, "(1)"
+ line 420, "pan.___", state 580, "(1)"
+ line 424, "pan.___", state 587, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 589, "(1)"
+ line 424, "pan.___", state 590, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 590, "else"
+ line 424, "pan.___", state 593, "(1)"
+ line 424, "pan.___", state 594, "(1)"
+ line 424, "pan.___", state 594, "(1)"
+ line 422, "pan.___", state 599, "((i<2))"
+ line 422, "pan.___", state 599, "((i>=2))"
+ line 249, "pan.___", state 605, "(1)"
+ line 253, "pan.___", state 613, "(1)"
+ line 253, "pan.___", state 614, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 614, "else"
+ line 251, "pan.___", state 619, "((i<1))"
+ line 251, "pan.___", state 619, "((i>=1))"
+ line 257, "pan.___", state 625, "(1)"
+ line 257, "pan.___", state 626, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 626, "else"
+ line 261, "pan.___", state 633, "(1)"
+ line 261, "pan.___", state 634, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 634, "else"
+ line 259, "pan.___", state 639, "((i<2))"
+ line 259, "pan.___", state 639, "((i>=2))"
+ line 266, "pan.___", state 643, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 643, "else"
+ line 431, "pan.___", state 645, "(1)"
+ line 431, "pan.___", state 645, "(1)"
+ line 1117, "pan.___", state 649, "_proc_urcu_writer = (_proc_urcu_writer|(1<<10))"
+ line 411, "pan.___", state 654, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 656, "(1)"
+ line 411, "pan.___", state 657, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 657, "else"
+ line 411, "pan.___", state 660, "(1)"
+ line 415, "pan.___", state 668, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 670, "(1)"
+ line 415, "pan.___", state 671, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 671, "else"
+ line 415, "pan.___", state 674, "(1)"
+ line 415, "pan.___", state 675, "(1)"
+ line 415, "pan.___", state 675, "(1)"
+ line 413, "pan.___", state 680, "((i<1))"
+ line 413, "pan.___", state 680, "((i>=1))"
+ line 420, "pan.___", state 686, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 688, "(1)"
+ line 420, "pan.___", state 689, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 689, "else"
+ line 420, "pan.___", state 692, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 420, "pan.___", state 693, "(1)"
+ line 424, "pan.___", state 700, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 702, "(1)"
+ line 424, "pan.___", state 703, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 703, "else"
+ line 424, "pan.___", state 706, "(1)"
+ line 424, "pan.___", state 707, "(1)"
+ line 424, "pan.___", state 707, "(1)"
+ line 422, "pan.___", state 712, "((i<2))"
+ line 422, "pan.___", state 712, "((i>=2))"
+ line 249, "pan.___", state 718, "(1)"
+ line 253, "pan.___", state 726, "(1)"
+ line 253, "pan.___", state 727, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 727, "else"
+ line 251, "pan.___", state 732, "((i<1))"
+ line 251, "pan.___", state 732, "((i>=1))"
+ line 257, "pan.___", state 738, "(1)"
+ line 257, "pan.___", state 739, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 739, "else"
+ line 261, "pan.___", state 746, "(1)"
+ line 261, "pan.___", state 747, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 747, "else"
+ line 259, "pan.___", state 752, "((i<2))"
+ line 259, "pan.___", state 752, "((i>=2))"
+ line 266, "pan.___", state 756, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 756, "else"
+ line 431, "pan.___", state 758, "(1)"
+ line 431, "pan.___", state 758, "(1)"
+ line 1133, "pan.___", state 763, "_proc_urcu_writer = (_proc_urcu_writer|(1<<11))"
+ line 1128, "pan.___", state 764, "(((tmp2&((1<<7)-1))&&((tmp2^0)&(1<<7))))"
+ line 1128, "pan.___", state 764, "else"
+ line 1153, "pan.___", state 768, "_proc_urcu_writer = (_proc_urcu_writer&~(((1<<12)|(1<<11))))"
+ line 272, "pan.___", state 799, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 823, "(1)"
+ line 284, "pan.___", state 830, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 846, "(1)"
+ line 253, "pan.___", state 854, "(1)"
+ line 257, "pan.___", state 866, "(1)"
+ line 261, "pan.___", state 874, "(1)"
+ line 276, "pan.___", state 899, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 912, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 921, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 937, "(1)"
+ line 253, "pan.___", state 945, "(1)"
+ line 257, "pan.___", state 957, "(1)"
+ line 261, "pan.___", state 965, "(1)"
+ line 272, "pan.___", state 981, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 272, "pan.___", state 983, "(1)"
+ line 276, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 992, "(1)"
+ line 276, "pan.___", state 993, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 276, "pan.___", state 993, "else"
+ line 274, "pan.___", state 998, "((i<1))"
+ line 274, "pan.___", state 998, "((i>=1))"
+ line 280, "pan.___", state 1003, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1005, "(1)"
+ line 280, "pan.___", state 1006, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 280, "pan.___", state 1006, "else"
+ line 284, "pan.___", state 1012, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1014, "(1)"
+ line 284, "pan.___", state 1015, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 284, "pan.___", state 1015, "else"
+ line 282, "pan.___", state 1020, "((i<2))"
+ line 282, "pan.___", state 1020, "((i>=2))"
+ line 249, "pan.___", state 1028, "(1)"
+ line 253, "pan.___", state 1036, "(1)"
+ line 253, "pan.___", state 1037, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 1037, "else"
+ line 251, "pan.___", state 1042, "((i<1))"
+ line 251, "pan.___", state 1042, "((i>=1))"
+ line 257, "pan.___", state 1048, "(1)"
+ line 257, "pan.___", state 1049, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 1049, "else"
+ line 261, "pan.___", state 1056, "(1)"
+ line 261, "pan.___", state 1057, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 1057, "else"
+ line 266, "pan.___", state 1066, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 1066, "else"
+ line 299, "pan.___", state 1068, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 299, "pan.___", state 1068, "else"
+ line 276, "pan.___", state 1081, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1094, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1103, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1119, "(1)"
+ line 253, "pan.___", state 1127, "(1)"
+ line 257, "pan.___", state 1139, "(1)"
+ line 261, "pan.___", state 1147, "(1)"
+ line 1237, "pan.___", state 1162, "-end-"
+ (145 of 1162 states)
+unreached in proctype :init:
+ line 1248, "pan.___", state 9, "((j<2))"
+ line 1248, "pan.___", state 9, "((j>=2))"
+ line 1249, "pan.___", state 20, "((j<2))"
+ line 1249, "pan.___", state 20, "((j>=2))"
+ line 1254, "pan.___", state 33, "((j<2))"
+ line 1254, "pan.___", state 33, "((j>=2))"
+ line 1252, "pan.___", state 43, "((i<1))"
+ line 1252, "pan.___", state 43, "((i>=1))"
+ line 1262, "pan.___", state 54, "((j<2))"
+ line 1262, "pan.___", state 54, "((j>=2))"
+ line 1266, "pan.___", state 67, "((j<2))"
+ line 1266, "pan.___", state 67, "((j>=2))"
+ (6 of 78 states)
+unreached in proctype :never:
+ line 1300, "pan.___", state 8, "-end-"
+ (1 of 8 states)
+
+pan: elapsed time 86.8 seconds
+pan: rate 19690.388 states/second
+pan: avg transition delay 2.7571e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define SINGLE_FLIP
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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--- /dev/null
+([] <> !np_)
--- /dev/null
+#define READER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+depth 23: Claim reached state 9 (line 1300)
+depth 1053: Claim reached state 9 (line 1299)
+Depth= 6090 States= 1e+06 Transitions= 2.22e+07 Memory= 510.295 t= 64.5 R= 2e+04
+Depth= 6090 States= 2e+06 Transitions= 5.32e+07 Memory= 552.776 t= 157 R= 1e+04
+Depth= 6090 States= 3e+06 Transitions= 8.56e+07 Memory= 597.014 t= 253 R= 1e+04
+pan: resizing hashtable to -w22.. done
+Depth= 6090 States= 4e+06 Transitions= 1.18e+08 Memory= 672.764 t= 351 R= 1e+04
+Depth= 6090 States= 5e+06 Transitions= 1.49e+08 Memory= 716.416 t= 443 R= 1e+04
+Depth= 6090 States= 6e+06 Transitions= 1.79e+08 Memory= 760.459 t= 531 R= 1e+04
+Depth= 6090 States= 7e+06 Transitions= 2.11e+08 Memory= 804.990 t= 627 R= 1e+04
+Depth= 6090 States= 8e+06 Transitions= 2.44e+08 Memory= 848.057 t= 727 R= 1e+04
+Depth= 6090 States= 9e+06 Transitions= 2.77e+08 Memory= 891.807 t= 827 R= 1e+04
+pan: resizing hashtable to -w24.. done
+Depth= 6090 States= 1e+07 Transitions= 3.11e+08 Memory= 1062.385 t= 928 R= 1e+04
+Depth= 6090 States= 1.1e+07 Transitions= 3.41e+08 Memory= 1105.744 t= 1.02e+03 R= 1e+04
+Depth= 6090 States= 1.2e+07 Transitions= 3.7e+08 Memory= 1151.252 t= 1.1e+03 R= 1e+04
+Depth= 6090 States= 1.3e+07 Transitions= 4.06e+08 Memory= 1193.635 t= 1.21e+03 R= 1e+04
+Depth= 6090 States= 1.4e+07 Transitions= 4.4e+08 Memory= 1236.506 t= 1.31e+03 R= 1e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 6090, errors: 0
+ 7774591 states, stored (1.48046e+07 visited)
+4.51403e+08 states, matched
+4.6620756e+08 transitions (= visited+matched)
+7.4729019e+09 atomic steps
+hash conflicts: 1.6384912e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 860.074 equivalent memory usage for states (stored*(State-vector + overhead))
+ 689.043 actual memory usage for states (compression: 80.11%)
+ state-vector as stored = 65 byte + 28 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1274.299 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 597, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 411, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 310, "(1)"
+ line 257, "pan.___", state 330, "(1)"
+ line 261, "pan.___", state 338, "(1)"
+ line 411, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 361, "(1)"
+ line 411, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 362, "else"
+ line 411, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 375, "(1)"
+ line 415, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 376, "else"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 413, "pan.___", state 385, "((i<1))"
+ line 413, "pan.___", state 385, "((i>=1))"
+ line 420, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 393, "(1)"
+ line 420, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 394, "else"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 424, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 407, "(1)"
+ line 424, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 408, "else"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 422, "pan.___", state 417, "((i<2))"
+ line 422, "pan.___", state 417, "((i>=2))"
+ line 249, "pan.___", state 423, "(1)"
+ line 253, "pan.___", state 431, "(1)"
+ line 253, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 432, "else"
+ line 251, "pan.___", state 437, "((i<1))"
+ line 251, "pan.___", state 437, "((i>=1))"
+ line 257, "pan.___", state 443, "(1)"
+ line 257, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 444, "else"
+ line 261, "pan.___", state 451, "(1)"
+ line 261, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 452, "else"
+ line 259, "pan.___", state 457, "((i<2))"
+ line 259, "pan.___", state 457, "((i>=2))"
+ line 266, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 461, "else"
+ line 431, "pan.___", state 463, "(1)"
+ line 431, "pan.___", state 463, "(1)"
+ line 597, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 468, "(1)"
+ line 272, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 483, "(1)"
+ line 280, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 519, "(1)"
+ line 253, "pan.___", state 527, "(1)"
+ line 257, "pan.___", state 539, "(1)"
+ line 261, "pan.___", state 547, "(1)"
+ line 411, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 629, "(1)"
+ line 253, "pan.___", state 637, "(1)"
+ line 257, "pan.___", state 649, "(1)"
+ line 261, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 747, "(1)"
+ line 257, "pan.___", state 767, "(1)"
+ line 261, "pan.___", state 775, "(1)"
+ line 411, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 796, "(1)"
+ line 411, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 797, "else"
+ line 411, "pan.___", state 800, "(1)"
+ line 415, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 810, "(1)"
+ line 415, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 811, "else"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 413, "pan.___", state 820, "((i<1))"
+ line 413, "pan.___", state 820, "((i>=1))"
+ line 420, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 828, "(1)"
+ line 420, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 829, "else"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 424, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 842, "(1)"
+ line 424, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 843, "else"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 422, "pan.___", state 852, "((i<2))"
+ line 422, "pan.___", state 852, "((i>=2))"
+ line 249, "pan.___", state 858, "(1)"
+ line 253, "pan.___", state 866, "(1)"
+ line 253, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 867, "else"
+ line 251, "pan.___", state 872, "((i<1))"
+ line 251, "pan.___", state 872, "((i>=1))"
+ line 257, "pan.___", state 878, "(1)"
+ line 257, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 879, "else"
+ line 261, "pan.___", state 886, "(1)"
+ line 261, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 887, "else"
+ line 259, "pan.___", state 892, "((i<2))"
+ line 259, "pan.___", state 892, "((i>=2))"
+ line 266, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 896, "else"
+ line 431, "pan.___", state 898, "(1)"
+ line 431, "pan.___", state 898, "(1)"
+ line 605, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 971, "(1)"
+ line 253, "pan.___", state 979, "(1)"
+ line 257, "pan.___", state 991, "(1)"
+ line 261, "pan.___", state 999, "(1)"
+ line 411, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1085, "(1)"
+ line 257, "pan.___", state 1105, "(1)"
+ line 261, "pan.___", state 1113, "(1)"
+ line 411, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1200, "(1)"
+ line 257, "pan.___", state 1220, "(1)"
+ line 261, "pan.___", state 1228, "(1)"
+ line 411, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1311, "(1)"
+ line 257, "pan.___", state 1331, "(1)"
+ line 261, "pan.___", state 1339, "(1)"
+ line 272, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1407, "(1)"
+ line 253, "pan.___", state 1415, "(1)"
+ line 257, "pan.___", state 1427, "(1)"
+ line 261, "pan.___", state 1435, "(1)"
+ line 411, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1517, "(1)"
+ line 253, "pan.___", state 1525, "(1)"
+ line 257, "pan.___", state 1537, "(1)"
+ line 261, "pan.___", state 1545, "(1)"
+ line 411, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1628, "(1)"
+ line 253, "pan.___", state 1636, "(1)"
+ line 257, "pan.___", state 1648, "(1)"
+ line 261, "pan.___", state 1656, "(1)"
+ line 411, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1742, "(1)"
+ line 257, "pan.___", state 1762, "(1)"
+ line 261, "pan.___", state 1770, "(1)"
+ line 644, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1860, "(1)"
+ line 257, "pan.___", state 1880, "(1)"
+ line 261, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1971, "(1)"
+ line 257, "pan.___", state 1991, "(1)"
+ line 261, "pan.___", state 1999, "(1)"
+ line 411, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2022, "(1)"
+ line 411, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2023, "else"
+ line 411, "pan.___", state 2026, "(1)"
+ line 415, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2036, "(1)"
+ line 415, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2037, "else"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 413, "pan.___", state 2046, "((i<1))"
+ line 413, "pan.___", state 2046, "((i>=1))"
+ line 420, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2054, "(1)"
+ line 420, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2055, "else"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 424, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2068, "(1)"
+ line 424, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2069, "else"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 422, "pan.___", state 2078, "((i<2))"
+ line 422, "pan.___", state 2078, "((i>=2))"
+ line 249, "pan.___", state 2084, "(1)"
+ line 253, "pan.___", state 2092, "(1)"
+ line 253, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2093, "else"
+ line 251, "pan.___", state 2098, "((i<1))"
+ line 251, "pan.___", state 2098, "((i>=1))"
+ line 257, "pan.___", state 2104, "(1)"
+ line 257, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2105, "else"
+ line 261, "pan.___", state 2112, "(1)"
+ line 261, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2113, "else"
+ line 259, "pan.___", state 2118, "((i<2))"
+ line 259, "pan.___", state 2118, "((i>=2))"
+ line 266, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2122, "else"
+ line 431, "pan.___", state 2124, "(1)"
+ line 431, "pan.___", state 2124, "(1)"
+ line 644, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2129, "(1)"
+ line 272, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2180, "(1)"
+ line 253, "pan.___", state 2188, "(1)"
+ line 257, "pan.___", state 2200, "(1)"
+ line 261, "pan.___", state 2208, "(1)"
+ line 411, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2290, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2310, "(1)"
+ line 261, "pan.___", state 2318, "(1)"
+ line 272, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2387, "(1)"
+ line 253, "pan.___", state 2395, "(1)"
+ line 257, "pan.___", state 2407, "(1)"
+ line 261, "pan.___", state 2415, "(1)"
+ line 411, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2497, "(1)"
+ line 253, "pan.___", state 2505, "(1)"
+ line 257, "pan.___", state 2517, "(1)"
+ line 261, "pan.___", state 2525, "(1)"
+ line 411, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2608, "(1)"
+ line 253, "pan.___", state 2616, "(1)"
+ line 257, "pan.___", state 2628, "(1)"
+ line 261, "pan.___", state 2636, "(1)"
+ line 249, "pan.___", state 2667, "(1)"
+ line 257, "pan.___", state 2687, "(1)"
+ line 261, "pan.___", state 2695, "(1)"
+ line 249, "pan.___", state 2710, "(1)"
+ line 253, "pan.___", state 2718, "(1)"
+ line 257, "pan.___", state 2730, "(1)"
+ line 261, "pan.___", state 2738, "(1)"
+ line 898, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 82, "(1)"
+ line 253, "pan.___", state 90, "(1)"
+ line 257, "pan.___", state 102, "(1)"
+ line 272, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 257, "(1)"
+ line 253, "pan.___", state 265, "(1)"
+ line 257, "pan.___", state 277, "(1)"
+ line 261, "pan.___", state 285, "(1)"
+ line 415, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 378, "(1)"
+ line 257, "pan.___", state 390, "(1)"
+ line 261, "pan.___", state 398, "(1)"
+ line 415, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 499, "(1)"
+ line 257, "pan.___", state 511, "(1)"
+ line 261, "pan.___", state 519, "(1)"
+ line 415, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 610, "(1)"
+ line 257, "pan.___", state 622, "(1)"
+ line 261, "pan.___", state 630, "(1)"
+ line 415, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 723, "(1)"
+ line 257, "pan.___", state 735, "(1)"
+ line 261, "pan.___", state 743, "(1)"
+ line 272, "pan.___", state 791, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 800, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 813, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 838, "(1)"
+ line 253, "pan.___", state 846, "(1)"
+ line 257, "pan.___", state 858, "(1)"
+ line 261, "pan.___", state 866, "(1)"
+ line 272, "pan.___", state 886, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 895, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 910, "(1)"
+ line 284, "pan.___", state 917, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 933, "(1)"
+ line 253, "pan.___", state 941, "(1)"
+ line 257, "pan.___", state 953, "(1)"
+ line 261, "pan.___", state 961, "(1)"
+ line 276, "pan.___", state 986, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 999, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1008, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1024, "(1)"
+ line 253, "pan.___", state 1032, "(1)"
+ line 257, "pan.___", state 1044, "(1)"
+ line 261, "pan.___", state 1052, "(1)"
+ line 276, "pan.___", state 1077, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1090, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1099, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1115, "(1)"
+ line 253, "pan.___", state 1123, "(1)"
+ line 257, "pan.___", state 1135, "(1)"
+ line 261, "pan.___", state 1143, "(1)"
+ line 276, "pan.___", state 1168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1181, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1190, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1206, "(1)"
+ line 253, "pan.___", state 1214, "(1)"
+ line 257, "pan.___", state 1226, "(1)"
+ line 261, "pan.___", state 1234, "(1)"
+ line 1237, "pan.___", state 1249, "-end-"
+ (78 of 1249 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1302, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 1.39e+03 seconds
+pan: rate 10656.973 states/second
+pan: avg transition delay 2.9798e-06 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define READER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1295)
+depth 23: Claim reached state 9 (line 1300)
+depth 1404: Claim reached state 9 (line 1299)
+Depth= 4122 States= 1e+06 Transitions= 2.18e+07 Memory= 494.377 t= 63.1 R= 2e+04
+Depth= 4237 States= 2e+06 Transitions= 4.19e+07 Memory= 522.209 t= 122 R= 2e+04
+Depth= 4557 States= 3e+06 Transitions= 6.67e+07 Memory= 550.139 t= 195 R= 2e+04
+pan: resizing hashtable to -w22.. done
+Depth= 4762 States= 4e+06 Transitions= 9.06e+07 Memory= 609.190 t= 264 R= 2e+04
+Depth= 4793 States= 5e+06 Transitions= 1.25e+08 Memory= 666.709 t= 366 R= 1e+04
+Depth= 4793 States= 6e+06 Transitions= 1.62e+08 Memory= 713.877 t= 473 R= 1e+04
+Depth= 4980 States= 7e+06 Transitions= 1.97e+08 Memory= 760.752 t= 578 R= 1e+04
+Depth= 4980 States= 8e+06 Transitions= 2.29e+08 Memory= 809.190 t= 674 R= 1e+04
+Depth= 4980 States= 9e+06 Transitions= 2.66e+08 Memory= 862.803 t= 784 R= 1e+04
+pan: resizing hashtable to -w24.. done
+Depth= 4980 States= 1e+07 Transitions= 2.98e+08 Memory= 1029.377 t= 880 R= 1e+04
+Depth= 4980 States= 1.1e+07 Transitions= 3.34e+08 Memory= 1080.061 t= 987 R= 1e+04
+Depth= 4980 States= 1.2e+07 Transitions= 3.69e+08 Memory= 1129.279 t= 1.09e+03 R= 1e+04
+Depth= 4980 States= 1.3e+07 Transitions= 4.01e+08 Memory= 1177.912 t= 1.18e+03 R= 1e+04
+Depth= 4980 States= 1.4e+07 Transitions= 4.4e+08 Memory= 1226.447 t= 1.3e+03 R= 1e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 4980, errors: 0
+ 7808338 states, stored (1.48869e+07 visited)
+4.5734827e+08 states, matched
+4.7223515e+08 transitions (= visited+matched)
+7.5648218e+09 atomic steps
+hash conflicts: 1.2909926e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 863.807 equivalent memory usage for states (stored*(State-vector + overhead))
+ 691.866 actual memory usage for states (compression: 80.09%)
+ state-vector as stored = 65 byte + 28 byte overhead
+ 128.000 memory used for hash table (-w24)
+ 457.764 memory used for DFS stack (-m10000000)
+ 1277.131 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 411, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 81, "(1)"
+ line 257, "pan.___", state 101, "(1)"
+ line 261, "pan.___", state 109, "(1)"
+ line 597, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 411, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 199, "(1)"
+ line 257, "pan.___", state 219, "(1)"
+ line 261, "pan.___", state 227, "(1)"
+ line 411, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 310, "(1)"
+ line 257, "pan.___", state 330, "(1)"
+ line 261, "pan.___", state 338, "(1)"
+ line 411, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 361, "(1)"
+ line 411, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 362, "else"
+ line 411, "pan.___", state 365, "(1)"
+ line 415, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 375, "(1)"
+ line 415, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 376, "else"
+ line 415, "pan.___", state 379, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 415, "pan.___", state 380, "(1)"
+ line 413, "pan.___", state 385, "((i<1))"
+ line 413, "pan.___", state 385, "((i>=1))"
+ line 420, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 393, "(1)"
+ line 420, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 394, "else"
+ line 420, "pan.___", state 397, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 420, "pan.___", state 398, "(1)"
+ line 424, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 407, "(1)"
+ line 424, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 408, "else"
+ line 424, "pan.___", state 411, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 424, "pan.___", state 412, "(1)"
+ line 422, "pan.___", state 417, "((i<2))"
+ line 422, "pan.___", state 417, "((i>=2))"
+ line 249, "pan.___", state 423, "(1)"
+ line 253, "pan.___", state 431, "(1)"
+ line 253, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 432, "else"
+ line 251, "pan.___", state 437, "((i<1))"
+ line 251, "pan.___", state 437, "((i>=1))"
+ line 257, "pan.___", state 443, "(1)"
+ line 257, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 444, "else"
+ line 261, "pan.___", state 451, "(1)"
+ line 261, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 452, "else"
+ line 259, "pan.___", state 457, "((i<2))"
+ line 259, "pan.___", state 457, "((i>=2))"
+ line 266, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 461, "else"
+ line 431, "pan.___", state 463, "(1)"
+ line 431, "pan.___", state 463, "(1)"
+ line 597, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 597, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 597, "pan.___", state 468, "(1)"
+ line 272, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 483, "(1)"
+ line 280, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 519, "(1)"
+ line 253, "pan.___", state 527, "(1)"
+ line 257, "pan.___", state 539, "(1)"
+ line 261, "pan.___", state 547, "(1)"
+ line 411, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 629, "(1)"
+ line 253, "pan.___", state 637, "(1)"
+ line 257, "pan.___", state 649, "(1)"
+ line 261, "pan.___", state 657, "(1)"
+ line 411, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 747, "(1)"
+ line 257, "pan.___", state 767, "(1)"
+ line 261, "pan.___", state 775, "(1)"
+ line 411, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 796, "(1)"
+ line 411, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 797, "else"
+ line 411, "pan.___", state 800, "(1)"
+ line 415, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 810, "(1)"
+ line 415, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 811, "else"
+ line 415, "pan.___", state 814, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 415, "pan.___", state 815, "(1)"
+ line 413, "pan.___", state 820, "((i<1))"
+ line 413, "pan.___", state 820, "((i>=1))"
+ line 420, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 828, "(1)"
+ line 420, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 829, "else"
+ line 420, "pan.___", state 832, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 420, "pan.___", state 833, "(1)"
+ line 424, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 842, "(1)"
+ line 424, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 843, "else"
+ line 424, "pan.___", state 846, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 424, "pan.___", state 847, "(1)"
+ line 422, "pan.___", state 852, "((i<2))"
+ line 422, "pan.___", state 852, "((i>=2))"
+ line 249, "pan.___", state 858, "(1)"
+ line 253, "pan.___", state 866, "(1)"
+ line 253, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 867, "else"
+ line 251, "pan.___", state 872, "((i<1))"
+ line 251, "pan.___", state 872, "((i>=1))"
+ line 257, "pan.___", state 878, "(1)"
+ line 257, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 879, "else"
+ line 261, "pan.___", state 886, "(1)"
+ line 261, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 887, "else"
+ line 259, "pan.___", state 892, "((i<2))"
+ line 259, "pan.___", state 892, "((i>=2))"
+ line 266, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 896, "else"
+ line 431, "pan.___", state 898, "(1)"
+ line 431, "pan.___", state 898, "(1)"
+ line 605, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 411, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 971, "(1)"
+ line 253, "pan.___", state 979, "(1)"
+ line 257, "pan.___", state 991, "(1)"
+ line 261, "pan.___", state 999, "(1)"
+ line 411, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1085, "(1)"
+ line 257, "pan.___", state 1105, "(1)"
+ line 261, "pan.___", state 1113, "(1)"
+ line 411, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1200, "(1)"
+ line 257, "pan.___", state 1220, "(1)"
+ line 261, "pan.___", state 1228, "(1)"
+ line 411, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1311, "(1)"
+ line 257, "pan.___", state 1331, "(1)"
+ line 261, "pan.___", state 1339, "(1)"
+ line 272, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1407, "(1)"
+ line 253, "pan.___", state 1415, "(1)"
+ line 257, "pan.___", state 1427, "(1)"
+ line 261, "pan.___", state 1435, "(1)"
+ line 411, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1517, "(1)"
+ line 253, "pan.___", state 1525, "(1)"
+ line 257, "pan.___", state 1537, "(1)"
+ line 261, "pan.___", state 1545, "(1)"
+ line 411, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1628, "(1)"
+ line 253, "pan.___", state 1636, "(1)"
+ line 257, "pan.___", state 1648, "(1)"
+ line 261, "pan.___", state 1656, "(1)"
+ line 411, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1742, "(1)"
+ line 257, "pan.___", state 1762, "(1)"
+ line 261, "pan.___", state 1770, "(1)"
+ line 644, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 411, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1860, "(1)"
+ line 257, "pan.___", state 1880, "(1)"
+ line 261, "pan.___", state 1888, "(1)"
+ line 411, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1971, "(1)"
+ line 257, "pan.___", state 1991, "(1)"
+ line 261, "pan.___", state 1999, "(1)"
+ line 411, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 2022, "(1)"
+ line 411, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 411, "pan.___", state 2023, "else"
+ line 411, "pan.___", state 2026, "(1)"
+ line 415, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2036, "(1)"
+ line 415, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 415, "pan.___", state 2037, "else"
+ line 415, "pan.___", state 2040, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 415, "pan.___", state 2041, "(1)"
+ line 413, "pan.___", state 2046, "((i<1))"
+ line 413, "pan.___", state 2046, "((i>=1))"
+ line 420, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2054, "(1)"
+ line 420, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 420, "pan.___", state 2055, "else"
+ line 420, "pan.___", state 2058, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 420, "pan.___", state 2059, "(1)"
+ line 424, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2068, "(1)"
+ line 424, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 424, "pan.___", state 2069, "else"
+ line 424, "pan.___", state 2072, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 424, "pan.___", state 2073, "(1)"
+ line 422, "pan.___", state 2078, "((i<2))"
+ line 422, "pan.___", state 2078, "((i>=2))"
+ line 249, "pan.___", state 2084, "(1)"
+ line 253, "pan.___", state 2092, "(1)"
+ line 253, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 253, "pan.___", state 2093, "else"
+ line 251, "pan.___", state 2098, "((i<1))"
+ line 251, "pan.___", state 2098, "((i>=1))"
+ line 257, "pan.___", state 2104, "(1)"
+ line 257, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 257, "pan.___", state 2105, "else"
+ line 261, "pan.___", state 2112, "(1)"
+ line 261, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 261, "pan.___", state 2113, "else"
+ line 259, "pan.___", state 2118, "((i<2))"
+ line 259, "pan.___", state 2118, "((i>=2))"
+ line 266, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 266, "pan.___", state 2122, "else"
+ line 431, "pan.___", state 2124, "(1)"
+ line 431, "pan.___", state 2124, "(1)"
+ line 644, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 644, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 644, "pan.___", state 2129, "(1)"
+ line 272, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2180, "(1)"
+ line 253, "pan.___", state 2188, "(1)"
+ line 257, "pan.___", state 2200, "(1)"
+ line 261, "pan.___", state 2208, "(1)"
+ line 411, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2290, "(1)"
+ line 253, "pan.___", state 2298, "(1)"
+ line 257, "pan.___", state 2310, "(1)"
+ line 261, "pan.___", state 2318, "(1)"
+ line 272, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2387, "(1)"
+ line 253, "pan.___", state 2395, "(1)"
+ line 257, "pan.___", state 2407, "(1)"
+ line 261, "pan.___", state 2415, "(1)"
+ line 411, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2497, "(1)"
+ line 253, "pan.___", state 2505, "(1)"
+ line 257, "pan.___", state 2517, "(1)"
+ line 261, "pan.___", state 2525, "(1)"
+ line 411, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 2608, "(1)"
+ line 253, "pan.___", state 2616, "(1)"
+ line 257, "pan.___", state 2628, "(1)"
+ line 261, "pan.___", state 2636, "(1)"
+ line 249, "pan.___", state 2667, "(1)"
+ line 257, "pan.___", state 2687, "(1)"
+ line 261, "pan.___", state 2695, "(1)"
+ line 249, "pan.___", state 2710, "(1)"
+ line 253, "pan.___", state 2718, "(1)"
+ line 257, "pan.___", state 2730, "(1)"
+ line 261, "pan.___", state 2738, "(1)"
+ line 898, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 411, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 82, "(1)"
+ line 253, "pan.___", state 90, "(1)"
+ line 257, "pan.___", state 102, "(1)"
+ line 272, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 411, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 415, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 257, "(1)"
+ line 253, "pan.___", state 265, "(1)"
+ line 257, "pan.___", state 277, "(1)"
+ line 261, "pan.___", state 285, "(1)"
+ line 415, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 378, "(1)"
+ line 257, "pan.___", state 390, "(1)"
+ line 261, "pan.___", state 398, "(1)"
+ line 415, "pan.___", state 441, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 459, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 473, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 499, "(1)"
+ line 257, "pan.___", state 511, "(1)"
+ line 261, "pan.___", state 519, "(1)"
+ line 415, "pan.___", state 552, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 570, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 584, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 610, "(1)"
+ line 257, "pan.___", state 622, "(1)"
+ line 261, "pan.___", state 630, "(1)"
+ line 415, "pan.___", state 665, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 420, "pan.___", state 683, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 424, "pan.___", state 697, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 253, "pan.___", state 723, "(1)"
+ line 257, "pan.___", state 735, "(1)"
+ line 261, "pan.___", state 743, "(1)"
+ line 272, "pan.___", state 796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 276, "pan.___", state 805, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 820, "(1)"
+ line 284, "pan.___", state 827, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 843, "(1)"
+ line 253, "pan.___", state 851, "(1)"
+ line 257, "pan.___", state 863, "(1)"
+ line 261, "pan.___", state 871, "(1)"
+ line 276, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 909, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 918, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 934, "(1)"
+ line 253, "pan.___", state 942, "(1)"
+ line 257, "pan.___", state 954, "(1)"
+ line 261, "pan.___", state 962, "(1)"
+ line 276, "pan.___", state 987, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1000, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1009, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1025, "(1)"
+ line 253, "pan.___", state 1033, "(1)"
+ line 257, "pan.___", state 1045, "(1)"
+ line 261, "pan.___", state 1053, "(1)"
+ line 276, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 280, "pan.___", state 1091, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 284, "pan.___", state 1100, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 249, "pan.___", state 1116, "(1)"
+ line 253, "pan.___", state 1124, "(1)"
+ line 257, "pan.___", state 1136, "(1)"
+ line 261, "pan.___", state 1144, "(1)"
+ line 1237, "pan.___", state 1159, "-end-"
+ (71 of 1159 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1302, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 1.4e+03 seconds
+pan: rate 10667.087 states/second
+pan: avg transition delay 2.9553e-06 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
--- /dev/null
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 1296)
+depth 23: Claim reached state 9 (line 1301)
+depth 1404: Claim reached state 9 (line 1300)
+pan: acceptance cycle (at depth 1950)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+ + Partial Order Reduction
+
+Full statespace search for:
+ never claim +
+ assertion violations + (if within scope of claim)
+ acceptance cycles + (fairness enabled)
+ invalid end states - (disabled by never claim)
+
+State-vector 88 byte, depth reached 4997, errors: 1
+ 64372 states, stored (197067 visited)
+ 2733089 states, matched
+ 2930156 transitions (= visited+matched)
+ 44244571 atomic steps
+hash conflicts: 43483 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7.121 equivalent memory usage for states (stored*(State-vector + overhead))
+ 6.154 actual memory usage for states (compression: 86.41%)
+ state-vector as stored = 72 byte + 28 byte overhead
+ 8.000 memory used for hash table (-w20)
+ 457.764 memory used for DFS stack (-m10000000)
+ 471.818 total actual memory usage
+
+unreached in proctype urcu_reader
+ line 412, "pan.___", state 17, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 49, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 63, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 81, "(1)"
+ line 258, "pan.___", state 101, "(1)"
+ line 262, "pan.___", state 109, "(1)"
+ line 598, "pan.___", state 128, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<1))"
+ line 412, "pan.___", state 135, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 167, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 181, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 199, "(1)"
+ line 258, "pan.___", state 219, "(1)"
+ line 262, "pan.___", state 227, "(1)"
+ line 412, "pan.___", state 246, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 278, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 292, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 310, "(1)"
+ line 258, "pan.___", state 330, "(1)"
+ line 262, "pan.___", state 338, "(1)"
+ line 412, "pan.___", state 359, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 361, "(1)"
+ line 412, "pan.___", state 362, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 362, "else"
+ line 412, "pan.___", state 365, "(1)"
+ line 416, "pan.___", state 373, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 375, "(1)"
+ line 416, "pan.___", state 376, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 376, "else"
+ line 416, "pan.___", state 379, "(1)"
+ line 416, "pan.___", state 380, "(1)"
+ line 416, "pan.___", state 380, "(1)"
+ line 414, "pan.___", state 385, "((i<1))"
+ line 414, "pan.___", state 385, "((i>=1))"
+ line 421, "pan.___", state 391, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 393, "(1)"
+ line 421, "pan.___", state 394, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 394, "else"
+ line 421, "pan.___", state 397, "(1)"
+ line 421, "pan.___", state 398, "(1)"
+ line 421, "pan.___", state 398, "(1)"
+ line 425, "pan.___", state 405, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 407, "(1)"
+ line 425, "pan.___", state 408, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 408, "else"
+ line 425, "pan.___", state 411, "(1)"
+ line 425, "pan.___", state 412, "(1)"
+ line 425, "pan.___", state 412, "(1)"
+ line 423, "pan.___", state 417, "((i<2))"
+ line 423, "pan.___", state 417, "((i>=2))"
+ line 250, "pan.___", state 423, "(1)"
+ line 254, "pan.___", state 431, "(1)"
+ line 254, "pan.___", state 432, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 432, "else"
+ line 252, "pan.___", state 437, "((i<1))"
+ line 252, "pan.___", state 437, "((i>=1))"
+ line 258, "pan.___", state 443, "(1)"
+ line 258, "pan.___", state 444, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 444, "else"
+ line 262, "pan.___", state 451, "(1)"
+ line 262, "pan.___", state 452, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 452, "else"
+ line 260, "pan.___", state 457, "((i<2))"
+ line 260, "pan.___", state 457, "((i>=2))"
+ line 267, "pan.___", state 461, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 461, "else"
+ line 432, "pan.___", state 463, "(1)"
+ line 432, "pan.___", state 463, "(1)"
+ line 598, "pan.___", state 466, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 598, "pan.___", state 467, "_proc_urcu_reader = (_proc_urcu_reader|(1<<5))"
+ line 598, "pan.___", state 468, "(1)"
+ line 273, "pan.___", state 472, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 483, "(1)"
+ line 281, "pan.___", state 494, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 503, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 519, "(1)"
+ line 254, "pan.___", state 527, "(1)"
+ line 258, "pan.___", state 539, "(1)"
+ line 262, "pan.___", state 547, "(1)"
+ line 412, "pan.___", state 565, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 579, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 597, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 611, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 629, "(1)"
+ line 254, "pan.___", state 637, "(1)"
+ line 258, "pan.___", state 649, "(1)"
+ line 262, "pan.___", state 657, "(1)"
+ line 412, "pan.___", state 683, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 715, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 729, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 747, "(1)"
+ line 258, "pan.___", state 767, "(1)"
+ line 262, "pan.___", state 775, "(1)"
+ line 412, "pan.___", state 794, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 796, "(1)"
+ line 412, "pan.___", state 797, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 797, "else"
+ line 412, "pan.___", state 800, "(1)"
+ line 416, "pan.___", state 808, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 810, "(1)"
+ line 416, "pan.___", state 811, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 811, "else"
+ line 416, "pan.___", state 814, "(1)"
+ line 416, "pan.___", state 815, "(1)"
+ line 416, "pan.___", state 815, "(1)"
+ line 414, "pan.___", state 820, "((i<1))"
+ line 414, "pan.___", state 820, "((i>=1))"
+ line 421, "pan.___", state 826, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 828, "(1)"
+ line 421, "pan.___", state 829, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 829, "else"
+ line 421, "pan.___", state 832, "(1)"
+ line 421, "pan.___", state 833, "(1)"
+ line 421, "pan.___", state 833, "(1)"
+ line 425, "pan.___", state 840, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 842, "(1)"
+ line 425, "pan.___", state 843, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 843, "else"
+ line 425, "pan.___", state 846, "(1)"
+ line 425, "pan.___", state 847, "(1)"
+ line 425, "pan.___", state 847, "(1)"
+ line 423, "pan.___", state 852, "((i<2))"
+ line 423, "pan.___", state 852, "((i>=2))"
+ line 250, "pan.___", state 858, "(1)"
+ line 254, "pan.___", state 866, "(1)"
+ line 254, "pan.___", state 867, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 867, "else"
+ line 252, "pan.___", state 872, "((i<1))"
+ line 252, "pan.___", state 872, "((i>=1))"
+ line 258, "pan.___", state 878, "(1)"
+ line 258, "pan.___", state 879, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 879, "else"
+ line 262, "pan.___", state 886, "(1)"
+ line 262, "pan.___", state 887, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 887, "else"
+ line 260, "pan.___", state 892, "((i<2))"
+ line 260, "pan.___", state 892, "((i>=2))"
+ line 267, "pan.___", state 896, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 896, "else"
+ line 432, "pan.___", state 898, "(1)"
+ line 432, "pan.___", state 898, "(1)"
+ line 606, "pan.___", state 902, "_proc_urcu_reader = (_proc_urcu_reader|(1<<11))"
+ line 412, "pan.___", state 907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 921, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 971, "(1)"
+ line 254, "pan.___", state 979, "(1)"
+ line 258, "pan.___", state 991, "(1)"
+ line 262, "pan.___", state 999, "(1)"
+ line 412, "pan.___", state 1021, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1053, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1067, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1085, "(1)"
+ line 258, "pan.___", state 1105, "(1)"
+ line 262, "pan.___", state 1113, "(1)"
+ line 412, "pan.___", state 1136, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1168, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1182, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1200, "(1)"
+ line 258, "pan.___", state 1220, "(1)"
+ line 262, "pan.___", state 1228, "(1)"
+ line 412, "pan.___", state 1247, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1279, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1293, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1311, "(1)"
+ line 258, "pan.___", state 1331, "(1)"
+ line 262, "pan.___", state 1339, "(1)"
+ line 273, "pan.___", state 1360, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 1382, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 1391, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1407, "(1)"
+ line 254, "pan.___", state 1415, "(1)"
+ line 258, "pan.___", state 1427, "(1)"
+ line 262, "pan.___", state 1435, "(1)"
+ line 412, "pan.___", state 1453, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1467, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1485, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1499, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1517, "(1)"
+ line 254, "pan.___", state 1525, "(1)"
+ line 258, "pan.___", state 1537, "(1)"
+ line 262, "pan.___", state 1545, "(1)"
+ line 412, "pan.___", state 1564, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1596, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1610, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1628, "(1)"
+ line 254, "pan.___", state 1636, "(1)"
+ line 258, "pan.___", state 1648, "(1)"
+ line 262, "pan.___", state 1656, "(1)"
+ line 412, "pan.___", state 1678, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1710, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1724, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1742, "(1)"
+ line 258, "pan.___", state 1762, "(1)"
+ line 262, "pan.___", state 1770, "(1)"
+ line 645, "pan.___", state 1789, "_proc_urcu_reader = (_proc_urcu_reader|((1<<2)<<19))"
+ line 412, "pan.___", state 1796, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1828, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1842, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1860, "(1)"
+ line 258, "pan.___", state 1880, "(1)"
+ line 262, "pan.___", state 1888, "(1)"
+ line 412, "pan.___", state 1907, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 1939, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 1953, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1971, "(1)"
+ line 258, "pan.___", state 1991, "(1)"
+ line 262, "pan.___", state 1999, "(1)"
+ line 412, "pan.___", state 2020, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 2022, "(1)"
+ line 412, "pan.___", state 2023, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 2023, "else"
+ line 412, "pan.___", state 2026, "(1)"
+ line 416, "pan.___", state 2034, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2036, "(1)"
+ line 416, "pan.___", state 2037, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 2037, "else"
+ line 416, "pan.___", state 2040, "(1)"
+ line 416, "pan.___", state 2041, "(1)"
+ line 416, "pan.___", state 2041, "(1)"
+ line 414, "pan.___", state 2046, "((i<1))"
+ line 414, "pan.___", state 2046, "((i>=1))"
+ line 421, "pan.___", state 2052, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2054, "(1)"
+ line 421, "pan.___", state 2055, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 2055, "else"
+ line 421, "pan.___", state 2058, "(1)"
+ line 421, "pan.___", state 2059, "(1)"
+ line 421, "pan.___", state 2059, "(1)"
+ line 425, "pan.___", state 2066, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2068, "(1)"
+ line 425, "pan.___", state 2069, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 2069, "else"
+ line 425, "pan.___", state 2072, "(1)"
+ line 425, "pan.___", state 2073, "(1)"
+ line 425, "pan.___", state 2073, "(1)"
+ line 423, "pan.___", state 2078, "((i<2))"
+ line 423, "pan.___", state 2078, "((i>=2))"
+ line 250, "pan.___", state 2084, "(1)"
+ line 254, "pan.___", state 2092, "(1)"
+ line 254, "pan.___", state 2093, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 2093, "else"
+ line 252, "pan.___", state 2098, "((i<1))"
+ line 252, "pan.___", state 2098, "((i>=1))"
+ line 258, "pan.___", state 2104, "(1)"
+ line 258, "pan.___", state 2105, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 2105, "else"
+ line 262, "pan.___", state 2112, "(1)"
+ line 262, "pan.___", state 2113, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 2113, "else"
+ line 260, "pan.___", state 2118, "((i<2))"
+ line 260, "pan.___", state 2118, "((i>=2))"
+ line 267, "pan.___", state 2122, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 2122, "else"
+ line 432, "pan.___", state 2124, "(1)"
+ line 432, "pan.___", state 2124, "(1)"
+ line 645, "pan.___", state 2127, "cached_urcu_active_readers.val[_pid] = (tmp+1)"
+ line 645, "pan.___", state 2128, "_proc_urcu_reader = (_proc_urcu_reader|(1<<23))"
+ line 645, "pan.___", state 2129, "(1)"
+ line 273, "pan.___", state 2133, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 2155, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 2164, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2180, "(1)"
+ line 254, "pan.___", state 2188, "(1)"
+ line 258, "pan.___", state 2200, "(1)"
+ line 262, "pan.___", state 2208, "(1)"
+ line 412, "pan.___", state 2226, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2240, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2258, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2272, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2290, "(1)"
+ line 254, "pan.___", state 2298, "(1)"
+ line 258, "pan.___", state 2310, "(1)"
+ line 262, "pan.___", state 2318, "(1)"
+ line 273, "pan.___", state 2340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 2349, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 2362, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 2371, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2387, "(1)"
+ line 254, "pan.___", state 2395, "(1)"
+ line 258, "pan.___", state 2407, "(1)"
+ line 262, "pan.___", state 2415, "(1)"
+ line 412, "pan.___", state 2433, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2447, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2465, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2479, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2497, "(1)"
+ line 254, "pan.___", state 2505, "(1)"
+ line 258, "pan.___", state 2517, "(1)"
+ line 262, "pan.___", state 2525, "(1)"
+ line 412, "pan.___", state 2544, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 2558, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 2576, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 2590, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 2608, "(1)"
+ line 254, "pan.___", state 2616, "(1)"
+ line 258, "pan.___", state 2628, "(1)"
+ line 262, "pan.___", state 2636, "(1)"
+ line 250, "pan.___", state 2667, "(1)"
+ line 258, "pan.___", state 2687, "(1)"
+ line 262, "pan.___", state 2695, "(1)"
+ line 250, "pan.___", state 2710, "(1)"
+ line 254, "pan.___", state 2718, "(1)"
+ line 258, "pan.___", state 2730, "(1)"
+ line 262, "pan.___", state 2738, "(1)"
+ line 899, "pan.___", state 2755, "-end-"
+ (259 of 2755 states)
+unreached in proctype urcu_writer
+ line 412, "pan.___", state 18, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 24, "(1)"
+ line 416, "pan.___", state 32, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 38, "(1)"
+ line 416, "pan.___", state 39, "(1)"
+ line 416, "pan.___", state 39, "(1)"
+ line 414, "pan.___", state 44, "((i<1))"
+ line 414, "pan.___", state 44, "((i>=1))"
+ line 421, "pan.___", state 50, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 56, "(1)"
+ line 421, "pan.___", state 57, "(1)"
+ line 421, "pan.___", state 57, "(1)"
+ line 425, "pan.___", state 64, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 70, "(1)"
+ line 425, "pan.___", state 71, "(1)"
+ line 425, "pan.___", state 71, "(1)"
+ line 423, "pan.___", state 76, "((i<2))"
+ line 423, "pan.___", state 76, "((i>=2))"
+ line 250, "pan.___", state 82, "(1)"
+ line 254, "pan.___", state 90, "(1)"
+ line 254, "pan.___", state 91, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 91, "else"
+ line 252, "pan.___", state 96, "((i<1))"
+ line 252, "pan.___", state 96, "((i>=1))"
+ line 258, "pan.___", state 102, "(1)"
+ line 258, "pan.___", state 103, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 103, "else"
+ line 262, "pan.___", state 110, "(1)"
+ line 262, "pan.___", state 111, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 111, "else"
+ line 260, "pan.___", state 116, "((i<2))"
+ line 260, "pan.___", state 116, "((i>=2))"
+ line 267, "pan.___", state 120, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 120, "else"
+ line 432, "pan.___", state 122, "(1)"
+ line 432, "pan.___", state 122, "(1)"
+ line 273, "pan.___", state 131, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 140, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 148, "((i<1))"
+ line 275, "pan.___", state 148, "((i>=1))"
+ line 281, "pan.___", state 153, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 1022, "pan.___", state 181, "old_data = cached_rcu_ptr.val[_pid]"
+ line 412, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 199, "(1)"
+ line 416, "pan.___", state 207, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 213, "(1)"
+ line 416, "pan.___", state 214, "(1)"
+ line 416, "pan.___", state 214, "(1)"
+ line 414, "pan.___", state 219, "((i<1))"
+ line 414, "pan.___", state 219, "((i>=1))"
+ line 421, "pan.___", state 225, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 231, "(1)"
+ line 421, "pan.___", state 232, "(1)"
+ line 421, "pan.___", state 232, "(1)"
+ line 425, "pan.___", state 239, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 245, "(1)"
+ line 425, "pan.___", state 246, "(1)"
+ line 425, "pan.___", state 246, "(1)"
+ line 423, "pan.___", state 251, "((i<2))"
+ line 423, "pan.___", state 251, "((i>=2))"
+ line 250, "pan.___", state 257, "(1)"
+ line 254, "pan.___", state 265, "(1)"
+ line 254, "pan.___", state 266, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 266, "else"
+ line 252, "pan.___", state 271, "((i<1))"
+ line 252, "pan.___", state 271, "((i>=1))"
+ line 258, "pan.___", state 277, "(1)"
+ line 258, "pan.___", state 278, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 278, "else"
+ line 262, "pan.___", state 285, "(1)"
+ line 262, "pan.___", state 286, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 286, "else"
+ line 260, "pan.___", state 291, "((i<2))"
+ line 260, "pan.___", state 291, "((i>=2))"
+ line 267, "pan.___", state 295, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 295, "else"
+ line 432, "pan.___", state 297, "(1)"
+ line 432, "pan.___", state 297, "(1)"
+ line 412, "pan.___", state 308, "(1)"
+ line 412, "pan.___", state 309, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 309, "else"
+ line 412, "pan.___", state 312, "(1)"
+ line 416, "pan.___", state 320, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 326, "(1)"
+ line 416, "pan.___", state 327, "(1)"
+ line 416, "pan.___", state 327, "(1)"
+ line 414, "pan.___", state 332, "((i<1))"
+ line 414, "pan.___", state 332, "((i>=1))"
+ line 421, "pan.___", state 338, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 344, "(1)"
+ line 421, "pan.___", state 345, "(1)"
+ line 421, "pan.___", state 345, "(1)"
+ line 425, "pan.___", state 352, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 358, "(1)"
+ line 425, "pan.___", state 359, "(1)"
+ line 425, "pan.___", state 359, "(1)"
+ line 423, "pan.___", state 364, "((i<2))"
+ line 423, "pan.___", state 364, "((i>=2))"
+ line 250, "pan.___", state 370, "(1)"
+ line 254, "pan.___", state 378, "(1)"
+ line 254, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 379, "else"
+ line 252, "pan.___", state 384, "((i<1))"
+ line 252, "pan.___", state 384, "((i>=1))"
+ line 258, "pan.___", state 390, "(1)"
+ line 258, "pan.___", state 391, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 391, "else"
+ line 262, "pan.___", state 398, "(1)"
+ line 262, "pan.___", state 399, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 399, "else"
+ line 260, "pan.___", state 404, "((i<2))"
+ line 260, "pan.___", state 404, "((i>=2))"
+ line 267, "pan.___", state 408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 408, "else"
+ line 432, "pan.___", state 410, "(1)"
+ line 432, "pan.___", state 410, "(1)"
+ line 412, "pan.___", state 423, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 425, "(1)"
+ line 412, "pan.___", state 426, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+ line 412, "pan.___", state 426, "else"
+ line 412, "pan.___", state 429, "(1)"
+ line 416, "pan.___", state 437, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 439, "(1)"
+ line 416, "pan.___", state 440, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+ line 416, "pan.___", state 440, "else"
+ line 416, "pan.___", state 443, "(1)"
+ line 416, "pan.___", state 444, "(1)"
+ line 416, "pan.___", state 444, "(1)"
+ line 414, "pan.___", state 449, "((i<1))"
+ line 414, "pan.___", state 449, "((i>=1))"
+ line 421, "pan.___", state 455, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 457, "(1)"
+ line 421, "pan.___", state 458, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 421, "pan.___", state 458, "else"
+ line 421, "pan.___", state 461, "(1)"
+ line 421, "pan.___", state 462, "(1)"
+ line 421, "pan.___", state 462, "(1)"
+ line 425, "pan.___", state 469, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 471, "(1)"
+ line 425, "pan.___", state 472, "((cache_dirty_rcu_data[i].bitfield&(1<<_pid)))"
+ line 425, "pan.___", state 472, "else"
+ line 425, "pan.___", state 475, "(1)"
+ line 425, "pan.___", state 476, "(1)"
+ line 425, "pan.___", state 476, "(1)"
+ line 423, "pan.___", state 481, "((i<2))"
+ line 423, "pan.___", state 481, "((i>=2))"
+ line 250, "pan.___", state 487, "(1)"
+ line 254, "pan.___", state 495, "(1)"
+ line 254, "pan.___", state 496, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 496, "else"
+ line 252, "pan.___", state 501, "((i<1))"
+ line 252, "pan.___", state 501, "((i>=1))"
+ line 258, "pan.___", state 507, "(1)"
+ line 258, "pan.___", state 508, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 508, "else"
+ line 262, "pan.___", state 515, "(1)"
+ line 262, "pan.___", state 516, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 516, "else"
+ line 267, "pan.___", state 525, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 525, "else"
+ line 432, "pan.___", state 527, "(1)"
+ line 432, "pan.___", state 527, "(1)"
+ line 412, "pan.___", state 533, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 539, "(1)"
+ line 416, "pan.___", state 547, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 553, "(1)"
+ line 416, "pan.___", state 554, "(1)"
+ line 416, "pan.___", state 554, "(1)"
+ line 414, "pan.___", state 559, "((i<1))"
+ line 414, "pan.___", state 559, "((i>=1))"
+ line 421, "pan.___", state 565, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 571, "(1)"
+ line 421, "pan.___", state 572, "(1)"
+ line 421, "pan.___", state 572, "(1)"
+ line 425, "pan.___", state 579, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 585, "(1)"
+ line 425, "pan.___", state 586, "(1)"
+ line 425, "pan.___", state 586, "(1)"
+ line 423, "pan.___", state 591, "((i<2))"
+ line 423, "pan.___", state 591, "((i>=2))"
+ line 250, "pan.___", state 597, "(1)"
+ line 254, "pan.___", state 605, "(1)"
+ line 254, "pan.___", state 606, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 606, "else"
+ line 252, "pan.___", state 611, "((i<1))"
+ line 252, "pan.___", state 611, "((i>=1))"
+ line 258, "pan.___", state 617, "(1)"
+ line 258, "pan.___", state 618, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 618, "else"
+ line 262, "pan.___", state 625, "(1)"
+ line 262, "pan.___", state 626, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 626, "else"
+ line 267, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 635, "else"
+ line 432, "pan.___", state 637, "(1)"
+ line 432, "pan.___", state 637, "(1)"
+ line 412, "pan.___", state 644, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 412, "pan.___", state 650, "(1)"
+ line 416, "pan.___", state 658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 416, "pan.___", state 664, "(1)"
+ line 416, "pan.___", state 665, "(1)"
+ line 416, "pan.___", state 665, "(1)"
+ line 414, "pan.___", state 670, "((i<1))"
+ line 414, "pan.___", state 670, "((i>=1))"
+ line 421, "pan.___", state 676, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 682, "(1)"
+ line 421, "pan.___", state 683, "(1)"
+ line 421, "pan.___", state 683, "(1)"
+ line 425, "pan.___", state 690, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 696, "(1)"
+ line 425, "pan.___", state 697, "(1)"
+ line 425, "pan.___", state 697, "(1)"
+ line 423, "pan.___", state 702, "((i<2))"
+ line 423, "pan.___", state 702, "((i>=2))"
+ line 250, "pan.___", state 708, "(1)"
+ line 254, "pan.___", state 716, "(1)"
+ line 254, "pan.___", state 717, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 717, "else"
+ line 252, "pan.___", state 722, "((i<1))"
+ line 252, "pan.___", state 722, "((i>=1))"
+ line 258, "pan.___", state 728, "(1)"
+ line 258, "pan.___", state 729, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 729, "else"
+ line 262, "pan.___", state 736, "(1)"
+ line 262, "pan.___", state 737, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 737, "else"
+ line 260, "pan.___", state 742, "((i<2))"
+ line 260, "pan.___", state 742, "((i>=2))"
+ line 267, "pan.___", state 746, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 746, "else"
+ line 432, "pan.___", state 748, "(1)"
+ line 432, "pan.___", state 748, "(1)"
+ line 416, "pan.___", state 771, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 789, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 803, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 254, "pan.___", state 829, "(1)"
+ line 258, "pan.___", state 841, "(1)"
+ line 262, "pan.___", state 849, "(1)"
+ line 416, "pan.___", state 887, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 421, "pan.___", state 905, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 425, "pan.___", state 919, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 254, "pan.___", state 945, "(1)"
+ line 258, "pan.___", state 957, "(1)"
+ line 262, "pan.___", state 965, "(1)"
+ line 273, "pan.___", state 1009, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+ line 277, "pan.___", state 1018, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 275, "pan.___", state 1026, "((i<1))"
+ line 275, "pan.___", state 1026, "((i>=1))"
+ line 281, "pan.___", state 1033, "(1)"
+ line 281, "pan.___", state 1034, "((cache_dirty_rcu_ptr.bitfield&(1<<_pid)))"
+ line 281, "pan.___", state 1034, "else"
+ line 285, "pan.___", state 1040, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 283, "pan.___", state 1048, "((i<2))"
+ line 283, "pan.___", state 1048, "((i>=2))"
+ line 250, "pan.___", state 1056, "(1)"
+ line 254, "pan.___", state 1064, "(1)"
+ line 254, "pan.___", state 1065, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+ line 254, "pan.___", state 1065, "else"
+ line 252, "pan.___", state 1070, "((i<1))"
+ line 252, "pan.___", state 1070, "((i>=1))"
+ line 258, "pan.___", state 1076, "(1)"
+ line 258, "pan.___", state 1077, "(!((cache_dirty_rcu_ptr.bitfield&(1<<_pid))))"
+ line 258, "pan.___", state 1077, "else"
+ line 262, "pan.___", state 1084, "(1)"
+ line 262, "pan.___", state 1085, "(!((cache_dirty_rcu_data[i].bitfield&(1<<_pid))))"
+ line 262, "pan.___", state 1085, "else"
+ line 267, "pan.___", state 1094, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+ line 267, "pan.___", state 1094, "else"
+ line 277, "pan.___", state 1109, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+ line 281, "pan.___", state 1122, "cache_dirty_rcu_ptr.bitfield = (cache_dirty_rcu_ptr.bitfield&~((1<<_pid)))"
+ line 285, "pan.___", state 1131, "cache_dirty_rcu_data[i].bitfield = (cache_dirty_rcu_data[i].bitfield&~((1<<_pid)))"
+ line 250, "pan.___", state 1147, "(1)"
+ line 254, "pan.___", state 1155, "(1)"
+ line 258, "pan.___", state 1167, "(1)"
+ line 262, "pan.___", state 1175, "(1)"
+ line 1238, "pan.___", state 1190, "-end-"
+ (192 of 1190 states)
+unreached in proctype :init:
+ (0 of 78 states)
+unreached in proctype :never:
+ line 1303, "pan.___", state 11, "-end-"
+ (1 of 11 states)
+
+pan: elapsed time 8.1 seconds
+pan: rate 24329.259 states/second
+pan: avg transition delay 2.7644e-06 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu-controldataflow-intel-no-ipi'
--- /dev/null
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+// Poison value for freed memory
+#define POISON 1
+// Memory with correct data
+#define WINE 0
+#define SLAB_SIZE 2
+
+#define read_poison (data_read_first[0] == POISON || data_read_second[0] == POISON)
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+//disabled
+//#define REMOTE_BARRIERS
+
+//#define ARCH_ALPHA
+#define ARCH_INTEL
+//#define ARCH_POWERPC
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory
+ * and out-of-order instruction scheduling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid() (_pid)
+
+#define get_readerid() (get_pid())
+
+/*
+ * Produced process control and data flow. Updated after each instruction to
+ * show which variables are ready. Using one-hot bit encoding per variable to
+ * save state space. Used as triggers to execute the instructions having those
+ * variables as input. Leaving bits active to inhibit instruction execution.
+ * Scheme used to make instruction disabling and automatic dependency fall-back
+ * automatic.
+ */
+
+#define CONSUME_TOKENS(state, bits, notbits) \
+ ((!(state & (notbits))) && (state & (bits)) == (bits))
+
+#define PRODUCE_TOKENS(state, bits) \
+ state = state | (bits);
+
+#define CLEAR_TOKENS(state, bits) \
+ state = state & ~(bits)
+
+/*
+ * Types of dependency :
+ *
+ * Data dependency
+ *
+ * - True dependency, Read-after-Write (RAW)
+ *
+ * This type of dependency happens when a statement depends on the result of a
+ * previous statement. This applies to any statement which needs to read a
+ * variable written by a preceding statement.
+ *
+ * - False dependency, Write-after-Read (WAR)
+ *
+ * Typically, variable renaming can ensure that this dependency goes away.
+ * However, if the statements must read and then write from/to the same variable
+ * in the OOO memory model, renaming may be impossible, and therefore this
+ * causes a WAR dependency.
+ *
+ * - Output dependency, Write-after-Write (WAW)
+ *
+ * Two writes to the same variable in subsequent statements. Variable renaming
+ * can ensure this is not needed, but can be required when writing multiple
+ * times to the same OOO mem model variable.
+ *
+ * Control dependency
+ *
+ * Execution of a given instruction depends on a previous instruction evaluating
+ * in a way that allows its execution. E.g. : branches.
+ *
+ * Useful considerations for joining dependencies after branch
+ *
+ * - Pre-dominance
+ *
+ * "We say box i dominates box j if every path (leading from input to output
+ * through the diagram) which passes through box j must also pass through box
+ * i. Thus box i dominates box j if box j is subordinate to box i in the
+ * program."
+ *
+ * http://www.hipersoft.rice.edu/grads/publications/dom14.pdf
+ * Other classic algorithm to calculate dominance : Lengauer-Tarjan (in gcc)
+ *
+ * - Post-dominance
+ *
+ * Just as pre-dominance, but with arcs of the data flow inverted, and input vs
+ * output exchanged. Therefore, i post-dominating j ensures that every path
+ * passing by j will pass by i before reaching the output.
+ *
+ * Prefetch and speculative execution
+ *
+ * If an instruction depends on the result of a previous branch, but it does not
+ * have side-effects, it can be executed before the branch result is known.
+ * however, it must be restarted if a core-synchronizing instruction is issued.
+ * Note that instructions which depend on the speculative instruction result
+ * but that have side-effects must depend on the branch completion in addition
+ * to the speculatively executed instruction.
+ *
+ * Other considerations
+ *
+ * Note about "volatile" keyword dependency : The compiler will order volatile
+ * accesses so they appear in the right order on a given CPU. They can be
+ * reordered by the CPU instruction scheduling. This therefore cannot be
+ * considered as a depencency.
+ *
+ * References :
+ *
+ * Cooper, Keith D.; & Torczon, Linda. (2005). Engineering a Compiler. Morgan
+ * Kaufmann. ISBN 1-55860-698-X.
+ * Kennedy, Ken; & Allen, Randy. (2001). Optimizing Compilers for Modern
+ * Architectures: A Dependence-based Approach. Morgan Kaufmann. ISBN
+ * 1-55860-286-0.
+ * Muchnick, Steven S. (1997). Advanced Compiler Design and Implementation.
+ * Morgan Kaufmann. ISBN 1-55860-320-4.
+ */
+
+/*
+ * Note about loops and nested calls
+ *
+ * To keep this model simple, loops expressed in the framework will behave as if
+ * there was a core synchronizing instruction between loops. To see the effect
+ * of loop unrolling, manually unrolling loops is required. Note that if loops
+ * end or start with a core synchronizing instruction, the model is appropriate.
+ * Nested calls are not supported.
+ */
+
+/*
+ * Only Alpha has out-of-order cache bank loads. Other architectures (intel,
+ * powerpc, arm) ensure that dependent reads won't be reordered. c.f.
+ * http://www.linuxjournal.com/article/8212)
+ */
+#ifdef ARCH_ALPHA
+#define HAVE_OOO_CACHE_READ
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+ byte val[NR_PROCS];
+};
+
+typedef per_proc_bit {
+ bit val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bitfield {
+ byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x) \
+ type mem_##x; \
+ per_proc_##type cached_##x; \
+ per_proc_bitfield cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j) \
+ mem_##x = v; \
+ cache_dirty_##x.bitfield = 0; \
+ j = 0; \
+ do \
+ :: j < NR_PROCS -> \
+ cached_##x.val[j] = v; \
+ j++ \
+ :: j >= NR_PROCS -> break \
+ od;
+
+#define IS_CACHE_DIRTY(x, id) (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x) (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v) \
+ atomic { \
+ cached_##x.val[get_pid()] = v; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield | (1 << get_pid()); \
+ }
+
+#define CACHE_WRITE_TO_MEM(x, id) \
+ if \
+ :: IS_CACHE_DIRTY(x, id) -> \
+ mem_##x = cached_##x.val[id]; \
+ cache_dirty_##x.bitfield = \
+ cache_dirty_##x.bitfield & (~(1 << id)); \
+ :: else -> \
+ skip \
+ fi;
+
+#define CACHE_READ_FROM_MEM(x, id) \
+ if \
+ :: !IS_CACHE_DIRTY(x, id) -> \
+ cached_##x.val[id] = mem_##x;\
+ :: else -> \
+ skip \
+ fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+ if \
+ :: 1 -> CACHE_READ_FROM_MEM(x, id); \
+ :: 1 -> skip \
+ fi;
+
+/* Must consume all prior read tokens. All subsequent reads depend on it. */
+inline smp_rmb(i)
+{
+ atomic {
+ CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Must consume all prior write tokens. All subsequent writes depend on it. */
+inline smp_wmb(i)
+{
+ atomic {
+ CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+ }
+}
+
+/* Synchronization point. Must consume all prior read and write tokens. All
+ * subsequent reads and writes depend on it. */
+inline smp_mb(i)
+{
+ atomic {
+ smp_wmb(i);
+ smp_rmb(i);
+ }
+}
+
+#ifdef REMOTE_BARRIERS
+
+bit reader_barrier[NR_READERS];
+
+/*
+ * We cannot leave the barriers dependencies in place in REMOTE_BARRIERS mode
+ * because they would add unexisting core synchronization and would therefore
+ * create an incomplete model.
+ * Therefore, we model the read-side memory barriers by completely disabling the
+ * memory barriers and their dependencies from the read-side. One at a time
+ * (different verification runs), we make a different instruction listen for
+ * signals.
+ */
+
+#define smp_mb_reader(i, j)
+
+/*
+ * Service 0, 1 or many barrier requests.
+ */
+inline smp_mb_recv(i, j)
+{
+ do
+ :: (reader_barrier[get_readerid()] == 1) ->
+ /*
+ * We choose to ignore cycles caused by writer busy-looping,
+ * waiting for the reader, sending barrier requests, and the
+ * reader always services them without continuing execution.
+ */
+progress_ignoring_mb1:
+ smp_mb(i);
+ reader_barrier[get_readerid()] = 0;
+ :: 1 ->
+ /*
+ * We choose to ignore writer's non-progress caused by the
+ * reader ignoring the writer's mb() requests.
+ */
+progress_ignoring_mb2:
+ break;
+ od;
+}
+
+#define PROGRESS_LABEL(progressid) progress_writer_progid_##progressid:
+
+#define smp_mb_send(i, j, progressid) \
+{ \
+ smp_mb(i); \
+ i = 0; \
+ do \
+ :: i < NR_READERS -> \
+ reader_barrier[i] = 1; \
+ /* \
+ * Busy-looping waiting for reader barrier handling is of little\
+ * interest, given the reader has the ability to totally ignore \
+ * barrier requests. \
+ */ \
+ do \
+ :: (reader_barrier[i] == 1) -> \
+PROGRESS_LABEL(progressid) \
+ skip; \
+ :: (reader_barrier[i] == 0) -> break; \
+ od; \
+ i++; \
+ :: i >= NR_READERS -> \
+ break \
+ od; \
+ smp_mb(i); \
+}
+
+#else
+
+#define smp_mb_send(i, j, progressid) smp_mb(i)
+#define smp_mb_reader(i, j) smp_mb(i)
+#define smp_mb_recv(i, j)
+
+#endif
+
+/* Keep in sync manually with smp_rmb, smp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* RCU data */
+DECLARE_CACHED_VAR(bit, rcu_data[SLAB_SIZE]);
+
+/* RCU pointer */
+#if (SLAB_SIZE == 2)
+DECLARE_CACHED_VAR(bit, rcu_ptr);
+bit ptr_read_first[NR_READERS];
+bit ptr_read_second[NR_READERS];
+#else
+DECLARE_CACHED_VAR(byte, rcu_ptr);
+byte ptr_read_first[NR_READERS];
+byte ptr_read_second[NR_READERS];
+#endif
+
+bit data_read_first[NR_READERS];
+bit data_read_second[NR_READERS];
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+ do
+ :: init_done == 0 -> skip;
+ :: else -> break;
+ od;
+}
+
+inline ooo_mem(i)
+{
+ atomic {
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_WRITE_TO_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#ifdef HAVE_OOO_CACHE_READ
+ RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+ get_pid());
+ i++
+ :: i >= NR_READERS -> break
+ od;
+ RANDOM_CACHE_READ_FROM_MEM(rcu_ptr, get_pid());
+ i = 0;
+ do
+ :: i < SLAB_SIZE ->
+ RANDOM_CACHE_READ_FROM_MEM(rcu_data[i], get_pid());
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+#else
+ smp_rmb(i);
+#endif /* HAVE_OOO_CACHE_READ */
+ }
+}
+
+/*
+ * Bit encoding, urcu_reader :
+ */
+
+int _proc_urcu_reader;
+#define proc_urcu_reader _proc_urcu_reader
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROD_A_READ (1 << 0)
+#define READ_PROD_B_IF_TRUE (1 << 1)
+#define READ_PROD_B_IF_FALSE (1 << 2)
+#define READ_PROD_C_IF_TRUE_READ (1 << 3)
+
+#define PROCEDURE_READ_LOCK(base, consumetoken, consumetoken2, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, (consumetoken | consumetoken2), READ_PROD_A_READ << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_A_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ READ_PROD_A_READ << base, /* RAW, pre-dominant */ \
+ (READ_PROD_B_IF_TRUE | READ_PROD_B_IF_FALSE) << base) -> \
+ if \
+ :: (!(tmp & RCU_GP_CTR_NEST_MASK)) -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_TRUE << base); \
+ :: else -> \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_B_IF_FALSE << base); \
+ fi; \
+ /* IF TRUE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, consumetoken, /* prefetch */ \
+ READ_PROD_C_IF_TRUE_READ << base) -> \
+ ooo_mem(i); \
+ tmp2 = READ_CACHED_VAR(urcu_gp_ctr); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_C_IF_TRUE_READ << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_TRUE \
+ | READ_PROD_C_IF_TRUE_READ /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ELSE */ \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ (READ_PROD_B_IF_FALSE /* pre-dominant */ \
+ | READ_PROD_A_READ) << base, /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], \
+ tmp + 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ /* IF_MERGE implies \
+ * post-dominance */ \
+ /* ENDIF */ \
+ skip
+
+/* Body of PROCEDURE_READ_LOCK */
+#define READ_PROC_READ_UNLOCK (1 << 0)
+
+#define PROCEDURE_READ_UNLOCK(base, consumetoken, producetoken) \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken, \
+ READ_PROC_READ_UNLOCK << base) -> \
+ ooo_mem(i); \
+ tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]); \
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_UNLOCK << base); \
+ :: CONSUME_TOKENS(proc_urcu_reader, \
+ consumetoken \
+ | (READ_PROC_READ_UNLOCK << base), /* WAR */ \
+ producetoken) -> \
+ ooo_mem(i); \
+ WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp - 1); \
+ PRODUCE_TOKENS(proc_urcu_reader, producetoken); \
+ skip
+
+
+#define READ_PROD_NONE (1 << 0)
+
+/* PROCEDURE_READ_LOCK base = << 1 : 1 to 5 */
+#define READ_LOCK_BASE 1
+#define READ_LOCK_OUT (1 << 5)
+
+#define READ_PROC_FIRST_MB (1 << 6)
+
+/* PROCEDURE_READ_LOCK (NESTED) base : << 7 : 7 to 11 */
+#define READ_LOCK_NESTED_BASE 7
+#define READ_LOCK_NESTED_OUT (1 << 11)
+
+#define READ_PROC_READ_GEN (1 << 12)
+#define READ_PROC_ACCESS_GEN (1 << 13)
+
+/* PROCEDURE_READ_UNLOCK (NESTED) base = << 14 : 14 to 15 */
+#define READ_UNLOCK_NESTED_BASE 14
+#define READ_UNLOCK_NESTED_OUT (1 << 15)
+
+#define READ_PROC_SECOND_MB (1 << 16)
+
+/* PROCEDURE_READ_UNLOCK base = << 17 : 17 to 18 */
+#define READ_UNLOCK_BASE 17
+#define READ_UNLOCK_OUT (1 << 18)
+
+/* PROCEDURE_READ_LOCK_UNROLL base = << 19 : 19 to 23 */
+#define READ_LOCK_UNROLL_BASE 19
+#define READ_LOCK_OUT_UNROLL (1 << 23)
+
+#define READ_PROC_THIRD_MB (1 << 24)
+
+#define READ_PROC_READ_GEN_UNROLL (1 << 25)
+#define READ_PROC_ACCESS_GEN_UNROLL (1 << 26)
+
+#define READ_PROC_FOURTH_MB (1 << 27)
+
+/* PROCEDURE_READ_UNLOCK_UNROLL base = << 28 : 28 to 29 */
+#define READ_UNLOCK_UNROLL_BASE 28
+#define READ_UNLOCK_OUT_UNROLL (1 << 29)
+
+
+/* Should not include branches */
+#define READ_PROC_ALL_TOKENS (READ_PROD_NONE \
+ | READ_LOCK_OUT \
+ | READ_PROC_FIRST_MB \
+ | READ_LOCK_NESTED_OUT \
+ | READ_PROC_READ_GEN \
+ | READ_PROC_ACCESS_GEN \
+ | READ_UNLOCK_NESTED_OUT \
+ | READ_PROC_SECOND_MB \
+ | READ_UNLOCK_OUT \
+ | READ_LOCK_OUT_UNROLL \
+ | READ_PROC_THIRD_MB \
+ | READ_PROC_READ_GEN_UNROLL \
+ | READ_PROC_ACCESS_GEN_UNROLL \
+ | READ_PROC_FOURTH_MB \
+ | READ_UNLOCK_OUT_UNROLL)
+
+/* Must clear all tokens, including branches */
+#define READ_PROC_ALL_TOKENS_CLEAR ((1 << 30) - 1)
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROD_NONE);
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+#ifdef REMOTE_BARRIERS
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+#endif
+
+ do
+ :: 1 ->
+
+#ifdef REMOTE_BARRIERS
+ /*
+ * Signal-based memory barrier will only execute when the
+ * execution order appears in program order.
+ */
+ if
+ :: 1 ->
+ atomic {
+ if
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE,
+ READ_LOCK_OUT | READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT
+ | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT | READ_LOCK_NESTED_OUT,
+ READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN,
+ READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT,
+ READ_UNLOCK_OUT
+ | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL,
+ READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL,
+ READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN
+ | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL,
+ READ_UNLOCK_OUT_UNROLL)
+ || CONSUME_TOKENS(proc_urcu_reader, READ_PROD_NONE | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT | READ_PROC_READ_GEN | READ_PROC_ACCESS_GEN | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT | READ_LOCK_OUT_UNROLL
+ | READ_PROC_READ_GEN_UNROLL | READ_PROC_ACCESS_GEN_UNROLL | READ_UNLOCK_OUT_UNROLL,
+ 0) ->
+ goto non_atomic3;
+non_atomic3_end:
+ skip;
+ fi;
+ }
+ fi;
+
+ goto non_atomic3_skip;
+non_atomic3:
+ smp_mb_recv(i, j);
+ goto non_atomic3_end;
+non_atomic3_skip:
+
+#endif /* REMOTE_BARRIERS */
+
+ atomic {
+ if
+ PROCEDURE_READ_LOCK(READ_LOCK_BASE, READ_PROD_NONE, 0, READ_LOCK_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_LOCK_OUT, /* post-dominant */
+ READ_PROC_FIRST_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FIRST_MB);
+
+ PROCEDURE_READ_LOCK(READ_LOCK_NESTED_BASE, READ_PROC_FIRST_MB, READ_LOCK_OUT,
+ READ_LOCK_NESTED_OUT);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN) ->
+ ooo_mem(i);
+ ptr_read_first[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_READ_GEN,
+ READ_PROC_ACCESS_GEN) ->
+ /* smp_read_barrier_depends */
+ goto rmb1;
+rmb1_end:
+ data_read_first[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_first[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN);
+
+
+ /* Note : we remove the nested memory barrier from the read unlock
+ * model, given it is not usually needed. The implementation has the barrier
+ * because the performance impact added by a branch in the common case does not
+ * justify it.
+ */
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_NESTED_BASE,
+ READ_PROC_FIRST_MB
+ | READ_LOCK_OUT
+ | READ_LOCK_NESTED_OUT,
+ READ_UNLOCK_NESTED_OUT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_ACCESS_GEN /* mb() orders reads */
+ | READ_PROC_READ_GEN /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_LOCK_OUT /* post-dominant */
+ | READ_LOCK_NESTED_OUT /* post-dominant */
+ | READ_UNLOCK_NESTED_OUT,
+ READ_PROC_SECOND_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_SECOND_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT);
+
+ /* Unrolling loop : second consecutive lock */
+ /* reading urcu_active_readers, which have been written by
+ * READ_UNLOCK_OUT : RAW */
+ PROCEDURE_READ_LOCK(READ_LOCK_UNROLL_BASE,
+ READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB, /* mb() orders reads */
+ READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT /* RAW */
+ | READ_UNLOCK_OUT, /* RAW */
+ READ_LOCK_OUT_UNROLL);
+
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_THIRD_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_THIRD_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_READ_GEN_UNROLL) ->
+ ooo_mem(i);
+ ptr_read_second[get_readerid()] = READ_CACHED_VAR(rcu_ptr);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_READ_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB, /* mb() orders reads */
+ READ_PROC_ACCESS_GEN_UNROLL) ->
+ /* smp_read_barrier_depends */
+ goto rmb2;
+rmb2_end:
+ data_read_second[get_readerid()] =
+ READ_CACHED_VAR(rcu_data[ptr_read_second[get_readerid()]]);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_ACCESS_GEN_UNROLL);
+
+ :: CONSUME_TOKENS(proc_urcu_reader,
+ READ_PROC_READ_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_ACCESS_GEN_UNROLL /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() ordered */
+ | READ_PROC_SECOND_MB /* mb() ordered */
+ | READ_PROC_THIRD_MB /* mb() ordered */
+ | READ_LOCK_OUT_UNROLL /* post-dominant */
+ | READ_LOCK_NESTED_OUT
+ | READ_LOCK_OUT
+ | READ_UNLOCK_NESTED_OUT
+ | READ_UNLOCK_OUT,
+ READ_PROC_FOURTH_MB) ->
+ smp_mb_reader(i, j);
+ PRODUCE_TOKENS(proc_urcu_reader, READ_PROC_FOURTH_MB);
+
+ PROCEDURE_READ_UNLOCK(READ_UNLOCK_UNROLL_BASE,
+ READ_PROC_FOURTH_MB /* mb() orders reads */
+ | READ_PROC_THIRD_MB /* mb() orders reads */
+ | READ_LOCK_OUT_UNROLL /* RAW */
+ | READ_PROC_SECOND_MB /* mb() orders reads */
+ | READ_PROC_FIRST_MB /* mb() orders reads */
+ | READ_LOCK_NESTED_OUT /* RAW */
+ | READ_LOCK_OUT /* RAW */
+ | READ_UNLOCK_NESTED_OUT, /* RAW */
+ READ_UNLOCK_OUT_UNROLL);
+ :: CONSUME_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_reader, READ_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Dependency between consecutive loops :
+ * RAW dependency on
+ * WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1)
+ * tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+ * between loops.
+ * _WHEN THE MB()s are in place_, they add full ordering of the
+ * generation pointer read wrt active reader count read, which ensures
+ * execution will not spill across loop execution.
+ * However, in the event mb()s are removed (execution using signal
+ * handler to promote barrier()() -> smp_mb()), nothing prevents one loop
+ * to spill its execution on other loop's execution.
+ */
+ goto end;
+rmb1:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb1_end;
+rmb2:
+#ifndef NO_RMB
+ smp_rmb(i);
+#else
+ ooo_mem(i);
+#endif
+ goto rmb2_end;
+end:
+ skip;
+}
+
+
+
+active proctype urcu_reader()
+{
+ byte i, j, nest_i;
+ byte tmp, tmp2;
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+end_reader:
+ do
+ :: 1 ->
+ /*
+ * We do not test reader's progress here, because we are mainly
+ * interested in writer's progress. The reader never blocks
+ * anyway. We have to test for reader/writer's progress
+ * separately, otherwise we could think the writer is doing
+ * progress when it's blocked by an always progressing reader.
+ */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+ urcu_one_read(i, j, nest_i, tmp, tmp2);
+ od;
+}
+
+/* no name clash please */
+#undef proc_urcu_reader
+
+
+/* Model the RCU update process. */
+
+/*
+ * Bit encoding, urcu_writer :
+ * Currently only supports one reader.
+ */
+
+int _proc_urcu_writer;
+#define proc_urcu_writer _proc_urcu_writer
+
+#define WRITE_PROD_NONE (1 << 0)
+
+#define WRITE_DATA (1 << 1)
+#define WRITE_PROC_WMB (1 << 2)
+#define WRITE_XCHG_PTR (1 << 3)
+
+#define WRITE_PROC_FIRST_MB (1 << 4)
+
+/* first flip */
+#define WRITE_PROC_FIRST_READ_GP (1 << 5)
+#define WRITE_PROC_FIRST_WRITE_GP (1 << 6)
+#define WRITE_PROC_FIRST_WAIT (1 << 7)
+#define WRITE_PROC_FIRST_WAIT_LOOP (1 << 8)
+
+/* second flip */
+#define WRITE_PROC_SECOND_READ_GP (1 << 9)
+#define WRITE_PROC_SECOND_WRITE_GP (1 << 10)
+#define WRITE_PROC_SECOND_WAIT (1 << 11)
+#define WRITE_PROC_SECOND_WAIT_LOOP (1 << 12)
+
+#define WRITE_PROC_SECOND_MB (1 << 13)
+
+#define WRITE_FREE (1 << 14)
+
+#define WRITE_PROC_ALL_TOKENS (WRITE_PROD_NONE \
+ | WRITE_DATA \
+ | WRITE_PROC_WMB \
+ | WRITE_XCHG_PTR \
+ | WRITE_PROC_FIRST_MB \
+ | WRITE_PROC_FIRST_READ_GP \
+ | WRITE_PROC_FIRST_WRITE_GP \
+ | WRITE_PROC_FIRST_WAIT \
+ | WRITE_PROC_SECOND_READ_GP \
+ | WRITE_PROC_SECOND_WRITE_GP \
+ | WRITE_PROC_SECOND_WAIT \
+ | WRITE_PROC_SECOND_MB \
+ | WRITE_FREE)
+
+#define WRITE_PROC_ALL_TOKENS_CLEAR ((1 << 15) - 1)
+
+/*
+ * Mutexes are implied around writer execution. A single writer at a time.
+ */
+active proctype urcu_writer()
+{
+ byte i, j;
+ byte tmp, tmp2, tmpa;
+ byte cur_data = 0, old_data, loop_nr = 0;
+ byte cur_gp_val = 0; /*
+ * Keep a local trace of the current parity so
+ * we don't add non-existing dependencies on the global
+ * GP update. Needed to test single flip case.
+ */
+
+ wait_init_done();
+
+ assert(get_pid() < NR_PROCS);
+
+ do
+ :: (loop_nr < 3) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+ loop_nr = loop_nr + 1;
+
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROD_NONE);
+
+#ifdef NO_WMB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+#endif
+
+#ifdef NO_MB
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+#endif
+
+#ifdef SINGLE_FLIP
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ /* For single flip, we need to know the current parity */
+ cur_gp_val = cur_gp_val ^ RCU_GP_CTR_BIT;
+#endif
+
+ do :: 1 ->
+ atomic {
+ if
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROD_NONE,
+ WRITE_DATA) ->
+ ooo_mem(i);
+ cur_data = (cur_data + 1) % SLAB_SIZE;
+ WRITE_CACHED_VAR(rcu_data[cur_data], WINE);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_DATA);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA,
+ WRITE_PROC_WMB) ->
+ smp_wmb(i);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_WMB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_WMB,
+ WRITE_XCHG_PTR) ->
+ /* rcu_xchg_pointer() */
+ atomic {
+ old_data = READ_CACHED_VAR(rcu_ptr);
+ WRITE_CACHED_VAR(rcu_ptr, cur_data);
+ }
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_XCHG_PTR);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR,
+ WRITE_PROC_FIRST_MB) ->
+ goto smp_mb_send1;
+smp_mb_send1_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_MB);
+
+ /* first flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB,
+ WRITE_PROC_FIRST_READ_GP) ->
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_MB | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP,
+ WRITE_PROC_FIRST_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_FIRST_WAIT | WRITE_PROC_FIRST_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+#ifndef SINGLE_FLIP
+ /* In normal execution, we are always starting by
+ * waiting for the even parity.
+ */
+ cur_gp_val = RCU_GP_CTR_BIT;
+#endif
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ cur_gp_val) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send2;
+smp_mb_send2_end:
+ /* The memory barrier will invalidate the
+ * second read done as prefetching. Note that all
+ * instructions with side-effects depending on
+ * WRITE_PROC_SECOND_READ_GP should also depend on
+ * completion of this busy-waiting loop. */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_FIRST_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_FIRST_WAIT_LOOP | WRITE_PROC_FIRST_WAIT);
+
+ /* second flip */
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WAIT | //test /* no dependency. Could pre-fetch, no side-effect. */
+ WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_READ_GP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ tmpa = READ_CACHED_VAR(urcu_gp_ctr);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_READ_GP);
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT /* dependency on first wait, because this
+ * instruction has globally observable
+ * side-effects.
+ */
+ | WRITE_PROC_FIRST_MB
+ | WRITE_PROC_WMB
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP,
+ WRITE_PROC_SECOND_WRITE_GP) ->
+ ooo_mem(i);
+ WRITE_CACHED_VAR(urcu_gp_ctr, tmpa ^ RCU_GP_CTR_BIT);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WRITE_GP);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ WRITE_PROC_SECOND_WAIT | WRITE_PROC_SECOND_WAIT_LOOP) ->
+ ooo_mem(i);
+ //smp_mb(i); /* TEST */
+ /* ONLY WAITING FOR READER 0 */
+ tmp2 = READ_CACHED_VAR(urcu_active_readers[0]);
+ if
+ :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+ && ((tmp2 ^ 0) & RCU_GP_CTR_BIT) ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP);
+ :: else ->
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT);
+ fi;
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ //WRITE_PROC_FIRST_WRITE_GP | /* TEST ADDING SYNC CORE */
+ WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_WAIT_LOOP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB, /* can be reordered before/after flips */
+ 0) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+ goto smp_mb_send3;
+smp_mb_send3_end:
+#else
+ ooo_mem(i);
+#endif
+ /* This instruction loops to WRITE_PROC_SECOND_WAIT */
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_WAIT_LOOP | WRITE_PROC_SECOND_WAIT);
+
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_FIRST_READ_GP
+ | WRITE_PROC_SECOND_READ_GP
+ | WRITE_PROC_FIRST_WRITE_GP
+ | WRITE_PROC_SECOND_WRITE_GP
+ | WRITE_DATA | WRITE_PROC_WMB | WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_MB,
+ WRITE_PROC_SECOND_MB) ->
+ goto smp_mb_send4;
+smp_mb_send4_end:
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_PROC_SECOND_MB);
+
+ :: CONSUME_TOKENS(proc_urcu_writer,
+ WRITE_XCHG_PTR
+ | WRITE_PROC_FIRST_WAIT
+ | WRITE_PROC_SECOND_WAIT
+ | WRITE_PROC_WMB /* No dependency on
+ * WRITE_DATA because we
+ * write to a
+ * different location. */
+ | WRITE_PROC_SECOND_MB
+ | WRITE_PROC_FIRST_MB,
+ WRITE_FREE) ->
+ WRITE_CACHED_VAR(rcu_data[old_data], POISON);
+ PRODUCE_TOKENS(proc_urcu_writer, WRITE_FREE);
+
+ :: CONSUME_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS, 0) ->
+ CLEAR_TOKENS(proc_urcu_writer, WRITE_PROC_ALL_TOKENS_CLEAR);
+ break;
+ fi;
+ }
+ od;
+ /*
+ * Note : Promela model adds implicit serialization of the
+ * WRITE_FREE instruction. Normally, it would be permitted to
+ * spill on the next loop execution. Given the validation we do
+ * checks for the data entry read to be poisoned, it's ok if
+ * we do not check "late arriving" memory poisoning.
+ */
+ :: else -> break;
+ od;
+ /*
+ * Given the reader loops infinitely, let the writer also busy-loop
+ * with progress here so, with weak fairness, we can test the
+ * writer's progress.
+ */
+end_writer:
+ do
+ :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+#ifdef READER_PROGRESS
+ /*
+ * Make sure we don't block the reader's progress.
+ */
+ smp_mb_send(i, j, 5);
+#endif
+ skip;
+ od;
+
+ /* Non-atomic parts of the loop */
+ goto end;
+smp_mb_send1:
+ smp_mb_send(i, j, 1);
+ goto smp_mb_send1_end;
+#ifndef GEN_ERROR_WRITER_PROGRESS
+smp_mb_send2:
+ smp_mb_send(i, j, 2);
+ goto smp_mb_send2_end;
+smp_mb_send3:
+ smp_mb_send(i, j, 3);
+ goto smp_mb_send3_end;
+#endif
+smp_mb_send4:
+ smp_mb_send(i, j, 4);
+ goto smp_mb_send4_end;
+end:
+ skip;
+}
+
+/* no name clash please */
+#undef proc_urcu_writer
+
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+ byte i, j;
+
+ atomic {
+ INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+ INIT_CACHED_VAR(rcu_ptr, 0, j);
+
+ i = 0;
+ do
+ :: i < NR_READERS ->
+ INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+ ptr_read_first[i] = 1;
+ ptr_read_second[i] = 1;
+ data_read_first[i] = WINE;
+ data_read_second[i] = WINE;
+ i++;
+ :: i >= NR_READERS -> break
+ od;
+ INIT_CACHED_VAR(rcu_data[0], WINE, j);
+ i = 1;
+ do
+ :: i < SLAB_SIZE ->
+ INIT_CACHED_VAR(rcu_data[i], POISON, j);
+ i++
+ :: i >= SLAB_SIZE -> break
+ od;
+
+ init_done = 1;
+ }
+}
--- /dev/null
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projects / urcu.git / commitdiff
