Commit urcu verif results
authorMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Wed, 1 Apr 2009 02:01:30 +0000 (22:01 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Wed, 1 Apr 2009 02:01:30 +0000 (22:01 -0400)
Use make summary is each dir.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
220 files changed:
formal-model/urcu/result-signal-over-reader/DEFINES [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/Makefile [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/asserts.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu.sh [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu.spin [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_reader.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_reader.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/DEFINES [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/Makefile [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/asserts.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/DEFINES [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/Makefile [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/result-signal-over-writer/references.txt [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/.input.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/.input.spin [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/DEFINES [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/Makefile [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/asserts.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/references.txt [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu.sh [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp2 [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp5 [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu.sh [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu.spin [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress.ltl [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_reader.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_reader.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.define [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.log [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input [new file with mode: 0644]
formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/DEFINES [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/Makefile [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/asserts.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu.sh [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu.spin [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free.ltl [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress.ltl [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/DEFINES [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/Makefile [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/asserts.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/asserts.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/asserts.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/references.txt [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu.sh [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu.spin [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free.ltl [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress.ltl [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input.trail [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.define [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.log [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input [new file with mode: 0644]
formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input.trail [new file with mode: 0644]

diff --git a/formal-model/urcu/result-signal-over-reader/DEFINES b/formal-model/urcu/result-signal-over-reader/DEFINES
new file mode 100644 (file)
index 0000000..2fcb038
--- /dev/null
@@ -0,0 +1,17 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-signal-over-reader/Makefile b/formal-model/urcu/result-signal-over-reader/Makefile
new file mode 100644 (file)
index 0000000..8af320d
--- /dev/null
@@ -0,0 +1,172 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       #nested useless with signal test.
+       #make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-signal-over-reader/asserts.log b/formal-model/urcu/result-signal-over-reader/asserts.log
new file mode 100644 (file)
index 0000000..d317f57
--- /dev/null
@@ -0,0 +1,312 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth=    4926 States=    1e+06 Transitions= 9.03e+06 Memory=   527.287        t=   5.98 R=   2e+05
+Depth=    7228 States=    2e+06 Transitions= 1.88e+07 Memory=   588.322        t=   12.9 R=   2e+05
+Depth=    7228 States=    3e+06 Transitions= 3.14e+07 Memory=   649.358        t=   21.9 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=    7228 States=    4e+06 Transitions=  4.3e+07 Memory=   741.416        t=   30.3 R=   1e+05
+Depth=    7228 States=    5e+06 Transitions= 5.65e+07 Memory=   802.451        t=   39.6 R=   1e+05
+Depth=    7228 States=    6e+06 Transitions= 6.78e+07 Memory=   863.486        t=   47.5 R=   1e+05
+Depth=    7228 States=    7e+06 Transitions= 8.05e+07 Memory=   924.522        t=   56.5 R=   1e+05
+Depth=    7228 States=    8e+06 Transitions= 9.49e+07 Memory=   985.557        t=   66.8 R=   1e+05
+Depth=    7228 States=    9e+06 Transitions= 1.06e+08 Memory=  1046.592        t=   74.7 R=   1e+05
+pan: resizing hashtable to -w24..  done
+Depth=    7228 States=    1e+07 Transitions= 1.18e+08 Memory=  1231.721        t=   84.9 R=   1e+05
+Depth=    7228 States=  1.1e+07 Transitions= 1.29e+08 Memory=  1292.756        t=   92.8 R=   1e+05
+Depth=    7228 States=  1.2e+07 Transitions=  1.4e+08 Memory=  1353.791        t=    100 R=   1e+05
+Depth=    7228 States=  1.3e+07 Transitions= 1.53e+08 Memory=  1414.826        t=    109 R=   1e+05
+Depth=    7228 States=  1.4e+07 Transitions= 1.65e+08 Memory=  1475.861        t=    117 R=   1e+05
+Depth=    7228 States=  1.5e+07 Transitions= 1.77e+08 Memory=  1536.897        t=    126 R=   1e+05
+Depth=    7228 States=  1.6e+07 Transitions= 1.89e+08 Memory=  1597.932        t=    134 R=   1e+05
+Depth=    7228 States=  1.7e+07 Transitions= 2.02e+08 Memory=  1658.967        t=    143 R=   1e+05
+Depth=    7228 States=  1.8e+07 Transitions= 2.16e+08 Memory=  1720.002        t=    153 R=   1e+05
+Depth=    7228 States=  1.9e+07 Transitions= 2.27e+08 Memory=  1781.037        t=    160 R=   1e+05
+Depth=    7228 States=    2e+07 Transitions= 2.39e+08 Memory=  1842.072        t=    169 R=   1e+05
+Depth=    7228 States=  2.1e+07 Transitions= 2.51e+08 Memory=  1903.108        t=    177 R=   1e+05
+Depth=    7228 States=  2.2e+07 Transitions= 2.62e+08 Memory=  1964.143        t=    185 R=   1e+05
+Depth=    7228 States=  2.3e+07 Transitions= 2.74e+08 Memory=  2025.178        t=    194 R=   1e+05
+Depth=    7228 States=  2.4e+07 Transitions= 2.86e+08 Memory=  2086.213        t=    203 R=   1e+05
+Depth=    7228 States=  2.5e+07 Transitions= 2.99e+08 Memory=  2147.248        t=    212 R=   1e+05
+Depth=    7228 States=  2.6e+07 Transitions=  3.1e+08 Memory=  2208.283        t=    220 R=   1e+05
+Depth=    7228 States=  2.7e+07 Transitions= 3.24e+08 Memory=  2269.318        t=    230 R=   1e+05
+Depth=    7228 States=  2.8e+07 Transitions= 3.37e+08 Memory=  2330.354        t=    239 R=   1e+05
+Depth=    7228 States=  2.9e+07 Transitions= 3.49e+08 Memory=  2391.389        t=    248 R=   1e+05
+Depth=    7228 States=    3e+07 Transitions=  3.6e+08 Memory=  2452.424        t=    256 R=   1e+05
+Depth=    7228 States=  3.1e+07 Transitions= 3.72e+08 Memory=  2513.459        t=    265 R=   1e+05
+Depth=    7228 States=  3.2e+07 Transitions= 3.83e+08 Memory=  2574.494        t=    273 R=   1e+05
+Depth=    7228 States=  3.3e+07 Transitions= 3.95e+08 Memory=  2635.529        t=    282 R=   1e+05
+Depth=    7228 States=  3.4e+07 Transitions= 4.07e+08 Memory=  2696.565        t=    291 R=   1e+05
+pan: resizing hashtable to -w26..  done
+Depth=    7228 States=  3.5e+07 Transitions=  4.2e+08 Memory=  3253.682        t=    308 R=   1e+05
+Depth=    7228 States=  3.6e+07 Transitions= 4.32e+08 Memory=  3314.717        t=    316 R=   1e+05
+Depth=    7228 States=  3.7e+07 Transitions= 4.45e+08 Memory=  3375.752        t=    325 R=   1e+05
+Depth=    7228 States=  3.8e+07 Transitions= 4.58e+08 Memory=  3436.787        t=    334 R=   1e+05
+Depth=    7228 States=  3.9e+07 Transitions= 4.71e+08 Memory=  3497.822        t=    343 R=   1e+05
+Depth=    7228 States=    4e+07 Transitions= 4.82e+08 Memory=  3558.858        t=    350 R=   1e+05
+Depth=    7228 States=  4.1e+07 Transitions= 4.94e+08 Memory=  3619.893        t=    359 R=   1e+05
+Depth=    7228 States=  4.2e+07 Transitions= 5.04e+08 Memory=  3680.928        t=    366 R=   1e+05
+Depth=    7228 States=  4.3e+07 Transitions= 5.16e+08 Memory=  3741.963        t=    374 R=   1e+05
+Depth=    7228 States=  4.4e+07 Transitions= 5.29e+08 Memory=  3802.998        t=    383 R=   1e+05
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             - (none specified)
+       assertion violations    +
+       cycle checks            - (disabled by -DSAFETY)
+       invalid end states      +
+
+State-vector 56 byte, depth reached 7228, errors: 0
+ 44157204 states, stored
+4.8641845e+08 states, matched
+5.3057565e+08 transitions (= stored+matched)
+1.8453582e+09 atomic steps
+hash conflicts: 2.8837553e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 3537.374      equivalent memory usage for states (stored*(State-vector + overhead))
+ 2843.050      actual memory usage for states (compression: 80.37%)
+               state-vector as stored = 40 byte + 28 byte overhead
+  512.000      memory used for hash table (-w26)
+  457.764      memory used for DFS stack (-m10000000)
+ 3812.568      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, ".input.spin", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 61, "(1)"
+       line 417, ".input.spin", state 91, "(1)"
+       line 398, ".input.spin", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 158, "(1)"
+       line 417, ".input.spin", state 188, "(1)"
+       line 398, ".input.spin", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 256, "(1)"
+       line 417, ".input.spin", state 286, "(1)"
+       line 398, ".input.spin", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 395, "(1)"
+       line 417, ".input.spin", state 425, "(1)"
+       line 539, ".input.spin", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 398, ".input.spin", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 70, "(1)"
+       line 417, ".input.spin", state 100, "(1)"
+       line 398, ".input.spin", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 158, "(1)"
+       line 417, ".input.spin", state 188, "(1)"
+       line 398, ".input.spin", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 247, "(1)"
+       line 417, ".input.spin", state 277, "(1)"
+       line 398, ".input.spin", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 359, "(1)"
+       line 417, ".input.spin", state 389, "(1)"
+       line 613, ".input.spin", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 398, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 59, "(1)"
+       line 412, ".input.spin", state 72, "(1)"
+       line 417, ".input.spin", state 89, "(1)"
+       line 398, ".input.spin", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 153, "(1)"
+       line 412, ".input.spin", state 166, "(1)"
+       line 651, ".input.spin", state 199, "(1)"
+       line 174, ".input.spin", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, ".input.spin", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 240, "(1)"
+       line 163, ".input.spin", state 248, "(1)"
+       line 167, ".input.spin", state 260, "(1)"
+       line 174, ".input.spin", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 303, "(1)"
+       line 163, ".input.spin", state 311, "(1)"
+       line 167, ".input.spin", state 323, "(1)"
+       line 174, ".input.spin", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, ".input.spin", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 370, "(1)"
+       line 163, ".input.spin", state 378, "(1)"
+       line 167, ".input.spin", state 390, "(1)"
+       line 398, ".input.spin", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 449, "(1)"
+       line 412, ".input.spin", state 462, "(1)"
+       line 417, ".input.spin", state 479, "(1)"
+       line 398, ".input.spin", state 498, "(1)"
+       line 402, ".input.spin", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 554, "(1)"
+       line 417, ".input.spin", state 571, "(1)"
+       line 402, ".input.spin", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 647, "(1)"
+       line 417, ".input.spin", state 664, "(1)"
+       line 178, ".input.spin", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 710, "(1)"
+       line 163, ".input.spin", state 718, "(1)"
+       line 167, ".input.spin", state 730, "(1)"
+       line 174, ".input.spin", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 773, "(1)"
+       line 163, ".input.spin", state 781, "(1)"
+       line 167, ".input.spin", state 793, "(1)"
+       line 174, ".input.spin", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, ".input.spin", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 840, "(1)"
+       line 163, ".input.spin", state 848, "(1)"
+       line 167, ".input.spin", state 860, "(1)"
+       line 398, ".input.spin", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, ".input.spin", state 884, "(1)"
+       line 398, ".input.spin", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, ".input.spin", state 885, "else"
+       line 398, ".input.spin", state 888, "(1)"
+       line 402, ".input.spin", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 898, "(1)"
+       line 402, ".input.spin", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 899, "else"
+       line 402, ".input.spin", state 902, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 400, ".input.spin", state 908, "((i<1))"
+       line 400, ".input.spin", state 908, "((i>=1))"
+       line 407, ".input.spin", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 927, "(1)"
+       line 408, ".input.spin", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 408, ".input.spin", state 928, "else"
+       line 408, ".input.spin", state 931, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 412, ".input.spin", state 940, "(1)"
+       line 412, ".input.spin", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 412, ".input.spin", state 941, "else"
+       line 412, ".input.spin", state 944, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 410, ".input.spin", state 950, "((i<1))"
+       line 410, ".input.spin", state 950, "((i>=1))"
+       line 417, ".input.spin", state 957, "(1)"
+       line 417, ".input.spin", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 417, ".input.spin", state 958, "else"
+       line 417, ".input.spin", state 961, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 402, ".input.spin", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 1040, "(1)"
+       line 417, ".input.spin", state 1057, "(1)"
+       line 402, ".input.spin", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 1130, "(1)"
+       line 417, ".input.spin", state 1147, "(1)"
+       line 398, ".input.spin", state 1166, "(1)"
+       line 402, ".input.spin", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 1222, "(1)"
+       line 417, ".input.spin", state 1239, "(1)"
+       line 402, ".input.spin", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, ".input.spin", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, ".input.spin", state 1315, "(1)"
+       line 417, ".input.spin", state 1332, "(1)"
+       line 178, ".input.spin", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 1378, "(1)"
+       line 163, ".input.spin", state 1386, "(1)"
+       line 167, ".input.spin", state 1398, "(1)"
+       line 174, ".input.spin", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1441, "(1)"
+       line 163, ".input.spin", state 1449, "(1)"
+       line 167, ".input.spin", state 1461, "(1)"
+       line 174, ".input.spin", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, ".input.spin", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 1508, "(1)"
+       line 163, ".input.spin", state 1516, "(1)"
+       line 167, ".input.spin", state 1528, "(1)"
+       line 398, ".input.spin", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, ".input.spin", state 1552, "(1)"
+       line 398, ".input.spin", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, ".input.spin", state 1553, "else"
+       line 398, ".input.spin", state 1556, "(1)"
+       line 402, ".input.spin", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 1566, "(1)"
+       line 402, ".input.spin", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, ".input.spin", state 1567, "else"
+       line 402, ".input.spin", state 1570, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 400, ".input.spin", state 1576, "((i<1))"
+       line 400, ".input.spin", state 1576, "((i>=1))"
+       line 407, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, ".input.spin", state 1595, "(1)"
+       line 408, ".input.spin", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 408, ".input.spin", state 1596, "else"
+       line 408, ".input.spin", state 1599, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 412, ".input.spin", state 1608, "(1)"
+       line 412, ".input.spin", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 412, ".input.spin", state 1609, "else"
+       line 412, ".input.spin", state 1612, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 410, ".input.spin", state 1618, "((i<1))"
+       line 410, ".input.spin", state 1618, "((i>=1))"
+       line 417, ".input.spin", state 1625, "(1)"
+       line 417, ".input.spin", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 417, ".input.spin", state 1626, "else"
+       line 417, ".input.spin", state 1629, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 178, ".input.spin", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 1681, "(1)"
+       line 163, ".input.spin", state 1689, "(1)"
+       line 167, ".input.spin", state 1701, "(1)"
+       line 174, ".input.spin", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1744, "(1)"
+       line 163, ".input.spin", state 1752, "(1)"
+       line 167, ".input.spin", state 1764, "(1)"
+       line 174, ".input.spin", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, ".input.spin", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, ".input.spin", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, ".input.spin", state 1811, "(1)"
+       line 163, ".input.spin", state 1819, "(1)"
+       line 167, ".input.spin", state 1831, "(1)"
+       line 701, ".input.spin", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+
+pan: elapsed time 384 seconds
+pan: rate 114968.77 states/second
+pan: avg transition delay 7.2389e-07 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/asserts.spin.input b/formal-model/urcu/result-signal-over-reader/asserts.spin.input
new file mode 100644 (file)
index 0000000..2d7f62d
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/asserts.spin.input.trail b/formal-model/urcu/result-signal-over-reader/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-signal-over-reader/urcu.sh b/formal-model/urcu/result-signal-over-reader/urcu.sh
new file mode 100644 (file)
index 0000000..65ff517
--- /dev/null
@@ -0,0 +1,29 @@
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+#               Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+#          Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
diff --git a/formal-model/urcu/result-signal-over-reader/urcu.spin b/formal-model/urcu/result-signal-over-reader/urcu.spin
new file mode 100644 (file)
index 0000000..2cfcb70
--- /dev/null
@@ -0,0 +1,705 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free.log b/formal-model/urcu/result-signal-over-reader/urcu_free.log
new file mode 100644 (file)
index 0000000..a6ab537
--- /dev/null
@@ -0,0 +1,326 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 743)
+Depth=    6837 States=    1e+06 Transitions= 9.03e+06 Memory=   534.904        t=   7.74 R=   1e+05
+Depth=    8887 States=    2e+06 Transitions= 1.88e+07 Memory=   603.557        t=   16.6 R=   1e+05
+Depth=    8887 States=    3e+06 Transitions= 3.14e+07 Memory=   672.209        t=     28 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=    8887 States=    4e+06 Transitions= 4.33e+07 Memory=   771.885        t=   39.1 R=   1e+05
+Depth=    8887 States=    5e+06 Transitions= 5.65e+07 Memory=   840.635        t=   50.7 R=   1e+05
+Depth=    8887 States=    6e+06 Transitions= 6.79e+07 Memory=   909.287        t=     61 R=   1e+05
+Depth=    8887 States=    7e+06 Transitions= 8.08e+07 Memory=   977.940        t=   72.6 R=   1e+05
+Depth=    8887 States=    8e+06 Transitions=  9.5e+07 Memory=  1046.592        t=   85.5 R=   9e+04
+Depth=    8887 States=    9e+06 Transitions= 1.07e+08 Memory=  1115.342        t=   96.7 R=   9e+04
+pan: resizing hashtable to -w24..  done
+Depth=    8887 States=    1e+07 Transitions= 1.18e+08 Memory=  1308.088        t=    108 R=   9e+04
+Depth=    8887 States=  1.1e+07 Transitions=  1.3e+08 Memory=  1376.740        t=    119 R=   9e+04
+Depth=    8887 States=  1.2e+07 Transitions= 1.41e+08 Memory=  1445.393        t=    128 R=   9e+04
+Depth=    8887 States=  1.3e+07 Transitions= 1.51e+08 Memory=  1514.045        t=    138 R=   9e+04
+Depth=    8887 States=  1.4e+07 Transitions= 1.64e+08 Memory=  1582.795        t=    149 R=   9e+04
+Depth=    8887 States=  1.5e+07 Transitions= 1.77e+08 Memory=  1651.447        t=    160 R=   9e+04
+Depth=    8887 States=  1.6e+07 Transitions=  1.9e+08 Memory=  1720.100        t=    172 R=   9e+04
+Depth=    8887 States=  1.7e+07 Transitions= 2.02e+08 Memory=  1788.752        t=    183 R=   9e+04
+Depth=    8887 States=  1.8e+07 Transitions= 2.15e+08 Memory=  1857.502        t=    194 R=   9e+04
+Depth=    8887 States=  1.9e+07 Transitions= 2.29e+08 Memory=  1926.154        t=    207 R=   9e+04
+Depth=    8887 States=    2e+07 Transitions=  2.4e+08 Memory=  1994.807        t=    217 R=   9e+04
+Depth=    8887 States=  2.1e+07 Transitions= 2.51e+08 Memory=  2063.459        t=    227 R=   9e+04
+Depth=    8887 States=  2.2e+07 Transitions= 2.63e+08 Memory=  2132.209        t=    238 R=   9e+04
+Depth=    8887 States=  2.3e+07 Transitions= 2.74e+08 Memory=  2200.861        t=    248 R=   9e+04
+Depth=    8887 States=  2.4e+07 Transitions= 2.86e+08 Memory=  2269.514        t=    259 R=   9e+04
+Depth=    8887 States=  2.5e+07 Transitions= 2.98e+08 Memory=  2338.166        t=    270 R=   9e+04
+Depth=    8887 States=  2.6e+07 Transitions=  3.1e+08 Memory=  2406.916        t=    281 R=   9e+04
+Depth=    8887 States=  2.7e+07 Transitions= 3.24e+08 Memory=  2475.568        t=    294 R=   9e+04
+Depth=    8887 States=  2.8e+07 Transitions= 3.36e+08 Memory=  2544.221        t=    305 R=   9e+04
+Depth=    8887 States=  2.9e+07 Transitions= 3.49e+08 Memory=  2612.873        t=    317 R=   9e+04
+Depth=    8887 States=    3e+07 Transitions= 3.63e+08 Memory=  2681.526        t=    329 R=   9e+04
+Depth=    8887 States=  3.1e+07 Transitions= 3.73e+08 Memory=  2750.276        t=    339 R=   9e+04
+Depth=    8887 States=  3.2e+07 Transitions= 3.85e+08 Memory=  2818.928        t=    351 R=   9e+04
+Depth=    8887 States=  3.3e+07 Transitions= 3.97e+08 Memory=  2887.580        t=    362 R=   9e+04
+Depth=    8887 States=  3.4e+07 Transitions= 4.08e+08 Memory=  2956.233        t=    373 R=   9e+04
+pan: resizing hashtable to -w26..  done
+Depth=    8887 States=  3.5e+07 Transitions=  4.2e+08 Memory=  3520.967        t=    391 R=   9e+04
+Depth=    8887 States=  3.6e+07 Transitions= 4.32e+08 Memory=  3589.619        t=    402 R=   9e+04
+Depth=    8887 States=  3.7e+07 Transitions= 4.44e+08 Memory=  3658.272        t=    413 R=   9e+04
+Depth=    8887 States=  3.8e+07 Transitions= 4.58e+08 Memory=  3727.022        t=    425 R=   9e+04
+Depth=    8887 States=  3.9e+07 Transitions=  4.7e+08 Memory=  3795.674        t=    435 R=   9e+04
+Depth=    8887 States=    4e+07 Transitions= 4.83e+08 Memory=  3864.326        t=    447 R=   9e+04
+Depth=    8887 States=  4.1e+07 Transitions= 4.97e+08 Memory=  3932.979        t=    459 R=   9e+04
+Depth=    8887 States=  4.2e+07 Transitions= 5.07e+08 Memory=  4001.729        t=    468 R=   9e+04
+Depth=    8887 States=  4.3e+07 Transitions= 5.19e+08 Memory=  4070.381        t=    479 R=   9e+04
+Depth=    8887 States=  4.4e+07 Transitions= 5.31e+08 Memory=  4139.033        t=    489 R=   9e+04
+Depth=    8887 States=  4.5e+07 Transitions= 5.42e+08 Memory=  4207.686        t=    499 R=   9e+04
+Depth=    8887 States=  4.6e+07 Transitions= 5.54e+08 Memory=  4276.338        t=    510 R=   9e+04
+Depth=    8887 States=  4.7e+07 Transitions= 5.67e+08 Memory=  4345.088        t=    521 R=   9e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 8887, errors: 0
+ 47143033 states, stored
+5.2129161e+08 states, matched
+5.6843464e+08 transitions (= stored+matched)
+1.9783052e+09 atomic steps
+hash conflicts: 3.1395137e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 4136.237      equivalent memory usage for states (stored*(State-vector + overhead))
+ 3385.741      actual memory usage for states (compression: 81.86%)
+               state-vector as stored = 47 byte + 28 byte overhead
+  512.000      memory used for hash table (-w26)
+  457.764      memory used for DFS stack (-m10000000)
+ 4354.854      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 61, "(1)"
+       line 417, "pan.___", state 91, "(1)"
+       line 398, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 158, "(1)"
+       line 417, "pan.___", state 188, "(1)"
+       line 398, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 256, "(1)"
+       line 417, "pan.___", state 286, "(1)"
+       line 398, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 395, "(1)"
+       line 417, "pan.___", state 425, "(1)"
+       line 539, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 398, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 70, "(1)"
+       line 417, "pan.___", state 100, "(1)"
+       line 398, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 158, "(1)"
+       line 417, "pan.___", state 188, "(1)"
+       line 398, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 247, "(1)"
+       line 417, "pan.___", state 277, "(1)"
+       line 398, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 359, "(1)"
+       line 417, "pan.___", state 389, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 59, "(1)"
+       line 412, "pan.___", state 72, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 153, "(1)"
+       line 412, "pan.___", state 166, "(1)"
+       line 651, "pan.___", state 199, "(1)"
+       line 174, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 240, "(1)"
+       line 163, "pan.___", state 248, "(1)"
+       line 167, "pan.___", state 260, "(1)"
+       line 174, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 303, "(1)"
+       line 163, "pan.___", state 311, "(1)"
+       line 167, "pan.___", state 323, "(1)"
+       line 174, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 370, "(1)"
+       line 163, "pan.___", state 378, "(1)"
+       line 167, "pan.___", state 390, "(1)"
+       line 398, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 449, "(1)"
+       line 412, "pan.___", state 462, "(1)"
+       line 417, "pan.___", state 479, "(1)"
+       line 398, "pan.___", state 498, "(1)"
+       line 402, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 554, "(1)"
+       line 417, "pan.___", state 571, "(1)"
+       line 402, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 647, "(1)"
+       line 417, "pan.___", state 664, "(1)"
+       line 178, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 710, "(1)"
+       line 163, "pan.___", state 718, "(1)"
+       line 167, "pan.___", state 730, "(1)"
+       line 174, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 773, "(1)"
+       line 163, "pan.___", state 781, "(1)"
+       line 167, "pan.___", state 793, "(1)"
+       line 174, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 840, "(1)"
+       line 163, "pan.___", state 848, "(1)"
+       line 167, "pan.___", state 860, "(1)"
+       line 398, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, "pan.___", state 884, "(1)"
+       line 398, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, "pan.___", state 885, "else"
+       line 398, "pan.___", state 888, "(1)"
+       line 402, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 899, "else"
+       line 402, "pan.___", state 902, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 400, "pan.___", state 908, "((i<1))"
+       line 400, "pan.___", state 908, "((i>=1))"
+       line 407, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 927, "(1)"
+       line 408, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 408, "pan.___", state 928, "else"
+       line 408, "pan.___", state 931, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 412, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 412, "pan.___", state 941, "else"
+       line 412, "pan.___", state 944, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 410, "pan.___", state 950, "((i<1))"
+       line 410, "pan.___", state 950, "((i>=1))"
+       line 417, "pan.___", state 957, "(1)"
+       line 417, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 417, "pan.___", state 958, "else"
+       line 417, "pan.___", state 961, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 402, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 1040, "(1)"
+       line 417, "pan.___", state 1057, "(1)"
+       line 402, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 1130, "(1)"
+       line 417, "pan.___", state 1147, "(1)"
+       line 398, "pan.___", state 1166, "(1)"
+       line 402, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 1222, "(1)"
+       line 417, "pan.___", state 1239, "(1)"
+       line 402, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 407, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 412, "pan.___", state 1315, "(1)"
+       line 417, "pan.___", state 1332, "(1)"
+       line 178, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 1378, "(1)"
+       line 163, "pan.___", state 1386, "(1)"
+       line 167, "pan.___", state 1398, "(1)"
+       line 174, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1441, "(1)"
+       line 163, "pan.___", state 1449, "(1)"
+       line 167, "pan.___", state 1461, "(1)"
+       line 174, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 1508, "(1)"
+       line 163, "pan.___", state 1516, "(1)"
+       line 167, "pan.___", state 1528, "(1)"
+       line 398, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, "pan.___", state 1552, "(1)"
+       line 398, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 398, "pan.___", state 1553, "else"
+       line 398, "pan.___", state 1556, "(1)"
+       line 402, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 1566, "(1)"
+       line 402, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 402, "pan.___", state 1567, "else"
+       line 402, "pan.___", state 1570, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 400, "pan.___", state 1576, "((i<1))"
+       line 400, "pan.___", state 1576, "((i>=1))"
+       line 407, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1595, "(1)"
+       line 408, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 408, "pan.___", state 1596, "else"
+       line 408, "pan.___", state 1599, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 412, "pan.___", state 1608, "(1)"
+       line 412, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 412, "pan.___", state 1609, "else"
+       line 412, "pan.___", state 1612, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 410, "pan.___", state 1618, "((i<1))"
+       line 410, "pan.___", state 1618, "((i>=1))"
+       line 417, "pan.___", state 1625, "(1)"
+       line 417, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 417, "pan.___", state 1626, "else"
+       line 417, "pan.___", state 1629, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 178, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 1681, "(1)"
+       line 163, "pan.___", state 1689, "(1)"
+       line 167, "pan.___", state 1701, "(1)"
+       line 174, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1744, "(1)"
+       line 163, "pan.___", state 1752, "(1)"
+       line 167, "pan.___", state 1764, "(1)"
+       line 174, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 182, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 159, "pan.___", state 1811, "(1)"
+       line 163, "pan.___", state 1819, "(1)"
+       line 167, "pan.___", state 1831, "(1)"
+       line 701, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 748, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 523 seconds
+pan: rate 90149.985 states/second
+pan: avg transition delay 9.1997e-07 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free.ltl b/formal-model/urcu/result-signal-over-reader/urcu_free.ltl
new file mode 100644 (file)
index 0000000..1954414
--- /dev/null
@@ -0,0 +1 @@
+[] (read_free -> !read_free_race)
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_free.spin.input
new file mode 100644 (file)
index 0000000..2d7f62d
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_free.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.define b/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.define
new file mode 100644 (file)
index 0000000..136ef67
--- /dev/null
@@ -0,0 +1,2 @@
+#define NO_RMB
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.log b/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.log
new file mode 100644 (file)
index 0000000..3afaead
--- /dev/null
@@ -0,0 +1,303 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+Depth=    6009 States=    1e+06 Transitions= 1.08e+07 Memory=   534.904        t=   9.22 R=   1e+05
+Depth=    6009 States=    2e+06 Transitions=  3.4e+07 Memory=   603.557        t=   31.1 R=   6e+04
+Depth=    7527 States=    3e+06 Transitions= 4.91e+07 Memory=   672.209        t=   45.6 R=   7e+04
+pan: resizing hashtable to -w22..  done
+Depth=   68651 States=    4e+06 Transitions= 6.74e+07 Memory=   772.080        t=   62.9 R=   6e+04
+Depth=   68651 States=    5e+06 Transitions= 8.62e+07 Memory=   840.733        t=   80.2 R=   6e+04
+Depth=   68651 States=    6e+06 Transitions= 1.03e+08 Memory=   909.385        t=   95.7 R=   6e+04
+Depth=   68651 States=    7e+06 Transitions= 1.21e+08 Memory=   978.037        t=    112 R=   6e+04
+Depth=   68651 States=    8e+06 Transitions= 1.37e+08 Memory=  1046.690        t=    128 R=   6e+04
+Depth=   68651 States=    9e+06 Transitions= 1.52e+08 Memory=  1115.440        t=    143 R=   6e+04
+pan: resizing hashtable to -w24..  done
+Depth=   68651 States=    1e+07 Transitions= 1.72e+08 Memory=  1308.186        t=    163 R=   6e+04
+Depth=   68651 States=  1.1e+07 Transitions= 1.89e+08 Memory=  1376.838        t=    178 R=   6e+04
+Depth=   68651 States=  1.2e+07 Transitions= 2.05e+08 Memory=  1445.490        t=    193 R=   6e+04
+Depth=   68651 States=  1.3e+07 Transitions= 2.22e+08 Memory=  1514.143        t=    208 R=   6e+04
+Depth=   68651 States=  1.4e+07 Transitions= 2.39e+08 Memory=  1582.893        t=    224 R=   6e+04
+pan: claim violated! (at depth 2141)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 88 byte, depth reached 68651, errors: 1
+ 14155711 states, stored
+2.2815817e+08 states, matched
+2.4231388e+08 transitions (= stored+matched)
+8.5461256e+08 atomic steps
+hash conflicts: 1.1483359e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1565.993      equivalent memory usage for states (stored*(State-vector + overhead))
+ 1008.042      actual memory usage for states (compression: 64.37%)
+               state-vector as stored = 47 byte + 28 byte overhead
+  128.000      memory used for hash table (-w24)
+  457.764      memory used for DFS stack (-m10000000)
+ 1593.537      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 158, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 400, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 227, "(1)"
+       line 409, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 256, "(1)"
+       line 419, "pan.___", state 286, "(1)"
+       line 400, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 366, "(1)"
+       line 409, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 395, "(1)"
+       line 419, "pan.___", state 425, "(1)"
+       line 541, "pan.___", state 456, "-end-"
+       (19 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 400, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 70, "(1)"
+       line 419, "pan.___", state 100, "(1)"
+       line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 158, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 400, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 247, "(1)"
+       line 419, "pan.___", state 277, "(1)"
+       line 400, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 330, "(1)"
+       line 409, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 359, "(1)"
+       line 419, "pan.___", state 389, "(1)"
+       line 615, "pan.___", state 411, "-end-"
+       (18 of 411 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 410, "pan.___", state 153, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 400, "pan.___", state 209, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 223, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 254, "(1)"
+       line 414, "pan.___", state 267, "(1)"
+       line 400, "pan.___", state 300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 314, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 345, "(1)"
+       line 414, "pan.___", state 358, "(1)"
+       line 400, "pan.___", state 395, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 409, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 440, "(1)"
+       line 414, "pan.___", state 453, "(1)"
+       line 400, "pan.___", state 488, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 533, "(1)"
+       line 414, "pan.___", state 546, "(1)"
+       line 400, "pan.___", state 582, "(1)"
+       line 404, "pan.___", state 594, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 638, "(1)"
+       line 404, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 731, "(1)"
+       line 404, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 821, "(1)"
+       line 419, "pan.___", state 838, "(1)"
+       line 404, "pan.___", state 868, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 886, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 912, "(1)"
+       line 419, "pan.___", state 929, "(1)"
+       line 404, "pan.___", state 963, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 981, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1007, "(1)"
+       line 419, "pan.___", state 1024, "(1)"
+       line 400, "pan.___", state 1050, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1053, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1053, "else"
+       line 400, "pan.___", state 1056, "(1)"
+       line 404, "pan.___", state 1064, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1066, "(1)"
+       line 404, "pan.___", state 1067, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1067, "else"
+       line 404, "pan.___", state 1070, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 402, "pan.___", state 1076, "((i<1))"
+       line 402, "pan.___", state 1076, "((i>=1))"
+       line 409, "pan.___", state 1082, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 1095, "(1)"
+       line 410, "pan.___", state 1096, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 1096, "else"
+       line 410, "pan.___", state 1099, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 414, "pan.___", state 1108, "(1)"
+       line 414, "pan.___", state 1109, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 1109, "else"
+       line 414, "pan.___", state 1112, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 412, "pan.___", state 1118, "((i<1))"
+       line 412, "pan.___", state 1118, "((i>=1))"
+       line 419, "pan.___", state 1125, "(1)"
+       line 419, "pan.___", state 1126, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 1126, "else"
+       line 419, "pan.___", state 1129, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 404, "pan.___", state 1164, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1208, "(1)"
+       line 404, "pan.___", state 1254, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1298, "(1)"
+       line 400, "pan.___", state 1334, "(1)"
+       line 404, "pan.___", state 1346, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1390, "(1)"
+       line 404, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1483, "(1)"
+       line 404, "pan.___", state 1529, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1547, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1573, "(1)"
+       line 419, "pan.___", state 1590, "(1)"
+       line 404, "pan.___", state 1620, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1638, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1664, "(1)"
+       line 419, "pan.___", state 1681, "(1)"
+       line 404, "pan.___", state 1715, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1733, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1759, "(1)"
+       line 419, "pan.___", state 1776, "(1)"
+       line 400, "pan.___", state 1802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1804, "(1)"
+       line 400, "pan.___", state 1805, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1805, "else"
+       line 400, "pan.___", state 1808, "(1)"
+       line 404, "pan.___", state 1816, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1818, "(1)"
+       line 404, "pan.___", state 1819, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1819, "else"
+       line 404, "pan.___", state 1822, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 402, "pan.___", state 1828, "((i<1))"
+       line 402, "pan.___", state 1828, "((i>=1))"
+       line 409, "pan.___", state 1834, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 1847, "(1)"
+       line 410, "pan.___", state 1848, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 1848, "else"
+       line 410, "pan.___", state 1851, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 414, "pan.___", state 1860, "(1)"
+       line 414, "pan.___", state 1861, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 1861, "else"
+       line 414, "pan.___", state 1864, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 412, "pan.___", state 1870, "((i<1))"
+       line 412, "pan.___", state 1870, "((i>=1))"
+       line 419, "pan.___", state 1877, "(1)"
+       line 419, "pan.___", state 1878, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 1878, "else"
+       line 419, "pan.___", state 1881, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 404, "pan.___", state 1916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1960, "(1)"
+       line 404, "pan.___", state 2007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 2051, "(1)"
+       line 404, "pan.___", state 2102, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 2146, "(1)"
+       line 703, "pan.___", state 2192, "-end-"
+       (144 of 2192 states)
+unreached in proctype :init:
+       line 710, "pan.___", state 9, "((j<2))"
+       line 710, "pan.___", state 9, "((j>=2))"
+       line 711, "pan.___", state 20, "((j<2))"
+       line 711, "pan.___", state 20, "((j>=2))"
+       line 716, "pan.___", state 33, "((j<2))"
+       line 716, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 750, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 227 seconds
+pan: rate 62472.797 states/second
+pan: avg transition delay 9.3511e-07 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input
new file mode 100644 (file)
index 0000000..5de16b8
--- /dev/null
@@ -0,0 +1,724 @@
+#define NO_RMB
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_free_no_mb.spin.input.trail
new file mode 100644 (file)
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diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.define b/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.define
new file mode 100644 (file)
index 0000000..73e61a4
--- /dev/null
@@ -0,0 +1 @@
+#define NO_RMB
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.log b/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.log
new file mode 100644 (file)
index 0000000..5bcef22
--- /dev/null
@@ -0,0 +1,300 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+Depth=    5678 States=    1e+06 Transitions= 8.21e+06 Memory=   534.904        t=   6.72 R=   1e+05
+Depth=    5678 States=    2e+06 Transitions=  1.6e+07 Memory=   603.557        t=   13.4 R=   1e+05
+Depth=   16003 States=    3e+06 Transitions= 2.49e+07 Memory=   672.209        t=   21.5 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=   31043 States=    4e+06 Transitions= 3.44e+07 Memory=   771.983        t=   30.1 R=   1e+05
+Depth=   31043 States=    5e+06 Transitions= 4.41e+07 Memory=   840.635        t=   38.4 R=   1e+05
+Depth=   31043 States=    6e+06 Transitions= 5.25e+07 Memory=   909.287        t=   45.7 R=   1e+05
+Depth=   31043 States=    7e+06 Transitions= 6.12e+07 Memory=   977.940        t=   53.4 R=   1e+05
+Depth=   31043 States=    8e+06 Transitions= 6.95e+07 Memory=  1046.690        t=   60.8 R=   1e+05
+Depth=   31043 States=    9e+06 Transitions= 7.78e+07 Memory=  1115.342        t=   68.5 R=   1e+05
+pan: resizing hashtable to -w24..  done
+Depth=   31043 States=    1e+07 Transitions= 8.68e+07 Memory=  1308.088        t=   77.9 R=   1e+05
+Depth=   31043 States=  1.1e+07 Transitions= 1.01e+08 Memory=  1376.740        t=   90.1 R=   1e+05
+Depth=   31043 States=  1.2e+07 Transitions= 1.13e+08 Memory=  1445.393        t=    101 R=   1e+05
+Depth=   31043 States=  1.3e+07 Transitions= 1.25e+08 Memory=  1514.045        t=    111 R=   1e+05
+Depth=   31043 States=  1.4e+07 Transitions= 1.38e+08 Memory=  1582.795        t=    122 R=   1e+05
+pan: claim violated! (at depth 1774)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 31043, errors: 1
+ 14288659 states, stored
+1.2755714e+08 states, matched
+1.418458e+08 transitions (= stored+matched)
+4.6616273e+08 atomic steps
+hash conflicts:  65726574 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 1253.659      equivalent memory usage for states (stored*(State-vector + overhead))
+ 1017.191      actual memory usage for states (compression: 81.14%)
+               state-vector as stored = 47 byte + 28 byte overhead
+  128.000      memory used for hash table (-w24)
+  457.764      memory used for DFS stack (-m10000000)
+ 1602.619      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 256, "(1)"
+       line 418, "pan.___", state 286, "(1)"
+       line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 395, "(1)"
+       line 418, "pan.___", state 425, "(1)"
+       line 540, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 70, "(1)"
+       line 418, "pan.___", state 100, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 247, "(1)"
+       line 418, "pan.___", state 277, "(1)"
+       line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 359, "(1)"
+       line 418, "pan.___", state 389, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 175, "pan.___", state 243, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 265, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 291, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 304, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 320, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 334, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 352, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 365, "(1)"
+       line 413, "pan.___", state 378, "(1)"
+       line 418, "pan.___", state 395, "(1)"
+       line 399, "pan.___", state 414, "(1)"
+       line 403, "pan.___", state 426, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 444, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 470, "(1)"
+       line 418, "pan.___", state 487, "(1)"
+       line 403, "pan.___", state 519, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 537, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 563, "(1)"
+       line 418, "pan.___", state 580, "(1)"
+       line 179, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 175, "pan.___", state 629, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 651, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 677, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 690, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 714, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 716, "(1)"
+       line 399, "pan.___", state 717, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 717, "else"
+       line 399, "pan.___", state 720, "(1)"
+       line 403, "pan.___", state 728, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 730, "(1)"
+       line 403, "pan.___", state 731, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 731, "else"
+       line 403, "pan.___", state 734, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 401, "pan.___", state 740, "((i<1))"
+       line 401, "pan.___", state 740, "((i>=1))"
+       line 408, "pan.___", state 746, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 759, "(1)"
+       line 409, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 760, "else"
+       line 409, "pan.___", state 763, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 413, "pan.___", state 772, "(1)"
+       line 413, "pan.___", state 773, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 773, "else"
+       line 413, "pan.___", state 776, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 411, "pan.___", state 782, "((i<1))"
+       line 411, "pan.___", state 782, "((i>=1))"
+       line 418, "pan.___", state 789, "(1)"
+       line 418, "pan.___", state 790, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 790, "else"
+       line 418, "pan.___", state 793, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 403, "pan.___", state 828, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 846, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 872, "(1)"
+       line 418, "pan.___", state 889, "(1)"
+       line 403, "pan.___", state 918, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 936, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 979, "(1)"
+       line 399, "pan.___", state 998, "(1)"
+       line 403, "pan.___", state 1010, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1028, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1054, "(1)"
+       line 418, "pan.___", state 1071, "(1)"
+       line 403, "pan.___", state 1103, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1121, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1147, "(1)"
+       line 418, "pan.___", state 1164, "(1)"
+       line 179, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1200, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 175, "pan.___", state 1213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1235, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1252, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1261, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1300, "(1)"
+       line 399, "pan.___", state 1301, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1301, "else"
+       line 399, "pan.___", state 1304, "(1)"
+       line 403, "pan.___", state 1312, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1314, "(1)"
+       line 403, "pan.___", state 1315, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1315, "else"
+       line 403, "pan.___", state 1318, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 401, "pan.___", state 1324, "((i<1))"
+       line 401, "pan.___", state 1324, "((i>=1))"
+       line 408, "pan.___", state 1330, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1343, "(1)"
+       line 409, "pan.___", state 1344, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 1344, "else"
+       line 409, "pan.___", state 1347, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 413, "pan.___", state 1356, "(1)"
+       line 413, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 1357, "else"
+       line 413, "pan.___", state 1360, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 411, "pan.___", state 1366, "((i<1))"
+       line 411, "pan.___", state 1366, "((i>=1))"
+       line 418, "pan.___", state 1373, "(1)"
+       line 418, "pan.___", state 1374, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 1374, "else"
+       line 418, "pan.___", state 1377, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 179, "pan.___", state 1406, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1419, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 175, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1454, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1471, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1480, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1493, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 702, "pan.___", state 1520, "-end-"
+       (144 of 1520 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 125 seconds
+pan: rate 114108.44 states/second
+pan: avg transition delay 8.8279e-07 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input
new file mode 100644 (file)
index 0000000..ccf5f5c
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_RMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_free_no_rmb.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.define b/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.define
new file mode 100644 (file)
index 0000000..710f29d
--- /dev/null
@@ -0,0 +1 @@
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.log b/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.log
new file mode 100644 (file)
index 0000000..0423ec5
--- /dev/null
@@ -0,0 +1,320 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+Depth=   10656 States=    1e+06 Transitions= 8.86e+06 Memory=   534.807        t=   7.38 R=   1e+05
+Depth=   35214 States=    2e+06 Transitions= 1.82e+07 Memory=   603.557        t=   15.5 R=   1e+05
+Depth=   35214 States=    3e+06 Transitions= 2.73e+07 Memory=   672.209        t=   23.8 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=   35214 States=    4e+06 Transitions= 4.08e+07 Memory=   771.885        t=   35.9 R=   1e+05
+pan: claim violated! (at depth 1650)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 35214, errors: 1
+  4154272 states, stored
+ 38595853 states, matched
+ 42750125 transitions (= stored+matched)
+1.4058824e+08 atomic steps
+hash conflicts:  21492325 (resolved)
+
+Stats on memory usage (in Megabytes):
+  364.488      equivalent memory usage for states (stored*(State-vector + overhead))
+  292.863      actual memory usage for states (compression: 80.35%)
+               state-vector as stored = 46 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  782.529      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 227, "(1)"
+       line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 256, "(1)"
+       line 418, "pan.___", state 286, "(1)"
+       line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 366, "(1)"
+       line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 395, "(1)"
+       line 418, "pan.___", state 425, "(1)"
+       line 540, "pan.___", state 456, "-end-"
+       (19 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 70, "(1)"
+       line 418, "pan.___", state 100, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 247, "(1)"
+       line 418, "pan.___", state 277, "(1)"
+       line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 330, "(1)"
+       line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 359, "(1)"
+       line 418, "pan.___", state 389, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (18 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 401, "pan.___", state 134, "((i<1))"
+       line 401, "pan.___", state 134, "((i>=1))"
+       line 409, "pan.___", state 153, "(1)"
+       line 409, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 154, "else"
+       line 409, "pan.___", state 157, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 413, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 167, "else"
+       line 413, "pan.___", state 170, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 411, "pan.___", state 176, "((i<1))"
+       line 411, "pan.___", state 176, "((i>=1))"
+       line 418, "pan.___", state 183, "(1)"
+       line 418, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 184, "else"
+       line 418, "pan.___", state 187, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 369, "pan.___", state 193, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 646, "pan.___", state 202, "((write_lock==0))"
+       line 646, "pan.___", state 202, "else"
+       line 644, "pan.___", state 203, "(1)"
+       line 160, "pan.___", state 209, "(1)"
+       line 164, "pan.___", state 217, "(1)"
+       line 164, "pan.___", state 218, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 164, "pan.___", state 218, "else"
+       line 162, "pan.___", state 223, "((j<1))"
+       line 162, "pan.___", state 223, "((j>=1))"
+       line 168, "pan.___", state 229, "(1)"
+       line 168, "pan.___", state 230, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 168, "pan.___", state 230, "else"
+       line 160, "pan.___", state 241, "(1)"
+       line 168, "pan.___", state 261, "(1)"
+       line 160, "pan.___", state 277, "(1)"
+       line 164, "pan.___", state 285, "(1)"
+       line 168, "pan.___", state 297, "(1)"
+       line 399, "pan.___", state 311, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 325, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 343, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 356, "(1)"
+       line 413, "pan.___", state 369, "(1)"
+       line 418, "pan.___", state 386, "(1)"
+       line 399, "pan.___", state 405, "(1)"
+       line 403, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 461, "(1)"
+       line 418, "pan.___", state 478, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 164, "pan.___", state 594, "(1)"
+       line 168, "pan.___", state 606, "(1)"
+       line 160, "pan.___", state 618, "(1)"
+       line 168, "pan.___", state 638, "(1)"
+       line 164, "pan.___", state 662, "(1)"
+       line 168, "pan.___", state 674, "(1)"
+       line 399, "pan.___", state 696, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 698, "(1)"
+       line 399, "pan.___", state 699, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 699, "else"
+       line 399, "pan.___", state 702, "(1)"
+       line 403, "pan.___", state 710, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 712, "(1)"
+       line 403, "pan.___", state 713, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 713, "else"
+       line 403, "pan.___", state 716, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 401, "pan.___", state 722, "((i<1))"
+       line 401, "pan.___", state 722, "((i>=1))"
+       line 408, "pan.___", state 728, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 741, "(1)"
+       line 409, "pan.___", state 742, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 742, "else"
+       line 409, "pan.___", state 745, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 413, "pan.___", state 754, "(1)"
+       line 413, "pan.___", state 755, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 755, "else"
+       line 413, "pan.___", state 758, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 411, "pan.___", state 764, "((i<1))"
+       line 411, "pan.___", state 764, "((i>=1))"
+       line 418, "pan.___", state 771, "(1)"
+       line 418, "pan.___", state 772, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 772, "else"
+       line 418, "pan.___", state 775, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 403, "pan.___", state 810, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 828, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 854, "(1)"
+       line 418, "pan.___", state 871, "(1)"
+       line 403, "pan.___", state 900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 918, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 944, "(1)"
+       line 418, "pan.___", state 961, "(1)"
+       line 399, "pan.___", state 980, "(1)"
+       line 403, "pan.___", state 992, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1010, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1036, "(1)"
+       line 418, "pan.___", state 1053, "(1)"
+       line 403, "pan.___", state 1085, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1103, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1129, "(1)"
+       line 418, "pan.___", state 1146, "(1)"
+       line 164, "pan.___", state 1169, "(1)"
+       line 168, "pan.___", state 1181, "(1)"
+       line 160, "pan.___", state 1193, "(1)"
+       line 168, "pan.___", state 1213, "(1)"
+       line 164, "pan.___", state 1237, "(1)"
+       line 168, "pan.___", state 1249, "(1)"
+       line 399, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1273, "(1)"
+       line 399, "pan.___", state 1274, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1274, "else"
+       line 399, "pan.___", state 1277, "(1)"
+       line 403, "pan.___", state 1285, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1287, "(1)"
+       line 403, "pan.___", state 1288, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1288, "else"
+       line 403, "pan.___", state 1291, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 401, "pan.___", state 1297, "((i<1))"
+       line 401, "pan.___", state 1297, "((i>=1))"
+       line 408, "pan.___", state 1303, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1316, "(1)"
+       line 409, "pan.___", state 1317, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 1317, "else"
+       line 409, "pan.___", state 1320, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 413, "pan.___", state 1329, "(1)"
+       line 413, "pan.___", state 1330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 1330, "else"
+       line 413, "pan.___", state 1333, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 411, "pan.___", state 1339, "((i<1))"
+       line 411, "pan.___", state 1339, "((i>=1))"
+       line 418, "pan.___", state 1346, "(1)"
+       line 418, "pan.___", state 1347, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 1347, "else"
+       line 418, "pan.___", state 1350, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 164, "pan.___", state 1379, "(1)"
+       line 168, "pan.___", state 1391, "(1)"
+       line 160, "pan.___", state 1403, "(1)"
+       line 168, "pan.___", state 1423, "(1)"
+       line 164, "pan.___", state 1447, "(1)"
+       line 168, "pan.___", state 1459, "(1)"
+       line 702, "pan.___", state 1484, "-end-"
+       (160 of 1484 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 37.6 seconds
+pan: rate 110515.35 states/second
+pan: avg transition delay 8.793e-07 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input
new file mode 100644 (file)
index 0000000..d5d174d
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_free_no_wmb.spin.input.trail
new file mode 100644 (file)
index 0000000..f2ce974
--- /dev/null
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+1632:3:2309
+1633:3:2310
+1634:3:2317
+1635:3:2322
+1636:0:2399
+1637:3:2333
+1638:0:2399
+1639:3:2335
+1640:0:2399
+1641:3:2336
+1642:0:2399
+1643:3:2339
+1644:0:2399
+1645:3:2344
+1646:0:2399
+1647:2:759
+1648:0:2397
+1649:3:2345
+1650:0:2403
+1651:2:518
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.define b/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.define
new file mode 100644 (file)
index 0000000..5e642ef
--- /dev/null
@@ -0,0 +1 @@
+#define SINGLE_FLIP
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.log b/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.log
new file mode 100644 (file)
index 0000000..5d7d35c
--- /dev/null
@@ -0,0 +1,217 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+Depth=    8352 States=    1e+06 Transitions= 1.05e+07 Memory=   534.807        t=   8.93 R=   1e+05
+pan: claim violated! (at depth 1352)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 8352, errors: 1
+  1456373 states, stored
+ 13442538 states, matched
+ 14898911 transitions (= stored+matched)
+ 50580660 atomic steps
+hash conflicts:   5166006 (resolved)
+
+Stats on memory usage (in Megabytes):
+  127.779      equivalent memory usage for states (stored*(State-vector + overhead))
+  100.443      actual memory usage for states (compression: 78.61%)
+               state-vector as stored = 44 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  566.154      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 256, "(1)"
+       line 418, "pan.___", state 286, "(1)"
+       line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 395, "(1)"
+       line 418, "pan.___", state 425, "(1)"
+       line 540, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 70, "(1)"
+       line 418, "pan.___", state 100, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 247, "(1)"
+       line 418, "pan.___", state 277, "(1)"
+       line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 359, "(1)"
+       line 418, "pan.___", state 389, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 179, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1003, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1013, "(1)"
+       line 164, "pan.___", state 1021, "(1)"
+       line 168, "pan.___", state 1033, "(1)"
+       line 175, "pan.___", state 1044, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1066, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1076, "(1)"
+       line 164, "pan.___", state 1084, "(1)"
+       line 168, "pan.___", state 1096, "(1)"
+       line 175, "pan.___", state 1111, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1133, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1143, "(1)"
+       line 164, "pan.___", state 1151, "(1)"
+       line 168, "pan.___", state 1163, "(1)"
+       line 702, "pan.___", state 1188, "-end-"
+       (100 of 1188 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 12.8 seconds
+pan: rate 113424.69 states/second
+pan: avg transition delay 8.6181e-07 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input
new file mode 100644 (file)
index 0000000..103464e
--- /dev/null
@@ -0,0 +1,723 @@
+#define SINGLE_FLIP
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_free_single_flip.spin.input.trail
new file mode 100644 (file)
index 0000000..e81c46c
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diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress.ltl b/formal-model/urcu/result-signal-over-reader/urcu_progress.ltl
new file mode 100644 (file)
index 0000000..8718641
--- /dev/null
@@ -0,0 +1 @@
+([] <> !np_)
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.define b/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.define
new file mode 100644 (file)
index 0000000..ff3f783
--- /dev/null
@@ -0,0 +1 @@
+#define READER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.log b/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.log
new file mode 100644 (file)
index 0000000..e3ec127
--- /dev/null
@@ -0,0 +1,506 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 1803: Claim reached state 9 (line 748)
+Depth=    5838 States=    1e+06 Transitions= 1.06e+07 Memory=   494.865        t=   9.24 R=   1e+05
+Depth=    5838 States=    2e+06 Transitions= 1.97e+07 Memory=   532.658        t=   17.7 R=   1e+05
+Depth=    5838 States=    3e+06 Transitions= 3.15e+07 Memory=   555.315        t=   28.4 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=    6855 States=    4e+06 Transitions= 4.32e+07 Memory=   613.096        t=   39.1 R=   1e+05
+Depth=    9059 States=    5e+06 Transitions= 5.48e+07 Memory=   642.295        t=   49.5 R=   1e+05
+Depth=    9059 States=    6e+06 Transitions= 6.91e+07 Memory=   672.178        t=   62.5 R=   1e+05
+Depth=    9059 States=    7e+06 Transitions= 7.99e+07 Memory=   706.455        t=   72.5 R=   1e+05
+Depth=    9059 States=    8e+06 Transitions= 9.23e+07 Memory=   735.752        t=     84 R=   1e+05
+Depth=    9059 States=    9e+06 Transitions= 1.04e+08 Memory=   766.318        t=   94.5 R=   1e+05
+pan: resizing hashtable to -w24..  done
+Depth=    9059 States=    1e+07 Transitions= 1.16e+08 Memory=   920.002        t=    106 R=   9e+04
+Depth=    9059 States=  1.1e+07 Transitions=  1.3e+08 Memory=   945.002        t=    119 R=   9e+04
+Depth=    9059 States=  1.2e+07 Transitions= 1.54e+08 Memory=   967.756        t=    140 R=   9e+04
+Depth=    9059 States=  1.3e+07 Transitions= 1.72e+08 Memory=   995.002        t=    157 R=   8e+04
+Depth=    9059 States=  1.4e+07 Transitions= 1.92e+08 Memory=  1022.736        t=    175 R=   8e+04
+Depth=    9059 States=  1.5e+07 Transitions=  2.1e+08 Memory=  1050.080        t=    191 R=   8e+04
+Depth=    9059 States=  1.6e+07 Transitions= 2.22e+08 Memory=  1082.502        t=    203 R=   8e+04
+Depth=    9059 States=  1.7e+07 Transitions= 2.41e+08 Memory=  1108.479        t=    219 R=   8e+04
+Depth=    9059 States=  1.8e+07 Transitions= 2.58e+08 Memory=  1134.455        t=    235 R=   8e+04
+Depth=    9059 States=  1.9e+07 Transitions=  2.7e+08 Memory=  1164.533        t=    246 R=   8e+04
+Depth=    9059 States=    2e+07 Transitions= 2.83e+08 Memory=  1193.830        t=    258 R=   8e+04
+Depth=    9059 States=  2.1e+07 Transitions= 3.03e+08 Memory=  1219.026        t=    276 R=   8e+04
+Depth=    9059 States=  2.2e+07 Transitions= 3.19e+08 Memory=  1248.420        t=    291 R=   8e+04
+Depth=    9059 States=  2.3e+07 Transitions= 3.42e+08 Memory=  1271.858        t=    312 R=   7e+04
+Depth=    9059 States=  2.4e+07 Transitions=  3.6e+08 Memory=  1298.908        t=    328 R=   7e+04
+Depth=    9059 States=  2.5e+07 Transitions= 3.84e+08 Memory=  1323.127        t=    350 R=   7e+04
+Depth=    9059 States=  2.6e+07 Transitions=    4e+08 Memory=  1348.518        t=    365 R=   7e+04
+Depth=    9059 States=  2.7e+07 Transitions= 4.16e+08 Memory=  1379.865        t=    380 R=   7e+04
+Depth=    9059 States=  2.8e+07 Transitions= 4.26e+08 Memory=  1411.115        t=    389 R=   7e+04
+Depth=    9059 States=  2.9e+07 Transitions= 4.42e+08 Memory=  1439.631        t=    404 R=   7e+04
+Depth=    9059 States=    3e+07 Transitions= 4.64e+08 Memory=  1462.385        t=    423 R=   7e+04
+Depth=    9059 States=  3.1e+07 Transitions= 4.82e+08 Memory=  1490.998        t=    439 R=   7e+04
+Depth=    9059 States=  3.2e+07 Transitions= 4.99e+08 Memory=  1519.514        t=    456 R=   7e+04
+Depth=    9059 States=  3.3e+07 Transitions= 5.18e+08 Memory=  1545.393        t=    473 R=   7e+04
+Depth=    9059 States=  3.4e+07 Transitions= 5.33e+08 Memory=  1578.108        t=    486 R=   7e+04
+pan: resizing hashtable to -w26..  done
+Depth=    9059 States=  3.5e+07 Transitions= 5.49e+08 Memory=  2098.994        t=    504 R=   7e+04
+Depth=    9059 States=  3.6e+07 Transitions= 5.74e+08 Memory=  2121.651        t=    528 R=   7e+04
+Depth=    9059 States=  3.7e+07 Transitions= 5.96e+08 Memory=  2147.334        t=    547 R=   7e+04
+Depth=    9059 States=  3.8e+07 Transitions= 6.17e+08 Memory=  2170.186        t=    567 R=   7e+04
+Depth=    9059 States=  3.9e+07 Transitions=  6.3e+08 Memory=  2199.776        t=    578 R=   7e+04
+Depth=    9059 States=    4e+07 Transitions= 6.53e+08 Memory=  2225.459        t=    599 R=   7e+04
+Depth=    9059 States=  4.1e+07 Transitions= 6.69e+08 Memory=  2250.361        t=    614 R=   7e+04
+Depth=    9059 States=  4.2e+07 Transitions= 6.85e+08 Memory=  2279.268        t=    628 R=   7e+04
+Depth=    9059 States=  4.3e+07 Transitions= 7.03e+08 Memory=  2304.463        t=    644 R=   7e+04
+Depth=    9059 States=  4.4e+07 Transitions= 7.13e+08 Memory=  2338.252        t=    654 R=   7e+04
+Depth=    9059 States=  4.5e+07 Transitions= 7.25e+08 Memory=  2366.768        t=    665 R=   7e+04
+Depth=    9059 States=  4.6e+07 Transitions= 7.41e+08 Memory=  2393.330        t=    679 R=   7e+04
+Depth=    9059 States=  4.7e+07 Transitions= 7.57e+08 Memory=  2420.381        t=    694 R=   7e+04
+Depth=    9059 States=  4.8e+07 Transitions= 7.72e+08 Memory=  2447.041        t=    708 R=   7e+04
+Depth=    9059 States=  4.9e+07 Transitions= 7.88e+08 Memory=  2476.143        t=    722 R=   7e+04
+Depth=    9059 States=    5e+07 Transitions= 8.04e+08 Memory=  2501.045        t=    737 R=   7e+04
+Depth=    9059 States=  5.1e+07 Transitions=  8.2e+08 Memory=  2530.440        t=    752 R=   7e+04
+Depth=    9059 States=  5.2e+07 Transitions= 8.37e+08 Memory=  2554.854        t=    766 R=   7e+04
+Depth=    9059 States=  5.3e+07 Transitions=  8.5e+08 Memory=  2583.467        t=    779 R=   7e+04
+Depth=    9059 States=  5.4e+07 Transitions= 8.66e+08 Memory=  2611.299        t=    794 R=   7e+04
+Depth=    9059 States=  5.5e+07 Transitions= 8.79e+08 Memory=  2640.791        t=    805 R=   7e+04
+Depth=    9059 States=  5.6e+07 Transitions=  8.9e+08 Memory=  2672.139        t=    815 R=   7e+04
+Depth=    9059 States=  5.7e+07 Transitions= 9.05e+08 Memory=  2702.705        t=    829 R=   7e+04
+Depth=    9059 States=  5.8e+07 Transitions= 9.22e+08 Memory=  2727.998        t=    845 R=   7e+04
+Depth=    9059 States=  5.9e+07 Transitions= 9.38e+08 Memory=  2754.463        t=    859 R=   7e+04
+Depth=    9059 States=    6e+07 Transitions= 9.49e+08 Memory=  2789.717        t=    870 R=   7e+04
+Depth=    9059 States=  6.1e+07 Transitions= 9.62e+08 Memory=  2817.744        t=    881 R=   7e+04
+Depth=    9059 States=  6.2e+07 Transitions= 9.79e+08 Memory=  2838.447        t=    896 R=   7e+04
+Depth=    9059 States=  6.3e+07 Transitions=    1e+09 Memory=  2863.154        t=    919 R=   7e+04
+Depth=    9059 States=  6.4e+07 Transitions= 1.02e+09 Memory=  2889.131        t=    936 R=   7e+04
+Depth=    9059 States=  6.5e+07 Transitions= 1.04e+09 Memory=  2919.502        t=    952 R=   7e+04
+Depth=    9059 States=  6.6e+07 Transitions= 1.06e+09 Memory=  2943.916        t=    968 R=   7e+04
+Depth=    9059 States=  6.7e+07 Transitions= 1.07e+09 Memory=  2978.975        t=    979 R=   7e+04
+Depth=    9059 States=  6.8e+07 Transitions= 1.09e+09 Memory=  3003.877        t=    996 R=   7e+04
+Depth=    9059 States=  6.9e+07 Transitions= 1.11e+09 Memory=  3028.584        t= 1.01e+03 R=   7e+04
+Depth=    9059 States=    7e+07 Transitions= 1.12e+09 Memory=  3058.174        t= 1.02e+03 R=   7e+04
+Depth=    9059 States=  7.1e+07 Transitions= 1.13e+09 Memory=  3088.350        t= 1.04e+03 R=   7e+04
+Depth=    9059 States=  7.2e+07 Transitions= 1.15e+09 Memory=  3113.350        t= 1.05e+03 R=   7e+04
+Depth=    9059 States=  7.3e+07 Transitions= 1.17e+09 Memory=  3142.158        t= 1.07e+03 R=   7e+04
+Depth=    9059 States=  7.4e+07 Transitions= 1.19e+09 Memory=  3166.279        t= 1.09e+03 R=   7e+04
+Depth=    9059 States=  7.5e+07 Transitions= 1.21e+09 Memory=  3192.744        t= 1.11e+03 R=   7e+04
+Depth=    9059 States=  7.6e+07 Transitions= 1.23e+09 Memory=  3217.256        t= 1.13e+03 R=   7e+04
+Depth=    9059 States=  7.7e+07 Transitions= 1.25e+09 Memory=  3242.549        t= 1.14e+03 R=   7e+04
+Depth=    9059 States=  7.8e+07 Transitions= 1.26e+09 Memory=  3273.115        t= 1.16e+03 R=   7e+04
+Depth=    9059 States=  7.9e+07 Transitions= 1.27e+09 Memory=  3303.975        t= 1.17e+03 R=   7e+04
+Depth=    9059 States=    8e+07 Transitions= 1.29e+09 Memory=  3334.541        t= 1.18e+03 R=   7e+04
+Depth=    9059 States=  8.1e+07 Transitions= 1.31e+09 Memory=  3356.221        t= 1.2e+03 R=   7e+04
+Depth=    9059 States=  8.2e+07 Transitions= 1.33e+09 Memory=  3385.127        t= 1.22e+03 R=   7e+04
+Depth=    9059 States=  8.3e+07 Transitions= 1.35e+09 Memory=  3412.959        t= 1.23e+03 R=   7e+04
+Depth=    9059 States=  8.4e+07 Transitions= 1.37e+09 Memory=  3438.936        t= 1.25e+03 R=   7e+04
+Depth=    9059 States=  8.5e+07 Transitions= 1.38e+09 Memory=  3471.455        t= 1.26e+03 R=   7e+04
+Depth=    9059 States=  8.6e+07 Transitions=  1.4e+09 Memory=  3498.115        t= 1.28e+03 R=   7e+04
+Depth=    9059 States=  8.7e+07 Transitions= 1.42e+09 Memory=  3519.014        t= 1.3e+03 R=   7e+04
+Depth=    9059 States=  8.8e+07 Transitions= 1.44e+09 Memory=  3546.162        t= 1.32e+03 R=   7e+04
+Depth=    9059 States=  8.9e+07 Transitions= 1.46e+09 Memory=  3567.842        t= 1.34e+03 R=   7e+04
+Depth=    9059 States=    9e+07 Transitions= 1.48e+09 Memory=  3598.799        t= 1.35e+03 R=   7e+04
+Depth=    9059 States=  9.1e+07 Transitions=  1.5e+09 Memory=  3622.920        t= 1.37e+03 R=   7e+04
+Depth=    9059 States=  9.2e+07 Transitions= 1.52e+09 Memory=  3648.701        t= 1.39e+03 R=   7e+04
+Depth=    9059 States=  9.3e+07 Transitions= 1.53e+09 Memory=  3676.045        t= 1.4e+03 R=   7e+04
+Depth=    9059 States=  9.4e+07 Transitions= 1.55e+09 Memory=  3702.412        t= 1.42e+03 R=   7e+04
+Depth=    9059 States=  9.5e+07 Transitions= 1.56e+09 Memory=  3735.713        t= 1.43e+03 R=   7e+04
+Depth=    9059 States=  9.6e+07 Transitions= 1.57e+09 Memory=  3764.522        t= 1.44e+03 R=   7e+04
+Depth=    9059 States=  9.7e+07 Transitions= 1.59e+09 Memory=  3790.693        t= 1.45e+03 R=   7e+04
+Depth=    9059 States=  9.8e+07 Transitions= 1.61e+09 Memory=  3817.940        t= 1.47e+03 R=   7e+04
+Depth=    9059 States=  9.9e+07 Transitions= 1.62e+09 Memory=  3845.283        t= 1.48e+03 R=   7e+04
+Depth=    9059 States=    1e+08 Transitions= 1.64e+09 Memory=  3873.213        t= 1.5e+03 R=   7e+04
+Depth=    9059 States= 1.01e+08 Transitions= 1.65e+09 Memory=  3897.920        t= 1.51e+03 R=   7e+04
+Depth=    9059 States= 1.02e+08 Transitions= 1.67e+09 Memory=  3926.631        t= 1.53e+03 R=   7e+04
+Depth=    9059 States= 1.03e+08 Transitions= 1.68e+09 Memory=  3952.315        t= 1.54e+03 R=   7e+04
+Depth=    9059 States= 1.04e+08 Transitions=  1.7e+09 Memory=  3981.026        t= 1.56e+03 R=   7e+04
+Depth=    9059 States= 1.05e+08 Transitions= 1.71e+09 Memory=  4010.029        t= 1.57e+03 R=   7e+04
+Depth=    9059 States= 1.06e+08 Transitions= 1.73e+09 Memory=  4038.838        t= 1.58e+03 R=   7e+04
+Depth=    9059 States= 1.07e+08 Transitions= 1.74e+09 Memory=  4070.381        t= 1.59e+03 R=   7e+04
+Depth=    9059 States= 1.08e+08 Transitions= 1.75e+09 Memory=  4099.385        t= 1.61e+03 R=   7e+04
+Depth=    9059 States= 1.09e+08 Transitions= 1.77e+09 Memory=  4126.338        t= 1.62e+03 R=   7e+04
+Depth=    9059 States=  1.1e+08 Transitions= 1.79e+09 Memory=  4151.924        t= 1.64e+03 R=   7e+04
+Depth=    9059 States= 1.11e+08 Transitions=  1.8e+09 Memory=  4187.276        t= 1.65e+03 R=   7e+04
+Depth=    9059 States= 1.12e+08 Transitions= 1.81e+09 Memory=  4214.326        t= 1.66e+03 R=   7e+04
+Depth=    9059 States= 1.13e+08 Transitions= 1.83e+09 Memory=  4237.471        t= 1.67e+03 R=   7e+04
+Depth=    9059 States= 1.14e+08 Transitions= 1.85e+09 Memory=  4261.104        t= 1.7e+03 R=   7e+04
+Depth=    9059 States= 1.15e+08 Transitions= 1.87e+09 Memory=  4286.690        t= 1.71e+03 R=   7e+04
+Depth=    9059 States= 1.16e+08 Transitions= 1.89e+09 Memory=  4314.619        t= 1.73e+03 R=   7e+04
+Depth=    9059 States= 1.17e+08 Transitions= 1.91e+09 Memory=  4341.768        t= 1.75e+03 R=   7e+04
+Depth=    9059 States= 1.18e+08 Transitions= 1.92e+09 Memory=  4375.166        t= 1.76e+03 R=   7e+04
+Depth=    9059 States= 1.19e+08 Transitions= 1.94e+09 Memory=  4401.338        t= 1.78e+03 R=   7e+04
+Depth=    9059 States=  1.2e+08 Transitions= 1.95e+09 Memory=  4426.436        t= 1.79e+03 R=   7e+04
+Depth=    9059 States= 1.21e+08 Transitions= 1.97e+09 Memory=  4456.807        t= 1.8e+03 R=   7e+04
+Depth=    9059 States= 1.22e+08 Transitions= 1.98e+09 Memory=  4486.592        t= 1.82e+03 R=   7e+04
+Depth=    9059 States= 1.23e+08 Transitions=    2e+09 Memory=  4511.787        t= 1.83e+03 R=   7e+04
+Depth=    9059 States= 1.24e+08 Transitions= 2.02e+09 Memory=  4540.108        t= 1.85e+03 R=   7e+04
+Depth=    9059 States= 1.25e+08 Transitions= 2.04e+09 Memory=  4564.033        t= 1.87e+03 R=   7e+04
+Depth=    9059 States= 1.26e+08 Transitions= 2.06e+09 Memory=  4591.865        t= 1.89e+03 R=   7e+04
+Depth=    9059 States= 1.27e+08 Transitions= 2.08e+09 Memory=  4615.889        t= 1.91e+03 R=   7e+04
+Depth=    9059 States= 1.28e+08 Transitions=  2.1e+09 Memory=  4640.303        t= 1.92e+03 R=   7e+04
+Depth=    9059 States= 1.29e+08 Transitions= 2.11e+09 Memory=  4670.479        t= 1.94e+03 R=   7e+04
+Depth=    9059 States=  1.3e+08 Transitions= 2.12e+09 Memory=  4702.998        t= 1.95e+03 R=   7e+04
+Depth=    9059 States= 1.31e+08 Transitions= 2.14e+09 Memory=  4732.393        t= 1.96e+03 R=   7e+04
+Depth=    9059 States= 1.32e+08 Transitions= 2.16e+09 Memory=  4754.756        t= 1.98e+03 R=   7e+04
+Depth=    9059 States= 1.33e+08 Transitions= 2.18e+09 Memory=  4783.174        t=  2e+03 R=   7e+04
+Depth=    9059 States= 1.34e+08 Transitions= 2.19e+09 Memory=  4810.518        t= 2.01e+03 R=   7e+04
+Depth=    9059 States= 1.35e+08 Transitions= 2.21e+09 Memory=  4837.568        t= 2.03e+03 R=   7e+04
+pan: resizing hashtable to -w28..  done
+Depth=    9059 States= 1.36e+08 Transitions= 2.23e+09 Memory=  6885.568        t= 2.06e+03 R=   7e+04
+Depth=    9059 States= 1.37e+08 Transitions= 2.24e+09 Memory=  6885.568        t= 2.08e+03 R=   7e+04
+Depth=    9059 States= 1.38e+08 Transitions= 2.27e+09 Memory=  6900.412        t= 2.1e+03 R=   7e+04
+Depth=    9059 States= 1.39e+08 Transitions= 2.29e+09 Memory=  6927.658        t= 2.12e+03 R=   7e+04
+Depth=    9059 States=  1.4e+08 Transitions= 2.31e+09 Memory=  6950.315        t= 2.14e+03 R=   7e+04
+Depth=    9059 States= 1.41e+08 Transitions= 2.33e+09 Memory=  6981.858        t= 2.15e+03 R=   7e+04
+Depth=    9059 States= 1.42e+08 Transitions= 2.35e+09 Memory=  7005.295        t= 2.17e+03 R=   7e+04
+Depth=    9059 States= 1.43e+08 Transitions= 2.36e+09 Memory=  7031.076        t= 2.18e+03 R=   7e+04
+Depth=    9059 States= 1.44e+08 Transitions= 2.38e+09 Memory=  7056.955        t= 2.2e+03 R=   7e+04
+Depth=    9059 States= 1.45e+08 Transitions=  2.4e+09 Memory=  7084.494        t= 2.22e+03 R=   7e+04
+Depth=    9059 States= 1.46e+08 Transitions= 2.41e+09 Memory=  7115.744        t= 2.23e+03 R=   7e+04
+Depth=    9059 States= 1.47e+08 Transitions= 2.42e+09 Memory=  7146.604        t= 2.24e+03 R=   7e+04
+Depth=    9059 States= 1.48e+08 Transitions= 2.44e+09 Memory=  7172.287        t= 2.25e+03 R=   7e+04
+Depth=    9059 States= 1.49e+08 Transitions= 2.45e+09 Memory=  7200.315        t= 2.26e+03 R=   7e+04
+Depth=    9059 States=  1.5e+08 Transitions= 2.47e+09 Memory=  7226.389        t= 2.28e+03 R=   7e+04
+Depth=    9059 States= 1.51e+08 Transitions= 2.48e+09 Memory=  7253.733        t= 2.29e+03 R=   7e+04
+Depth=    9059 States= 1.52e+08 Transitions=  2.5e+09 Memory=  7279.709        t= 2.31e+03 R=   7e+04
+Depth=    9059 States= 1.53e+08 Transitions= 2.52e+09 Memory=  7309.104        t= 2.32e+03 R=   7e+04
+Depth=    9059 States= 1.54e+08 Transitions= 2.53e+09 Memory=  7334.592        t= 2.34e+03 R=   7e+04
+Depth=    9059 States= 1.55e+08 Transitions= 2.55e+09 Memory=  7362.229        t= 2.35e+03 R=   7e+04
+Depth=    9059 States= 1.56e+08 Transitions= 2.56e+09 Memory=  7391.135        t= 2.36e+03 R=   7e+04
+Depth=    9059 States= 1.57e+08 Transitions= 2.57e+09 Memory=  7420.822        t= 2.38e+03 R=   7e+04
+Depth=    9059 States= 1.58e+08 Transitions= 2.59e+09 Memory=  7452.854        t= 2.39e+03 R=   7e+04
+Depth=    9059 States= 1.59e+08 Transitions=  2.6e+09 Memory=  7481.760        t= 2.4e+03 R=   7e+04
+Depth=    9059 States=  1.6e+08 Transitions= 2.62e+09 Memory=  7509.299        t= 2.41e+03 R=   7e+04
+Depth=    9059 States= 1.61e+08 Transitions= 2.63e+09 Memory=  7534.201        t= 2.43e+03 R=   7e+04
+Depth=    9059 States= 1.62e+08 Transitions= 2.65e+09 Memory=  7567.600        t= 2.44e+03 R=   7e+04
+Depth=    9059 States= 1.63e+08 Transitions= 2.66e+09 Memory=  7594.846        t= 2.45e+03 R=   7e+04
+Depth=    9059 States= 1.64e+08 Transitions= 2.67e+09 Memory=  7619.455        t= 2.47e+03 R=   7e+04
+Depth=    9059 States= 1.65e+08 Transitions=  2.7e+09 Memory=  7642.502        t= 2.49e+03 R=   7e+04
+Depth=    9059 States= 1.66e+08 Transitions= 2.72e+09 Memory=  7669.260        t= 2.51e+03 R=   7e+04
+Depth=    9059 States= 1.67e+08 Transitions= 2.73e+09 Memory=  7696.799        t= 2.52e+03 R=   7e+04
+Depth=    9059 States= 1.68e+08 Transitions= 2.75e+09 Memory=  7723.850        t= 2.54e+03 R=   7e+04
+Depth=    9059 States= 1.69e+08 Transitions= 2.77e+09 Memory=  7757.053        t= 2.55e+03 R=   7e+04
+Depth=    9059 States=  1.7e+08 Transitions= 2.78e+09 Memory=  7782.346        t= 2.57e+03 R=   7e+04
+Depth=    9059 States= 1.71e+08 Transitions=  2.8e+09 Memory=  7808.908        t= 2.58e+03 R=   7e+04
+Depth=    9059 States= 1.72e+08 Transitions= 2.81e+09 Memory=  7838.791        t= 2.59e+03 R=   7e+04
+Depth=    9059 States= 1.73e+08 Transitions= 2.83e+09 Memory=  7867.893        t= 2.61e+03 R=   7e+04
+Depth=    9059 States= 1.74e+08 Transitions= 2.85e+09 Memory=  7892.990        t= 2.62e+03 R=   7e+04
+Depth=    9059 States= 1.75e+08 Transitions= 2.86e+09 Memory=  7922.190        t= 2.64e+03 R=   7e+04
+Depth=    9059 States= 1.76e+08 Transitions= 2.89e+09 Memory=  7945.627        t= 2.66e+03 R=   7e+04
+Depth=    9059 States= 1.77e+08 Transitions=  2.9e+09 Memory=  7973.947        t= 2.68e+03 R=   7e+04
+Depth=    9059 States= 1.78e+08 Transitions= 2.93e+09 Memory=  7997.483        t= 2.7e+03 R=   7e+04
+Depth=    9059 States= 1.79e+08 Transitions= 2.94e+09 Memory=  8020.920        t= 2.71e+03 R=   7e+04
+Depth=    9059 States=  1.8e+08 Transitions= 2.96e+09 Memory=  8050.412        t= 2.73e+03 R=   7e+04
+Depth=    9059 States= 1.81e+08 Transitions= 2.97e+09 Memory=  8085.666        t= 2.74e+03 R=   7e+04
+Depth=    9059 States= 1.82e+08 Transitions= 2.98e+09 Memory=  8114.279        t= 2.75e+03 R=   7e+04
+Depth=    9059 States= 1.83e+08 Transitions=    3e+09 Memory=  8137.131        t= 2.77e+03 R=   7e+04
+Depth=    9059 States= 1.84e+08 Transitions= 3.02e+09 Memory=  8165.451        t= 2.79e+03 R=   7e+04
+Depth=    9059 States= 1.85e+08 Transitions= 3.04e+09 Memory=  8193.186        t= 2.8e+03 R=   7e+04
+Depth=    9059 States= 1.86e+08 Transitions= 3.06e+09 Memory=  8218.674        t= 2.82e+03 R=   7e+04
+Depth=    9059 States= 1.87e+08 Transitions= 3.08e+09 Memory=  8255.100        t= 2.83e+03 R=   7e+04
+Depth=    9059 States= 1.88e+08 Transitions= 3.09e+09 Memory=  8279.221        t= 2.85e+03 R=   7e+04
+Depth=    9059 States= 1.89e+08 Transitions= 3.12e+09 Memory=  8298.264        t= 2.87e+03 R=   7e+04
+Depth=    9059 States=  1.9e+08 Transitions= 3.14e+09 Memory=  8325.998        t= 2.89e+03 R=   7e+04
+Depth=    9059 States= 1.91e+08 Transitions= 3.16e+09 Memory=  8349.338        t= 2.91e+03 R=   7e+04
+Depth=    9059 States= 1.92e+08 Transitions= 3.17e+09 Memory=  8379.221        t= 2.92e+03 R=   7e+04
+Depth=    9059 States= 1.93e+08 Transitions= 3.19e+09 Memory=  8403.440        t= 2.94e+03 R=   7e+04
+Depth=    9059 States= 1.94e+08 Transitions= 3.21e+09 Memory=  8430.100        t= 2.96e+03 R=   7e+04
+Depth=    9059 States= 1.95e+08 Transitions= 3.23e+09 Memory=  8455.295        t= 2.97e+03 R=   7e+04
+Depth=    9059 States= 1.96e+08 Transitions= 3.25e+09 Memory=  8482.932        t= 2.99e+03 R=   7e+04
+Depth=    9059 States= 1.97e+08 Transitions= 3.26e+09 Memory=  8515.256        t=  3e+03 R=   7e+04
+Depth=    9059 States= 1.98e+08 Transitions= 3.27e+09 Memory=  8542.502        t= 3.01e+03 R=   7e+04
+Depth=    9059 States= 1.99e+08 Transitions= 3.29e+09 Memory=  8569.260        t= 3.02e+03 R=   7e+04
+Depth=    9059 States=    2e+08 Transitions=  3.3e+09 Memory=  8598.459        t= 3.04e+03 R=   7e+04
+Depth=    9059 States= 2.01e+08 Transitions= 3.32e+09 Memory=  8624.631        t= 3.05e+03 R=   7e+04
+Depth=    9059 States= 2.02e+08 Transitions= 3.33e+09 Memory=  8652.365        t= 3.07e+03 R=   7e+04
+Depth=    9059 States= 2.03e+08 Transitions= 3.35e+09 Memory=  8678.440        t= 3.08e+03 R=   7e+04
+Depth=    9059 States= 2.04e+08 Transitions= 3.36e+09 Memory=  8706.369        t= 3.1e+03 R=   7e+04
+Depth=    9059 States= 2.05e+08 Transitions= 3.38e+09 Memory=  8732.932        t= 3.11e+03 R=   7e+04
+Depth=    9059 States= 2.06e+08 Transitions= 3.39e+09 Memory=  8760.276        t= 3.12e+03 R=   7e+04
+Depth=    9059 States= 2.07e+08 Transitions= 3.41e+09 Memory=  8789.475        t= 3.14e+03 R=   7e+04
+Depth=    9059 States= 2.08e+08 Transitions= 3.42e+09 Memory=  8819.455        t= 3.15e+03 R=   7e+04
+Depth=    9059 States= 2.09e+08 Transitions= 3.43e+09 Memory=  8851.779        t= 3.16e+03 R=   7e+04
+Depth=    9059 States=  2.1e+08 Transitions= 3.45e+09 Memory=  8880.100        t= 3.17e+03 R=   7e+04
+Depth=    9059 States= 2.11e+08 Transitions= 3.46e+09 Memory=  8907.053        t= 3.19e+03 R=   7e+04
+Depth=    9059 States= 2.12e+08 Transitions= 3.48e+09 Memory=  8932.639        t= 3.2e+03 R=   7e+04
+Depth=    9059 States= 2.13e+08 Transitions= 3.49e+09 Memory=  8964.572        t= 3.22e+03 R=   7e+04
+Depth=    9059 States= 2.14e+08 Transitions= 3.51e+09 Memory=  8991.526        t= 3.23e+03 R=   7e+04
+Depth=    9059 States= 2.15e+08 Transitions= 3.52e+09 Memory=  9018.088        t= 3.24e+03 R=   7e+04
+Depth=    9059 States= 2.16e+08 Transitions= 3.54e+09 Memory=  9039.865        t= 3.26e+03 R=   7e+04
+Depth=    9059 States= 2.17e+08 Transitions= 3.56e+09 Memory=  9067.600        t= 3.28e+03 R=   7e+04
+Depth=    9059 States= 2.18e+08 Transitions= 3.58e+09 Memory=  9094.260        t= 3.3e+03 R=   7e+04
+Depth=    9059 States= 2.19e+08 Transitions=  3.6e+09 Memory=  9122.483        t= 3.31e+03 R=   7e+04
+Depth=    9059 States=  2.2e+08 Transitions= 3.61e+09 Memory=  9153.635        t= 3.32e+03 R=   7e+04
+Depth=    9059 States= 2.21e+08 Transitions= 3.63e+09 Memory=  9181.272        t= 3.34e+03 R=   7e+04
+Depth=    9059 States= 2.22e+08 Transitions= 3.65e+09 Memory=  9207.639        t= 3.36e+03 R=   7e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 9059, errors: 0
+ 88961904 states, stored (2.22145e+08 visited)
+3.4291111e+09 states, matched
+3.6512561e+09 transitions (= visited+matched)
+1.2885947e+10 atomic steps
+hash conflicts: 7.2188776e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7805.343      equivalent memory usage for states (stored*(State-vector + overhead))
+ 6706.219      actual memory usage for states (compression: 85.92%)
+               state-vector as stored = 51 byte + 28 byte overhead
+ 2048.000      memory used for hash table (-w28)
+  457.764      memory used for DFS stack (-m10000000)
+    1.122      memory lost to fragmentation
+ 9210.861      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 256, "(1)"
+       line 418, "pan.___", state 286, "(1)"
+       line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 395, "(1)"
+       line 418, "pan.___", state 425, "(1)"
+       line 540, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 70, "(1)"
+       line 418, "pan.___", state 100, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 247, "(1)"
+       line 418, "pan.___", state 277, "(1)"
+       line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 359, "(1)"
+       line 418, "pan.___", state 389, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 3.36e+03 seconds
+pan: rate 66138.803 states/second
+pan: avg transition delay 9.1989e-07 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input
new file mode 100644 (file)
index 0000000..91b1126
--- /dev/null
@@ -0,0 +1,723 @@
+#define READER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_progress_reader.spin.input.trail
new file mode 100644 (file)
index 0000000..7c42af1
--- /dev/null
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diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.define b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.define
new file mode 100644 (file)
index 0000000..1e4417f
--- /dev/null
@@ -0,0 +1 @@
+#define WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.log b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.log
new file mode 100644 (file)
index 0000000..fc83245
--- /dev/null
@@ -0,0 +1,524 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 1194: Claim reached state 9 (line 748)
+Depth=    3253 States=    1e+06 Transitions= 1.06e+07 Memory=   484.416        t=   9.64 R=   1e+05
+Depth=    3253 States=    2e+06 Transitions= 2.04e+07 Memory=   501.311        t=   18.6 R=   1e+05
+Depth=    3253 States=    3e+06 Transitions= 3.44e+07 Memory=   516.252        t=   31.6 R=   9e+04
+pan: resizing hashtable to -w22..  done
+Depth=    7995 States=    4e+06 Transitions= 4.66e+07 Memory=   563.486        t=   42.8 R=   9e+04
+Depth=    7995 States=    5e+06 Transitions= 6.05e+07 Memory=   580.674        t=   55.6 R=   9e+04
+Depth=    7995 States=    6e+06 Transitions= 7.12e+07 Memory=   599.229        t=   65.5 R=   9e+04
+Depth=    7995 States=    7e+06 Transitions= 8.58e+07 Memory=   613.975        t=   78.9 R=   9e+04
+Depth=    7995 States=    8e+06 Transitions= 9.62e+07 Memory=   631.846        t=   88.7 R=   9e+04
+Depth=    7995 States=    9e+06 Transitions=  1.1e+08 Memory=   646.592        t=    101 R=   9e+04
+pan: resizing hashtable to -w24..  done
+Depth=    7995 States=    1e+07 Transitions= 1.32e+08 Memory=   783.869        t=    122 R=   8e+04
+Depth=    7995 States=  1.1e+07 Transitions= 1.52e+08 Memory=   799.104        t=    140 R=   8e+04
+Depth=    7995 States=  1.2e+07 Transitions= 1.71e+08 Memory=   814.533        t=    157 R=   8e+04
+Depth=    7995 States=  1.3e+07 Transitions=  1.9e+08 Memory=   829.670        t=    174 R=   7e+04
+Depth=    7995 States=  1.4e+07 Transitions= 2.01e+08 Memory=   848.029        t=    185 R=   8e+04
+Depth=    7995 States=  1.5e+07 Transitions= 2.21e+08 Memory=   862.287        t=    203 R=   7e+04
+Depth=    7995 States=  1.6e+07 Transitions= 2.35e+08 Memory=   877.815        t=    215 R=   7e+04
+Depth=    7995 States=  1.7e+07 Transitions= 2.44e+08 Memory=   897.736        t=    223 R=   8e+04
+Depth=    7995 States=  1.8e+07 Transitions= 2.57e+08 Memory=   911.115        t=    235 R=   8e+04
+Depth=    7995 States=  1.9e+07 Transitions= 2.69e+08 Memory=   927.033        t=    246 R=   8e+04
+Depth=    8341 States=    2e+07 Transitions= 2.83e+08 Memory=   943.440        t=    259 R=   8e+04
+Depth=    8341 States=  2.1e+07 Transitions= 2.96e+08 Memory=   961.604        t=    271 R=   8e+04
+Depth=    8341 States=  2.2e+07 Transitions= 3.07e+08 Memory=   978.791        t=    281 R=   8e+04
+Depth=    8341 States=  2.3e+07 Transitions=  3.2e+08 Memory=   996.369        t=    293 R=   8e+04
+Depth=    8341 States=  2.4e+07 Transitions= 3.32e+08 Memory=  1013.264        t=    304 R=   8e+04
+Depth=    8341 States=  2.5e+07 Transitions= 3.48e+08 Memory=  1024.885        t=    319 R=   8e+04
+Depth=    8341 States=  2.6e+07 Transitions= 3.72e+08 Memory=  1038.947        t=    341 R=   8e+04
+Depth=    8341 States=  2.7e+07 Transitions= 3.91e+08 Memory=  1055.158        t=    358 R=   8e+04
+Depth=    8341 States=  2.8e+07 Transitions= 4.09e+08 Memory=  1069.904        t=    374 R=   7e+04
+Depth=    8341 States=  2.9e+07 Transitions= 4.25e+08 Memory=  1086.701        t=    389 R=   7e+04
+Depth=    8341 States=    3e+07 Transitions= 4.43e+08 Memory=  1102.131        t=    405 R=   7e+04
+Depth=    8341 States=  3.1e+07 Transitions= 4.58e+08 Memory=  1117.268        t=    419 R=   7e+04
+Depth=    8341 States=  3.2e+07 Transitions= 4.68e+08 Memory=  1136.213        t=    429 R=   7e+04
+Depth=    8341 States=  3.3e+07 Transitions=  4.8e+08 Memory=  1151.154        t=    440 R=   8e+04
+Depth=    8341 States=  3.4e+07 Transitions= 4.92e+08 Memory=  1166.779        t=    451 R=   8e+04
+pan: resizing hashtable to -w26..  done
+Depth=    8687 States=  3.5e+07 Transitions= 5.05e+08 Memory=  1679.658        t=    464 R=   8e+04
+Depth=    8687 States=  3.6e+07 Transitions= 5.18e+08 Memory=  1697.432        t=    477 R=   8e+04
+Depth=    8687 States=  3.7e+07 Transitions= 5.29e+08 Memory=  1714.326        t=    487 R=   8e+04
+Depth=    8687 States=  3.8e+07 Transitions= 5.44e+08 Memory=  1730.244        t=    500 R=   8e+04
+Depth=    8687 States=  3.9e+07 Transitions= 5.55e+08 Memory=  1747.920        t=    511 R=   8e+04
+Depth=    8687 States=    4e+07 Transitions= 5.69e+08 Memory=  1761.885        t=    523 R=   8e+04
+Depth=    8687 States=  4.1e+07 Transitions= 5.92e+08 Memory=  1775.850        t=    544 R=   8e+04
+Depth=    8687 States=  4.2e+07 Transitions= 6.12e+08 Memory=  1790.498        t=    562 R=   7e+04
+Depth=    8687 States=  4.3e+07 Transitions= 6.29e+08 Memory=  1807.783        t=    578 R=   7e+04
+Depth=    8687 States=  4.4e+07 Transitions= 6.48e+08 Memory=  1822.432        t=    595 R=   7e+04
+Depth=    8687 States=  4.5e+07 Transitions= 6.61e+08 Memory=  1838.838        t=    606 R=   7e+04
+Depth=    8687 States=  4.6e+07 Transitions= 6.81e+08 Memory=  1853.291        t=    625 R=   7e+04
+Depth=    8687 States=  4.7e+07 Transitions= 6.93e+08 Memory=  1870.772        t=    635 R=   7e+04
+Depth=    8687 States=  4.8e+07 Transitions= 7.02e+08 Memory=  1889.912        t=    644 R=   7e+04
+Depth=    8687 States=  4.9e+07 Transitions= 7.15e+08 Memory=  1902.998        t=    656 R=   7e+04
+Depth=    8687 States=    5e+07 Transitions= 7.27e+08 Memory=  1919.600        t=    667 R=   7e+04
+Depth=    9033 States=  5.1e+07 Transitions= 7.42e+08 Memory=  1935.518        t=    681 R=   7e+04
+Depth=    9033 States=  5.2e+07 Transitions= 7.53e+08 Memory=  1954.170        t=    691 R=   8e+04
+Depth=    9033 States=  5.3e+07 Transitions= 7.66e+08 Memory=  1969.990        t=    703 R=   8e+04
+Depth=    9033 States=  5.4e+07 Transitions= 7.77e+08 Memory=  1988.545        t=    713 R=   8e+04
+Depth=    9033 States=  5.5e+07 Transitions=  7.9e+08 Memory=  2004.756        t=    725 R=   8e+04
+Depth=    9033 States=  5.6e+07 Transitions=  8.1e+08 Memory=  2016.084        t=    743 R=   8e+04
+Depth=    9033 States=  5.7e+07 Transitions= 8.32e+08 Memory=  2030.440        t=    763 R=   7e+04
+Depth=    9033 States=  5.8e+07 Transitions= 8.51e+08 Memory=  2046.260        t=    781 R=   7e+04
+Depth=    9033 States=  5.9e+07 Transitions=  8.7e+08 Memory=  2061.592        t=    797 R=   7e+04
+Depth=    9033 States=    6e+07 Transitions= 8.83e+08 Memory=  2078.779        t=    809 R=   7e+04
+Depth=    9033 States=  6.1e+07 Transitions= 9.01e+08 Memory=  2094.014        t=    826 R=   7e+04
+Depth=    9033 States=  6.2e+07 Transitions= 9.16e+08 Memory=  2108.467        t=    840 R=   7e+04
+Depth=    9033 States=  6.3e+07 Transitions= 9.26e+08 Memory=  2126.924        t=    849 R=   7e+04
+Depth=    9033 States=  6.4e+07 Transitions= 9.38e+08 Memory=  2142.158        t=    860 R=   7e+04
+Depth=    9033 States=  6.5e+07 Transitions= 9.51e+08 Memory=  2157.295        t=    871 R=   7e+04
+Depth=    9379 States=  6.6e+07 Transitions= 9.63e+08 Memory=  2173.115        t=    883 R=   7e+04
+Depth=    9379 States=  6.7e+07 Transitions= 9.77e+08 Memory=  2190.401        t=    895 R=   7e+04
+Depth=    9379 States=  6.8e+07 Transitions= 9.88e+08 Memory=  2208.955        t=    905 R=   8e+04
+Depth=    9379 States=  6.9e+07 Transitions=    1e+09 Memory=  2223.311        t=    919 R=   8e+04
+Depth=    9379 States=    7e+07 Transitions= 1.01e+09 Memory=  2242.256        t=    928 R=   8e+04
+Depth=    9379 States=  7.1e+07 Transitions= 1.03e+09 Memory=  2257.295        t=    940 R=   8e+04
+Depth=    9379 States=  7.2e+07 Transitions= 1.05e+09 Memory=  2269.307        t=    960 R=   8e+04
+Depth=    9379 States=  7.3e+07 Transitions= 1.07e+09 Memory=  2283.760        t=    979 R=   7e+04
+Depth=    9379 States=  7.4e+07 Transitions= 1.09e+09 Memory=  2299.385        t=    996 R=   7e+04
+Depth=    9379 States=  7.5e+07 Transitions= 1.11e+09 Memory=  2314.619        t= 1.01e+03 R=   7e+04
+Depth=    9379 States=  7.6e+07 Transitions= 1.12e+09 Memory=  2333.369        t= 1.02e+03 R=   7e+04
+Depth=    9379 States=  7.7e+07 Transitions= 1.14e+09 Memory=  2347.139        t= 1.04e+03 R=   7e+04
+Depth=    9379 States=  7.8e+07 Transitions= 1.15e+09 Memory=  2385.029        t= 1.06e+03 R=   7e+04
+Depth=    9379 States=  7.9e+07 Transitions= 1.17e+09 Memory=  2453.682        t= 1.07e+03 R=   7e+04
+Depth=    9379 States=    8e+07 Transitions= 1.18e+09 Memory=  2522.236        t= 1.08e+03 R=   7e+04
+Depth=    9379 States=  8.1e+07 Transitions=  1.2e+09 Memory=  2590.889        t= 1.1e+03 R=   7e+04
+Depth=    9379 States=  8.2e+07 Transitions= 1.22e+09 Memory=  2624.287        t= 1.12e+03 R=   7e+04
+Depth=    9379 States=  8.3e+07 Transitions= 1.23e+09 Memory=  2640.303        t= 1.13e+03 R=   7e+04
+Depth=    9379 States=  8.4e+07 Transitions= 1.25e+09 Memory=  2654.170        t= 1.15e+03 R=   7e+04
+Depth=    9379 States=  8.5e+07 Transitions= 1.27e+09 Memory=  2669.111        t= 1.16e+03 R=   7e+04
+Depth=    9379 States=  8.6e+07 Transitions= 1.29e+09 Memory=  2684.053        t= 1.18e+03 R=   7e+04
+Depth=    9379 States=  8.7e+07 Transitions= 1.31e+09 Memory=  2698.604        t= 1.2e+03 R=   7e+04
+Depth=    9379 States=  8.8e+07 Transitions= 1.33e+09 Memory=  2719.697        t= 1.22e+03 R=   7e+04
+Depth=    9379 States=  8.9e+07 Transitions= 1.35e+09 Memory=  2788.350        t= 1.24e+03 R=   7e+04
+Depth=    9379 States=    9e+07 Transitions= 1.37e+09 Memory=  2819.990        t= 1.26e+03 R=   7e+04
+Depth=    9379 States=  9.1e+07 Transitions= 1.39e+09 Memory=  2846.553        t= 1.27e+03 R=   7e+04
+Depth=    9379 States=  9.2e+07 Transitions=  1.4e+09 Memory=  2864.912        t= 1.28e+03 R=   7e+04
+Depth=    9379 States=  9.3e+07 Transitions= 1.41e+09 Memory=  2877.901        t= 1.3e+03 R=   7e+04
+Depth=    9379 States=  9.4e+07 Transitions= 1.44e+09 Memory=  2892.842        t= 1.31e+03 R=   7e+04
+Depth=    9379 States=  9.5e+07 Transitions= 1.45e+09 Memory=  2908.076        t= 1.33e+03 R=   7e+04
+Depth=    9379 States=  9.6e+07 Transitions= 1.47e+09 Memory=  2922.627        t= 1.35e+03 R=   7e+04
+Depth=    9379 States=  9.7e+07 Transitions= 1.49e+09 Memory=  2940.693        t= 1.36e+03 R=   7e+04
+Depth=    9379 States=  9.8e+07 Transitions= 1.51e+09 Memory=  2953.291        t= 1.38e+03 R=   7e+04
+Depth=    9379 States=  9.9e+07 Transitions= 1.53e+09 Memory=  2968.526        t= 1.4e+03 R=   7e+04
+Depth=    9379 States=    1e+08 Transitions= 1.56e+09 Memory=  2981.709        t= 1.42e+03 R=   7e+04
+Depth=    9379 States= 1.01e+08 Transitions= 1.57e+09 Memory=  2997.236        t= 1.44e+03 R=   7e+04
+Depth=    9379 States= 1.02e+08 Transitions= 1.59e+09 Memory=  3011.592        t= 1.46e+03 R=   7e+04
+Depth=    9379 States= 1.03e+08 Transitions= 1.61e+09 Memory=  3037.861        t= 1.47e+03 R=   7e+04
+Depth=    9379 States= 1.04e+08 Transitions= 1.63e+09 Memory=  3106.514        t= 1.49e+03 R=   7e+04
+Depth=    9379 States= 1.05e+08 Transitions= 1.65e+09 Memory=  3175.166        t= 1.51e+03 R=   7e+04
+Depth=    9379 States= 1.06e+08 Transitions= 1.67e+09 Memory=  3223.897        t= 1.52e+03 R=   7e+04
+Depth=    9379 States= 1.07e+08 Transitions= 1.68e+09 Memory=  3246.846        t= 1.54e+03 R=   7e+04
+Depth=    9379 States= 1.08e+08 Transitions=  1.7e+09 Memory=  3283.467        t= 1.56e+03 R=   7e+04
+Depth=    9379 States= 1.09e+08 Transitions= 1.72e+09 Memory=  3316.670        t= 1.57e+03 R=   7e+04
+Depth=    9379 States=  1.1e+08 Transitions= 1.73e+09 Memory=  3344.209        t= 1.59e+03 R=   7e+04
+Depth=    9379 States= 1.11e+08 Transitions= 1.75e+09 Memory=  3376.338        t= 1.6e+03 R=   7e+04
+Depth=    9379 States= 1.12e+08 Transitions= 1.76e+09 Memory=  3396.943        t= 1.62e+03 R=   7e+04
+Depth=    9379 States= 1.13e+08 Transitions= 1.78e+09 Memory=  3426.143        t= 1.63e+03 R=   7e+04
+Depth=    9379 States= 1.14e+08 Transitions=  1.8e+09 Memory=  3452.705        t= 1.65e+03 R=   7e+04
+Depth=    9379 States= 1.15e+08 Transitions= 1.81e+09 Memory=  3493.818        t= 1.66e+03 R=   7e+04
+Depth=    9379 States= 1.16e+08 Transitions= 1.83e+09 Memory=  3533.369        t= 1.67e+03 R=   7e+04
+Depth=    9379 States= 1.17e+08 Transitions= 1.84e+09 Memory=  3566.182        t= 1.69e+03 R=   7e+04
+Depth=    9379 States= 1.18e+08 Transitions= 1.86e+09 Memory=  3582.881        t= 1.7e+03 R=   7e+04
+Depth=    9379 States= 1.19e+08 Transitions= 1.88e+09 Memory=  3630.830        t= 1.72e+03 R=   7e+04
+Depth=    9379 States=  1.2e+08 Transitions= 1.89e+09 Memory=  3692.744        t= 1.74e+03 R=   7e+04
+Depth=    9379 States= 1.21e+08 Transitions= 1.91e+09 Memory=  3750.361        t= 1.75e+03 R=   7e+04
+Depth=    9379 States= 1.22e+08 Transitions= 1.92e+09 Memory=  3767.354        t= 1.76e+03 R=   7e+04
+Depth=    9379 States= 1.23e+08 Transitions= 1.94e+09 Memory=  3781.904        t= 1.78e+03 R=   7e+04
+Depth=    9379 States= 1.24e+08 Transitions= 1.96e+09 Memory=  3797.529        t= 1.8e+03 R=   7e+04
+Depth=    9379 States= 1.25e+08 Transitions= 1.98e+09 Memory=  3810.908        t= 1.82e+03 R=   7e+04
+Depth=    9379 States= 1.26e+08 Transitions=    2e+09 Memory=  3826.143        t= 1.83e+03 R=   7e+04
+Depth=    9379 States= 1.27e+08 Transitions= 2.02e+09 Memory=  3839.717        t= 1.86e+03 R=   7e+04
+Depth=    9379 States= 1.28e+08 Transitions= 2.04e+09 Memory=  3881.709        t= 1.87e+03 R=   7e+04
+Depth=    9379 States= 1.29e+08 Transitions= 2.06e+09 Memory=  3946.553        t= 1.89e+03 R=   7e+04
+Depth=    9379 States=  1.3e+08 Transitions= 2.08e+09 Memory=  3970.479        t= 1.91e+03 R=   7e+04
+Depth=    9379 States= 1.31e+08 Transitions= 2.09e+09 Memory=  3991.768        t= 1.92e+03 R=   7e+04
+Depth=    9379 States= 1.32e+08 Transitions=  2.1e+09 Memory=  4007.490        t= 1.93e+03 R=   7e+04
+Depth=    9379 States= 1.33e+08 Transitions= 2.13e+09 Memory=  4020.772        t= 1.95e+03 R=   7e+04
+Depth=    9379 States= 1.34e+08 Transitions= 2.14e+09 Memory=  4036.201        t= 1.97e+03 R=   7e+04
+Depth=    9379 States= 1.35e+08 Transitions= 2.16e+09 Memory=  4051.924        t= 1.98e+03 R=   7e+04
+pan: resizing hashtable to -w28..  done
+Depth=    9379 States= 1.36e+08 Transitions= 2.18e+09 Memory=  6099.924        t= 2.02e+03 R=   7e+04
+Depth=    9379 States= 1.37e+08 Transitions=  2.2e+09 Memory=  6099.924        t= 2.03e+03 R=   7e+04
+Depth=    9379 States= 1.38e+08 Transitions= 2.22e+09 Memory=  6099.924        t= 2.05e+03 R=   7e+04
+Depth=    9379 States= 1.39e+08 Transitions= 2.24e+09 Memory=  6099.924        t= 2.07e+03 R=   7e+04
+Depth=    9379 States=  1.4e+08 Transitions= 2.26e+09 Memory=  6108.518        t= 2.09e+03 R=   7e+04
+Depth=    9379 States= 1.41e+08 Transitions= 2.28e+09 Memory=  6124.729        t= 2.1e+03 R=   7e+04
+Depth=    9379 States= 1.42e+08 Transitions=  2.3e+09 Memory=  6138.889        t= 2.12e+03 R=   7e+04
+Depth=    9379 States= 1.43e+08 Transitions= 2.31e+09 Memory=  6178.928        t= 2.13e+03 R=   7e+04
+Depth=    9379 States= 1.44e+08 Transitions= 2.33e+09 Memory=  6247.483        t= 2.15e+03 R=   7e+04
+Depth=    9379 States= 1.45e+08 Transitions= 2.35e+09 Memory=  6316.135        t= 2.17e+03 R=   7e+04
+Depth=    9379 States= 1.46e+08 Transitions= 2.37e+09 Memory=  6353.440        t= 2.19e+03 R=   7e+04
+Depth=    9379 States= 1.47e+08 Transitions= 2.39e+09 Memory=  6381.662        t= 2.21e+03 R=   7e+04
+Depth=    9379 States= 1.48e+08 Transitions= 2.41e+09 Memory=  6422.190        t= 2.22e+03 R=   7e+04
+Depth=    9379 States= 1.49e+08 Transitions= 2.42e+09 Memory=  6449.143        t= 2.23e+03 R=   7e+04
+Depth=    9379 States=  1.5e+08 Transitions= 2.44e+09 Memory=  6472.580        t= 2.25e+03 R=   7e+04
+Depth=    9379 States= 1.51e+08 Transitions= 2.45e+09 Memory=  6503.733        t= 2.26e+03 R=   7e+04
+Depth=    9379 States= 1.52e+08 Transitions= 2.47e+09 Memory=  6531.369        t= 2.28e+03 R=   7e+04
+Depth=    9379 States= 1.53e+08 Transitions= 2.49e+09 Memory=  6554.123        t= 2.29e+03 R=   7e+04
+Depth=    9379 States= 1.54e+08 Transitions=  2.5e+09 Memory=  6585.373        t= 2.31e+03 R=   7e+04
+Depth=    9379 States= 1.55e+08 Transitions= 2.52e+09 Memory=  6622.776        t= 2.32e+03 R=   7e+04
+Depth=    9379 States= 1.56e+08 Transitions= 2.54e+09 Memory=  6671.213        t= 2.34e+03 R=   7e+04
+Depth=    9379 States= 1.57e+08 Transitions= 2.55e+09 Memory=  6696.115        t= 2.35e+03 R=   7e+04
+Depth=    9379 States= 1.58e+08 Transitions= 2.57e+09 Memory=  6722.776        t= 2.37e+03 R=   7e+04
+Depth=    9379 States= 1.59e+08 Transitions= 2.58e+09 Memory=  6764.572        t= 2.38e+03 R=   7e+04
+Depth=    9379 States=  1.6e+08 Transitions=  2.6e+09 Memory=  6830.490        t= 2.4e+03 R=   7e+04
+Depth=    9379 States= 1.61e+08 Transitions= 2.62e+09 Memory=  6879.026        t= 2.41e+03 R=   7e+04
+Depth=    9379 States= 1.62e+08 Transitions= 2.63e+09 Memory=  6895.432        t= 2.42e+03 R=   7e+04
+Depth=    9379 States= 1.63e+08 Transitions= 2.65e+09 Memory=  6909.787        t= 2.44e+03 R=   7e+04
+Depth=    9379 States= 1.64e+08 Transitions= 2.67e+09 Memory=  6925.217        t= 2.46e+03 R=   7e+04
+Depth=    9379 States= 1.65e+08 Transitions= 2.69e+09 Memory=  6938.986        t= 2.48e+03 R=   7e+04
+Depth=    9379 States= 1.66e+08 Transitions= 2.71e+09 Memory=  6953.537        t= 2.5e+03 R=   7e+04
+Depth=    9379 States= 1.67e+08 Transitions= 2.73e+09 Memory=  6967.893        t= 2.52e+03 R=   7e+04
+Depth=    9379 States= 1.68e+08 Transitions= 2.75e+09 Memory=  7022.190        t= 2.53e+03 R=   7e+04
+Depth=    9379 States= 1.69e+08 Transitions= 2.77e+09 Memory=  7076.779        t= 2.55e+03 R=   7e+04
+Depth=    9379 States=  1.7e+08 Transitions= 2.79e+09 Memory=  7102.365        t= 2.57e+03 R=   7e+04
+Depth=    9379 States= 1.71e+08 Transitions=  2.8e+09 Memory=  7119.162        t= 2.58e+03 R=   7e+04
+Depth=    9379 States= 1.72e+08 Transitions= 2.81e+09 Memory=  7135.178        t= 2.59e+03 R=   7e+04
+Depth=    9379 States= 1.73e+08 Transitions= 2.84e+09 Memory=  7150.022        t= 2.61e+03 R=   7e+04
+Depth=    9379 States= 1.74e+08 Transitions= 2.85e+09 Memory=  7164.475        t= 2.63e+03 R=   7e+04
+Depth=    9379 States= 1.75e+08 Transitions= 2.87e+09 Memory=  7180.295        t= 2.64e+03 R=   7e+04
+Depth=    9379 States= 1.76e+08 Transitions= 2.89e+09 Memory=  7198.264        t= 2.66e+03 R=   7e+04
+Depth=    9379 States= 1.77e+08 Transitions=  2.9e+09 Memory=  7211.447        t= 2.67e+03 R=   7e+04
+Depth=    9379 States= 1.78e+08 Transitions= 2.93e+09 Memory=  7224.338        t= 2.7e+03 R=   7e+04
+Depth=    9379 States= 1.79e+08 Transitions= 2.95e+09 Memory=  7239.084        t= 2.72e+03 R=   7e+04
+Depth=    9379 States=  1.8e+08 Transitions= 2.97e+09 Memory=  7253.342        t= 2.74e+03 R=   7e+04
+Depth=    9379 States= 1.81e+08 Transitions= 2.99e+09 Memory=  7268.283        t= 2.75e+03 R=   7e+04
+Depth=    9379 States= 1.82e+08 Transitions= 3.01e+09 Memory=  7283.615        t= 2.77e+03 R=   7e+04
+Depth=    9379 States= 1.83e+08 Transitions= 3.02e+09 Memory=  7335.276        t= 2.78e+03 R=   7e+04
+Depth=    9379 States= 1.84e+08 Transitions= 3.04e+09 Memory=  7403.928        t= 2.8e+03 R=   7e+04
+Depth=    9379 States= 1.85e+08 Transitions= 3.06e+09 Memory=  7472.580        t= 2.82e+03 R=   7e+04
+Depth=    9379 States= 1.86e+08 Transitions= 3.08e+09 Memory=  7501.877        t= 2.84e+03 R=   7e+04
+Depth=    9379 States= 1.87e+08 Transitions=  3.1e+09 Memory=  7528.147        t= 2.85e+03 R=   7e+04
+Depth=    9379 States= 1.88e+08 Transitions= 3.11e+09 Memory=  7566.135        t= 2.87e+03 R=   7e+04
+Depth=    9379 States= 1.89e+08 Transitions= 3.13e+09 Memory=  7593.479        t= 2.88e+03 R=   7e+04
+Depth=    9379 States=  1.9e+08 Transitions= 3.15e+09 Memory=  7625.119        t= 2.9e+03 R=   7e+04
+Depth=    9379 States= 1.91e+08 Transitions= 3.16e+09 Memory=  7647.483        t= 2.91e+03 R=   7e+04
+Depth=    9379 States= 1.92e+08 Transitions= 3.18e+09 Memory=  7677.951        t= 2.93e+03 R=   7e+04
+Depth=    9379 States= 1.93e+08 Transitions=  3.2e+09 Memory=  7698.947        t= 2.94e+03 R=   7e+04
+Depth=    9379 States= 1.94e+08 Transitions= 3.21e+09 Memory=  7732.443        t= 2.96e+03 R=   7e+04
+Depth=    9379 States= 1.95e+08 Transitions= 3.23e+09 Memory=  7772.092        t= 2.97e+03 R=   7e+04
+Depth=    9379 States= 1.96e+08 Transitions= 3.24e+09 Memory=  7815.451        t= 2.98e+03 R=   7e+04
+Depth=    9379 States= 1.97e+08 Transitions= 3.26e+09 Memory=  7839.865        t=  3e+03 R=   7e+04
+Depth=    9379 States= 1.98e+08 Transitions= 3.28e+09 Memory=  7869.651        t= 3.01e+03 R=   7e+04
+Depth=    9379 States= 1.99e+08 Transitions= 3.29e+09 Memory=  7921.018        t= 3.03e+03 R=   7e+04
+Depth=    9379 States=    2e+08 Transitions= 3.31e+09 Memory=  7986.740        t= 3.05e+03 R=   7e+04
+Depth=    9379 States= 2.01e+08 Transitions= 3.33e+09 Memory=  8023.752        t= 3.06e+03 R=   7e+04
+Depth=    9379 States= 2.02e+08 Transitions= 3.34e+09 Memory=  8039.768        t= 3.07e+03 R=   7e+04
+Depth=    9379 States= 2.03e+08 Transitions= 3.36e+09 Memory=  8053.830        t= 3.09e+03 R=   7e+04
+Depth=    9379 States= 2.04e+08 Transitions= 3.38e+09 Memory=  8068.772        t= 3.11e+03 R=   7e+04
+Depth=    9379 States= 2.05e+08 Transitions=  3.4e+09 Memory=  8083.127        t= 3.13e+03 R=   7e+04
+Depth=    9379 States= 2.06e+08 Transitions= 3.42e+09 Memory=  8098.068        t= 3.15e+03 R=   7e+04
+Depth=    9379 States= 2.07e+08 Transitions= 3.44e+09 Memory=  8115.744        t= 3.16e+03 R=   7e+04
+Depth=    9379 States= 2.08e+08 Transitions= 3.46e+09 Memory=  8178.537        t= 3.18e+03 R=   7e+04
+Depth=    9379 States= 2.09e+08 Transitions= 3.48e+09 Memory=  8220.627        t= 3.2e+03 R=   7e+04
+Depth=    9379 States=  2.1e+08 Transitions= 3.49e+09 Memory=  8246.799        t= 3.21e+03 R=   7e+04
+Depth=    9379 States= 2.11e+08 Transitions=  3.5e+09 Memory=  8263.791        t= 3.22e+03 R=   7e+04
+Depth=    9379 States= 2.12e+08 Transitions= 3.52e+09 Memory=  8279.514        t= 3.24e+03 R=   7e+04
+Depth=    9379 States= 2.13e+08 Transitions= 3.54e+09 Memory=  8293.772        t= 3.26e+03 R=   7e+04
+Depth=    9379 States= 2.14e+08 Transitions= 3.56e+09 Memory=  8309.201        t= 3.28e+03 R=   7e+04
+Depth=    9379 States= 2.15e+08 Transitions= 3.58e+09 Memory=  8323.752        t= 3.29e+03 R=   7e+04
+Depth=    9379 States= 2.16e+08 Transitions=  3.6e+09 Memory=  8342.990        t= 3.31e+03 R=   7e+04
+Depth=    9379 States= 2.17e+08 Transitions= 3.61e+09 Memory=  8355.197        t= 3.32e+03 R=   7e+04
+Depth=    9379 States= 2.18e+08 Transitions= 3.64e+09 Memory=  8368.674        t= 3.35e+03 R=   7e+04
+Depth=    9379 States= 2.19e+08 Transitions= 3.66e+09 Memory=  8382.932        t= 3.37e+03 R=   7e+04
+Depth=    9379 States=  2.2e+08 Transitions= 3.68e+09 Memory=  8398.459        t= 3.38e+03 R=   7e+04
+Depth=    9379 States= 2.21e+08 Transitions=  3.7e+09 Memory=  8412.912        t= 3.4e+03 R=   6e+04
+Depth=    9379 States= 2.22e+08 Transitions= 3.71e+09 Memory=  8428.244        t= 3.42e+03 R=   6e+04
+Depth=    9379 States= 2.23e+08 Transitions= 3.73e+09 Memory=  8491.721        t= 3.43e+03 R=   6e+04
+Depth=    9379 States= 2.24e+08 Transitions= 3.75e+09 Memory=  8560.373        t= 3.45e+03 R=   6e+04
+Depth=    9379 States= 2.25e+08 Transitions= 3.77e+09 Memory=  8621.604        t= 3.47e+03 R=   6e+04
+Depth=    9379 States= 2.26e+08 Transitions= 3.79e+09 Memory=  8648.850        t= 3.48e+03 R=   6e+04
+Depth=    9379 States= 2.27e+08 Transitions= 3.81e+09 Memory=  8671.994        t= 3.5e+03 R=   6e+04
+Depth=    9379 States= 2.28e+08 Transitions= 3.82e+09 Memory=  8710.861        t= 3.51e+03 R=   6e+04
+Depth=    9379 States= 2.29e+08 Transitions= 3.84e+09 Memory=  8742.893        t= 3.53e+03 R=   6e+04
+Depth=    9379 States=  2.3e+08 Transitions= 3.85e+09 Memory=  8771.799        t= 3.54e+03 R=   6e+04
+Depth=    9379 States= 2.31e+08 Transitions= 3.87e+09 Memory=  8792.600        t= 3.56e+03 R=   6e+04
+Depth=    9379 States= 2.32e+08 Transitions= 3.89e+09 Memory=  8828.733        t= 3.57e+03 R=   6e+04
+Depth=    9379 States= 2.33e+08 Transitions=  3.9e+09 Memory=  8843.869        t= 3.59e+03 R=   6e+04
+Depth=    9379 States= 2.34e+08 Transitions= 3.92e+09 Memory=  8884.787        t= 3.6e+03 R=   6e+04
+Depth=    9379 States= 2.35e+08 Transitions= 3.93e+09 Memory=  8924.240        t= 3.62e+03 R=   6e+04
+Depth=    9379 States= 2.36e+08 Transitions= 3.95e+09 Memory=  8960.276        t= 3.63e+03 R=   6e+04
+Depth=    9379 States= 2.37e+08 Transitions= 3.97e+09 Memory=  8984.494        t= 3.65e+03 R=   6e+04
+Depth=    9379 States= 2.38e+08 Transitions= 3.98e+09 Memory=  9016.428        t= 3.66e+03 R=   6e+04
+Depth=    9379 States= 2.39e+08 Transitions=    4e+09 Memory=  9077.365        t= 3.68e+03 R=   6e+04
+Depth=    9379 States=  2.4e+08 Transitions= 4.02e+09 Memory=  9143.088        t= 3.7e+03 R=   6e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 9379, errors: 0
+ 88114592 states, stored (2.40192e+08 visited)
+3.782223e+09 states, matched
+4.0224152e+09 transitions (= visited+matched)
+1.4282782e+10 atomic steps
+hash conflicts: 5.384059e+08 (resolved)
+
+Stats on memory usage (in Megabytes):
+ 7731.001      equivalent memory usage for states (stored*(State-vector + overhead))
+ 6648.180      actual memory usage for states (compression: 85.99%)
+               state-vector as stored = 51 byte + 28 byte overhead
+ 2048.000      memory used for hash table (-w28)
+  457.764      memory used for DFS stack (-m10000000)
+    1.188      memory lost to fragmentation
+ 9152.756      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 256, "(1)"
+       line 418, "pan.___", state 286, "(1)"
+       line 399, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 395, "(1)"
+       line 418, "pan.___", state 425, "(1)"
+       line 540, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 399, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 70, "(1)"
+       line 418, "pan.___", state 100, "(1)"
+       line 399, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 158, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 399, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 247, "(1)"
+       line 418, "pan.___", state 277, "(1)"
+       line 399, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 359, "(1)"
+       line 418, "pan.___", state 389, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 3.7e+03 seconds
+pan: rate 64918.749 states/second
+pan: avg transition delay 9.1982e-07 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input
new file mode 100644 (file)
index 0000000..43221e7
--- /dev/null
@@ -0,0 +1,723 @@
+#define WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.define b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.define
new file mode 100644 (file)
index 0000000..8d304f5
--- /dev/null
@@ -0,0 +1,2 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.log b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.log
new file mode 100644 (file)
index 0000000..f870a6e
--- /dev/null
@@ -0,0 +1,535 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+depth 15: Claim reached state 9 (line 750)
+depth 1194: Claim reached state 9 (line 749)
+Depth=    3253 States=    1e+06 Transitions= 1.06e+07 Memory=   484.416        t=   9.57 R=   1e+05
+Depth=    3253 States=    2e+06 Transitions= 2.04e+07 Memory=   501.311        t=   18.5 R=   1e+05
+pan: acceptance cycle (at depth 1938)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 64 byte, depth reached 23684, errors: 1
+   682672 states, stored (2.81536e+06 visited)
+ 30226122 states, matched
+ 33041487 transitions (= visited+matched)
+1.1631626e+08 atomic steps
+hash conflicts:   6056013 (resolved)
+
+Stats on memory usage (in Megabytes):
+   59.896      equivalent memory usage for states (stored*(State-vector + overhead))
+   47.456      actual memory usage for states (compression: 79.23%)
+               state-vector as stored = 45 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  513.127      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 158, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 400, "pan.___", state 211, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 243, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 256, "(1)"
+       line 419, "pan.___", state 286, "(1)"
+       line 400, "pan.___", state 350, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 382, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 395, "(1)"
+       line 419, "pan.___", state 425, "(1)"
+       line 541, "pan.___", state 456, "-end-"
+       (17 of 456 states)
+unreached in proctype urcu_reader_sig
+       line 400, "pan.___", state 25, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 57, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 70, "(1)"
+       line 419, "pan.___", state 100, "(1)"
+       line 400, "pan.___", state 113, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 145, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 158, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 400, "pan.___", state 202, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 234, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 247, "(1)"
+       line 419, "pan.___", state 277, "(1)"
+       line 400, "pan.___", state 314, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 359, "(1)"
+       line 419, "pan.___", state 389, "(1)"
+       line 615, "pan.___", state 411, "-end-"
+       (17 of 411 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[( ((_pid<2)) ? (0) : (1) )]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 402, "pan.___", state 134, "((i<1))"
+       line 402, "pan.___", state 134, "((i>=1))"
+       line 410, "pan.___", state 153, "(1)"
+       line 410, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 154, "else"
+       line 410, "pan.___", state 157, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 414, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 167, "else"
+       line 414, "pan.___", state 170, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 412, "pan.___", state 176, "((i<1))"
+       line 412, "pan.___", state 176, "((i>=1))"
+       line 419, "pan.___", state 183, "(1)"
+       line 419, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 184, "else"
+       line 419, "pan.___", state 187, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 370, "pan.___", state 193, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 647, "pan.___", state 202, "((write_lock==0))"
+       line 647, "pan.___", state 202, "else"
+       line 645, "pan.___", state 203, "(1)"
+       line 176, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 180, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 225, "((j<1))"
+       line 178, "pan.___", state 225, "((j>=1))"
+       line 184, "pan.___", state 230, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 161, "pan.___", state 240, "(1)"
+       line 165, "pan.___", state 248, "(1)"
+       line 165, "pan.___", state 249, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 165, "pan.___", state 249, "else"
+       line 163, "pan.___", state 254, "((j<1))"
+       line 163, "pan.___", state 254, "((j>=1))"
+       line 169, "pan.___", state 260, "(1)"
+       line 169, "pan.___", state 261, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 169, "pan.___", state 261, "else"
+       line 171, "pan.___", state 264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 171, "pan.___", state 264, "else"
+       line 176, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 180, "pan.___", state 280, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 288, "((j<1))"
+       line 178, "pan.___", state 288, "((j>=1))"
+       line 184, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 303, "(1)"
+       line 165, "pan.___", state 311, "(1)"
+       line 165, "pan.___", state 312, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 165, "pan.___", state 312, "else"
+       line 163, "pan.___", state 317, "((j<1))"
+       line 163, "pan.___", state 317, "((j>=1))"
+       line 169, "pan.___", state 323, "(1)"
+       line 169, "pan.___", state 324, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 324, "else"
+       line 171, "pan.___", state 327, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 171, "pan.___", state 327, "else"
+       line 215, "pan.___", state 333, "((i<1))"
+       line 215, "pan.___", state 333, "((i>=1))"
+       line 176, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 180, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 178, "pan.___", state 355, "((j<1))"
+       line 178, "pan.___", state 355, "((j>=1))"
+       line 184, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 161, "pan.___", state 370, "(1)"
+       line 165, "pan.___", state 378, "(1)"
+       line 165, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 165, "pan.___", state 379, "else"
+       line 163, "pan.___", state 384, "((j<1))"
+       line 163, "pan.___", state 384, "((j>=1))"
+       line 169, "pan.___", state 390, "(1)"
+       line 169, "pan.___", state 391, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 169, "pan.___", state 391, "else"
+       line 171, "pan.___", state 394, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 171, "pan.___", state 394, "else"
+       line 400, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 410, "(1)"
+       line 404, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 424, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 402, "pan.___", state 430, "((i<1))"
+       line 402, "pan.___", state 430, "((i>=1))"
+       line 409, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 449, "(1)"
+       line 410, "pan.___", state 450, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 450, "else"
+       line 410, "pan.___", state 453, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 414, "pan.___", state 462, "(1)"
+       line 414, "pan.___", state 463, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 463, "else"
+       line 414, "pan.___", state 466, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 412, "pan.___", state 472, "((i<1))"
+       line 412, "pan.___", state 472, "((i>=1))"
+       line 419, "pan.___", state 479, "(1)"
+       line 419, "pan.___", state 480, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 480, "else"
+       line 419, "pan.___", state 483, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 370, "pan.___", state 489, "(1)"
+       line 662, "pan.___", state 492, "cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )] = (tmp^(1<<7))"
+       line 400, "pan.___", state 498, "(1)"
+       line 400, "pan.___", state 499, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 499, "else"
+       line 400, "pan.___", state 502, "(1)"
+       line 404, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 516, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 402, "pan.___", state 522, "((i<1))"
+       line 402, "pan.___", state 522, "((i>=1))"
+       line 409, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 541, "(1)"
+       line 410, "pan.___", state 542, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 542, "else"
+       line 410, "pan.___", state 545, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 414, "pan.___", state 554, "(1)"
+       line 414, "pan.___", state 555, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 555, "else"
+       line 414, "pan.___", state 558, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 412, "pan.___", state 564, "((i<1))"
+       line 412, "pan.___", state 564, "((i>=1))"
+       line 419, "pan.___", state 571, "(1)"
+       line 419, "pan.___", state 572, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 572, "else"
+       line 419, "pan.___", state 575, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 370, "pan.___", state 581, "(1)"
+       line 400, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 595, "(1)"
+       line 404, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 609, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 402, "pan.___", state 615, "((i<1))"
+       line 402, "pan.___", state 615, "((i>=1))"
+       line 409, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 634, "(1)"
+       line 410, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 635, "else"
+       line 410, "pan.___", state 638, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 414, "pan.___", state 647, "(1)"
+       line 414, "pan.___", state 648, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 648, "else"
+       line 414, "pan.___", state 651, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 412, "pan.___", state 657, "((i<1))"
+       line 412, "pan.___", state 657, "((i>=1))"
+       line 419, "pan.___", state 664, "(1)"
+       line 419, "pan.___", state 665, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 665, "else"
+       line 419, "pan.___", state 668, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 370, "pan.___", state 674, "(1)"
+       line 400, "pan.___", state 679, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 681, "(1)"
+       line 400, "pan.___", state 682, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 682, "else"
+       line 400, "pan.___", state 685, "(1)"
+       line 404, "pan.___", state 693, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 695, "(1)"
+       line 404, "pan.___", state 696, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 696, "else"
+       line 404, "pan.___", state 699, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 402, "pan.___", state 705, "((i<1))"
+       line 402, "pan.___", state 705, "((i>=1))"
+       line 409, "pan.___", state 711, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 724, "(1)"
+       line 410, "pan.___", state 725, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 725, "else"
+       line 410, "pan.___", state 728, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 414, "pan.___", state 737, "(1)"
+       line 414, "pan.___", state 738, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 738, "else"
+       line 414, "pan.___", state 741, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 412, "pan.___", state 747, "((i<1))"
+       line 412, "pan.___", state 747, "((i>=1))"
+       line 419, "pan.___", state 754, "(1)"
+       line 419, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 755, "else"
+       line 419, "pan.___", state 758, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 370, "pan.___", state 764, "(1)"
+       line 430, "pan.___", state 767, "(((tmp2&((1<<7)-1))&&((tmp2^cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )])&(1<<7))))"
+       line 430, "pan.___", state 767, "else"
+       line 400, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 779, "(1)"
+       line 400, "pan.___", state 780, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 780, "else"
+       line 400, "pan.___", state 783, "(1)"
+       line 404, "pan.___", state 791, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 793, "(1)"
+       line 404, "pan.___", state 794, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 794, "else"
+       line 404, "pan.___", state 797, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 402, "pan.___", state 803, "((i<1))"
+       line 402, "pan.___", state 803, "((i>=1))"
+       line 409, "pan.___", state 809, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 822, "(1)"
+       line 410, "pan.___", state 823, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 823, "else"
+       line 410, "pan.___", state 826, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 414, "pan.___", state 835, "(1)"
+       line 414, "pan.___", state 836, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 836, "else"
+       line 414, "pan.___", state 839, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 412, "pan.___", state 845, "((i<1))"
+       line 412, "pan.___", state 845, "((i>=1))"
+       line 419, "pan.___", state 852, "(1)"
+       line 419, "pan.___", state 853, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 853, "else"
+       line 419, "pan.___", state 856, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 370, "pan.___", state 862, "(1)"
+       line 449, "pan.___", state 870, "((tmp<1))"
+       line 449, "pan.___", state 870, "((tmp>=1))"
+       line 462, "pan.___", state 873, "tmp = 0"
+       line 400, "pan.___", state 877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 883, "(1)"
+       line 404, "pan.___", state 891, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 897, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 903, "((i<1))"
+       line 402, "pan.___", state 903, "((i>=1))"
+       line 409, "pan.___", state 909, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 922, "(1)"
+       line 410, "pan.___", state 923, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 923, "else"
+       line 410, "pan.___", state 926, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 414, "pan.___", state 935, "(1)"
+       line 414, "pan.___", state 936, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 936, "else"
+       line 414, "pan.___", state 939, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 945, "((i<1))"
+       line 412, "pan.___", state 945, "((i>=1))"
+       line 419, "pan.___", state 952, "(1)"
+       line 419, "pan.___", state 953, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 953, "else"
+       line 419, "pan.___", state 956, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 370, "pan.___", state 962, "(1)"
+       line 671, "pan.___", state 963, "tmp = cached_urcu_gp_ctr.val[( ((_pid<2)) ? (0) : (1) )]"
+       line 400, "pan.___", state 967, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 973, "(1)"
+       line 404, "pan.___", state 981, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 987, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 402, "pan.___", state 993, "((i<1))"
+       line 402, "pan.___", state 993, "((i>=1))"
+       line 409, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 1012, "(1)"
+       line 410, "pan.___", state 1013, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 1013, "else"
+       line 410, "pan.___", state 1016, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 414, "pan.___", state 1025, "(1)"
+       line 414, "pan.___", state 1026, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 1026, "else"
+       line 414, "pan.___", state 1029, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 412, "pan.___", state 1035, "((i<1))"
+       line 412, "pan.___", state 1035, "((i>=1))"
+       line 419, "pan.___", state 1042, "(1)"
+       line 419, "pan.___", state 1043, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 1043, "else"
+       line 419, "pan.___", state 1046, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 370, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1061, "(1)"
+       line 404, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1117, "(1)"
+       line 419, "pan.___", state 1134, "(1)"
+       line 404, "pan.___", state 1166, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1184, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 414, "pan.___", state 1210, "(1)"
+       line 419, "pan.___", state 1227, "(1)"
+       line 400, "pan.___", state 1242, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1256, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 409, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 1287, "(1)"
+       line 414, "pan.___", state 1300, "(1)"
+       line 419, "pan.___", state 1317, "(1)"
+       line 400, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1342, "(1)"
+       line 400, "pan.___", state 1343, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 400, "pan.___", state 1343, "else"
+       line 400, "pan.___", state 1346, "(1)"
+       line 404, "pan.___", state 1354, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1356, "(1)"
+       line 404, "pan.___", state 1357, "((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 404, "pan.___", state 1357, "else"
+       line 404, "pan.___", state 1360, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 402, "pan.___", state 1366, "((i<1))"
+       line 402, "pan.___", state 1366, "((i>=1))"
+       line 409, "pan.___", state 1372, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 410, "pan.___", state 1385, "(1)"
+       line 410, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 410, "pan.___", state 1386, "else"
+       line 410, "pan.___", state 1389, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 414, "pan.___", state 1398, "(1)"
+       line 414, "pan.___", state 1399, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 414, "pan.___", state 1399, "else"
+       line 414, "pan.___", state 1402, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 412, "pan.___", state 1408, "((i<1))"
+       line 412, "pan.___", state 1408, "((i>=1))"
+       line 419, "pan.___", state 1415, "(1)"
+       line 419, "pan.___", state 1416, "(!((cache_dirty_generation_ptr.bitfield&(1<<( ((_pid<2)) -> (0) : (1) )))))"
+       line 419, "pan.___", state 1416, "else"
+       line 419, "pan.___", state 1419, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 180, "pan.___", state 1448, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 184, "pan.___", state 1461, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 161, "pan.___", state 1471, "(1)"
+       line 165, "pan.___", state 1479, "(1)"
+       line 169, "pan.___", state 1491, "(1)"
+       line 176, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 184, "pan.___", state 1524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 1534, "(1)"
+       line 165, "pan.___", state 1542, "(1)"
+       line 169, "pan.___", state 1554, "(1)"
+       line 176, "pan.___", state 1569, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 180, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 184, "pan.___", state 1591, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<( ((_pid<2)) -> (0) : (1) ))))"
+       line 161, "pan.___", state 1601, "(1)"
+       line 165, "pan.___", state 1609, "(1)"
+       line 169, "pan.___", state 1621, "(1)"
+       line 370, "pan.___", state 1642, "(1)"
+       line 696, "pan.___", state 1643, "(1)"
+       line 703, "pan.___", state 1646, "-end-"
+       (308 of 1646 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 752, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 30.2 seconds
+pan: rate 93347.646 states/second
+pan: avg transition delay 9.1279e-07 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input
new file mode 100644 (file)
index 0000000..eb1d4e6
--- /dev/null
@@ -0,0 +1,724 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu/result-signal-over-reader/urcu_progress_writer_error.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-writer/DEFINES b/formal-model/urcu/result-signal-over-writer/DEFINES
new file mode 100644 (file)
index 0000000..ec600f0
--- /dev/null
@@ -0,0 +1,16 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-signal-over-writer/Makefile b/formal-model/urcu/result-signal-over-writer/Makefile
new file mode 100644 (file)
index 0000000..8af320d
--- /dev/null
@@ -0,0 +1,172 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       #nested useless with signal test.
+       #make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-signal-over-writer/asserts.log b/formal-model/urcu/result-signal-over-writer/asserts.log
new file mode 100644 (file)
index 0000000..c102ffb
--- /dev/null
@@ -0,0 +1,334 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             - (none specified)
+       assertion violations    +
+       cycle checks            - (disabled by -DSAFETY)
+       invalid end states      +
+
+State-vector 40 byte, depth reached 7872, errors: 0
+    20128 states, stored
+   191477 states, matched
+   211605 transitions (= stored+matched)
+   712166 atomic steps
+hash conflicts:       942 (resolved)
+
+Stats on memory usage (in Megabytes):
+    1.305      equivalent memory usage for states (stored*(State-vector + overhead))
+    1.467      actual memory usage for states (unsuccessful compression: 112.36%)
+               state-vector as stored = 48 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  467.229      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 401, ".input.spin", state 330, "(1)"
+       line 612, ".input.spin", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 397, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 406, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 59, "(1)"
+       line 416, ".input.spin", state 89, "(1)"
+       line 397, ".input.spin", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 160, "(1)"
+       line 650, ".input.spin", state 213, "(1)"
+       line 173, ".input.spin", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 233, "(1)"
+       line 158, ".input.spin", state 254, "(1)"
+       line 162, ".input.spin", state 262, "(1)"
+       line 166, ".input.spin", state 274, "(1)"
+       line 173, ".input.spin", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, ".input.spin", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 317, "(1)"
+       line 162, ".input.spin", state 325, "(1)"
+       line 166, ".input.spin", state 337, "(1)"
+       line 173, ".input.spin", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, ".input.spin", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 384, "(1)"
+       line 162, ".input.spin", state 392, "(1)"
+       line 166, ".input.spin", state 404, "(1)"
+       line 397, ".input.spin", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 441, "(1)"
+       line 406, ".input.spin", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 470, "(1)"
+       line 416, ".input.spin", state 500, "(1)"
+       line 397, ".input.spin", state 526, "(1)"
+       line 401, ".input.spin", state 540, "(1)"
+       line 406, ".input.spin", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 599, "(1)"
+       line 401, ".input.spin", state 640, "(1)"
+       line 406, ".input.spin", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 699, "(1)"
+       line 173, ".input.spin", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 722, "(1)"
+       line 177, ".input.spin", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 731, "(1)"
+       line 177, ".input.spin", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 732, "else"
+       line 175, ".input.spin", state 737, "((j<1))"
+       line 175, ".input.spin", state 737, "((j>=1))"
+       line 181, ".input.spin", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 752, "(1)"
+       line 162, ".input.spin", state 760, "(1)"
+       line 162, ".input.spin", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 761, "else"
+       line 160, ".input.spin", state 766, "((j<1))"
+       line 160, ".input.spin", state 766, "((j>=1))"
+       line 166, ".input.spin", state 772, "(1)"
+       line 166, ".input.spin", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 773, "else"
+       line 168, ".input.spin", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 776, "else"
+       line 173, ".input.spin", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, ".input.spin", state 785, "(1)"
+       line 177, ".input.spin", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 794, "(1)"
+       line 177, ".input.spin", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, ".input.spin", state 795, "else"
+       line 175, ".input.spin", state 800, "((j<1))"
+       line 175, ".input.spin", state 800, "((j>=1))"
+       line 181, ".input.spin", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 815, "(1)"
+       line 162, ".input.spin", state 823, "(1)"
+       line 162, ".input.spin", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, ".input.spin", state 824, "else"
+       line 160, ".input.spin", state 829, "((j<1))"
+       line 160, ".input.spin", state 829, "((j>=1))"
+       line 166, ".input.spin", state 835, "(1)"
+       line 166, ".input.spin", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, ".input.spin", state 836, "else"
+       line 168, ".input.spin", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, ".input.spin", state 839, "else"
+       line 200, ".input.spin", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, ".input.spin", state 841, "else"
+       line 212, ".input.spin", state 845, "((i<1))"
+       line 212, ".input.spin", state 845, "((i>=1))"
+       line 173, ".input.spin", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 852, "(1)"
+       line 177, ".input.spin", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 861, "(1)"
+       line 177, ".input.spin", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 862, "else"
+       line 175, ".input.spin", state 867, "((j<1))"
+       line 175, ".input.spin", state 867, "((j>=1))"
+       line 181, ".input.spin", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 882, "(1)"
+       line 162, ".input.spin", state 890, "(1)"
+       line 162, ".input.spin", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 891, "else"
+       line 160, ".input.spin", state 896, "((j<1))"
+       line 160, ".input.spin", state 896, "((j>=1))"
+       line 166, ".input.spin", state 902, "(1)"
+       line 166, ".input.spin", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 903, "else"
+       line 168, ".input.spin", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 906, "else"
+       line 200, ".input.spin", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, ".input.spin", state 908, "else"
+       line 219, ".input.spin", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, ".input.spin", state 909, "else"
+       line 354, ".input.spin", state 915, "((sighand_exec==1))"
+       line 354, ".input.spin", state 915, "else"
+       line 360, ".input.spin", state 918, "sighand_exec = 1"
+       line 397, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, ".input.spin", state 933, "(1)"
+       line 397, ".input.spin", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, ".input.spin", state 934, "else"
+       line 397, ".input.spin", state 937, "(1)"
+       line 401, ".input.spin", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 947, "(1)"
+       line 401, ".input.spin", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, ".input.spin", state 948, "else"
+       line 401, ".input.spin", state 951, "(1)"
+       line 401, ".input.spin", state 952, "(1)"
+       line 401, ".input.spin", state 952, "(1)"
+       line 399, ".input.spin", state 957, "((i<1))"
+       line 399, ".input.spin", state 957, "((i>=1))"
+       line 406, ".input.spin", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 976, "(1)"
+       line 407, ".input.spin", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, ".input.spin", state 977, "else"
+       line 407, ".input.spin", state 980, "(1)"
+       line 407, ".input.spin", state 981, "(1)"
+       line 407, ".input.spin", state 981, "(1)"
+       line 411, ".input.spin", state 989, "(1)"
+       line 411, ".input.spin", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, ".input.spin", state 990, "else"
+       line 411, ".input.spin", state 993, "(1)"
+       line 411, ".input.spin", state 994, "(1)"
+       line 411, ".input.spin", state 994, "(1)"
+       line 409, ".input.spin", state 999, "((i<1))"
+       line 409, ".input.spin", state 999, "((i>=1))"
+       line 416, ".input.spin", state 1006, "(1)"
+       line 416, ".input.spin", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, ".input.spin", state 1007, "else"
+       line 416, ".input.spin", state 1010, "(1)"
+       line 416, ".input.spin", state 1011, "(1)"
+       line 416, ".input.spin", state 1011, "(1)"
+       line 418, ".input.spin", state 1014, "(1)"
+       line 418, ".input.spin", state 1014, "(1)"
+       line 360, ".input.spin", state 1023, "sighand_exec = 1"
+       line 401, ".input.spin", state 1054, "(1)"
+       line 406, ".input.spin", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1113, "(1)"
+       line 401, ".input.spin", state 1151, "(1)"
+       line 406, ".input.spin", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1210, "(1)"
+       line 397, ".input.spin", state 1236, "(1)"
+       line 401, ".input.spin", state 1250, "(1)"
+       line 406, ".input.spin", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1309, "(1)"
+       line 401, ".input.spin", state 1350, "(1)"
+       line 406, ".input.spin", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1409, "(1)"
+       line 173, ".input.spin", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 1432, "(1)"
+       line 177, ".input.spin", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1441, "(1)"
+       line 177, ".input.spin", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 1442, "else"
+       line 175, ".input.spin", state 1447, "((j<1))"
+       line 175, ".input.spin", state 1447, "((j>=1))"
+       line 181, ".input.spin", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1462, "(1)"
+       line 162, ".input.spin", state 1470, "(1)"
+       line 162, ".input.spin", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 1471, "else"
+       line 160, ".input.spin", state 1476, "((j<1))"
+       line 160, ".input.spin", state 1476, "((j>=1))"
+       line 166, ".input.spin", state 1482, "(1)"
+       line 166, ".input.spin", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 1483, "else"
+       line 168, ".input.spin", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 1486, "else"
+       line 173, ".input.spin", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, ".input.spin", state 1495, "(1)"
+       line 177, ".input.spin", state 1502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 1504, "(1)"
+       line 177, ".input.spin", state 1505, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, ".input.spin", state 1505, "else"
+       line 175, ".input.spin", state 1510, "((j<1))"
+       line 175, ".input.spin", state 1510, "((j>=1))"
+       line 181, ".input.spin", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 1525, "(1)"
+       line 162, ".input.spin", state 1533, "(1)"
+       line 162, ".input.spin", state 1534, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, ".input.spin", state 1534, "else"
+       line 160, ".input.spin", state 1539, "((j<1))"
+       line 160, ".input.spin", state 1539, "((j>=1))"
+       line 166, ".input.spin", state 1545, "(1)"
+       line 166, ".input.spin", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, ".input.spin", state 1546, "else"
+       line 168, ".input.spin", state 1549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, ".input.spin", state 1549, "else"
+       line 200, ".input.spin", state 1551, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, ".input.spin", state 1551, "else"
+       line 212, ".input.spin", state 1555, "((i<1))"
+       line 212, ".input.spin", state 1555, "((i>=1))"
+       line 173, ".input.spin", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 1562, "(1)"
+       line 177, ".input.spin", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1571, "(1)"
+       line 177, ".input.spin", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 1572, "else"
+       line 175, ".input.spin", state 1577, "((j<1))"
+       line 175, ".input.spin", state 1577, "((j>=1))"
+       line 181, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1592, "(1)"
+       line 162, ".input.spin", state 1600, "(1)"
+       line 162, ".input.spin", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 1601, "else"
+       line 160, ".input.spin", state 1606, "((j<1))"
+       line 160, ".input.spin", state 1606, "((j>=1))"
+       line 166, ".input.spin", state 1612, "(1)"
+       line 166, ".input.spin", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 1613, "else"
+       line 168, ".input.spin", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 1616, "else"
+       line 200, ".input.spin", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, ".input.spin", state 1618, "else"
+       line 219, ".input.spin", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, ".input.spin", state 1619, "else"
+       line 354, ".input.spin", state 1625, "((sighand_exec==1))"
+       line 354, ".input.spin", state 1625, "else"
+       line 360, ".input.spin", state 1628, "sighand_exec = 1"
+       line 397, ".input.spin", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, ".input.spin", state 1643, "(1)"
+       line 397, ".input.spin", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, ".input.spin", state 1644, "else"
+       line 397, ".input.spin", state 1647, "(1)"
+       line 401, ".input.spin", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 1657, "(1)"
+       line 401, ".input.spin", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, ".input.spin", state 1658, "else"
+       line 401, ".input.spin", state 1661, "(1)"
+       line 401, ".input.spin", state 1662, "(1)"
+       line 401, ".input.spin", state 1662, "(1)"
+       line 399, ".input.spin", state 1667, "((i<1))"
+       line 399, ".input.spin", state 1667, "((i>=1))"
+       line 406, ".input.spin", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 1686, "(1)"
+       line 407, ".input.spin", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, ".input.spin", state 1687, "else"
+       line 407, ".input.spin", state 1690, "(1)"
+       line 407, ".input.spin", state 1691, "(1)"
+       line 407, ".input.spin", state 1691, "(1)"
+       line 411, ".input.spin", state 1699, "(1)"
+       line 411, ".input.spin", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, ".input.spin", state 1700, "else"
+       line 411, ".input.spin", state 1703, "(1)"
+       line 411, ".input.spin", state 1704, "(1)"
+       line 411, ".input.spin", state 1704, "(1)"
+       line 409, ".input.spin", state 1709, "((i<1))"
+       line 409, ".input.spin", state 1709, "((i>=1))"
+       line 416, ".input.spin", state 1716, "(1)"
+       line 416, ".input.spin", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, ".input.spin", state 1717, "else"
+       line 416, ".input.spin", state 1720, "(1)"
+       line 416, ".input.spin", state 1721, "(1)"
+       line 416, ".input.spin", state 1721, "(1)"
+       line 418, ".input.spin", state 1724, "(1)"
+       line 418, ".input.spin", state 1724, "(1)"
+       line 360, ".input.spin", state 1733, "sighand_exec = 1"
+       line 177, ".input.spin", state 1758, "(1)"
+       line 181, ".input.spin", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1779, "(1)"
+       line 162, ".input.spin", state 1787, "(1)"
+       line 166, ".input.spin", state 1799, "(1)"
+       line 173, ".input.spin", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 1819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, ".input.spin", state 1832, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 1842, "(1)"
+       line 162, ".input.spin", state 1850, "(1)"
+       line 166, ".input.spin", state 1862, "(1)"
+       line 173, ".input.spin", state 1877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1886, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, ".input.spin", state 1899, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1909, "(1)"
+       line 162, ".input.spin", state 1917, "(1)"
+       line 166, ".input.spin", state 1929, "(1)"
+       line 700, ".input.spin", state 1968, "-end-"
+       (215 of 1968 states)
+unreached in proctype :init:
+       (0 of 46 states)
+
+pan: elapsed time 0.12 seconds
+pan: rate 167733.33 states/second
+pan: avg transition delay 5.6709e-07 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/asserts.spin.input b/formal-model/urcu/result-signal-over-writer/asserts.spin.input
new file mode 100644 (file)
index 0000000..953115f
--- /dev/null
@@ -0,0 +1,721 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/asserts.spin.input.trail b/formal-model/urcu/result-signal-over-writer/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/DEFINES b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/DEFINES
new file mode 100644 (file)
index 0000000..ec600f0
--- /dev/null
@@ -0,0 +1,16 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/Makefile b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/Makefile
new file mode 100644 (file)
index 0000000..8af320d
--- /dev/null
@@ -0,0 +1,172 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       #nested useless with signal test.
+       #make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.log b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.log
new file mode 100644 (file)
index 0000000..c102ffb
--- /dev/null
@@ -0,0 +1,334 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             - (none specified)
+       assertion violations    +
+       cycle checks            - (disabled by -DSAFETY)
+       invalid end states      +
+
+State-vector 40 byte, depth reached 7872, errors: 0
+    20128 states, stored
+   191477 states, matched
+   211605 transitions (= stored+matched)
+   712166 atomic steps
+hash conflicts:       942 (resolved)
+
+Stats on memory usage (in Megabytes):
+    1.305      equivalent memory usage for states (stored*(State-vector + overhead))
+    1.467      actual memory usage for states (unsuccessful compression: 112.36%)
+               state-vector as stored = 48 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  467.229      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 401, ".input.spin", state 330, "(1)"
+       line 612, ".input.spin", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 397, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 406, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 59, "(1)"
+       line 416, ".input.spin", state 89, "(1)"
+       line 397, ".input.spin", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 160, "(1)"
+       line 650, ".input.spin", state 213, "(1)"
+       line 173, ".input.spin", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 233, "(1)"
+       line 158, ".input.spin", state 254, "(1)"
+       line 162, ".input.spin", state 262, "(1)"
+       line 166, ".input.spin", state 274, "(1)"
+       line 173, ".input.spin", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, ".input.spin", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 317, "(1)"
+       line 162, ".input.spin", state 325, "(1)"
+       line 166, ".input.spin", state 337, "(1)"
+       line 173, ".input.spin", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, ".input.spin", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 384, "(1)"
+       line 162, ".input.spin", state 392, "(1)"
+       line 166, ".input.spin", state 404, "(1)"
+       line 397, ".input.spin", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 441, "(1)"
+       line 406, ".input.spin", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 470, "(1)"
+       line 416, ".input.spin", state 500, "(1)"
+       line 397, ".input.spin", state 526, "(1)"
+       line 401, ".input.spin", state 540, "(1)"
+       line 406, ".input.spin", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 599, "(1)"
+       line 401, ".input.spin", state 640, "(1)"
+       line 406, ".input.spin", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 699, "(1)"
+       line 173, ".input.spin", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 722, "(1)"
+       line 177, ".input.spin", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 731, "(1)"
+       line 177, ".input.spin", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 732, "else"
+       line 175, ".input.spin", state 737, "((j<1))"
+       line 175, ".input.spin", state 737, "((j>=1))"
+       line 181, ".input.spin", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 752, "(1)"
+       line 162, ".input.spin", state 760, "(1)"
+       line 162, ".input.spin", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 761, "else"
+       line 160, ".input.spin", state 766, "((j<1))"
+       line 160, ".input.spin", state 766, "((j>=1))"
+       line 166, ".input.spin", state 772, "(1)"
+       line 166, ".input.spin", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 773, "else"
+       line 168, ".input.spin", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 776, "else"
+       line 173, ".input.spin", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, ".input.spin", state 785, "(1)"
+       line 177, ".input.spin", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 794, "(1)"
+       line 177, ".input.spin", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, ".input.spin", state 795, "else"
+       line 175, ".input.spin", state 800, "((j<1))"
+       line 175, ".input.spin", state 800, "((j>=1))"
+       line 181, ".input.spin", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 815, "(1)"
+       line 162, ".input.spin", state 823, "(1)"
+       line 162, ".input.spin", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, ".input.spin", state 824, "else"
+       line 160, ".input.spin", state 829, "((j<1))"
+       line 160, ".input.spin", state 829, "((j>=1))"
+       line 166, ".input.spin", state 835, "(1)"
+       line 166, ".input.spin", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, ".input.spin", state 836, "else"
+       line 168, ".input.spin", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, ".input.spin", state 839, "else"
+       line 200, ".input.spin", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, ".input.spin", state 841, "else"
+       line 212, ".input.spin", state 845, "((i<1))"
+       line 212, ".input.spin", state 845, "((i>=1))"
+       line 173, ".input.spin", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 852, "(1)"
+       line 177, ".input.spin", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 861, "(1)"
+       line 177, ".input.spin", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 862, "else"
+       line 175, ".input.spin", state 867, "((j<1))"
+       line 175, ".input.spin", state 867, "((j>=1))"
+       line 181, ".input.spin", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 882, "(1)"
+       line 162, ".input.spin", state 890, "(1)"
+       line 162, ".input.spin", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 891, "else"
+       line 160, ".input.spin", state 896, "((j<1))"
+       line 160, ".input.spin", state 896, "((j>=1))"
+       line 166, ".input.spin", state 902, "(1)"
+       line 166, ".input.spin", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 903, "else"
+       line 168, ".input.spin", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 906, "else"
+       line 200, ".input.spin", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, ".input.spin", state 908, "else"
+       line 219, ".input.spin", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, ".input.spin", state 909, "else"
+       line 354, ".input.spin", state 915, "((sighand_exec==1))"
+       line 354, ".input.spin", state 915, "else"
+       line 360, ".input.spin", state 918, "sighand_exec = 1"
+       line 397, ".input.spin", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, ".input.spin", state 933, "(1)"
+       line 397, ".input.spin", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, ".input.spin", state 934, "else"
+       line 397, ".input.spin", state 937, "(1)"
+       line 401, ".input.spin", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 947, "(1)"
+       line 401, ".input.spin", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, ".input.spin", state 948, "else"
+       line 401, ".input.spin", state 951, "(1)"
+       line 401, ".input.spin", state 952, "(1)"
+       line 401, ".input.spin", state 952, "(1)"
+       line 399, ".input.spin", state 957, "((i<1))"
+       line 399, ".input.spin", state 957, "((i>=1))"
+       line 406, ".input.spin", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 976, "(1)"
+       line 407, ".input.spin", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, ".input.spin", state 977, "else"
+       line 407, ".input.spin", state 980, "(1)"
+       line 407, ".input.spin", state 981, "(1)"
+       line 407, ".input.spin", state 981, "(1)"
+       line 411, ".input.spin", state 989, "(1)"
+       line 411, ".input.spin", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, ".input.spin", state 990, "else"
+       line 411, ".input.spin", state 993, "(1)"
+       line 411, ".input.spin", state 994, "(1)"
+       line 411, ".input.spin", state 994, "(1)"
+       line 409, ".input.spin", state 999, "((i<1))"
+       line 409, ".input.spin", state 999, "((i>=1))"
+       line 416, ".input.spin", state 1006, "(1)"
+       line 416, ".input.spin", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, ".input.spin", state 1007, "else"
+       line 416, ".input.spin", state 1010, "(1)"
+       line 416, ".input.spin", state 1011, "(1)"
+       line 416, ".input.spin", state 1011, "(1)"
+       line 418, ".input.spin", state 1014, "(1)"
+       line 418, ".input.spin", state 1014, "(1)"
+       line 360, ".input.spin", state 1023, "sighand_exec = 1"
+       line 401, ".input.spin", state 1054, "(1)"
+       line 406, ".input.spin", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1113, "(1)"
+       line 401, ".input.spin", state 1151, "(1)"
+       line 406, ".input.spin", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1210, "(1)"
+       line 397, ".input.spin", state 1236, "(1)"
+       line 401, ".input.spin", state 1250, "(1)"
+       line 406, ".input.spin", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1309, "(1)"
+       line 401, ".input.spin", state 1350, "(1)"
+       line 406, ".input.spin", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, ".input.spin", state 1409, "(1)"
+       line 173, ".input.spin", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 1432, "(1)"
+       line 177, ".input.spin", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1441, "(1)"
+       line 177, ".input.spin", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 1442, "else"
+       line 175, ".input.spin", state 1447, "((j<1))"
+       line 175, ".input.spin", state 1447, "((j>=1))"
+       line 181, ".input.spin", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1462, "(1)"
+       line 162, ".input.spin", state 1470, "(1)"
+       line 162, ".input.spin", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 1471, "else"
+       line 160, ".input.spin", state 1476, "((j<1))"
+       line 160, ".input.spin", state 1476, "((j>=1))"
+       line 166, ".input.spin", state 1482, "(1)"
+       line 166, ".input.spin", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 1483, "else"
+       line 168, ".input.spin", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 1486, "else"
+       line 173, ".input.spin", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, ".input.spin", state 1495, "(1)"
+       line 177, ".input.spin", state 1502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 1504, "(1)"
+       line 177, ".input.spin", state 1505, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, ".input.spin", state 1505, "else"
+       line 175, ".input.spin", state 1510, "((j<1))"
+       line 175, ".input.spin", state 1510, "((j>=1))"
+       line 181, ".input.spin", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 1525, "(1)"
+       line 162, ".input.spin", state 1533, "(1)"
+       line 162, ".input.spin", state 1534, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, ".input.spin", state 1534, "else"
+       line 160, ".input.spin", state 1539, "((j<1))"
+       line 160, ".input.spin", state 1539, "((j>=1))"
+       line 166, ".input.spin", state 1545, "(1)"
+       line 166, ".input.spin", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, ".input.spin", state 1546, "else"
+       line 168, ".input.spin", state 1549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, ".input.spin", state 1549, "else"
+       line 200, ".input.spin", state 1551, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, ".input.spin", state 1551, "else"
+       line 212, ".input.spin", state 1555, "((i<1))"
+       line 212, ".input.spin", state 1555, "((i>=1))"
+       line 173, ".input.spin", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, ".input.spin", state 1562, "(1)"
+       line 177, ".input.spin", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1571, "(1)"
+       line 177, ".input.spin", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, ".input.spin", state 1572, "else"
+       line 175, ".input.spin", state 1577, "((j<1))"
+       line 175, ".input.spin", state 1577, "((j>=1))"
+       line 181, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1592, "(1)"
+       line 162, ".input.spin", state 1600, "(1)"
+       line 162, ".input.spin", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, ".input.spin", state 1601, "else"
+       line 160, ".input.spin", state 1606, "((j<1))"
+       line 160, ".input.spin", state 1606, "((j>=1))"
+       line 166, ".input.spin", state 1612, "(1)"
+       line 166, ".input.spin", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, ".input.spin", state 1613, "else"
+       line 168, ".input.spin", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, ".input.spin", state 1616, "else"
+       line 200, ".input.spin", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, ".input.spin", state 1618, "else"
+       line 219, ".input.spin", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, ".input.spin", state 1619, "else"
+       line 354, ".input.spin", state 1625, "((sighand_exec==1))"
+       line 354, ".input.spin", state 1625, "else"
+       line 360, ".input.spin", state 1628, "sighand_exec = 1"
+       line 397, ".input.spin", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, ".input.spin", state 1643, "(1)"
+       line 397, ".input.spin", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, ".input.spin", state 1644, "else"
+       line 397, ".input.spin", state 1647, "(1)"
+       line 401, ".input.spin", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, ".input.spin", state 1657, "(1)"
+       line 401, ".input.spin", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, ".input.spin", state 1658, "else"
+       line 401, ".input.spin", state 1661, "(1)"
+       line 401, ".input.spin", state 1662, "(1)"
+       line 401, ".input.spin", state 1662, "(1)"
+       line 399, ".input.spin", state 1667, "((i<1))"
+       line 399, ".input.spin", state 1667, "((i>=1))"
+       line 406, ".input.spin", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, ".input.spin", state 1686, "(1)"
+       line 407, ".input.spin", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, ".input.spin", state 1687, "else"
+       line 407, ".input.spin", state 1690, "(1)"
+       line 407, ".input.spin", state 1691, "(1)"
+       line 407, ".input.spin", state 1691, "(1)"
+       line 411, ".input.spin", state 1699, "(1)"
+       line 411, ".input.spin", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, ".input.spin", state 1700, "else"
+       line 411, ".input.spin", state 1703, "(1)"
+       line 411, ".input.spin", state 1704, "(1)"
+       line 411, ".input.spin", state 1704, "(1)"
+       line 409, ".input.spin", state 1709, "((i<1))"
+       line 409, ".input.spin", state 1709, "((i>=1))"
+       line 416, ".input.spin", state 1716, "(1)"
+       line 416, ".input.spin", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, ".input.spin", state 1717, "else"
+       line 416, ".input.spin", state 1720, "(1)"
+       line 416, ".input.spin", state 1721, "(1)"
+       line 416, ".input.spin", state 1721, "(1)"
+       line 418, ".input.spin", state 1724, "(1)"
+       line 418, ".input.spin", state 1724, "(1)"
+       line 360, ".input.spin", state 1733, "sighand_exec = 1"
+       line 177, ".input.spin", state 1758, "(1)"
+       line 181, ".input.spin", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1779, "(1)"
+       line 162, ".input.spin", state 1787, "(1)"
+       line 166, ".input.spin", state 1799, "(1)"
+       line 173, ".input.spin", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, ".input.spin", state 1819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, ".input.spin", state 1832, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, ".input.spin", state 1842, "(1)"
+       line 162, ".input.spin", state 1850, "(1)"
+       line 166, ".input.spin", state 1862, "(1)"
+       line 173, ".input.spin", state 1877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, ".input.spin", state 1886, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, ".input.spin", state 1899, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, ".input.spin", state 1909, "(1)"
+       line 162, ".input.spin", state 1917, "(1)"
+       line 166, ".input.spin", state 1929, "(1)"
+       line 700, ".input.spin", state 1968, "-end-"
+       (215 of 1968 states)
+unreached in proctype :init:
+       (0 of 46 states)
+
+pan: elapsed time 0.12 seconds
+pan: rate 167733.33 states/second
+pan: avg transition delay 5.6709e-07 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input
new file mode 100644 (file)
index 0000000..953115f
--- /dev/null
@@ -0,0 +1,721 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/references.txt b/formal-model/urcu/result-signal-over-writer/result-signal-over-writer/references.txt
new file mode 100644 (file)
index 0000000..72c67a2
--- /dev/null
@@ -0,0 +1,13 @@
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+  (downloaded)
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/.input.define b/formal-model/urcu/result-signal-over-writer/testmerge/.input.define
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/.input.spin b/formal-model/urcu/result-signal-over-writer/testmerge/.input.spin
new file mode 100644 (file)
index 0000000..f2737c4
--- /dev/null
@@ -0,0 +1,531 @@
+
+#define NR_READERS 2
+#define NR_WRITERS 1
+
+#define NR_PROCS 3
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/DEFINES b/formal-model/urcu/result-signal-over-writer/testmerge/DEFINES
new file mode 100644 (file)
index 0000000..12c751b
--- /dev/null
@@ -0,0 +1,31 @@
+
+#define NR_READERS 2
+#define NR_WRITERS 1
+
+#define NR_PROCS 3
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/Makefile b/formal-model/urcu/result-signal-over-writer/testmerge/Makefile
new file mode 100644 (file)
index 0000000..ca932b7
--- /dev/null
@@ -0,0 +1,165 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/asserts.log b/formal-model/urcu/result-signal-over-writer/testmerge/asserts.log
new file mode 100644 (file)
index 0000000..75f2427
--- /dev/null
@@ -0,0 +1,10 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+spin: line 295 replacement value: tmp
+spin: line 295 ".input.spin", Error: formal par of wait_for_quiescent_state contains replacement value saw '-2'' near 'readerid'
+spin: 1 error(s) - aborting
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input
new file mode 100644 (file)
index 0000000..b06898a
--- /dev/null
@@ -0,0 +1,409 @@
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#define read_free_race (read_generation == last_free_gen)
+#define read_free      (free_done && data_access)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               if
+               :: (NR_READERS > 1) && (i < NR_READERS - 1)
+                       -> ooo_mem(j);
+               :: else
+                       -> skip;
+               fi;
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [NR_WRITERS] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               smp_mb(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/references.txt b/formal-model/urcu/result-signal-over-writer/testmerge/references.txt
new file mode 100644 (file)
index 0000000..72c67a2
--- /dev/null
@@ -0,0 +1,13 @@
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+  (downloaded)
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu.sh b/formal-model/urcu/result-signal-over-writer/testmerge/urcu.sh
new file mode 100644 (file)
index 0000000..65ff517
--- /dev/null
@@ -0,0 +1,29 @@
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+#               Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+#          Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin b/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin
new file mode 100644 (file)
index 0000000..61d9052
--- /dev/null
@@ -0,0 +1,500 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp2 b/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp2
new file mode 100644 (file)
index 0000000..b1c8311
--- /dev/null
@@ -0,0 +1,395 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_WRITERS 1
+#define NR_READERS 3
+
+/* Number of reader and writer processes */
+#define NR_PROCS 5
+
+/* Includes reader, writer and init process */
+#define MAX_NR_PROCS 5
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+               skip;
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+               skip;
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_writerid() (get_pid())
+#define get_readerid() (get_writerrid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       skip;
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2, nest)
+{
+       nest_i = 0;
+       do
+       :: nest_i < nest ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               ooo_mem(i);
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= nest -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < nest ->
+               ooo_mem(i);
+               smp_mb(i);
+               ooo_mem(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= nest -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [2] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2, 2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [1] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               ooo_mem(i);
+               smp_mb(i);
+               ooo_mem(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp5 b/formal-model/urcu/result-signal-over-writer/testmerge/urcu.spin.bkp5
new file mode 100644 (file)
index 0000000..324ee39
--- /dev/null
@@ -0,0 +1,398 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               if
+               :: (NR_READERS > 1) && (i < NR_READERS - 1)
+                       -> ooo_mem(j);
+               :: else
+                       -> skip;
+               fi;
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [NR_WRITERS] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               smp_mb(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.log
new file mode 100644 (file)
index 0000000..6a04aba
--- /dev/null
@@ -0,0 +1,414 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 566)
+Depth=    4234 States=    1e+06 Transitions=  1.7e+07 Memory=   527.287        t=   31.3 R=   3e+04
+Depth=    4234 States=    2e+06 Transitions= 3.44e+07 Memory=   588.322        t=   63.9 R=   3e+04
+Depth=    4234 States=    3e+06 Transitions=  5.2e+07 Memory=   649.358        t=     97 R=   3e+04
+pan: resizing hashtable to -w22..  done
+Depth=    4234 States=    4e+06 Transitions= 6.97e+07 Memory=   741.416        t=    130 R=   3e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 4234, errors: 0
+  4027146 states, stored
+ 66145121 states, matched
+ 70172267 transitions (= stored+matched)
+2.6437688e+08 atomic steps
+hash conflicts:  47318190 (resolved)
+
+Stats on memory usage (in Megabytes):
+  322.609      equivalent memory usage for states (stored*(State-vector + overhead))
+  253.418      actual memory usage for states (compression: 78.55%)
+               state-vector as stored = 38 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  743.076      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 288, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 61, "(1)"
+       line 307, "pan.___", state 91, "(1)"
+       line 288, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 149, "(1)"
+       line 307, "pan.___", state 179, "(1)"
+       line 288, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 238, "(1)"
+       line 307, "pan.___", state 268, "(1)"
+       line 158, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 291, "(1)"
+       line 162, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 300, "(1)"
+       line 162, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 301, "else"
+       line 160, "pan.___", state 306, "((j<1))"
+       line 160, "pan.___", state 306, "((j>=1))"
+       line 166, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 321, "(1)"
+       line 147, "pan.___", state 329, "(1)"
+       line 147, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 330, "else"
+       line 145, "pan.___", state 335, "((j<1))"
+       line 145, "pan.___", state 335, "((j>=1))"
+       line 151, "pan.___", state 341, "(1)"
+       line 151, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 342, "else"
+       line 153, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 345, "else"
+       line 185, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 347, "else"
+       line 158, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 354, "(1)"
+       line 162, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 162, "pan.___", state 363, "(1)"
+       line 162, "pan.___", state 364, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 162, "pan.___", state 364, "else"
+       line 160, "pan.___", state 369, "((j<1))"
+       line 160, "pan.___", state 369, "((j>=1))"
+       line 166, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 384, "(1)"
+       line 147, "pan.___", state 392, "(1)"
+       line 147, "pan.___", state 393, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 147, "pan.___", state 393, "else"
+       line 145, "pan.___", state 398, "((j<1))"
+       line 145, "pan.___", state 398, "((j>=1))"
+       line 151, "pan.___", state 404, "(1)"
+       line 151, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 151, "pan.___", state 405, "else"
+       line 153, "pan.___", state 408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 153, "pan.___", state 408, "else"
+       line 185, "pan.___", state 410, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 185, "pan.___", state 410, "else"
+       line 199, "pan.___", state 414, "((i<1))"
+       line 199, "pan.___", state 414, "((i>=1))"
+       line 158, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 421, "(1)"
+       line 162, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 430, "(1)"
+       line 162, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 431, "else"
+       line 160, "pan.___", state 436, "((j<1))"
+       line 160, "pan.___", state 436, "((j>=1))"
+       line 166, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 451, "(1)"
+       line 147, "pan.___", state 459, "(1)"
+       line 147, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 460, "else"
+       line 145, "pan.___", state 465, "((j<1))"
+       line 145, "pan.___", state 465, "((j>=1))"
+       line 151, "pan.___", state 471, "(1)"
+       line 151, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 472, "else"
+       line 153, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 475, "else"
+       line 185, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 477, "else"
+       line 288, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 537, "(1)"
+       line 307, "pan.___", state 567, "(1)"
+       line 288, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 625, "(1)"
+       line 307, "pan.___", state 655, "(1)"
+       line 288, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 713, "(1)"
+       line 307, "pan.___", state 743, "(1)"
+       line 158, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 760, "(1)"
+       line 162, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 769, "(1)"
+       line 162, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 770, "else"
+       line 160, "pan.___", state 775, "((j<1))"
+       line 160, "pan.___", state 775, "((j>=1))"
+       line 166, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 790, "(1)"
+       line 147, "pan.___", state 798, "(1)"
+       line 147, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 799, "else"
+       line 145, "pan.___", state 804, "((j<1))"
+       line 145, "pan.___", state 804, "((j>=1))"
+       line 151, "pan.___", state 810, "(1)"
+       line 151, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 811, "else"
+       line 153, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 814, "else"
+       line 185, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 816, "else"
+       line 158, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 823, "(1)"
+       line 162, "pan.___", state 830, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 162, "pan.___", state 832, "(1)"
+       line 162, "pan.___", state 833, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 162, "pan.___", state 833, "else"
+       line 160, "pan.___", state 838, "((j<1))"
+       line 160, "pan.___", state 838, "((j>=1))"
+       line 166, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 853, "(1)"
+       line 147, "pan.___", state 861, "(1)"
+       line 147, "pan.___", state 862, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 147, "pan.___", state 862, "else"
+       line 145, "pan.___", state 867, "((j<1))"
+       line 145, "pan.___", state 867, "((j>=1))"
+       line 151, "pan.___", state 873, "(1)"
+       line 151, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 151, "pan.___", state 874, "else"
+       line 153, "pan.___", state 877, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 153, "pan.___", state 877, "else"
+       line 185, "pan.___", state 879, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 185, "pan.___", state 879, "else"
+       line 199, "pan.___", state 883, "((i<1))"
+       line 199, "pan.___", state 883, "((i>=1))"
+       line 158, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 890, "(1)"
+       line 162, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 899, "(1)"
+       line 162, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 900, "else"
+       line 160, "pan.___", state 905, "((j<1))"
+       line 160, "pan.___", state 905, "((j>=1))"
+       line 166, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 920, "(1)"
+       line 147, "pan.___", state 928, "(1)"
+       line 147, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 929, "else"
+       line 145, "pan.___", state 934, "((j<1))"
+       line 145, "pan.___", state 934, "((j>=1))"
+       line 151, "pan.___", state 940, "(1)"
+       line 151, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 941, "else"
+       line 153, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 944, "else"
+       line 185, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 946, "else"
+       line 288, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1001, "(1)"
+       line 307, "pan.___", state 1031, "(1)"
+       line 288, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1097, "(1)"
+       line 307, "pan.___", state 1127, "(1)"
+       line 433, "pan.___", state 1140, "-end-"
+       (125 of 1140 states)
+unreached in proctype urcu_writer
+       line 288, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 59, "(1)"
+       line 302, "pan.___", state 72, "(1)"
+       line 307, "pan.___", state 89, "(1)"
+       line 288, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 151, "(1)"
+       line 302, "pan.___", state 164, "(1)"
+       line 467, "pan.___", state 195, "(1)"
+       line 158, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 237, "(1)"
+       line 147, "pan.___", state 245, "(1)"
+       line 151, "pan.___", state 257, "(1)"
+       line 158, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 290, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 300, "(1)"
+       line 147, "pan.___", state 308, "(1)"
+       line 151, "pan.___", state 320, "(1)"
+       line 158, "pan.___", state 335, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 344, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 357, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 367, "(1)"
+       line 147, "pan.___", state 375, "(1)"
+       line 151, "pan.___", state 387, "(1)"
+       line 288, "pan.___", state 403, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 448, "(1)"
+       line 302, "pan.___", state 461, "(1)"
+       line 307, "pan.___", state 478, "(1)"
+       line 288, "pan.___", state 495, "(1)"
+       line 292, "pan.___", state 507, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 525, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 551, "(1)"
+       line 307, "pan.___", state 568, "(1)"
+       line 292, "pan.___", state 598, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 642, "(1)"
+       line 307, "pan.___", state 659, "(1)"
+       line 162, "pan.___", state 681, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 694, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 704, "(1)"
+       line 147, "pan.___", state 712, "(1)"
+       line 151, "pan.___", state 724, "(1)"
+       line 158, "pan.___", state 735, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 757, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 767, "(1)"
+       line 147, "pan.___", state 775, "(1)"
+       line 151, "pan.___", state 787, "(1)"
+       line 158, "pan.___", state 802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 811, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 824, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 834, "(1)"
+       line 147, "pan.___", state 842, "(1)"
+       line 151, "pan.___", state 854, "(1)"
+       line 288, "pan.___", state 878, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 288, "pan.___", state 880, "(1)"
+       line 288, "pan.___", state 881, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 288, "pan.___", state 881, "else"
+       line 288, "pan.___", state 884, "(1)"
+       line 292, "pan.___", state 892, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 894, "(1)"
+       line 292, "pan.___", state 895, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 292, "pan.___", state 895, "else"
+       line 292, "pan.___", state 898, "(1)"
+       line 292, "pan.___", state 899, "(1)"
+       line 292, "pan.___", state 899, "(1)"
+       line 290, "pan.___", state 904, "((i<1))"
+       line 290, "pan.___", state 904, "((i>=1))"
+       line 297, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 923, "(1)"
+       line 298, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 298, "pan.___", state 924, "else"
+       line 298, "pan.___", state 927, "(1)"
+       line 298, "pan.___", state 928, "(1)"
+       line 298, "pan.___", state 928, "(1)"
+       line 302, "pan.___", state 936, "(1)"
+       line 302, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 302, "pan.___", state 937, "else"
+       line 302, "pan.___", state 940, "(1)"
+       line 302, "pan.___", state 941, "(1)"
+       line 302, "pan.___", state 941, "(1)"
+       line 300, "pan.___", state 946, "((i<1))"
+       line 300, "pan.___", state 946, "((i>=1))"
+       line 307, "pan.___", state 953, "(1)"
+       line 307, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 307, "pan.___", state 954, "else"
+       line 307, "pan.___", state 957, "(1)"
+       line 307, "pan.___", state 958, "(1)"
+       line 307, "pan.___", state 958, "(1)"
+       line 309, "pan.___", state 961, "(1)"
+       line 309, "pan.___", state 961, "(1)"
+       line 292, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1008, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1034, "(1)"
+       line 307, "pan.___", state 1051, "(1)"
+       line 292, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1096, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1122, "(1)"
+       line 307, "pan.___", state 1139, "(1)"
+       line 288, "pan.___", state 1156, "(1)"
+       line 292, "pan.___", state 1168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1186, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1212, "(1)"
+       line 307, "pan.___", state 1229, "(1)"
+       line 292, "pan.___", state 1259, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1277, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1303, "(1)"
+       line 307, "pan.___", state 1320, "(1)"
+       line 162, "pan.___", state 1342, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1355, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1365, "(1)"
+       line 147, "pan.___", state 1373, "(1)"
+       line 151, "pan.___", state 1385, "(1)"
+       line 158, "pan.___", state 1396, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 1418, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 1428, "(1)"
+       line 147, "pan.___", state 1436, "(1)"
+       line 151, "pan.___", state 1448, "(1)"
+       line 158, "pan.___", state 1463, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 1472, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1485, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1495, "(1)"
+       line 147, "pan.___", state 1503, "(1)"
+       line 151, "pan.___", state 1515, "(1)"
+       line 288, "pan.___", state 1539, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 288, "pan.___", state 1541, "(1)"
+       line 288, "pan.___", state 1542, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 288, "pan.___", state 1542, "else"
+       line 288, "pan.___", state 1545, "(1)"
+       line 292, "pan.___", state 1553, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 1555, "(1)"
+       line 292, "pan.___", state 1556, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 292, "pan.___", state 1556, "else"
+       line 292, "pan.___", state 1559, "(1)"
+       line 292, "pan.___", state 1560, "(1)"
+       line 292, "pan.___", state 1560, "(1)"
+       line 290, "pan.___", state 1565, "((i<1))"
+       line 290, "pan.___", state 1565, "((i>=1))"
+       line 297, "pan.___", state 1571, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1584, "(1)"
+       line 298, "pan.___", state 1585, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 298, "pan.___", state 1585, "else"
+       line 298, "pan.___", state 1588, "(1)"
+       line 298, "pan.___", state 1589, "(1)"
+       line 298, "pan.___", state 1589, "(1)"
+       line 302, "pan.___", state 1597, "(1)"
+       line 302, "pan.___", state 1598, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 302, "pan.___", state 1598, "else"
+       line 302, "pan.___", state 1601, "(1)"
+       line 302, "pan.___", state 1602, "(1)"
+       line 302, "pan.___", state 1602, "(1)"
+       line 300, "pan.___", state 1607, "((i<1))"
+       line 300, "pan.___", state 1607, "((i>=1))"
+       line 307, "pan.___", state 1614, "(1)"
+       line 307, "pan.___", state 1615, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 307, "pan.___", state 1615, "else"
+       line 307, "pan.___", state 1618, "(1)"
+       line 307, "pan.___", state 1619, "(1)"
+       line 307, "pan.___", state 1619, "(1)"
+       line 309, "pan.___", state 1622, "(1)"
+       line 309, "pan.___", state 1622, "(1)"
+       line 162, "pan.___", state 1646, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1659, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1669, "(1)"
+       line 147, "pan.___", state 1677, "(1)"
+       line 151, "pan.___", state 1689, "(1)"
+       line 158, "pan.___", state 1700, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 1722, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 1732, "(1)"
+       line 147, "pan.___", state 1740, "(1)"
+       line 151, "pan.___", state 1752, "(1)"
+       line 158, "pan.___", state 1767, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 1776, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1789, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1799, "(1)"
+       line 147, "pan.___", state 1807, "(1)"
+       line 151, "pan.___", state 1819, "(1)"
+       line 510, "pan.___", state 1845, "-end-"
+       (158 of 1845 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 571, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 131 seconds
+pan: rate 30683.017 states/second
+pan: avg transition delay 1.8704e-06 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.ltl b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.ltl
new file mode 100644 (file)
index 0000000..1954414
--- /dev/null
@@ -0,0 +1 @@
+[] (read_free -> !read_free_race)
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input
new file mode 100644 (file)
index 0000000..18f99c4
--- /dev/null
@@ -0,0 +1,531 @@
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free.spin.input.trail
new file mode 100644 (file)
index 0000000..0d22946
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+1889:1:626
+1890:1:637
+1891:1:642
+1892:1:643
+1893:0:3013
+1894:2:2964
+1895:0:3013
+1896:1:655
+1897:0:3011
+1898:2:2963
+1899:0:3017
+1900:1:655
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.define
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.log
new file mode 100644 (file)
index 0000000..708dee2
--- /dev/null
@@ -0,0 +1,415 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_nested.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 566)
+Depth=    4234 States=    1e+06 Transitions=  1.7e+07 Memory=   527.287        t=   31.2 R=   3e+04
+Depth=    4234 States=    2e+06 Transitions= 3.44e+07 Memory=   588.322        t=   63.7 R=   3e+04
+Depth=    4234 States=    3e+06 Transitions=  5.2e+07 Memory=   649.358        t=   96.8 R=   3e+04
+pan: resizing hashtable to -w22..  done
+Depth=    4234 States=    4e+06 Transitions= 6.97e+07 Memory=   741.416        t=    130 R=   3e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 4234, errors: 0
+  4027146 states, stored
+ 66145121 states, matched
+ 70172267 transitions (= stored+matched)
+2.6437688e+08 atomic steps
+hash conflicts:  47318190 (resolved)
+
+Stats on memory usage (in Megabytes):
+  322.609      equivalent memory usage for states (stored*(State-vector + overhead))
+  253.418      actual memory usage for states (compression: 78.55%)
+               state-vector as stored = 38 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  743.076      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 288, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 61, "(1)"
+       line 307, "pan.___", state 91, "(1)"
+       line 288, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 149, "(1)"
+       line 307, "pan.___", state 179, "(1)"
+       line 288, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 238, "(1)"
+       line 307, "pan.___", state 268, "(1)"
+       line 158, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 291, "(1)"
+       line 162, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 300, "(1)"
+       line 162, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 301, "else"
+       line 160, "pan.___", state 306, "((j<1))"
+       line 160, "pan.___", state 306, "((j>=1))"
+       line 166, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 321, "(1)"
+       line 147, "pan.___", state 329, "(1)"
+       line 147, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 330, "else"
+       line 145, "pan.___", state 335, "((j<1))"
+       line 145, "pan.___", state 335, "((j>=1))"
+       line 151, "pan.___", state 341, "(1)"
+       line 151, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 342, "else"
+       line 153, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 345, "else"
+       line 185, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 347, "else"
+       line 158, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 354, "(1)"
+       line 162, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 162, "pan.___", state 363, "(1)"
+       line 162, "pan.___", state 364, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 162, "pan.___", state 364, "else"
+       line 160, "pan.___", state 369, "((j<1))"
+       line 160, "pan.___", state 369, "((j>=1))"
+       line 166, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 384, "(1)"
+       line 147, "pan.___", state 392, "(1)"
+       line 147, "pan.___", state 393, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 147, "pan.___", state 393, "else"
+       line 145, "pan.___", state 398, "((j<1))"
+       line 145, "pan.___", state 398, "((j>=1))"
+       line 151, "pan.___", state 404, "(1)"
+       line 151, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 151, "pan.___", state 405, "else"
+       line 153, "pan.___", state 408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 153, "pan.___", state 408, "else"
+       line 185, "pan.___", state 410, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 185, "pan.___", state 410, "else"
+       line 199, "pan.___", state 414, "((i<1))"
+       line 199, "pan.___", state 414, "((i>=1))"
+       line 158, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 421, "(1)"
+       line 162, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 430, "(1)"
+       line 162, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 431, "else"
+       line 160, "pan.___", state 436, "((j<1))"
+       line 160, "pan.___", state 436, "((j>=1))"
+       line 166, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 451, "(1)"
+       line 147, "pan.___", state 459, "(1)"
+       line 147, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 460, "else"
+       line 145, "pan.___", state 465, "((j<1))"
+       line 145, "pan.___", state 465, "((j>=1))"
+       line 151, "pan.___", state 471, "(1)"
+       line 151, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 472, "else"
+       line 153, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 475, "else"
+       line 185, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 477, "else"
+       line 288, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 537, "(1)"
+       line 307, "pan.___", state 567, "(1)"
+       line 288, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 625, "(1)"
+       line 307, "pan.___", state 655, "(1)"
+       line 288, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 713, "(1)"
+       line 307, "pan.___", state 743, "(1)"
+       line 158, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 760, "(1)"
+       line 162, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 769, "(1)"
+       line 162, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 770, "else"
+       line 160, "pan.___", state 775, "((j<1))"
+       line 160, "pan.___", state 775, "((j>=1))"
+       line 166, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 790, "(1)"
+       line 147, "pan.___", state 798, "(1)"
+       line 147, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 799, "else"
+       line 145, "pan.___", state 804, "((j<1))"
+       line 145, "pan.___", state 804, "((j>=1))"
+       line 151, "pan.___", state 810, "(1)"
+       line 151, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 811, "else"
+       line 153, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 814, "else"
+       line 185, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 816, "else"
+       line 158, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 823, "(1)"
+       line 162, "pan.___", state 830, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 162, "pan.___", state 832, "(1)"
+       line 162, "pan.___", state 833, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 162, "pan.___", state 833, "else"
+       line 160, "pan.___", state 838, "((j<1))"
+       line 160, "pan.___", state 838, "((j>=1))"
+       line 166, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 853, "(1)"
+       line 147, "pan.___", state 861, "(1)"
+       line 147, "pan.___", state 862, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 147, "pan.___", state 862, "else"
+       line 145, "pan.___", state 867, "((j<1))"
+       line 145, "pan.___", state 867, "((j>=1))"
+       line 151, "pan.___", state 873, "(1)"
+       line 151, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 151, "pan.___", state 874, "else"
+       line 153, "pan.___", state 877, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 153, "pan.___", state 877, "else"
+       line 185, "pan.___", state 879, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 185, "pan.___", state 879, "else"
+       line 199, "pan.___", state 883, "((i<1))"
+       line 199, "pan.___", state 883, "((i>=1))"
+       line 158, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 158, "pan.___", state 890, "(1)"
+       line 162, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 899, "(1)"
+       line 162, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 162, "pan.___", state 900, "else"
+       line 160, "pan.___", state 905, "((j<1))"
+       line 160, "pan.___", state 905, "((j>=1))"
+       line 166, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 920, "(1)"
+       line 147, "pan.___", state 928, "(1)"
+       line 147, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 147, "pan.___", state 929, "else"
+       line 145, "pan.___", state 934, "((j<1))"
+       line 145, "pan.___", state 934, "((j>=1))"
+       line 151, "pan.___", state 940, "(1)"
+       line 151, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 151, "pan.___", state 941, "else"
+       line 153, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 153, "pan.___", state 944, "else"
+       line 185, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 185, "pan.___", state 946, "else"
+       line 288, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1001, "(1)"
+       line 307, "pan.___", state 1031, "(1)"
+       line 288, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1097, "(1)"
+       line 307, "pan.___", state 1127, "(1)"
+       line 433, "pan.___", state 1140, "-end-"
+       (125 of 1140 states)
+unreached in proctype urcu_writer
+       line 288, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 59, "(1)"
+       line 302, "pan.___", state 72, "(1)"
+       line 307, "pan.___", state 89, "(1)"
+       line 288, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 151, "(1)"
+       line 302, "pan.___", state 164, "(1)"
+       line 467, "pan.___", state 195, "(1)"
+       line 158, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 237, "(1)"
+       line 147, "pan.___", state 245, "(1)"
+       line 151, "pan.___", state 257, "(1)"
+       line 158, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 290, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 300, "(1)"
+       line 147, "pan.___", state 308, "(1)"
+       line 151, "pan.___", state 320, "(1)"
+       line 158, "pan.___", state 335, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 344, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 357, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 367, "(1)"
+       line 147, "pan.___", state 375, "(1)"
+       line 151, "pan.___", state 387, "(1)"
+       line 288, "pan.___", state 403, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 448, "(1)"
+       line 302, "pan.___", state 461, "(1)"
+       line 307, "pan.___", state 478, "(1)"
+       line 288, "pan.___", state 495, "(1)"
+       line 292, "pan.___", state 507, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 525, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 551, "(1)"
+       line 307, "pan.___", state 568, "(1)"
+       line 292, "pan.___", state 598, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 642, "(1)"
+       line 307, "pan.___", state 659, "(1)"
+       line 162, "pan.___", state 681, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 694, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 704, "(1)"
+       line 147, "pan.___", state 712, "(1)"
+       line 151, "pan.___", state 724, "(1)"
+       line 158, "pan.___", state 735, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 757, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 767, "(1)"
+       line 147, "pan.___", state 775, "(1)"
+       line 151, "pan.___", state 787, "(1)"
+       line 158, "pan.___", state 802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 811, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 824, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 834, "(1)"
+       line 147, "pan.___", state 842, "(1)"
+       line 151, "pan.___", state 854, "(1)"
+       line 288, "pan.___", state 878, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 288, "pan.___", state 880, "(1)"
+       line 288, "pan.___", state 881, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 288, "pan.___", state 881, "else"
+       line 288, "pan.___", state 884, "(1)"
+       line 292, "pan.___", state 892, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 894, "(1)"
+       line 292, "pan.___", state 895, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 292, "pan.___", state 895, "else"
+       line 292, "pan.___", state 898, "(1)"
+       line 292, "pan.___", state 899, "(1)"
+       line 292, "pan.___", state 899, "(1)"
+       line 290, "pan.___", state 904, "((i<1))"
+       line 290, "pan.___", state 904, "((i>=1))"
+       line 297, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 923, "(1)"
+       line 298, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 298, "pan.___", state 924, "else"
+       line 298, "pan.___", state 927, "(1)"
+       line 298, "pan.___", state 928, "(1)"
+       line 298, "pan.___", state 928, "(1)"
+       line 302, "pan.___", state 936, "(1)"
+       line 302, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 302, "pan.___", state 937, "else"
+       line 302, "pan.___", state 940, "(1)"
+       line 302, "pan.___", state 941, "(1)"
+       line 302, "pan.___", state 941, "(1)"
+       line 300, "pan.___", state 946, "((i<1))"
+       line 300, "pan.___", state 946, "((i>=1))"
+       line 307, "pan.___", state 953, "(1)"
+       line 307, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 307, "pan.___", state 954, "else"
+       line 307, "pan.___", state 957, "(1)"
+       line 307, "pan.___", state 958, "(1)"
+       line 307, "pan.___", state 958, "(1)"
+       line 309, "pan.___", state 961, "(1)"
+       line 309, "pan.___", state 961, "(1)"
+       line 292, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1008, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1034, "(1)"
+       line 307, "pan.___", state 1051, "(1)"
+       line 292, "pan.___", state 1078, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1096, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1122, "(1)"
+       line 307, "pan.___", state 1139, "(1)"
+       line 288, "pan.___", state 1156, "(1)"
+       line 292, "pan.___", state 1168, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1186, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1212, "(1)"
+       line 307, "pan.___", state 1229, "(1)"
+       line 292, "pan.___", state 1259, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 297, "pan.___", state 1277, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 302, "pan.___", state 1303, "(1)"
+       line 307, "pan.___", state 1320, "(1)"
+       line 162, "pan.___", state 1342, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1355, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1365, "(1)"
+       line 147, "pan.___", state 1373, "(1)"
+       line 151, "pan.___", state 1385, "(1)"
+       line 158, "pan.___", state 1396, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 1418, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 1428, "(1)"
+       line 147, "pan.___", state 1436, "(1)"
+       line 151, "pan.___", state 1448, "(1)"
+       line 158, "pan.___", state 1463, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 1472, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1485, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1495, "(1)"
+       line 147, "pan.___", state 1503, "(1)"
+       line 151, "pan.___", state 1515, "(1)"
+       line 288, "pan.___", state 1539, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 288, "pan.___", state 1541, "(1)"
+       line 288, "pan.___", state 1542, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 288, "pan.___", state 1542, "else"
+       line 288, "pan.___", state 1545, "(1)"
+       line 292, "pan.___", state 1553, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 292, "pan.___", state 1555, "(1)"
+       line 292, "pan.___", state 1556, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 292, "pan.___", state 1556, "else"
+       line 292, "pan.___", state 1559, "(1)"
+       line 292, "pan.___", state 1560, "(1)"
+       line 292, "pan.___", state 1560, "(1)"
+       line 290, "pan.___", state 1565, "((i<1))"
+       line 290, "pan.___", state 1565, "((i>=1))"
+       line 297, "pan.___", state 1571, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1584, "(1)"
+       line 298, "pan.___", state 1585, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 298, "pan.___", state 1585, "else"
+       line 298, "pan.___", state 1588, "(1)"
+       line 298, "pan.___", state 1589, "(1)"
+       line 298, "pan.___", state 1589, "(1)"
+       line 302, "pan.___", state 1597, "(1)"
+       line 302, "pan.___", state 1598, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 302, "pan.___", state 1598, "else"
+       line 302, "pan.___", state 1601, "(1)"
+       line 302, "pan.___", state 1602, "(1)"
+       line 302, "pan.___", state 1602, "(1)"
+       line 300, "pan.___", state 1607, "((i<1))"
+       line 300, "pan.___", state 1607, "((i>=1))"
+       line 307, "pan.___", state 1614, "(1)"
+       line 307, "pan.___", state 1615, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 307, "pan.___", state 1615, "else"
+       line 307, "pan.___", state 1618, "(1)"
+       line 307, "pan.___", state 1619, "(1)"
+       line 307, "pan.___", state 1619, "(1)"
+       line 309, "pan.___", state 1622, "(1)"
+       line 309, "pan.___", state 1622, "(1)"
+       line 162, "pan.___", state 1646, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1659, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1669, "(1)"
+       line 147, "pan.___", state 1677, "(1)"
+       line 151, "pan.___", state 1689, "(1)"
+       line 158, "pan.___", state 1700, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 166, "pan.___", state 1722, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 143, "pan.___", state 1732, "(1)"
+       line 147, "pan.___", state 1740, "(1)"
+       line 151, "pan.___", state 1752, "(1)"
+       line 158, "pan.___", state 1767, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 162, "pan.___", state 1776, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 166, "pan.___", state 1789, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 143, "pan.___", state 1799, "(1)"
+       line 147, "pan.___", state 1807, "(1)"
+       line 151, "pan.___", state 1819, "(1)"
+       line 510, "pan.___", state 1845, "-end-"
+       (158 of 1845 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 571, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 131 seconds
+pan: rate 30755.659 states/second
+pan: avg transition delay 1.866e-06 usec
+cp .input.spin urcu_free_nested.spin.input
+cp .input.spin.trail urcu_free_nested.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input
new file mode 100644 (file)
index 0000000..18f99c4
--- /dev/null
@@ -0,0 +1,531 @@
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_nested.spin.input.trail
new file mode 100644 (file)
index 0000000..2cefe6b
--- /dev/null
@@ -0,0 +1,7 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:0:2679
+5:3:1129
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.define
new file mode 100644 (file)
index 0000000..136ef67
--- /dev/null
@@ -0,0 +1,2 @@
+#define NO_RMB
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.log
new file mode 100644 (file)
index 0000000..c722840
--- /dev/null
@@ -0,0 +1,16 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+spin: line 291 "pan.___", Error: syntax error  saw 'operator: ='
+spin: line 291 "pan.___", Error: syntax error  saw 'operator: ='
+spin: 2 error(s) - aborting
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input
new file mode 100644 (file)
index 0000000..1346c4e
--- /dev/null
@@ -0,0 +1,533 @@
+#define NO_RMB
+#define NO_WMB
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_mb.spin.input.trail
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+1926:1:194
+1927:1:202
+1928:1:203
+1929:1:207
+1930:1:208
+1931:1:216
+1932:1:221
+1933:1:225
+1934:1:226
+1935:1:233
+1936:1:234
+1937:1:245
+1938:1:246
+1939:1:247
+1940:1:258
+1941:1:263
+1942:1:264
+1943:0:3537
+1944:2:3484
+1945:0:3537
+1946:1:276
+1947:0:3537
+1948:2:3483
+1949:0:3537
+1950:1:561
+1951:0:3537
+1952:2:3484
+1953:0:3537
+1954:1:562
+1955:0:3537
+1956:2:3483
+1957:0:3537
+1958:1:11
+1959:0:3537
+1960:2:3484
+1961:0:3537
+1962:1:12
+1963:1:16
+1964:1:17
+1965:1:25
+1966:1:26
+1967:1:27
+1968:1:39
+1969:1:44
+1970:1:48
+1971:1:49
+1972:1:56
+1973:1:57
+1974:1:68
+1975:1:69
+1976:1:70
+1977:1:81
+1978:1:86
+1979:1:87
+1980:0:3537
+1981:2:3483
+1982:0:3537
+1983:1:99
+1984:0:3537
+1985:2:3484
+1986:0:3537
+1987:1:100
+1988:1:104
+1989:1:105
+1990:1:113
+1991:1:114
+1992:1:118
+1993:1:119
+1994:1:127
+1995:1:132
+1996:1:136
+1997:1:137
+1998:1:144
+1999:1:145
+2000:1:156
+2001:1:157
+2002:1:158
+2003:1:169
+2004:1:174
+2005:1:175
+2006:0:3537
+2007:2:3483
+2008:0:3537
+2009:1:279
+2010:0:3537
+2011:2:3484
+2012:0:3537
+2013:1:280
+2014:0:3537
+2015:2:3483
+2016:0:3537
+2017:1:561
+2018:0:3537
+2019:2:3484
+2020:0:3537
+2021:1:562
+2022:0:3537
+2023:2:3483
+2024:0:3537
+2025:1:567
+2026:0:3537
+2027:2:3484
+2028:0:3537
+2029:1:572
+2030:1:576
+2031:1:577
+2032:1:585
+2033:1:586
+2034:1:587
+2035:1:599
+2036:1:604
+2037:1:608
+2038:1:609
+2039:1:616
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+2041:1:628
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+2043:1:630
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+2051:0:3537
+2052:2:3484
+2053:0:3537
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+2057:1:673
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+2063:1:696
+2064:1:697
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+2066:1:705
+2067:1:716
+2068:1:717
+2069:1:718
+2070:1:729
+2071:1:734
+2072:1:735
+2073:0:3537
+2074:2:3483
+2075:0:3537
+2076:1:747
+2077:0:3535
+2078:2:3484
+2079:0:3541
+2080:1:1280
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.define
new file mode 100644 (file)
index 0000000..73e61a4
--- /dev/null
@@ -0,0 +1 @@
+#define NO_RMB
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.log
new file mode 100644 (file)
index 0000000..6a46f80
--- /dev/null
@@ -0,0 +1,369 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 567)
+Depth=    5645 States=    1e+06 Transitions= 1.47e+07 Memory=   527.287        t=   27.1 R=   4e+04
+pan: claim violated! (at depth 1736)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 5645, errors: 1
+  1039881 states, stored
+ 14441478 states, matched
+ 15481359 transitions (= stored+matched)
+ 57000435 atomic steps
+hash conflicts:   2892596 (resolved)
+
+Stats on memory usage (in Megabytes):
+   83.303      equivalent memory usage for states (stored*(State-vector + overhead))
+   64.050      actual memory usage for states (compression: 76.89%)
+               state-vector as stored = 37 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  529.729      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 61, "(1)"
+       line 308, "pan.___", state 91, "(1)"
+       line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 149, "(1)"
+       line 308, "pan.___", state 179, "(1)"
+       line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 238, "(1)"
+       line 308, "pan.___", state 268, "(1)"
+       line 159, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 291, "(1)"
+       line 163, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 300, "(1)"
+       line 163, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 301, "else"
+       line 161, "pan.___", state 306, "((j<1))"
+       line 161, "pan.___", state 306, "((j>=1))"
+       line 167, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 313, "(1)"
+       line 167, "pan.___", state 314, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))"
+       line 167, "pan.___", state 314, "else"
+       line 177, "pan.___", state 319, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 177, "pan.___", state 319, "else"
+       line 159, "pan.___", state 324, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 326, "(1)"
+       line 163, "pan.___", state 333, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 163, "pan.___", state 335, "(1)"
+       line 163, "pan.___", state 336, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 163, "pan.___", state 336, "else"
+       line 161, "pan.___", state 341, "((j<1))"
+       line 161, "pan.___", state 341, "((j>=1))"
+       line 167, "pan.___", state 346, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 348, "(1)"
+       line 167, "pan.___", state 349, "((cache_dirty_generation_ptr.bitfield&(1<<i)))"
+       line 167, "pan.___", state 349, "else"
+       line 177, "pan.___", state 354, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 177, "pan.___", state 354, "else"
+       line 200, "pan.___", state 358, "((i<1))"
+       line 200, "pan.___", state 358, "((i>=1))"
+       line 159, "pan.___", state 363, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 365, "(1)"
+       line 163, "pan.___", state 372, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 374, "(1)"
+       line 163, "pan.___", state 375, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 375, "else"
+       line 161, "pan.___", state 380, "((j<1))"
+       line 161, "pan.___", state 380, "((j>=1))"
+       line 167, "pan.___", state 385, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 387, "(1)"
+       line 167, "pan.___", state 388, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))"
+       line 167, "pan.___", state 388, "else"
+       line 177, "pan.___", state 393, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 177, "pan.___", state 393, "else"
+       line 289, "pan.___", state 408, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 440, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 453, "(1)"
+       line 308, "pan.___", state 483, "(1)"
+       line 289, "pan.___", state 496, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 541, "(1)"
+       line 308, "pan.___", state 571, "(1)"
+       line 289, "pan.___", state 584, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 629, "(1)"
+       line 308, "pan.___", state 659, "(1)"
+       line 159, "pan.___", state 674, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 676, "(1)"
+       line 163, "pan.___", state 683, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 685, "(1)"
+       line 163, "pan.___", state 686, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 686, "else"
+       line 161, "pan.___", state 691, "((j<1))"
+       line 161, "pan.___", state 691, "((j>=1))"
+       line 167, "pan.___", state 696, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 698, "(1)"
+       line 167, "pan.___", state 699, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))"
+       line 167, "pan.___", state 699, "else"
+       line 177, "pan.___", state 704, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 177, "pan.___", state 704, "else"
+       line 159, "pan.___", state 709, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 711, "(1)"
+       line 163, "pan.___", state 718, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 163, "pan.___", state 720, "(1)"
+       line 163, "pan.___", state 721, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 163, "pan.___", state 721, "else"
+       line 161, "pan.___", state 726, "((j<1))"
+       line 161, "pan.___", state 726, "((j>=1))"
+       line 167, "pan.___", state 731, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 733, "(1)"
+       line 167, "pan.___", state 734, "((cache_dirty_generation_ptr.bitfield&(1<<i)))"
+       line 167, "pan.___", state 734, "else"
+       line 177, "pan.___", state 739, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 177, "pan.___", state 739, "else"
+       line 200, "pan.___", state 743, "((i<1))"
+       line 200, "pan.___", state 743, "((i>=1))"
+       line 159, "pan.___", state 748, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 750, "(1)"
+       line 163, "pan.___", state 757, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 759, "(1)"
+       line 163, "pan.___", state 760, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 760, "else"
+       line 161, "pan.___", state 765, "((j<1))"
+       line 161, "pan.___", state 765, "((j>=1))"
+       line 167, "pan.___", state 770, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 772, "(1)"
+       line 167, "pan.___", state 773, "((cache_dirty_generation_ptr.bitfield&(1<<_pid)))"
+       line 167, "pan.___", state 773, "else"
+       line 177, "pan.___", state 778, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 177, "pan.___", state 778, "else"
+       line 289, "pan.___", state 788, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 820, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 833, "(1)"
+       line 308, "pan.___", state 863, "(1)"
+       line 289, "pan.___", state 884, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 916, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 929, "(1)"
+       line 308, "pan.___", state 959, "(1)"
+       line 434, "pan.___", state 972, "-end-"
+       (95 of 972 states)
+unreached in proctype urcu_writer
+       line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 20, "(1)"
+       line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 34, "(1)"
+       line 293, "pan.___", state 35, "(1)"
+       line 293, "pan.___", state 35, "(1)"
+       line 291, "pan.___", state 40, "((i<1))"
+       line 291, "pan.___", state 40, "((i>=1))"
+       line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 59, "(1)"
+       line 299, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 60, "else"
+       line 299, "pan.___", state 63, "(1)"
+       line 299, "pan.___", state 64, "(1)"
+       line 299, "pan.___", state 64, "(1)"
+       line 303, "pan.___", state 72, "(1)"
+       line 303, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 73, "else"
+       line 303, "pan.___", state 76, "(1)"
+       line 303, "pan.___", state 77, "(1)"
+       line 303, "pan.___", state 77, "(1)"
+       line 301, "pan.___", state 82, "((i<1))"
+       line 301, "pan.___", state 82, "((i>=1))"
+       line 308, "pan.___", state 89, "(1)"
+       line 308, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 90, "else"
+       line 308, "pan.___", state 93, "(1)"
+       line 308, "pan.___", state 94, "(1)"
+       line 308, "pan.___", state 94, "(1)"
+       line 310, "pan.___", state 97, "(1)"
+       line 310, "pan.___", state 97, "(1)"
+       line 456, "pan.___", state 101, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 454, "pan.___", state 102, "old_gen = cached_generation_ptr.val[_pid]"
+       line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 112, "(1)"
+       line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 126, "(1)"
+       line 293, "pan.___", state 127, "(1)"
+       line 293, "pan.___", state 127, "(1)"
+       line 299, "pan.___", state 151, "(1)"
+       line 303, "pan.___", state 164, "(1)"
+       line 310, "pan.___", state 189, "(1)"
+       line 310, "pan.___", state 189, "(1)"
+       line 468, "pan.___", state 195, "(1)"
+       line 159, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 240, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 262, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 279, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 288, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 301, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 319, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 333, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 351, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 364, "(1)"
+       line 303, "pan.___", state 377, "(1)"
+       line 308, "pan.___", state 394, "(1)"
+       line 289, "pan.___", state 411, "(1)"
+       line 293, "pan.___", state 423, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 467, "(1)"
+       line 308, "pan.___", state 484, "(1)"
+       line 293, "pan.___", state 514, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 532, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 558, "(1)"
+       line 308, "pan.___", state 575, "(1)"
+       line 163, "pan.___", state 597, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 610, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 623, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 645, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 662, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 671, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 684, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 710, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 712, "(1)"
+       line 289, "pan.___", state 713, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 289, "pan.___", state 713, "else"
+       line 289, "pan.___", state 716, "(1)"
+       line 293, "pan.___", state 724, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 726, "(1)"
+       line 293, "pan.___", state 727, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 293, "pan.___", state 727, "else"
+       line 293, "pan.___", state 730, "(1)"
+       line 293, "pan.___", state 731, "(1)"
+       line 293, "pan.___", state 731, "(1)"
+       line 291, "pan.___", state 736, "((i<1))"
+       line 291, "pan.___", state 736, "((i>=1))"
+       line 298, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 755, "(1)"
+       line 299, "pan.___", state 756, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 756, "else"
+       line 299, "pan.___", state 759, "(1)"
+       line 299, "pan.___", state 760, "(1)"
+       line 299, "pan.___", state 760, "(1)"
+       line 303, "pan.___", state 768, "(1)"
+       line 303, "pan.___", state 769, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 769, "else"
+       line 303, "pan.___", state 772, "(1)"
+       line 303, "pan.___", state 773, "(1)"
+       line 303, "pan.___", state 773, "(1)"
+       line 301, "pan.___", state 778, "((i<1))"
+       line 301, "pan.___", state 778, "((i>=1))"
+       line 308, "pan.___", state 785, "(1)"
+       line 308, "pan.___", state 786, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 786, "else"
+       line 308, "pan.___", state 789, "(1)"
+       line 308, "pan.___", state 790, "(1)"
+       line 308, "pan.___", state 790, "(1)"
+       line 310, "pan.___", state 793, "(1)"
+       line 310, "pan.___", state 793, "(1)"
+       line 293, "pan.___", state 822, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 840, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 866, "(1)"
+       line 308, "pan.___", state 883, "(1)"
+       line 293, "pan.___", state 910, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 928, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 954, "(1)"
+       line 308, "pan.___", state 971, "(1)"
+       line 289, "pan.___", state 988, "(1)"
+       line 293, "pan.___", state 1000, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1018, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 1044, "(1)"
+       line 308, "pan.___", state 1061, "(1)"
+       line 293, "pan.___", state 1091, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1109, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 1135, "(1)"
+       line 308, "pan.___", state 1152, "(1)"
+       line 163, "pan.___", state 1174, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 1187, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1200, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 1222, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1239, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 1248, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 1261, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 1287, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 1289, "(1)"
+       line 289, "pan.___", state 1290, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 289, "pan.___", state 1290, "else"
+       line 289, "pan.___", state 1293, "(1)"
+       line 293, "pan.___", state 1301, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 1303, "(1)"
+       line 293, "pan.___", state 1304, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 293, "pan.___", state 1304, "else"
+       line 293, "pan.___", state 1307, "(1)"
+       line 293, "pan.___", state 1308, "(1)"
+       line 293, "pan.___", state 1308, "(1)"
+       line 291, "pan.___", state 1313, "((i<1))"
+       line 291, "pan.___", state 1313, "((i>=1))"
+       line 298, "pan.___", state 1319, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 1332, "(1)"
+       line 299, "pan.___", state 1333, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 1333, "else"
+       line 299, "pan.___", state 1336, "(1)"
+       line 299, "pan.___", state 1337, "(1)"
+       line 299, "pan.___", state 1337, "(1)"
+       line 303, "pan.___", state 1345, "(1)"
+       line 303, "pan.___", state 1346, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 1346, "else"
+       line 303, "pan.___", state 1349, "(1)"
+       line 303, "pan.___", state 1350, "(1)"
+       line 303, "pan.___", state 1350, "(1)"
+       line 301, "pan.___", state 1355, "((i<1))"
+       line 301, "pan.___", state 1355, "((i>=1))"
+       line 308, "pan.___", state 1362, "(1)"
+       line 308, "pan.___", state 1363, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 1363, "else"
+       line 308, "pan.___", state 1366, "(1)"
+       line 308, "pan.___", state 1367, "(1)"
+       line 308, "pan.___", state 1367, "(1)"
+       line 310, "pan.___", state 1370, "(1)"
+       line 310, "pan.___", state 1370, "(1)"
+       line 163, "pan.___", state 1394, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 1407, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1420, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 1442, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1459, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 1468, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 1481, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 511, "pan.___", state 1509, "-end-"
+       (143 of 1509 states)
+unreached in proctype :init:
+       line 518, "pan.___", state 9, "((j<2))"
+       line 518, "pan.___", state 9, "((j>=2))"
+       line 519, "pan.___", state 20, "((j<2))"
+       line 519, "pan.___", state 20, "((j>=2))"
+       line 524, "pan.___", state 33, "((j<2))"
+       line 524, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 572, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 28.5 seconds
+pan: rate 36487.053 states/second
+pan: avg transition delay 1.8409e-06 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input
new file mode 100644 (file)
index 0000000..899fdb4
--- /dev/null
@@ -0,0 +1,532 @@
+#define NO_RMB
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_rmb.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.define
new file mode 100644 (file)
index 0000000..710f29d
--- /dev/null
@@ -0,0 +1 @@
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.log
new file mode 100644 (file)
index 0000000..477c85d
--- /dev/null
@@ -0,0 +1,381 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 567)
+pan: claim violated! (at depth 1889)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 6646, errors: 1
+   377244 states, stored
+  5291719 states, matched
+  5668963 transitions (= stored+matched)
+ 20822372 atomic steps
+hash conflicts:    405371 (resolved)
+
+Stats on memory usage (in Megabytes):
+   30.221      equivalent memory usage for states (stored*(State-vector + overhead))
+   23.526      actual memory usage for states (compression: 77.85%)
+               state-vector as stored = 37 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  489.201      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 61, "(1)"
+       line 308, "pan.___", state 91, "(1)"
+       line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 149, "(1)"
+       line 308, "pan.___", state 179, "(1)"
+       line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 238, "(1)"
+       line 308, "pan.___", state 268, "(1)"
+       line 144, "pan.___", state 290, "(1)"
+       line 148, "pan.___", state 298, "(1)"
+       line 148, "pan.___", state 299, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 299, "else"
+       line 146, "pan.___", state 304, "((j<1))"
+       line 146, "pan.___", state 304, "((j>=1))"
+       line 152, "pan.___", state 310, "(1)"
+       line 152, "pan.___", state 311, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 311, "else"
+       line 186, "pan.___", state 316, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 186, "pan.___", state 316, "else"
+       line 144, "pan.___", state 322, "(1)"
+       line 148, "pan.___", state 330, "(1)"
+       line 148, "pan.___", state 331, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 148, "pan.___", state 331, "else"
+       line 146, "pan.___", state 336, "((j<1))"
+       line 146, "pan.___", state 336, "((j>=1))"
+       line 152, "pan.___", state 342, "(1)"
+       line 152, "pan.___", state 343, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 152, "pan.___", state 343, "else"
+       line 186, "pan.___", state 348, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 186, "pan.___", state 348, "else"
+       line 200, "pan.___", state 352, "((i<1))"
+       line 200, "pan.___", state 352, "((i>=1))"
+       line 144, "pan.___", state 358, "(1)"
+       line 148, "pan.___", state 366, "(1)"
+       line 148, "pan.___", state 367, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 367, "else"
+       line 146, "pan.___", state 372, "((j<1))"
+       line 146, "pan.___", state 372, "((j>=1))"
+       line 152, "pan.___", state 378, "(1)"
+       line 152, "pan.___", state 379, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 379, "else"
+       line 186, "pan.___", state 384, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 186, "pan.___", state 384, "else"
+       line 289, "pan.___", state 399, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 415, "(1)"
+       line 298, "pan.___", state 431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 444, "(1)"
+       line 308, "pan.___", state 474, "(1)"
+       line 289, "pan.___", state 487, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 519, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 532, "(1)"
+       line 308, "pan.___", state 562, "(1)"
+       line 289, "pan.___", state 575, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 607, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 620, "(1)"
+       line 308, "pan.___", state 650, "(1)"
+       line 144, "pan.___", state 666, "(1)"
+       line 148, "pan.___", state 674, "(1)"
+       line 148, "pan.___", state 675, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 675, "else"
+       line 146, "pan.___", state 680, "((j<1))"
+       line 146, "pan.___", state 680, "((j>=1))"
+       line 152, "pan.___", state 686, "(1)"
+       line 152, "pan.___", state 687, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 687, "else"
+       line 186, "pan.___", state 692, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 186, "pan.___", state 692, "else"
+       line 144, "pan.___", state 698, "(1)"
+       line 148, "pan.___", state 706, "(1)"
+       line 148, "pan.___", state 707, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 148, "pan.___", state 707, "else"
+       line 146, "pan.___", state 712, "((j<1))"
+       line 146, "pan.___", state 712, "((j>=1))"
+       line 152, "pan.___", state 718, "(1)"
+       line 152, "pan.___", state 719, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 152, "pan.___", state 719, "else"
+       line 186, "pan.___", state 724, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 186, "pan.___", state 724, "else"
+       line 200, "pan.___", state 728, "((i<1))"
+       line 200, "pan.___", state 728, "((i>=1))"
+       line 144, "pan.___", state 734, "(1)"
+       line 148, "pan.___", state 742, "(1)"
+       line 148, "pan.___", state 743, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 743, "else"
+       line 146, "pan.___", state 748, "((j<1))"
+       line 146, "pan.___", state 748, "((j>=1))"
+       line 152, "pan.___", state 754, "(1)"
+       line 152, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 755, "else"
+       line 186, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 186, "pan.___", state 760, "else"
+       line 289, "pan.___", state 770, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 802, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 815, "(1)"
+       line 308, "pan.___", state 845, "(1)"
+       line 289, "pan.___", state 866, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 882, "(1)"
+       line 298, "pan.___", state 898, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 911, "(1)"
+       line 308, "pan.___", state 941, "(1)"
+       line 434, "pan.___", state 954, "-end-"
+       (79 of 954 states)
+unreached in proctype urcu_writer
+       line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 20, "(1)"
+       line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 34, "(1)"
+       line 293, "pan.___", state 35, "(1)"
+       line 293, "pan.___", state 35, "(1)"
+       line 291, "pan.___", state 40, "((i<1))"
+       line 291, "pan.___", state 40, "((i>=1))"
+       line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 59, "(1)"
+       line 299, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 60, "else"
+       line 299, "pan.___", state 63, "(1)"
+       line 299, "pan.___", state 64, "(1)"
+       line 299, "pan.___", state 64, "(1)"
+       line 303, "pan.___", state 72, "(1)"
+       line 303, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 73, "else"
+       line 303, "pan.___", state 76, "(1)"
+       line 303, "pan.___", state 77, "(1)"
+       line 303, "pan.___", state 77, "(1)"
+       line 301, "pan.___", state 82, "((i<1))"
+       line 301, "pan.___", state 82, "((i>=1))"
+       line 308, "pan.___", state 89, "(1)"
+       line 308, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 90, "else"
+       line 308, "pan.___", state 93, "(1)"
+       line 308, "pan.___", state 94, "(1)"
+       line 308, "pan.___", state 94, "(1)"
+       line 310, "pan.___", state 97, "(1)"
+       line 310, "pan.___", state 97, "(1)"
+       line 456, "pan.___", state 101, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 454, "pan.___", state 102, "old_gen = cached_generation_ptr.val[_pid]"
+       line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 112, "(1)"
+       line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 126, "(1)"
+       line 293, "pan.___", state 127, "(1)"
+       line 293, "pan.___", state 127, "(1)"
+       line 291, "pan.___", state 132, "((i<1))"
+       line 291, "pan.___", state 132, "((i>=1))"
+       line 299, "pan.___", state 151, "(1)"
+       line 299, "pan.___", state 152, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 152, "else"
+       line 299, "pan.___", state 155, "(1)"
+       line 299, "pan.___", state 156, "(1)"
+       line 299, "pan.___", state 156, "(1)"
+       line 303, "pan.___", state 164, "(1)"
+       line 303, "pan.___", state 165, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 165, "else"
+       line 303, "pan.___", state 168, "(1)"
+       line 303, "pan.___", state 169, "(1)"
+       line 303, "pan.___", state 169, "(1)"
+       line 301, "pan.___", state 174, "((i<1))"
+       line 301, "pan.___", state 174, "((i>=1))"
+       line 308, "pan.___", state 181, "(1)"
+       line 308, "pan.___", state 182, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 182, "else"
+       line 308, "pan.___", state 185, "(1)"
+       line 308, "pan.___", state 186, "(1)"
+       line 308, "pan.___", state 186, "(1)"
+       line 310, "pan.___", state 189, "(1)"
+       line 310, "pan.___", state 189, "(1)"
+       line 468, "pan.___", state 195, "(1)"
+       line 462, "pan.___", state 198, "((write_lock==0))"
+       line 462, "pan.___", state 198, "else"
+       line 460, "pan.___", state 199, "(1)"
+       line 144, "pan.___", state 206, "(1)"
+       line 148, "pan.___", state 214, "(1)"
+       line 148, "pan.___", state 215, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 215, "else"
+       line 146, "pan.___", state 220, "((j<1))"
+       line 146, "pan.___", state 220, "((j>=1))"
+       line 152, "pan.___", state 226, "(1)"
+       line 152, "pan.___", state 227, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 227, "else"
+       line 186, "pan.___", state 232, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 186, "pan.___", state 232, "else"
+       line 144, "pan.___", state 238, "(1)"
+       line 152, "pan.___", state 258, "(1)"
+       line 144, "pan.___", state 274, "(1)"
+       line 148, "pan.___", state 282, "(1)"
+       line 152, "pan.___", state 294, "(1)"
+       line 289, "pan.___", state 310, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 324, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 342, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 355, "(1)"
+       line 303, "pan.___", state 368, "(1)"
+       line 308, "pan.___", state 385, "(1)"
+       line 289, "pan.___", state 402, "(1)"
+       line 293, "pan.___", state 414, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 432, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 458, "(1)"
+       line 308, "pan.___", state 475, "(1)"
+       line 293, "pan.___", state 505, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 523, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 549, "(1)"
+       line 308, "pan.___", state 566, "(1)"
+       line 148, "pan.___", state 588, "(1)"
+       line 152, "pan.___", state 600, "(1)"
+       line 144, "pan.___", state 612, "(1)"
+       line 152, "pan.___", state 632, "(1)"
+       line 148, "pan.___", state 656, "(1)"
+       line 152, "pan.___", state 668, "(1)"
+       line 289, "pan.___", state 692, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 694, "(1)"
+       line 289, "pan.___", state 695, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 289, "pan.___", state 695, "else"
+       line 289, "pan.___", state 698, "(1)"
+       line 293, "pan.___", state 706, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 708, "(1)"
+       line 293, "pan.___", state 709, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 293, "pan.___", state 709, "else"
+       line 293, "pan.___", state 712, "(1)"
+       line 293, "pan.___", state 713, "(1)"
+       line 293, "pan.___", state 713, "(1)"
+       line 291, "pan.___", state 718, "((i<1))"
+       line 291, "pan.___", state 718, "((i>=1))"
+       line 298, "pan.___", state 724, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 737, "(1)"
+       line 299, "pan.___", state 738, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 738, "else"
+       line 299, "pan.___", state 741, "(1)"
+       line 299, "pan.___", state 742, "(1)"
+       line 299, "pan.___", state 742, "(1)"
+       line 303, "pan.___", state 750, "(1)"
+       line 303, "pan.___", state 751, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 751, "else"
+       line 303, "pan.___", state 754, "(1)"
+       line 303, "pan.___", state 755, "(1)"
+       line 303, "pan.___", state 755, "(1)"
+       line 301, "pan.___", state 760, "((i<1))"
+       line 301, "pan.___", state 760, "((i>=1))"
+       line 308, "pan.___", state 767, "(1)"
+       line 308, "pan.___", state 768, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 768, "else"
+       line 308, "pan.___", state 771, "(1)"
+       line 308, "pan.___", state 772, "(1)"
+       line 308, "pan.___", state 772, "(1)"
+       line 310, "pan.___", state 775, "(1)"
+       line 310, "pan.___", state 775, "(1)"
+       line 293, "pan.___", state 804, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 822, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 848, "(1)"
+       line 308, "pan.___", state 865, "(1)"
+       line 293, "pan.___", state 892, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 936, "(1)"
+       line 308, "pan.___", state 953, "(1)"
+       line 289, "pan.___", state 970, "(1)"
+       line 293, "pan.___", state 982, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1000, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 1026, "(1)"
+       line 308, "pan.___", state 1043, "(1)"
+       line 293, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 1117, "(1)"
+       line 308, "pan.___", state 1134, "(1)"
+       line 148, "pan.___", state 1156, "(1)"
+       line 152, "pan.___", state 1168, "(1)"
+       line 144, "pan.___", state 1180, "(1)"
+       line 152, "pan.___", state 1200, "(1)"
+       line 148, "pan.___", state 1224, "(1)"
+       line 152, "pan.___", state 1236, "(1)"
+       line 289, "pan.___", state 1260, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 1262, "(1)"
+       line 289, "pan.___", state 1263, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 289, "pan.___", state 1263, "else"
+       line 289, "pan.___", state 1266, "(1)"
+       line 293, "pan.___", state 1274, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 1276, "(1)"
+       line 293, "pan.___", state 1277, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 293, "pan.___", state 1277, "else"
+       line 293, "pan.___", state 1280, "(1)"
+       line 293, "pan.___", state 1281, "(1)"
+       line 293, "pan.___", state 1281, "(1)"
+       line 291, "pan.___", state 1286, "((i<1))"
+       line 291, "pan.___", state 1286, "((i>=1))"
+       line 298, "pan.___", state 1292, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 1305, "(1)"
+       line 299, "pan.___", state 1306, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 1306, "else"
+       line 299, "pan.___", state 1309, "(1)"
+       line 299, "pan.___", state 1310, "(1)"
+       line 299, "pan.___", state 1310, "(1)"
+       line 303, "pan.___", state 1318, "(1)"
+       line 303, "pan.___", state 1319, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 1319, "else"
+       line 303, "pan.___", state 1322, "(1)"
+       line 303, "pan.___", state 1323, "(1)"
+       line 303, "pan.___", state 1323, "(1)"
+       line 301, "pan.___", state 1328, "((i<1))"
+       line 301, "pan.___", state 1328, "((i>=1))"
+       line 308, "pan.___", state 1335, "(1)"
+       line 308, "pan.___", state 1336, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 1336, "else"
+       line 308, "pan.___", state 1339, "(1)"
+       line 308, "pan.___", state 1340, "(1)"
+       line 308, "pan.___", state 1340, "(1)"
+       line 310, "pan.___", state 1343, "(1)"
+       line 310, "pan.___", state 1343, "(1)"
+       line 148, "pan.___", state 1367, "(1)"
+       line 152, "pan.___", state 1379, "(1)"
+       line 144, "pan.___", state 1391, "(1)"
+       line 152, "pan.___", state 1411, "(1)"
+       line 148, "pan.___", state 1435, "(1)"
+       line 152, "pan.___", state 1447, "(1)"
+       line 511, "pan.___", state 1473, "-end-"
+       (159 of 1473 states)
+unreached in proctype :init:
+       line 518, "pan.___", state 9, "((j<2))"
+       line 518, "pan.___", state 9, "((j>=2))"
+       line 519, "pan.___", state 20, "((j<2))"
+       line 519, "pan.___", state 20, "((j>=2))"
+       line 524, "pan.___", state 33, "((j<2))"
+       line 524, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 572, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 10.4 seconds
+pan: rate 36378.399 states/second
+pan: avg transition delay 1.8293e-06 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input
new file mode 100644 (file)
index 0000000..12cde50
--- /dev/null
@@ -0,0 +1,532 @@
+#define NO_WMB
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_no_wmb.spin.input.trail
new file mode 100644 (file)
index 0000000..ec82525
--- /dev/null
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diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.define
new file mode 100644 (file)
index 0000000..5e642ef
--- /dev/null
@@ -0,0 +1 @@
+#define SINGLE_FLIP
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.log
new file mode 100644 (file)
index 0000000..6a9d040
--- /dev/null
@@ -0,0 +1,349 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 567)
+pan: claim violated! (at depth 1353)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3705, errors: 1
+   216253 states, stored
+  2924019 states, matched
+  3140272 transitions (= stored+matched)
+ 11791015 atomic steps
+hash conflicts:    155585 (resolved)
+
+Stats on memory usage (in Megabytes):
+   17.324      equivalent memory usage for states (stored*(State-vector + overhead))
+   13.576      actual memory usage for states (compression: 78.37%)
+               state-vector as stored = 38 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  479.338      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 289, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 61, "(1)"
+       line 308, "pan.___", state 91, "(1)"
+       line 289, "pan.___", state 104, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 136, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 149, "(1)"
+       line 308, "pan.___", state 179, "(1)"
+       line 289, "pan.___", state 193, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 225, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 238, "(1)"
+       line 308, "pan.___", state 268, "(1)"
+       line 159, "pan.___", state 289, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 291, "(1)"
+       line 163, "pan.___", state 298, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 300, "(1)"
+       line 163, "pan.___", state 301, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 301, "else"
+       line 161, "pan.___", state 306, "((j<1))"
+       line 161, "pan.___", state 306, "((j>=1))"
+       line 167, "pan.___", state 311, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 321, "(1)"
+       line 148, "pan.___", state 329, "(1)"
+       line 148, "pan.___", state 330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 330, "else"
+       line 146, "pan.___", state 335, "((j<1))"
+       line 146, "pan.___", state 335, "((j>=1))"
+       line 152, "pan.___", state 341, "(1)"
+       line 152, "pan.___", state 342, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 342, "else"
+       line 154, "pan.___", state 345, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 154, "pan.___", state 345, "else"
+       line 186, "pan.___", state 347, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 186, "pan.___", state 347, "else"
+       line 159, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 354, "(1)"
+       line 163, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 163, "pan.___", state 363, "(1)"
+       line 163, "pan.___", state 364, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 163, "pan.___", state 364, "else"
+       line 161, "pan.___", state 369, "((j<1))"
+       line 161, "pan.___", state 369, "((j>=1))"
+       line 167, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 144, "pan.___", state 384, "(1)"
+       line 148, "pan.___", state 392, "(1)"
+       line 148, "pan.___", state 393, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 148, "pan.___", state 393, "else"
+       line 146, "pan.___", state 398, "((j<1))"
+       line 146, "pan.___", state 398, "((j>=1))"
+       line 152, "pan.___", state 404, "(1)"
+       line 152, "pan.___", state 405, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 152, "pan.___", state 405, "else"
+       line 154, "pan.___", state 408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 154, "pan.___", state 408, "else"
+       line 186, "pan.___", state 410, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 186, "pan.___", state 410, "else"
+       line 200, "pan.___", state 414, "((i<1))"
+       line 200, "pan.___", state 414, "((i>=1))"
+       line 159, "pan.___", state 419, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 421, "(1)"
+       line 163, "pan.___", state 428, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 430, "(1)"
+       line 163, "pan.___", state 431, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 431, "else"
+       line 161, "pan.___", state 436, "((j<1))"
+       line 161, "pan.___", state 436, "((j>=1))"
+       line 167, "pan.___", state 441, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 451, "(1)"
+       line 148, "pan.___", state 459, "(1)"
+       line 148, "pan.___", state 460, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 460, "else"
+       line 146, "pan.___", state 465, "((j<1))"
+       line 146, "pan.___", state 465, "((j>=1))"
+       line 152, "pan.___", state 471, "(1)"
+       line 152, "pan.___", state 472, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 472, "else"
+       line 154, "pan.___", state 475, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 154, "pan.___", state 475, "else"
+       line 186, "pan.___", state 477, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 186, "pan.___", state 477, "else"
+       line 289, "pan.___", state 492, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 537, "(1)"
+       line 308, "pan.___", state 567, "(1)"
+       line 289, "pan.___", state 580, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 612, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 625, "(1)"
+       line 308, "pan.___", state 655, "(1)"
+       line 289, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 713, "(1)"
+       line 308, "pan.___", state 743, "(1)"
+       line 159, "pan.___", state 758, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 760, "(1)"
+       line 163, "pan.___", state 767, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 769, "(1)"
+       line 163, "pan.___", state 770, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 770, "else"
+       line 161, "pan.___", state 775, "((j<1))"
+       line 161, "pan.___", state 775, "((j>=1))"
+       line 167, "pan.___", state 780, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 790, "(1)"
+       line 148, "pan.___", state 798, "(1)"
+       line 148, "pan.___", state 799, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 799, "else"
+       line 146, "pan.___", state 804, "((j<1))"
+       line 146, "pan.___", state 804, "((j>=1))"
+       line 152, "pan.___", state 810, "(1)"
+       line 152, "pan.___", state 811, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 811, "else"
+       line 154, "pan.___", state 814, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 154, "pan.___", state 814, "else"
+       line 186, "pan.___", state 816, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 186, "pan.___", state 816, "else"
+       line 159, "pan.___", state 821, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 823, "(1)"
+       line 163, "pan.___", state 830, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 163, "pan.___", state 832, "(1)"
+       line 163, "pan.___", state 833, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 163, "pan.___", state 833, "else"
+       line 161, "pan.___", state 838, "((j<1))"
+       line 161, "pan.___", state 838, "((j>=1))"
+       line 167, "pan.___", state 843, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 144, "pan.___", state 853, "(1)"
+       line 148, "pan.___", state 861, "(1)"
+       line 148, "pan.___", state 862, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 148, "pan.___", state 862, "else"
+       line 146, "pan.___", state 867, "((j<1))"
+       line 146, "pan.___", state 867, "((j>=1))"
+       line 152, "pan.___", state 873, "(1)"
+       line 152, "pan.___", state 874, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 152, "pan.___", state 874, "else"
+       line 154, "pan.___", state 877, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 154, "pan.___", state 877, "else"
+       line 186, "pan.___", state 879, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 186, "pan.___", state 879, "else"
+       line 200, "pan.___", state 883, "((i<1))"
+       line 200, "pan.___", state 883, "((i>=1))"
+       line 159, "pan.___", state 888, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 890, "(1)"
+       line 163, "pan.___", state 897, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 899, "(1)"
+       line 163, "pan.___", state 900, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 163, "pan.___", state 900, "else"
+       line 161, "pan.___", state 905, "((j<1))"
+       line 161, "pan.___", state 905, "((j>=1))"
+       line 167, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 920, "(1)"
+       line 148, "pan.___", state 928, "(1)"
+       line 148, "pan.___", state 929, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 148, "pan.___", state 929, "else"
+       line 146, "pan.___", state 934, "((j<1))"
+       line 146, "pan.___", state 934, "((j>=1))"
+       line 152, "pan.___", state 940, "(1)"
+       line 152, "pan.___", state 941, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 152, "pan.___", state 941, "else"
+       line 154, "pan.___", state 944, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 154, "pan.___", state 944, "else"
+       line 186, "pan.___", state 946, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 186, "pan.___", state 946, "else"
+       line 289, "pan.___", state 956, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 988, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 1001, "(1)"
+       line 308, "pan.___", state 1031, "(1)"
+       line 289, "pan.___", state 1052, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 1084, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 1097, "(1)"
+       line 308, "pan.___", state 1127, "(1)"
+       line 434, "pan.___", state 1140, "-end-"
+       (125 of 1140 states)
+unreached in proctype urcu_writer
+       line 289, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 59, "(1)"
+       line 303, "pan.___", state 72, "(1)"
+       line 308, "pan.___", state 89, "(1)"
+       line 289, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 151, "(1)"
+       line 303, "pan.___", state 164, "(1)"
+       line 468, "pan.___", state 195, "(1)"
+       line 159, "pan.___", state 205, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 214, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 237, "(1)"
+       line 148, "pan.___", state 245, "(1)"
+       line 152, "pan.___", state 257, "(1)"
+       line 159, "pan.___", state 268, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 290, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 144, "pan.___", state 300, "(1)"
+       line 148, "pan.___", state 308, "(1)"
+       line 152, "pan.___", state 320, "(1)"
+       line 159, "pan.___", state 335, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 344, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 357, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 367, "(1)"
+       line 148, "pan.___", state 375, "(1)"
+       line 152, "pan.___", state 387, "(1)"
+       line 289, "pan.___", state 403, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 448, "(1)"
+       line 303, "pan.___", state 461, "(1)"
+       line 308, "pan.___", state 478, "(1)"
+       line 289, "pan.___", state 495, "(1)"
+       line 293, "pan.___", state 507, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 525, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 551, "(1)"
+       line 308, "pan.___", state 568, "(1)"
+       line 293, "pan.___", state 598, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 298, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 303, "pan.___", state 642, "(1)"
+       line 308, "pan.___", state 659, "(1)"
+       line 163, "pan.___", state 681, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 694, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 704, "(1)"
+       line 148, "pan.___", state 712, "(1)"
+       line 152, "pan.___", state 724, "(1)"
+       line 159, "pan.___", state 735, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 757, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 144, "pan.___", state 767, "(1)"
+       line 148, "pan.___", state 775, "(1)"
+       line 152, "pan.___", state 787, "(1)"
+       line 159, "pan.___", state 802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 811, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 824, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 834, "(1)"
+       line 148, "pan.___", state 842, "(1)"
+       line 152, "pan.___", state 854, "(1)"
+       line 289, "pan.___", state 878, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 289, "pan.___", state 880, "(1)"
+       line 289, "pan.___", state 881, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 289, "pan.___", state 881, "else"
+       line 289, "pan.___", state 884, "(1)"
+       line 293, "pan.___", state 892, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 293, "pan.___", state 894, "(1)"
+       line 293, "pan.___", state 895, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 293, "pan.___", state 895, "else"
+       line 293, "pan.___", state 898, "(1)"
+       line 293, "pan.___", state 899, "(1)"
+       line 293, "pan.___", state 899, "(1)"
+       line 291, "pan.___", state 904, "((i<1))"
+       line 291, "pan.___", state 904, "((i>=1))"
+       line 298, "pan.___", state 910, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 299, "pan.___", state 923, "(1)"
+       line 299, "pan.___", state 924, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 299, "pan.___", state 924, "else"
+       line 299, "pan.___", state 927, "(1)"
+       line 299, "pan.___", state 928, "(1)"
+       line 299, "pan.___", state 928, "(1)"
+       line 303, "pan.___", state 936, "(1)"
+       line 303, "pan.___", state 937, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 303, "pan.___", state 937, "else"
+       line 303, "pan.___", state 940, "(1)"
+       line 303, "pan.___", state 941, "(1)"
+       line 303, "pan.___", state 941, "(1)"
+       line 301, "pan.___", state 946, "((i<1))"
+       line 301, "pan.___", state 946, "((i>=1))"
+       line 308, "pan.___", state 953, "(1)"
+       line 308, "pan.___", state 954, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 308, "pan.___", state 954, "else"
+       line 308, "pan.___", state 957, "(1)"
+       line 308, "pan.___", state 958, "(1)"
+       line 308, "pan.___", state 958, "(1)"
+       line 310, "pan.___", state 961, "(1)"
+       line 310, "pan.___", state 961, "(1)"
+       line 163, "pan.___", state 985, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 998, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 1008, "(1)"
+       line 148, "pan.___", state 1016, "(1)"
+       line 152, "pan.___", state 1028, "(1)"
+       line 159, "pan.___", state 1039, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 167, "pan.___", state 1061, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 144, "pan.___", state 1071, "(1)"
+       line 148, "pan.___", state 1079, "(1)"
+       line 152, "pan.___", state 1091, "(1)"
+       line 159, "pan.___", state 1106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 163, "pan.___", state 1115, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 167, "pan.___", state 1128, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 144, "pan.___", state 1138, "(1)"
+       line 148, "pan.___", state 1146, "(1)"
+       line 152, "pan.___", state 1158, "(1)"
+       line 511, "pan.___", state 1184, "-end-"
+       (100 of 1184 states)
+unreached in proctype :init:
+       line 518, "pan.___", state 9, "((j<2))"
+       line 518, "pan.___", state 9, "((j>=2))"
+       line 519, "pan.___", state 20, "((j<2))"
+       line 519, "pan.___", state 20, "((j>=2))"
+       line 524, "pan.___", state 33, "((j<2))"
+       line 524, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 572, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 5.58 seconds
+pan: rate 38755.018 states/second
+pan: avg transition delay 1.7769e-06 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input
new file mode 100644 (file)
index 0000000..244a7b2
--- /dev/null
@@ -0,0 +1,532 @@
+#define SINGLE_FLIP
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+
+#if (NR_READERS == 1)
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#elif (NR_READERS == 2)
+
+#define read_free_race (read_generation[0] == last_free_gen || read_generation[1] == last_free_gen)
+#define read_free      (free_done && (data_access[0] || data_access[1]))
+
+#else
+
+#error "Too many readers"
+
+#endif
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               atomic {
+                       if
+                       :: get_readerid() == 0 ->
+progress_reader:
+                               skip;
+                       :: else ->
+                               skip;
+                       fi;
+               }
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_free_single_flip.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress.ltl b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress.ltl
new file mode 100644 (file)
index 0000000..8718641
--- /dev/null
@@ -0,0 +1 @@
+([] <> !np_)
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.define
new file mode 100644 (file)
index 0000000..ff3f783
--- /dev/null
@@ -0,0 +1 @@
+#define READER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.log
new file mode 100644 (file)
index 0000000..ceb438f
--- /dev/null
@@ -0,0 +1,16 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+spin: line 296 replacement value: tmp
+spin: line 296 "pan.___", Error: formal par of wait_for_quiescent_state contains replacement value     saw '-2'' near 'readerid'
+spin: 1 error(s) - aborting
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input
new file mode 100644 (file)
index 0000000..cc55960
--- /dev/null
@@ -0,0 +1,410 @@
+#define READER_PROGRESS
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#define read_free_race (read_generation == last_free_gen)
+#define read_free      (free_done && data_access)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               if
+               :: (NR_READERS > 1) && (i < NR_READERS - 1)
+                       -> ooo_mem(j);
+               :: else
+                       -> skip;
+               fi;
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [NR_WRITERS] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               smp_mb(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_reader.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.define
new file mode 100644 (file)
index 0000000..1e4417f
--- /dev/null
@@ -0,0 +1 @@
+#define WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.log
new file mode 100644 (file)
index 0000000..985f839
--- /dev/null
@@ -0,0 +1,14 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -w -DHASH64 -o pan pan.c
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input
new file mode 100644 (file)
index 0000000..28f1299
--- /dev/null
@@ -0,0 +1,410 @@
+#define WRITER_PROGRESS
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#define read_free_race (read_generation == last_free_gen)
+#define read_free      (free_done && data_access)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               if
+               :: (NR_READERS > 1) && (i < NR_READERS - 1)
+                       -> ooo_mem(j);
+               :: else
+                       -> skip;
+               fi;
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [NR_WRITERS] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               smp_mb(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.define b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.define
new file mode 100644 (file)
index 0000000..8d304f5
--- /dev/null
@@ -0,0 +1,2 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.log b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.log
new file mode 100644 (file)
index 0000000..26b6236
--- /dev/null
@@ -0,0 +1,16 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+spin: line 297 replacement value: tmp
+spin: line 297 "pan.___", Error: formal par of wait_for_quiescent_state contains replacement value     saw '-2'' near 'readerid'
+spin: 1 error(s) - aborting
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu/testmerge'
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input
new file mode 100644 (file)
index 0000000..43e979c
--- /dev/null
@@ -0,0 +1,411 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#define read_free_race (read_generation == last_free_gen)
+#define read_free      (free_done && data_access)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define get_pid()      (_pid)
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
+ * both.
+ */
+
+#define DECLARE_CACHED_VAR(type, x, v) \
+       type mem_##x = v;               \
+       type cached_##x[NR_PROCS] = v;  \
+       bit cache_dirty_##x[NR_PROCS] = 0
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x[id])
+
+#define READ_CACHED_VAR(x)     (cached_##x[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)         \
+       atomic {                        \
+               cached_##x[get_pid()] = v;      \
+               cache_dirty_##x[get_pid()] = 1; \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)              \
+       if                                      \
+       :: IS_CACHE_DIRTY(x, id) ->             \
+               mem_##x = cached_##x[id];       \
+               cache_dirty_##x[id] = 0;        \
+       :: else ->                              \
+               skip                            \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid());
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
+/* Note ! currently only one reader */
+DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr, 0);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation = 1;
+bit data_access = 0;
+
+bit write_lock = 0;
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
+                                               get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, id, i)
+{
+       do
+       :: 1 ->
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (tmp & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i);
+#else
+                       ooo_mem(i);
+#endif
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, i, j)
+{
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               wait_for_reader(tmp, i, j);
+               if
+               :: (NR_READERS > 1) && (i < NR_READERS - 1)
+                       -> ooo_mem(j);
+               :: else
+                       -> skip;
+               fi;
+               i++
+       :: i >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers_one,
+                                        tmp + 1);
+               fi;
+               smp_mb(i);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access = 1;
+       ooo_mem(i);
+       data_access = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active [NR_READERS] proctype urcu_reader()
+{
+       byte i, nest_i;
+       byte tmp, tmp2;
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, nest_i, tmp, tmp2);
+       od;
+}
+
+/* Model the RCU update process. */
+
+active [NR_WRITERS] proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp;
+       byte old_gen;
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               wait_for_quiescent_state(tmp, i, j);
+#endif
+               smp_mb(i);
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               skip;
+       od;
+}
diff --git a/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu/result-signal-over-writer/testmerge/urcu_progress_writer_error.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu.sh b/formal-model/urcu/result-signal-over-writer/urcu.sh
new file mode 100644 (file)
index 0000000..65ff517
--- /dev/null
@@ -0,0 +1,29 @@
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+#               Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+#          Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
diff --git a/formal-model/urcu/result-signal-over-writer/urcu.spin b/formal-model/urcu/result-signal-over-writer/urcu.spin
new file mode 100644 (file)
index 0000000..2cfcb70
--- /dev/null
@@ -0,0 +1,705 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free.log b/formal-model/urcu/result-signal-over-writer/urcu_free.log
new file mode 100644 (file)
index 0000000..9a22c47
--- /dev/null
@@ -0,0 +1,345 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 741)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10669, errors: 0
+    20146 states, stored
+   191615 states, matched
+   211761 transitions (= stored+matched)
+   712676 atomic steps
+hash conflicts:      1523 (resolved)
+
+Stats on memory usage (in Megabytes):
+    1.614      equivalent memory usage for states (stored*(State-vector + overhead))
+    1.661      actual memory usage for states (unsuccessful compression: 102.92%)
+               state-vector as stored = 58 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  467.326      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 401, "pan.___", state 330, "(1)"
+       line 612, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 397, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 406, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 59, "(1)"
+       line 416, "pan.___", state 89, "(1)"
+       line 397, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 160, "(1)"
+       line 650, "pan.___", state 213, "(1)"
+       line 173, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 233, "(1)"
+       line 158, "pan.___", state 254, "(1)"
+       line 162, "pan.___", state 262, "(1)"
+       line 166, "pan.___", state 274, "(1)"
+       line 173, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, "pan.___", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, "pan.___", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 317, "(1)"
+       line 162, "pan.___", state 325, "(1)"
+       line 166, "pan.___", state 337, "(1)"
+       line 173, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 384, "(1)"
+       line 162, "pan.___", state 392, "(1)"
+       line 166, "pan.___", state 404, "(1)"
+       line 397, "pan.___", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 401, "pan.___", state 441, "(1)"
+       line 406, "pan.___", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 470, "(1)"
+       line 416, "pan.___", state 500, "(1)"
+       line 397, "pan.___", state 526, "(1)"
+       line 401, "pan.___", state 540, "(1)"
+       line 406, "pan.___", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 599, "(1)"
+       line 401, "pan.___", state 640, "(1)"
+       line 406, "pan.___", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 699, "(1)"
+       line 173, "pan.___", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, "pan.___", state 722, "(1)"
+       line 177, "pan.___", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 731, "(1)"
+       line 177, "pan.___", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, "pan.___", state 732, "else"
+       line 175, "pan.___", state 737, "((j<1))"
+       line 175, "pan.___", state 737, "((j>=1))"
+       line 181, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 752, "(1)"
+       line 162, "pan.___", state 760, "(1)"
+       line 162, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, "pan.___", state 761, "else"
+       line 160, "pan.___", state 766, "((j<1))"
+       line 160, "pan.___", state 766, "((j>=1))"
+       line 166, "pan.___", state 772, "(1)"
+       line 166, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, "pan.___", state 773, "else"
+       line 168, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, "pan.___", state 776, "else"
+       line 173, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, "pan.___", state 785, "(1)"
+       line 177, "pan.___", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, "pan.___", state 794, "(1)"
+       line 177, "pan.___", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, "pan.___", state 795, "else"
+       line 175, "pan.___", state 800, "((j<1))"
+       line 175, "pan.___", state 800, "((j>=1))"
+       line 181, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 815, "(1)"
+       line 162, "pan.___", state 823, "(1)"
+       line 162, "pan.___", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, "pan.___", state 824, "else"
+       line 160, "pan.___", state 829, "((j<1))"
+       line 160, "pan.___", state 829, "((j>=1))"
+       line 166, "pan.___", state 835, "(1)"
+       line 166, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, "pan.___", state 836, "else"
+       line 168, "pan.___", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, "pan.___", state 839, "else"
+       line 200, "pan.___", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, "pan.___", state 841, "else"
+       line 212, "pan.___", state 845, "((i<1))"
+       line 212, "pan.___", state 845, "((i>=1))"
+       line 173, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, "pan.___", state 852, "(1)"
+       line 177, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 861, "(1)"
+       line 177, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, "pan.___", state 862, "else"
+       line 175, "pan.___", state 867, "((j<1))"
+       line 175, "pan.___", state 867, "((j>=1))"
+       line 181, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 882, "(1)"
+       line 162, "pan.___", state 890, "(1)"
+       line 162, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, "pan.___", state 891, "else"
+       line 160, "pan.___", state 896, "((j<1))"
+       line 160, "pan.___", state 896, "((j>=1))"
+       line 166, "pan.___", state 902, "(1)"
+       line 166, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, "pan.___", state 903, "else"
+       line 168, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, "pan.___", state 906, "else"
+       line 200, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, "pan.___", state 908, "else"
+       line 219, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, "pan.___", state 909, "else"
+       line 354, "pan.___", state 915, "((sighand_exec==1))"
+       line 354, "pan.___", state 915, "else"
+       line 360, "pan.___", state 918, "sighand_exec = 1"
+       line 397, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, "pan.___", state 933, "(1)"
+       line 397, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, "pan.___", state 934, "else"
+       line 397, "pan.___", state 937, "(1)"
+       line 401, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, "pan.___", state 947, "(1)"
+       line 401, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, "pan.___", state 948, "else"
+       line 401, "pan.___", state 951, "(1)"
+       line 401, "pan.___", state 952, "(1)"
+       line 401, "pan.___", state 952, "(1)"
+       line 399, "pan.___", state 957, "((i<1))"
+       line 399, "pan.___", state 957, "((i>=1))"
+       line 406, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 976, "(1)"
+       line 407, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, "pan.___", state 977, "else"
+       line 407, "pan.___", state 980, "(1)"
+       line 407, "pan.___", state 981, "(1)"
+       line 407, "pan.___", state 981, "(1)"
+       line 411, "pan.___", state 989, "(1)"
+       line 411, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, "pan.___", state 990, "else"
+       line 411, "pan.___", state 993, "(1)"
+       line 411, "pan.___", state 994, "(1)"
+       line 411, "pan.___", state 994, "(1)"
+       line 409, "pan.___", state 999, "((i<1))"
+       line 409, "pan.___", state 999, "((i>=1))"
+       line 416, "pan.___", state 1006, "(1)"
+       line 416, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, "pan.___", state 1007, "else"
+       line 416, "pan.___", state 1010, "(1)"
+       line 416, "pan.___", state 1011, "(1)"
+       line 416, "pan.___", state 1011, "(1)"
+       line 418, "pan.___", state 1014, "(1)"
+       line 418, "pan.___", state 1014, "(1)"
+       line 360, "pan.___", state 1023, "sighand_exec = 1"
+       line 401, "pan.___", state 1054, "(1)"
+       line 406, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 1113, "(1)"
+       line 401, "pan.___", state 1151, "(1)"
+       line 406, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 1210, "(1)"
+       line 397, "pan.___", state 1236, "(1)"
+       line 401, "pan.___", state 1250, "(1)"
+       line 406, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 1309, "(1)"
+       line 401, "pan.___", state 1350, "(1)"
+       line 406, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 416, "pan.___", state 1409, "(1)"
+       line 173, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, "pan.___", state 1432, "(1)"
+       line 177, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 1441, "(1)"
+       line 177, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, "pan.___", state 1442, "else"
+       line 175, "pan.___", state 1447, "((j<1))"
+       line 175, "pan.___", state 1447, "((j>=1))"
+       line 181, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 1462, "(1)"
+       line 162, "pan.___", state 1470, "(1)"
+       line 162, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, "pan.___", state 1471, "else"
+       line 160, "pan.___", state 1476, "((j<1))"
+       line 160, "pan.___", state 1476, "((j>=1))"
+       line 166, "pan.___", state 1482, "(1)"
+       line 166, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, "pan.___", state 1483, "else"
+       line 168, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, "pan.___", state 1486, "else"
+       line 173, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 173, "pan.___", state 1495, "(1)"
+       line 177, "pan.___", state 1502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 177, "pan.___", state 1504, "(1)"
+       line 177, "pan.___", state 1505, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 177, "pan.___", state 1505, "else"
+       line 175, "pan.___", state 1510, "((j<1))"
+       line 175, "pan.___", state 1510, "((j>=1))"
+       line 181, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 1525, "(1)"
+       line 162, "pan.___", state 1533, "(1)"
+       line 162, "pan.___", state 1534, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 162, "pan.___", state 1534, "else"
+       line 160, "pan.___", state 1539, "((j<1))"
+       line 160, "pan.___", state 1539, "((j>=1))"
+       line 166, "pan.___", state 1545, "(1)"
+       line 166, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 166, "pan.___", state 1546, "else"
+       line 168, "pan.___", state 1549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 168, "pan.___", state 1549, "else"
+       line 200, "pan.___", state 1551, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 200, "pan.___", state 1551, "else"
+       line 212, "pan.___", state 1555, "((i<1))"
+       line 212, "pan.___", state 1555, "((i>=1))"
+       line 173, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 173, "pan.___", state 1562, "(1)"
+       line 177, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 1571, "(1)"
+       line 177, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 177, "pan.___", state 1572, "else"
+       line 175, "pan.___", state 1577, "((j<1))"
+       line 175, "pan.___", state 1577, "((j>=1))"
+       line 181, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 1592, "(1)"
+       line 162, "pan.___", state 1600, "(1)"
+       line 162, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 162, "pan.___", state 1601, "else"
+       line 160, "pan.___", state 1606, "((j<1))"
+       line 160, "pan.___", state 1606, "((j>=1))"
+       line 166, "pan.___", state 1612, "(1)"
+       line 166, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 166, "pan.___", state 1613, "else"
+       line 168, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 168, "pan.___", state 1616, "else"
+       line 200, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 200, "pan.___", state 1618, "else"
+       line 219, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 219, "pan.___", state 1619, "else"
+       line 354, "pan.___", state 1625, "((sighand_exec==1))"
+       line 354, "pan.___", state 1625, "else"
+       line 360, "pan.___", state 1628, "sighand_exec = 1"
+       line 397, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 397, "pan.___", state 1643, "(1)"
+       line 397, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 397, "pan.___", state 1644, "else"
+       line 397, "pan.___", state 1647, "(1)"
+       line 401, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 401, "pan.___", state 1657, "(1)"
+       line 401, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 401, "pan.___", state 1658, "else"
+       line 401, "pan.___", state 1661, "(1)"
+       line 401, "pan.___", state 1662, "(1)"
+       line 401, "pan.___", state 1662, "(1)"
+       line 399, "pan.___", state 1667, "((i<1))"
+       line 399, "pan.___", state 1667, "((i>=1))"
+       line 406, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 1686, "(1)"
+       line 407, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 407, "pan.___", state 1687, "else"
+       line 407, "pan.___", state 1690, "(1)"
+       line 407, "pan.___", state 1691, "(1)"
+       line 407, "pan.___", state 1691, "(1)"
+       line 411, "pan.___", state 1699, "(1)"
+       line 411, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 411, "pan.___", state 1700, "else"
+       line 411, "pan.___", state 1703, "(1)"
+       line 411, "pan.___", state 1704, "(1)"
+       line 411, "pan.___", state 1704, "(1)"
+       line 409, "pan.___", state 1709, "((i<1))"
+       line 409, "pan.___", state 1709, "((i>=1))"
+       line 416, "pan.___", state 1716, "(1)"
+       line 416, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 416, "pan.___", state 1717, "else"
+       line 416, "pan.___", state 1720, "(1)"
+       line 416, "pan.___", state 1721, "(1)"
+       line 416, "pan.___", state 1721, "(1)"
+       line 418, "pan.___", state 1724, "(1)"
+       line 418, "pan.___", state 1724, "(1)"
+       line 360, "pan.___", state 1733, "sighand_exec = 1"
+       line 177, "pan.___", state 1758, "(1)"
+       line 181, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 1779, "(1)"
+       line 162, "pan.___", state 1787, "(1)"
+       line 166, "pan.___", state 1799, "(1)"
+       line 173, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 177, "pan.___", state 1819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 181, "pan.___", state 1832, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 158, "pan.___", state 1842, "(1)"
+       line 162, "pan.___", state 1850, "(1)"
+       line 166, "pan.___", state 1862, "(1)"
+       line 173, "pan.___", state 1877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 177, "pan.___", state 1886, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 181, "pan.___", state 1899, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 158, "pan.___", state 1909, "(1)"
+       line 162, "pan.___", state 1917, "(1)"
+       line 166, "pan.___", state 1929, "(1)"
+       line 700, "pan.___", state 1968, "-end-"
+       (215 of 1968 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 746, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 0.15 seconds
+pan: rate 134306.67 states/second
+pan: avg transition delay 7.0835e-07 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free.ltl b/formal-model/urcu/result-signal-over-writer/urcu_free.ltl
new file mode 100644 (file)
index 0000000..1954414
--- /dev/null
@@ -0,0 +1 @@
+[] (read_free -> !read_free_race)
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_free.spin.input
new file mode 100644 (file)
index 0000000..953115f
--- /dev/null
@@ -0,0 +1,721 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_free.spin.input.trail
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+15018:2:1782
+15019:2:1787
+15020:2:1791
+15021:2:1792
+15022:2:1799
+15023:2:1800
+15024:2:1811
+15025:2:1812
+15026:2:1813
+15027:2:1811
+15028:2:1812
+15029:2:1813
+15030:2:1824
+15031:2:1829
+15032:2:1830
+15033:0:4365
+15034:2:1842
+15035:0:4365
+15036:3:2427
+15037:0:4365
+15038:2:1844
+15039:0:4363
+15040:3:2428
+15041:0:4369
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.define b/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.define
new file mode 100644 (file)
index 0000000..136ef67
--- /dev/null
@@ -0,0 +1,2 @@
+#define NO_RMB
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.log b/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.log
new file mode 100644 (file)
index 0000000..4cee7dc
--- /dev/null
@@ -0,0 +1,382 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 743)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 72 byte, depth reached 10856, errors: 0
+   161519 states, stored
+  1724866 states, matched
+  1886385 transitions (= stored+matched)
+  6692565 atomic steps
+hash conflicts:     84009 (resolved)
+
+Stats on memory usage (in Megabytes):
+   15.404      equivalent memory usage for states (stored*(State-vector + overhead))
+   10.421      actual memory usage for states (compression: 67.65%)
+               state-vector as stored = 40 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  476.115      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 403, "pan.___", state 330, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 652, "pan.___", state 213, "(1)"
+       line 403, "pan.___", state 239, "(1)"
+       line 403, "pan.___", state 525, "(1)"
+       line 399, "pan.___", state 610, "(1)"
+       line 403, "pan.___", state 624, "(1)"
+       line 403, "pan.___", state 724, "(1)"
+       line 399, "pan.___", state 805, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 807, "(1)"
+       line 399, "pan.___", state 808, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 808, "else"
+       line 399, "pan.___", state 811, "(1)"
+       line 403, "pan.___", state 819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 821, "(1)"
+       line 403, "pan.___", state 822, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 822, "else"
+       line 403, "pan.___", state 825, "(1)"
+       line 403, "pan.___", state 826, "(1)"
+       line 403, "pan.___", state 826, "(1)"
+       line 401, "pan.___", state 831, "((j<1))"
+       line 401, "pan.___", state 831, "((j>=1))"
+       line 408, "pan.___", state 837, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 850, "(1)"
+       line 409, "pan.___", state 851, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 851, "else"
+       line 409, "pan.___", state 854, "(1)"
+       line 409, "pan.___", state 855, "(1)"
+       line 409, "pan.___", state 855, "(1)"
+       line 413, "pan.___", state 863, "(1)"
+       line 413, "pan.___", state 864, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 864, "else"
+       line 413, "pan.___", state 867, "(1)"
+       line 413, "pan.___", state 868, "(1)"
+       line 413, "pan.___", state 868, "(1)"
+       line 411, "pan.___", state 873, "((j<1))"
+       line 411, "pan.___", state 873, "((j>=1))"
+       line 418, "pan.___", state 880, "(1)"
+       line 418, "pan.___", state 881, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 881, "else"
+       line 418, "pan.___", state 884, "(1)"
+       line 418, "pan.___", state 885, "(1)"
+       line 418, "pan.___", state 885, "(1)"
+       line 399, "pan.___", state 896, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 898, "(1)"
+       line 399, "pan.___", state 899, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 899, "else"
+       line 399, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 910, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 912, "(1)"
+       line 403, "pan.___", state 913, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 913, "else"
+       line 403, "pan.___", state 916, "(1)"
+       line 403, "pan.___", state 917, "(1)"
+       line 403, "pan.___", state 917, "(1)"
+       line 401, "pan.___", state 922, "((j<1))"
+       line 401, "pan.___", state 922, "((j>=1))"
+       line 408, "pan.___", state 928, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 941, "(1)"
+       line 409, "pan.___", state 942, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 942, "else"
+       line 409, "pan.___", state 945, "(1)"
+       line 409, "pan.___", state 946, "(1)"
+       line 409, "pan.___", state 946, "(1)"
+       line 413, "pan.___", state 954, "(1)"
+       line 413, "pan.___", state 955, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 955, "else"
+       line 413, "pan.___", state 958, "(1)"
+       line 413, "pan.___", state 959, "(1)"
+       line 413, "pan.___", state 959, "(1)"
+       line 411, "pan.___", state 964, "((j<1))"
+       line 411, "pan.___", state 964, "((j>=1))"
+       line 418, "pan.___", state 971, "(1)"
+       line 418, "pan.___", state 972, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 972, "else"
+       line 418, "pan.___", state 975, "(1)"
+       line 418, "pan.___", state 976, "(1)"
+       line 418, "pan.___", state 976, "(1)"
+       line 194, "pan.___", state 981, "(1)"
+       line 194, "pan.___", state 981, "(1)"
+       line 214, "pan.___", state 985, "((i<1))"
+       line 214, "pan.___", state 985, "((i>=1))"
+       line 399, "pan.___", state 991, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 993, "(1)"
+       line 399, "pan.___", state 994, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 994, "else"
+       line 399, "pan.___", state 997, "(1)"
+       line 403, "pan.___", state 1005, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1007, "(1)"
+       line 403, "pan.___", state 1008, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1008, "else"
+       line 403, "pan.___", state 1011, "(1)"
+       line 403, "pan.___", state 1012, "(1)"
+       line 403, "pan.___", state 1012, "(1)"
+       line 401, "pan.___", state 1017, "((j<1))"
+       line 401, "pan.___", state 1017, "((j>=1))"
+       line 408, "pan.___", state 1023, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1036, "(1)"
+       line 409, "pan.___", state 1037, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1037, "else"
+       line 409, "pan.___", state 1040, "(1)"
+       line 409, "pan.___", state 1041, "(1)"
+       line 409, "pan.___", state 1041, "(1)"
+       line 413, "pan.___", state 1049, "(1)"
+       line 413, "pan.___", state 1050, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1050, "else"
+       line 413, "pan.___", state 1053, "(1)"
+       line 413, "pan.___", state 1054, "(1)"
+       line 413, "pan.___", state 1054, "(1)"
+       line 411, "pan.___", state 1059, "((j<1))"
+       line 411, "pan.___", state 1059, "((j>=1))"
+       line 418, "pan.___", state 1066, "(1)"
+       line 418, "pan.___", state 1067, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1067, "else"
+       line 418, "pan.___", state 1070, "(1)"
+       line 418, "pan.___", state 1071, "(1)"
+       line 418, "pan.___", state 1071, "(1)"
+       line 194, "pan.___", state 1076, "(1)"
+       line 194, "pan.___", state 1076, "(1)"
+       line 221, "pan.___", state 1077, "(1)"
+       line 221, "pan.___", state 1077, "(1)"
+       line 356, "pan.___", state 1083, "((sighand_exec==1))"
+       line 356, "pan.___", state 1083, "else"
+       line 362, "pan.___", state 1086, "sighand_exec = 1"
+       line 399, "pan.___", state 1099, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1101, "(1)"
+       line 399, "pan.___", state 1102, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1102, "else"
+       line 399, "pan.___", state 1105, "(1)"
+       line 403, "pan.___", state 1113, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1115, "(1)"
+       line 403, "pan.___", state 1116, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1116, "else"
+       line 403, "pan.___", state 1119, "(1)"
+       line 403, "pan.___", state 1120, "(1)"
+       line 403, "pan.___", state 1120, "(1)"
+       line 401, "pan.___", state 1125, "((i<1))"
+       line 401, "pan.___", state 1125, "((i>=1))"
+       line 408, "pan.___", state 1131, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1144, "(1)"
+       line 409, "pan.___", state 1145, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1145, "else"
+       line 409, "pan.___", state 1148, "(1)"
+       line 409, "pan.___", state 1149, "(1)"
+       line 409, "pan.___", state 1149, "(1)"
+       line 413, "pan.___", state 1157, "(1)"
+       line 413, "pan.___", state 1158, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1158, "else"
+       line 413, "pan.___", state 1161, "(1)"
+       line 413, "pan.___", state 1162, "(1)"
+       line 413, "pan.___", state 1162, "(1)"
+       line 411, "pan.___", state 1167, "((i<1))"
+       line 411, "pan.___", state 1167, "((i>=1))"
+       line 418, "pan.___", state 1174, "(1)"
+       line 418, "pan.___", state 1175, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1175, "else"
+       line 418, "pan.___", state 1178, "(1)"
+       line 418, "pan.___", state 1179, "(1)"
+       line 418, "pan.___", state 1179, "(1)"
+       line 420, "pan.___", state 1182, "(1)"
+       line 420, "pan.___", state 1182, "(1)"
+       line 362, "pan.___", state 1191, "sighand_exec = 1"
+       line 403, "pan.___", state 1222, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 399, "pan.___", state 1404, "(1)"
+       line 403, "pan.___", state 1418, "(1)"
+       line 403, "pan.___", state 1518, "(1)"
+       line 399, "pan.___", state 1599, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1601, "(1)"
+       line 399, "pan.___", state 1602, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1602, "else"
+       line 399, "pan.___", state 1605, "(1)"
+       line 403, "pan.___", state 1613, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1615, "(1)"
+       line 403, "pan.___", state 1616, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1616, "else"
+       line 403, "pan.___", state 1619, "(1)"
+       line 403, "pan.___", state 1620, "(1)"
+       line 403, "pan.___", state 1620, "(1)"
+       line 401, "pan.___", state 1625, "((j<1))"
+       line 401, "pan.___", state 1625, "((j>=1))"
+       line 408, "pan.___", state 1631, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1644, "(1)"
+       line 409, "pan.___", state 1645, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1645, "else"
+       line 409, "pan.___", state 1648, "(1)"
+       line 409, "pan.___", state 1649, "(1)"
+       line 409, "pan.___", state 1649, "(1)"
+       line 413, "pan.___", state 1657, "(1)"
+       line 413, "pan.___", state 1658, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1658, "else"
+       line 413, "pan.___", state 1661, "(1)"
+       line 413, "pan.___", state 1662, "(1)"
+       line 413, "pan.___", state 1662, "(1)"
+       line 411, "pan.___", state 1667, "((j<1))"
+       line 411, "pan.___", state 1667, "((j>=1))"
+       line 418, "pan.___", state 1674, "(1)"
+       line 418, "pan.___", state 1675, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1675, "else"
+       line 418, "pan.___", state 1678, "(1)"
+       line 418, "pan.___", state 1679, "(1)"
+       line 418, "pan.___", state 1679, "(1)"
+       line 399, "pan.___", state 1690, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1692, "(1)"
+       line 399, "pan.___", state 1693, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1693, "else"
+       line 399, "pan.___", state 1696, "(1)"
+       line 403, "pan.___", state 1704, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1706, "(1)"
+       line 403, "pan.___", state 1707, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1707, "else"
+       line 403, "pan.___", state 1710, "(1)"
+       line 403, "pan.___", state 1711, "(1)"
+       line 403, "pan.___", state 1711, "(1)"
+       line 401, "pan.___", state 1716, "((j<1))"
+       line 401, "pan.___", state 1716, "((j>=1))"
+       line 408, "pan.___", state 1722, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1735, "(1)"
+       line 409, "pan.___", state 1736, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1736, "else"
+       line 409, "pan.___", state 1739, "(1)"
+       line 409, "pan.___", state 1740, "(1)"
+       line 409, "pan.___", state 1740, "(1)"
+       line 413, "pan.___", state 1748, "(1)"
+       line 413, "pan.___", state 1749, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1749, "else"
+       line 413, "pan.___", state 1752, "(1)"
+       line 413, "pan.___", state 1753, "(1)"
+       line 413, "pan.___", state 1753, "(1)"
+       line 411, "pan.___", state 1758, "((j<1))"
+       line 411, "pan.___", state 1758, "((j>=1))"
+       line 418, "pan.___", state 1765, "(1)"
+       line 418, "pan.___", state 1766, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1766, "else"
+       line 418, "pan.___", state 1769, "(1)"
+       line 418, "pan.___", state 1770, "(1)"
+       line 418, "pan.___", state 1770, "(1)"
+       line 194, "pan.___", state 1775, "(1)"
+       line 194, "pan.___", state 1775, "(1)"
+       line 214, "pan.___", state 1779, "((i<1))"
+       line 214, "pan.___", state 1779, "((i>=1))"
+       line 399, "pan.___", state 1785, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1787, "(1)"
+       line 399, "pan.___", state 1788, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1788, "else"
+       line 399, "pan.___", state 1791, "(1)"
+       line 403, "pan.___", state 1799, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1801, "(1)"
+       line 403, "pan.___", state 1802, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1802, "else"
+       line 403, "pan.___", state 1805, "(1)"
+       line 403, "pan.___", state 1806, "(1)"
+       line 403, "pan.___", state 1806, "(1)"
+       line 401, "pan.___", state 1811, "((j<1))"
+       line 401, "pan.___", state 1811, "((j>=1))"
+       line 408, "pan.___", state 1817, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1830, "(1)"
+       line 409, "pan.___", state 1831, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1831, "else"
+       line 409, "pan.___", state 1834, "(1)"
+       line 409, "pan.___", state 1835, "(1)"
+       line 409, "pan.___", state 1835, "(1)"
+       line 413, "pan.___", state 1843, "(1)"
+       line 413, "pan.___", state 1844, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1844, "else"
+       line 413, "pan.___", state 1847, "(1)"
+       line 413, "pan.___", state 1848, "(1)"
+       line 413, "pan.___", state 1848, "(1)"
+       line 411, "pan.___", state 1853, "((j<1))"
+       line 411, "pan.___", state 1853, "((j>=1))"
+       line 418, "pan.___", state 1860, "(1)"
+       line 418, "pan.___", state 1861, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1861, "else"
+       line 418, "pan.___", state 1864, "(1)"
+       line 418, "pan.___", state 1865, "(1)"
+       line 418, "pan.___", state 1865, "(1)"
+       line 194, "pan.___", state 1870, "(1)"
+       line 194, "pan.___", state 1870, "(1)"
+       line 221, "pan.___", state 1871, "(1)"
+       line 221, "pan.___", state 1871, "(1)"
+       line 356, "pan.___", state 1877, "((sighand_exec==1))"
+       line 356, "pan.___", state 1877, "else"
+       line 362, "pan.___", state 1880, "sighand_exec = 1"
+       line 399, "pan.___", state 1893, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1895, "(1)"
+       line 399, "pan.___", state 1896, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1896, "else"
+       line 399, "pan.___", state 1899, "(1)"
+       line 403, "pan.___", state 1907, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1909, "(1)"
+       line 403, "pan.___", state 1910, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1910, "else"
+       line 403, "pan.___", state 1913, "(1)"
+       line 403, "pan.___", state 1914, "(1)"
+       line 403, "pan.___", state 1914, "(1)"
+       line 401, "pan.___", state 1919, "((i<1))"
+       line 401, "pan.___", state 1919, "((i>=1))"
+       line 408, "pan.___", state 1925, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1938, "(1)"
+       line 409, "pan.___", state 1939, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1939, "else"
+       line 409, "pan.___", state 1942, "(1)"
+       line 409, "pan.___", state 1943, "(1)"
+       line 409, "pan.___", state 1943, "(1)"
+       line 413, "pan.___", state 1951, "(1)"
+       line 413, "pan.___", state 1952, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1952, "else"
+       line 413, "pan.___", state 1955, "(1)"
+       line 413, "pan.___", state 1956, "(1)"
+       line 413, "pan.___", state 1956, "(1)"
+       line 411, "pan.___", state 1961, "((i<1))"
+       line 411, "pan.___", state 1961, "((i>=1))"
+       line 418, "pan.___", state 1968, "(1)"
+       line 418, "pan.___", state 1969, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1969, "else"
+       line 418, "pan.___", state 1972, "(1)"
+       line 418, "pan.___", state 1973, "(1)"
+       line 418, "pan.___", state 1973, "(1)"
+       line 420, "pan.___", state 1976, "(1)"
+       line 420, "pan.___", state 1976, "(1)"
+       line 362, "pan.___", state 1985, "sighand_exec = 1"
+       line 403, "pan.___", state 2016, "(1)"
+       line 702, "pan.___", state 2304, "-end-"
+       (221 of 2304 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 748, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 1.47 seconds
+pan: rate 109876.87 states/second
+pan: avg transition delay 7.7927e-07 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input
new file mode 100644 (file)
index 0000000..48411ec
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_RMB
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_free_no_mb.spin.input.trail
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+2029:1:56
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+2031:1:68
+2032:1:69
+2033:1:70
+2034:1:81
+2035:1:86
+2036:1:87
+2037:0:4249
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+2040:2:1025
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+2077:2:1077
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+2079:2:1085
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+2081:2:1097
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.define b/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.define
new file mode 100644 (file)
index 0000000..73e61a4
--- /dev/null
@@ -0,0 +1 @@
+#define NO_RMB
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.log b/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.log
new file mode 100644 (file)
index 0000000..5eb694e
--- /dev/null
@@ -0,0 +1,280 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10519, errors: 0
+    20146 states, stored
+   191615 states, matched
+   211761 transitions (= stored+matched)
+   711676 atomic steps
+hash conflicts:      1222 (resolved)
+
+Stats on memory usage (in Megabytes):
+    1.614      equivalent memory usage for states (stored*(State-vector + overhead))
+    1.509      actual memory usage for states (compression: 93.51%)
+               state-vector as stored = 51 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  467.229      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 402, "pan.___", state 330, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 160, "(1)"
+       line 651, "pan.___", state 213, "(1)"
+       line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 233, "(1)"
+       line 174, "pan.___", state 257, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 266, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 279, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 296, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 305, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 318, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 341, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 357, "(1)"
+       line 407, "pan.___", state 373, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 386, "(1)"
+       line 417, "pan.___", state 416, "(1)"
+       line 398, "pan.___", state 442, "(1)"
+       line 402, "pan.___", state 456, "(1)"
+       line 407, "pan.___", state 472, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 515, "(1)"
+       line 402, "pan.___", state 556, "(1)"
+       line 407, "pan.___", state 572, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 615, "(1)"
+       line 174, "pan.___", state 636, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 638, "(1)"
+       line 178, "pan.___", state 645, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 647, "(1)"
+       line 178, "pan.___", state 648, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 648, "else"
+       line 176, "pan.___", state 653, "((j<1))"
+       line 176, "pan.___", state 653, "((j>=1))"
+       line 182, "pan.___", state 658, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 660, "(1)"
+       line 182, "pan.___", state 661, "((cache_dirty_generation_ptr.bitfield&(1<<0)))"
+       line 182, "pan.___", state 661, "else"
+       line 174, "pan.___", state 671, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 673, "(1)"
+       line 178, "pan.___", state 680, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 682, "(1)"
+       line 178, "pan.___", state 683, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 683, "else"
+       line 176, "pan.___", state 688, "((j<1))"
+       line 176, "pan.___", state 688, "((j>=1))"
+       line 182, "pan.___", state 693, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 695, "(1)"
+       line 182, "pan.___", state 696, "((cache_dirty_generation_ptr.bitfield&(1<<i)))"
+       line 182, "pan.___", state 696, "else"
+       line 192, "pan.___", state 701, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 192, "pan.___", state 701, "else"
+       line 213, "pan.___", state 705, "((i<1))"
+       line 213, "pan.___", state 705, "((i>=1))"
+       line 174, "pan.___", state 710, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 712, "(1)"
+       line 178, "pan.___", state 719, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 721, "(1)"
+       line 178, "pan.___", state 722, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 722, "else"
+       line 176, "pan.___", state 727, "((j<1))"
+       line 176, "pan.___", state 727, "((j>=1))"
+       line 182, "pan.___", state 732, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 734, "(1)"
+       line 182, "pan.___", state 735, "((cache_dirty_generation_ptr.bitfield&(1<<0)))"
+       line 182, "pan.___", state 735, "else"
+       line 192, "pan.___", state 740, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 192, "pan.___", state 740, "else"
+       line 220, "pan.___", state 741, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 741, "else"
+       line 355, "pan.___", state 747, "((sighand_exec==1))"
+       line 355, "pan.___", state 747, "else"
+       line 361, "pan.___", state 750, "sighand_exec = 1"
+       line 398, "pan.___", state 763, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 765, "(1)"
+       line 398, "pan.___", state 766, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 766, "else"
+       line 398, "pan.___", state 769, "(1)"
+       line 402, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 779, "(1)"
+       line 402, "pan.___", state 780, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 780, "else"
+       line 402, "pan.___", state 783, "(1)"
+       line 402, "pan.___", state 784, "(1)"
+       line 402, "pan.___", state 784, "(1)"
+       line 400, "pan.___", state 789, "((i<1))"
+       line 400, "pan.___", state 789, "((i>=1))"
+       line 407, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 808, "(1)"
+       line 408, "pan.___", state 809, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 809, "else"
+       line 408, "pan.___", state 812, "(1)"
+       line 408, "pan.___", state 813, "(1)"
+       line 408, "pan.___", state 813, "(1)"
+       line 412, "pan.___", state 821, "(1)"
+       line 412, "pan.___", state 822, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 822, "else"
+       line 412, "pan.___", state 825, "(1)"
+       line 412, "pan.___", state 826, "(1)"
+       line 412, "pan.___", state 826, "(1)"
+       line 410, "pan.___", state 831, "((i<1))"
+       line 410, "pan.___", state 831, "((i>=1))"
+       line 417, "pan.___", state 838, "(1)"
+       line 417, "pan.___", state 839, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 839, "else"
+       line 417, "pan.___", state 842, "(1)"
+       line 417, "pan.___", state 843, "(1)"
+       line 417, "pan.___", state 843, "(1)"
+       line 419, "pan.___", state 846, "(1)"
+       line 419, "pan.___", state 846, "(1)"
+       line 361, "pan.___", state 855, "sighand_exec = 1"
+       line 402, "pan.___", state 886, "(1)"
+       line 407, "pan.___", state 902, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 945, "(1)"
+       line 402, "pan.___", state 983, "(1)"
+       line 407, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1042, "(1)"
+       line 398, "pan.___", state 1068, "(1)"
+       line 402, "pan.___", state 1082, "(1)"
+       line 407, "pan.___", state 1098, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1141, "(1)"
+       line 402, "pan.___", state 1182, "(1)"
+       line 407, "pan.___", state 1198, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1241, "(1)"
+       line 174, "pan.___", state 1262, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1264, "(1)"
+       line 178, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1273, "(1)"
+       line 178, "pan.___", state 1274, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1274, "else"
+       line 176, "pan.___", state 1279, "((j<1))"
+       line 176, "pan.___", state 1279, "((j>=1))"
+       line 182, "pan.___", state 1284, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1286, "(1)"
+       line 182, "pan.___", state 1287, "((cache_dirty_generation_ptr.bitfield&(1<<0)))"
+       line 182, "pan.___", state 1287, "else"
+       line 174, "pan.___", state 1297, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 1299, "(1)"
+       line 178, "pan.___", state 1306, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1308, "(1)"
+       line 178, "pan.___", state 1309, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 1309, "else"
+       line 176, "pan.___", state 1314, "((j<1))"
+       line 176, "pan.___", state 1314, "((j>=1))"
+       line 182, "pan.___", state 1319, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1321, "(1)"
+       line 182, "pan.___", state 1322, "((cache_dirty_generation_ptr.bitfield&(1<<i)))"
+       line 182, "pan.___", state 1322, "else"
+       line 192, "pan.___", state 1327, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 192, "pan.___", state 1327, "else"
+       line 213, "pan.___", state 1331, "((i<1))"
+       line 213, "pan.___", state 1331, "((i>=1))"
+       line 174, "pan.___", state 1336, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1338, "(1)"
+       line 178, "pan.___", state 1345, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1347, "(1)"
+       line 178, "pan.___", state 1348, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1348, "else"
+       line 176, "pan.___", state 1353, "((j<1))"
+       line 176, "pan.___", state 1353, "((j>=1))"
+       line 182, "pan.___", state 1358, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1360, "(1)"
+       line 182, "pan.___", state 1361, "((cache_dirty_generation_ptr.bitfield&(1<<0)))"
+       line 182, "pan.___", state 1361, "else"
+       line 192, "pan.___", state 1366, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 192, "pan.___", state 1366, "else"
+       line 220, "pan.___", state 1367, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 1367, "else"
+       line 355, "pan.___", state 1373, "((sighand_exec==1))"
+       line 355, "pan.___", state 1373, "else"
+       line 361, "pan.___", state 1376, "sighand_exec = 1"
+       line 398, "pan.___", state 1389, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 1391, "(1)"
+       line 398, "pan.___", state 1392, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 1392, "else"
+       line 398, "pan.___", state 1395, "(1)"
+       line 402, "pan.___", state 1403, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 1405, "(1)"
+       line 402, "pan.___", state 1406, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 1406, "else"
+       line 402, "pan.___", state 1409, "(1)"
+       line 402, "pan.___", state 1410, "(1)"
+       line 402, "pan.___", state 1410, "(1)"
+       line 400, "pan.___", state 1415, "((i<1))"
+       line 400, "pan.___", state 1415, "((i>=1))"
+       line 407, "pan.___", state 1421, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 1434, "(1)"
+       line 408, "pan.___", state 1435, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 1435, "else"
+       line 408, "pan.___", state 1438, "(1)"
+       line 408, "pan.___", state 1439, "(1)"
+       line 408, "pan.___", state 1439, "(1)"
+       line 412, "pan.___", state 1447, "(1)"
+       line 412, "pan.___", state 1448, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 1448, "else"
+       line 412, "pan.___", state 1451, "(1)"
+       line 412, "pan.___", state 1452, "(1)"
+       line 412, "pan.___", state 1452, "(1)"
+       line 410, "pan.___", state 1457, "((i<1))"
+       line 410, "pan.___", state 1457, "((i>=1))"
+       line 417, "pan.___", state 1464, "(1)"
+       line 417, "pan.___", state 1465, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1465, "else"
+       line 417, "pan.___", state 1468, "(1)"
+       line 417, "pan.___", state 1469, "(1)"
+       line 417, "pan.___", state 1469, "(1)"
+       line 419, "pan.___", state 1472, "(1)"
+       line 419, "pan.___", state 1472, "(1)"
+       line 361, "pan.___", state 1481, "sighand_exec = 1"
+       line 178, "pan.___", state 1506, "(1)"
+       line 182, "pan.___", state 1517, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1530, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1539, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1552, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 1569, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1591, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 701, "pan.___", state 1632, "-end-"
+       (167 of 1632 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 747, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 0.15 seconds
+pan: rate 134306.67 states/second
+pan: avg transition delay 7.0835e-07 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input
new file mode 100644 (file)
index 0000000..525bc1e
--- /dev/null
@@ -0,0 +1,722 @@
+#define NO_RMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_free_no_rmb.spin.input.trail
new file mode 100644 (file)
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.define b/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.define
new file mode 100644 (file)
index 0000000..710f29d
--- /dev/null
@@ -0,0 +1 @@
+#define NO_WMB
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.log b/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.log
new file mode 100644 (file)
index 0000000..a346ed9
--- /dev/null
@@ -0,0 +1,224 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10499, errors: 0
+   159431 states, stored
+  1505398 states, matched
+  1664829 transitions (= stored+matched)
+  5794809 atomic steps
+hash conflicts:     62144 (resolved)
+
+Stats on memory usage (in Megabytes):
+   12.772      equivalent memory usage for states (stored*(State-vector + overhead))
+    8.936      actual memory usage for states (compression: 69.96%)
+               state-vector as stored = 31 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  474.651      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 402, "pan.___", state 330, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 651, "pan.___", state 213, "(1)"
+       line 402, "pan.___", state 348, "(1)"
+       line 398, "pan.___", state 433, "(1)"
+       line 402, "pan.___", state 447, "(1)"
+       line 402, "pan.___", state 547, "(1)"
+       line 159, "pan.___", state 628, "(1)"
+       line 163, "pan.___", state 636, "(1)"
+       line 163, "pan.___", state 637, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 637, "else"
+       line 161, "pan.___", state 642, "((j<1))"
+       line 161, "pan.___", state 642, "((j>=1))"
+       line 167, "pan.___", state 648, "(1)"
+       line 167, "pan.___", state 649, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 649, "else"
+       line 159, "pan.___", state 660, "(1)"
+       line 163, "pan.___", state 668, "(1)"
+       line 163, "pan.___", state 669, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 669, "else"
+       line 161, "pan.___", state 674, "((j<1))"
+       line 161, "pan.___", state 674, "((j>=1))"
+       line 167, "pan.___", state 680, "(1)"
+       line 167, "pan.___", state 681, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 681, "else"
+       line 201, "pan.___", state 686, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 201, "pan.___", state 686, "else"
+       line 213, "pan.___", state 690, "((i<1))"
+       line 213, "pan.___", state 690, "((i>=1))"
+       line 159, "pan.___", state 696, "(1)"
+       line 163, "pan.___", state 704, "(1)"
+       line 163, "pan.___", state 705, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 705, "else"
+       line 161, "pan.___", state 710, "((j<1))"
+       line 161, "pan.___", state 710, "((j>=1))"
+       line 167, "pan.___", state 716, "(1)"
+       line 167, "pan.___", state 717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 717, "else"
+       line 201, "pan.___", state 722, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 201, "pan.___", state 722, "else"
+       line 220, "pan.___", state 723, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 220, "pan.___", state 723, "else"
+       line 355, "pan.___", state 729, "((sighand_exec==1))"
+       line 355, "pan.___", state 729, "else"
+       line 361, "pan.___", state 732, "sighand_exec = 1"
+       line 398, "pan.___", state 745, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 747, "(1)"
+       line 398, "pan.___", state 748, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 748, "else"
+       line 398, "pan.___", state 751, "(1)"
+       line 402, "pan.___", state 759, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 761, "(1)"
+       line 402, "pan.___", state 762, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 762, "else"
+       line 402, "pan.___", state 765, "(1)"
+       line 402, "pan.___", state 766, "(1)"
+       line 402, "pan.___", state 766, "(1)"
+       line 400, "pan.___", state 771, "((i<1))"
+       line 400, "pan.___", state 771, "((i>=1))"
+       line 407, "pan.___", state 777, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 790, "(1)"
+       line 408, "pan.___", state 791, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 791, "else"
+       line 408, "pan.___", state 794, "(1)"
+       line 408, "pan.___", state 795, "(1)"
+       line 408, "pan.___", state 795, "(1)"
+       line 412, "pan.___", state 803, "(1)"
+       line 412, "pan.___", state 804, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 804, "else"
+       line 412, "pan.___", state 807, "(1)"
+       line 412, "pan.___", state 808, "(1)"
+       line 412, "pan.___", state 808, "(1)"
+       line 410, "pan.___", state 813, "((i<1))"
+       line 410, "pan.___", state 813, "((i>=1))"
+       line 417, "pan.___", state 820, "(1)"
+       line 417, "pan.___", state 821, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 821, "else"
+       line 417, "pan.___", state 824, "(1)"
+       line 417, "pan.___", state 825, "(1)"
+       line 417, "pan.___", state 825, "(1)"
+       line 419, "pan.___", state 828, "(1)"
+       line 419, "pan.___", state 828, "(1)"
+       line 361, "pan.___", state 837, "sighand_exec = 1"
+       line 402, "pan.___", state 868, "(1)"
+       line 402, "pan.___", state 965, "(1)"
+       line 398, "pan.___", state 1050, "(1)"
+       line 402, "pan.___", state 1064, "(1)"
+       line 402, "pan.___", state 1164, "(1)"
+       line 159, "pan.___", state 1245, "(1)"
+       line 163, "pan.___", state 1253, "(1)"
+       line 163, "pan.___", state 1254, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1254, "else"
+       line 161, "pan.___", state 1259, "((j<1))"
+       line 161, "pan.___", state 1259, "((j>=1))"
+       line 167, "pan.___", state 1265, "(1)"
+       line 167, "pan.___", state 1266, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1266, "else"
+       line 159, "pan.___", state 1277, "(1)"
+       line 163, "pan.___", state 1285, "(1)"
+       line 163, "pan.___", state 1286, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 1286, "else"
+       line 161, "pan.___", state 1291, "((j<1))"
+       line 161, "pan.___", state 1291, "((j>=1))"
+       line 167, "pan.___", state 1297, "(1)"
+       line 167, "pan.___", state 1298, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 1298, "else"
+       line 201, "pan.___", state 1303, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 201, "pan.___", state 1303, "else"
+       line 213, "pan.___", state 1307, "((i<1))"
+       line 213, "pan.___", state 1307, "((i>=1))"
+       line 159, "pan.___", state 1313, "(1)"
+       line 163, "pan.___", state 1321, "(1)"
+       line 163, "pan.___", state 1322, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1322, "else"
+       line 161, "pan.___", state 1327, "((j<1))"
+       line 161, "pan.___", state 1327, "((j>=1))"
+       line 167, "pan.___", state 1333, "(1)"
+       line 167, "pan.___", state 1334, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1334, "else"
+       line 201, "pan.___", state 1339, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 201, "pan.___", state 1339, "else"
+       line 220, "pan.___", state 1340, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 220, "pan.___", state 1340, "else"
+       line 355, "pan.___", state 1346, "((sighand_exec==1))"
+       line 355, "pan.___", state 1346, "else"
+       line 361, "pan.___", state 1349, "sighand_exec = 1"
+       line 398, "pan.___", state 1362, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 1364, "(1)"
+       line 398, "pan.___", state 1365, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 1365, "else"
+       line 398, "pan.___", state 1368, "(1)"
+       line 402, "pan.___", state 1376, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 1378, "(1)"
+       line 402, "pan.___", state 1379, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 1379, "else"
+       line 402, "pan.___", state 1382, "(1)"
+       line 402, "pan.___", state 1383, "(1)"
+       line 402, "pan.___", state 1383, "(1)"
+       line 400, "pan.___", state 1388, "((i<1))"
+       line 400, "pan.___", state 1388, "((i>=1))"
+       line 407, "pan.___", state 1394, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 1407, "(1)"
+       line 408, "pan.___", state 1408, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 1408, "else"
+       line 408, "pan.___", state 1411, "(1)"
+       line 408, "pan.___", state 1412, "(1)"
+       line 408, "pan.___", state 1412, "(1)"
+       line 412, "pan.___", state 1420, "(1)"
+       line 412, "pan.___", state 1421, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 1421, "else"
+       line 412, "pan.___", state 1424, "(1)"
+       line 412, "pan.___", state 1425, "(1)"
+       line 412, "pan.___", state 1425, "(1)"
+       line 410, "pan.___", state 1430, "((i<1))"
+       line 410, "pan.___", state 1430, "((i>=1))"
+       line 417, "pan.___", state 1437, "(1)"
+       line 417, "pan.___", state 1438, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1438, "else"
+       line 417, "pan.___", state 1441, "(1)"
+       line 417, "pan.___", state 1442, "(1)"
+       line 417, "pan.___", state 1442, "(1)"
+       line 419, "pan.___", state 1445, "(1)"
+       line 419, "pan.___", state 1445, "(1)"
+       line 361, "pan.___", state 1454, "sighand_exec = 1"
+       line 701, "pan.___", state 1596, "-end-"
+       (111 of 1596 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 747, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 1.23 seconds
+pan: rate  129618.7 states/second
+pan: avg transition delay 7.3881e-07 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input
new file mode 100644 (file)
index 0000000..808154e
--- /dev/null
@@ -0,0 +1,722 @@
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_free_no_wmb.spin.input.trail
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.define b/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.define
new file mode 100644 (file)
index 0000000..5e642ef
--- /dev/null
@@ -0,0 +1 @@
+#define SINGLE_FLIP
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.log b/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.log
new file mode 100644 (file)
index 0000000..f854175
--- /dev/null
@@ -0,0 +1,224 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 6934, errors: 0
+     7626 states, stored
+    67235 states, matched
+    74861 transitions (= stored+matched)
+   248896 atomic steps
+hash conflicts:       113 (resolved)
+
+Stats on memory usage (in Megabytes):
+    0.611      equivalent memory usage for states (stored*(State-vector + overhead))
+    0.867      actual memory usage for states (unsuccessful compression: 141.88%)
+               state-vector as stored = 91 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  466.545      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 402, "pan.___", state 330, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 160, "(1)"
+       line 651, "pan.___", state 213, "(1)"
+       line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 233, "(1)"
+       line 159, "pan.___", state 254, "(1)"
+       line 163, "pan.___", state 262, "(1)"
+       line 167, "pan.___", state 274, "(1)"
+       line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 317, "(1)"
+       line 163, "pan.___", state 325, "(1)"
+       line 167, "pan.___", state 337, "(1)"
+       line 174, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 384, "(1)"
+       line 163, "pan.___", state 392, "(1)"
+       line 167, "pan.___", state 404, "(1)"
+       line 398, "pan.___", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 441, "(1)"
+       line 407, "pan.___", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 470, "(1)"
+       line 417, "pan.___", state 500, "(1)"
+       line 398, "pan.___", state 526, "(1)"
+       line 402, "pan.___", state 540, "(1)"
+       line 407, "pan.___", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 599, "(1)"
+       line 402, "pan.___", state 640, "(1)"
+       line 407, "pan.___", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 699, "(1)"
+       line 174, "pan.___", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 722, "(1)"
+       line 178, "pan.___", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 731, "(1)"
+       line 178, "pan.___", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 732, "else"
+       line 176, "pan.___", state 737, "((j<1))"
+       line 176, "pan.___", state 737, "((j>=1))"
+       line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 752, "(1)"
+       line 163, "pan.___", state 760, "(1)"
+       line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 761, "else"
+       line 161, "pan.___", state 766, "((j<1))"
+       line 161, "pan.___", state 766, "((j>=1))"
+       line 167, "pan.___", state 772, "(1)"
+       line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 773, "else"
+       line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 776, "else"
+       line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 785, "(1)"
+       line 178, "pan.___", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 794, "(1)"
+       line 178, "pan.___", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 795, "else"
+       line 176, "pan.___", state 800, "((j<1))"
+       line 176, "pan.___", state 800, "((j>=1))"
+       line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 815, "(1)"
+       line 163, "pan.___", state 823, "(1)"
+       line 163, "pan.___", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 824, "else"
+       line 161, "pan.___", state 829, "((j<1))"
+       line 161, "pan.___", state 829, "((j>=1))"
+       line 167, "pan.___", state 835, "(1)"
+       line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 836, "else"
+       line 169, "pan.___", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 839, "else"
+       line 201, "pan.___", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 201, "pan.___", state 841, "else"
+       line 213, "pan.___", state 845, "((i<1))"
+       line 213, "pan.___", state 845, "((i>=1))"
+       line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 852, "(1)"
+       line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 861, "(1)"
+       line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 862, "else"
+       line 176, "pan.___", state 867, "((j<1))"
+       line 176, "pan.___", state 867, "((j>=1))"
+       line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 882, "(1)"
+       line 163, "pan.___", state 890, "(1)"
+       line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 891, "else"
+       line 161, "pan.___", state 896, "((j<1))"
+       line 161, "pan.___", state 896, "((j>=1))"
+       line 167, "pan.___", state 902, "(1)"
+       line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 903, "else"
+       line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 906, "else"
+       line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 201, "pan.___", state 908, "else"
+       line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 909, "else"
+       line 355, "pan.___", state 915, "((sighand_exec==1))"
+       line 355, "pan.___", state 915, "else"
+       line 361, "pan.___", state 918, "sighand_exec = 1"
+       line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 933, "(1)"
+       line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 934, "else"
+       line 398, "pan.___", state 937, "(1)"
+       line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 947, "(1)"
+       line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 948, "else"
+       line 402, "pan.___", state 951, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 400, "pan.___", state 957, "((i<1))"
+       line 400, "pan.___", state 957, "((i>=1))"
+       line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 976, "(1)"
+       line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 977, "else"
+       line 408, "pan.___", state 980, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 412, "pan.___", state 989, "(1)"
+       line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 990, "else"
+       line 412, "pan.___", state 993, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 410, "pan.___", state 999, "((i<1))"
+       line 410, "pan.___", state 999, "((i>=1))"
+       line 417, "pan.___", state 1006, "(1)"
+       line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1007, "else"
+       line 417, "pan.___", state 1010, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 361, "pan.___", state 1023, "sighand_exec = 1"
+       line 178, "pan.___", state 1048, "(1)"
+       line 182, "pan.___", state 1059, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1069, "(1)"
+       line 163, "pan.___", state 1077, "(1)"
+       line 167, "pan.___", state 1089, "(1)"
+       line 174, "pan.___", state 1100, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1109, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1122, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1132, "(1)"
+       line 163, "pan.___", state 1140, "(1)"
+       line 167, "pan.___", state 1152, "(1)"
+       line 174, "pan.___", state 1167, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1176, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1189, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1199, "(1)"
+       line 163, "pan.___", state 1207, "(1)"
+       line 167, "pan.___", state 1219, "(1)"
+       line 701, "pan.___", state 1258, "-end-"
+       (128 of 1258 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 747, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 0.05 seconds
+pan: rate    152520 states/second
+pan: avg transition delay 6.679e-07 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input
new file mode 100644 (file)
index 0000000..c796593
--- /dev/null
@@ -0,0 +1,722 @@
+#define SINGLE_FLIP
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_free_single_flip.spin.input.trail
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+1210:3:1973
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+1223:3:2027
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress.ltl b/formal-model/urcu/result-signal-over-writer/urcu_progress.ltl
new file mode 100644 (file)
index 0000000..8718641
--- /dev/null
@@ -0,0 +1 @@
+([] <> !np_)
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.define b/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.define
new file mode 100644 (file)
index 0000000..ff3f783
--- /dev/null
@@ -0,0 +1 @@
+#define READER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.log b/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.log
new file mode 100644 (file)
index 0000000..a1a6122
--- /dev/null
@@ -0,0 +1,348 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+depth 12: Claim reached state 9 (line 747)
+depth 86: Claim reached state 9 (line 746)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10679, errors: 0
+    38182 states, stored (88898 visited)
+   997091 states, matched
+  1085989 transitions (= visited+matched)
+  3694897 atomic steps
+hash conflicts:      9602 (resolved)
+
+Stats on memory usage (in Megabytes):
+    3.059      equivalent memory usage for states (stored*(State-vector + overhead))
+    2.930      actual memory usage for states (compression: 95.79%)
+               state-vector as stored = 52 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  468.596      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 402, "pan.___", state 330, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 160, "(1)"
+       line 651, "pan.___", state 213, "(1)"
+       line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 233, "(1)"
+       line 159, "pan.___", state 254, "(1)"
+       line 163, "pan.___", state 262, "(1)"
+       line 167, "pan.___", state 274, "(1)"
+       line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 317, "(1)"
+       line 163, "pan.___", state 325, "(1)"
+       line 167, "pan.___", state 337, "(1)"
+       line 174, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 384, "(1)"
+       line 163, "pan.___", state 392, "(1)"
+       line 167, "pan.___", state 404, "(1)"
+       line 398, "pan.___", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 441, "(1)"
+       line 407, "pan.___", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 470, "(1)"
+       line 417, "pan.___", state 500, "(1)"
+       line 398, "pan.___", state 526, "(1)"
+       line 402, "pan.___", state 540, "(1)"
+       line 407, "pan.___", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 599, "(1)"
+       line 402, "pan.___", state 640, "(1)"
+       line 407, "pan.___", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 699, "(1)"
+       line 174, "pan.___", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 722, "(1)"
+       line 178, "pan.___", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 731, "(1)"
+       line 178, "pan.___", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 732, "else"
+       line 176, "pan.___", state 737, "((j<1))"
+       line 176, "pan.___", state 737, "((j>=1))"
+       line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 752, "(1)"
+       line 163, "pan.___", state 760, "(1)"
+       line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 761, "else"
+       line 161, "pan.___", state 766, "((j<1))"
+       line 161, "pan.___", state 766, "((j>=1))"
+       line 167, "pan.___", state 772, "(1)"
+       line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 773, "else"
+       line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 776, "else"
+       line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 785, "(1)"
+       line 178, "pan.___", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 794, "(1)"
+       line 178, "pan.___", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 795, "else"
+       line 176, "pan.___", state 800, "((j<1))"
+       line 176, "pan.___", state 800, "((j>=1))"
+       line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 815, "(1)"
+       line 163, "pan.___", state 823, "(1)"
+       line 163, "pan.___", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 824, "else"
+       line 161, "pan.___", state 829, "((j<1))"
+       line 161, "pan.___", state 829, "((j>=1))"
+       line 167, "pan.___", state 835, "(1)"
+       line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 836, "else"
+       line 169, "pan.___", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 839, "else"
+       line 201, "pan.___", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 201, "pan.___", state 841, "else"
+       line 213, "pan.___", state 845, "((i<1))"
+       line 213, "pan.___", state 845, "((i>=1))"
+       line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 852, "(1)"
+       line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 861, "(1)"
+       line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 862, "else"
+       line 176, "pan.___", state 867, "((j<1))"
+       line 176, "pan.___", state 867, "((j>=1))"
+       line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 882, "(1)"
+       line 163, "pan.___", state 890, "(1)"
+       line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 891, "else"
+       line 161, "pan.___", state 896, "((j<1))"
+       line 161, "pan.___", state 896, "((j>=1))"
+       line 167, "pan.___", state 902, "(1)"
+       line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 903, "else"
+       line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 906, "else"
+       line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 201, "pan.___", state 908, "else"
+       line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 909, "else"
+       line 355, "pan.___", state 915, "((sighand_exec==1))"
+       line 355, "pan.___", state 915, "else"
+       line 361, "pan.___", state 918, "sighand_exec = 1"
+       line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 933, "(1)"
+       line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 934, "else"
+       line 398, "pan.___", state 937, "(1)"
+       line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 947, "(1)"
+       line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 948, "else"
+       line 402, "pan.___", state 951, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 400, "pan.___", state 957, "((i<1))"
+       line 400, "pan.___", state 957, "((i>=1))"
+       line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 976, "(1)"
+       line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 977, "else"
+       line 408, "pan.___", state 980, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 412, "pan.___", state 989, "(1)"
+       line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 990, "else"
+       line 412, "pan.___", state 993, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 410, "pan.___", state 999, "((i<1))"
+       line 410, "pan.___", state 999, "((i>=1))"
+       line 417, "pan.___", state 1006, "(1)"
+       line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1007, "else"
+       line 417, "pan.___", state 1010, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 361, "pan.___", state 1023, "sighand_exec = 1"
+       line 402, "pan.___", state 1054, "(1)"
+       line 407, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1113, "(1)"
+       line 402, "pan.___", state 1151, "(1)"
+       line 407, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1210, "(1)"
+       line 398, "pan.___", state 1236, "(1)"
+       line 402, "pan.___", state 1250, "(1)"
+       line 407, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1309, "(1)"
+       line 402, "pan.___", state 1350, "(1)"
+       line 407, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1409, "(1)"
+       line 174, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1432, "(1)"
+       line 178, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1441, "(1)"
+       line 178, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1442, "else"
+       line 176, "pan.___", state 1447, "((j<1))"
+       line 176, "pan.___", state 1447, "((j>=1))"
+       line 182, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1462, "(1)"
+       line 163, "pan.___", state 1470, "(1)"
+       line 163, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1471, "else"
+       line 161, "pan.___", state 1476, "((j<1))"
+       line 161, "pan.___", state 1476, "((j>=1))"
+       line 167, "pan.___", state 1482, "(1)"
+       line 167, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1483, "else"
+       line 169, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 1486, "else"
+       line 174, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 1495, "(1)"
+       line 178, "pan.___", state 1502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1504, "(1)"
+       line 178, "pan.___", state 1505, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 1505, "else"
+       line 176, "pan.___", state 1510, "((j<1))"
+       line 176, "pan.___", state 1510, "((j>=1))"
+       line 182, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1525, "(1)"
+       line 163, "pan.___", state 1533, "(1)"
+       line 163, "pan.___", state 1534, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 1534, "else"
+       line 161, "pan.___", state 1539, "((j<1))"
+       line 161, "pan.___", state 1539, "((j>=1))"
+       line 167, "pan.___", state 1545, "(1)"
+       line 167, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 1546, "else"
+       line 169, "pan.___", state 1549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 1549, "else"
+       line 201, "pan.___", state 1551, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 201, "pan.___", state 1551, "else"
+       line 213, "pan.___", state 1555, "((i<1))"
+       line 213, "pan.___", state 1555, "((i>=1))"
+       line 174, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1562, "(1)"
+       line 178, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1571, "(1)"
+       line 178, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1572, "else"
+       line 176, "pan.___", state 1577, "((j<1))"
+       line 176, "pan.___", state 1577, "((j>=1))"
+       line 182, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1592, "(1)"
+       line 163, "pan.___", state 1600, "(1)"
+       line 163, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1601, "else"
+       line 161, "pan.___", state 1606, "((j<1))"
+       line 161, "pan.___", state 1606, "((j>=1))"
+       line 167, "pan.___", state 1612, "(1)"
+       line 167, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1613, "else"
+       line 169, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 1616, "else"
+       line 201, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 201, "pan.___", state 1618, "else"
+       line 220, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 1619, "else"
+       line 355, "pan.___", state 1625, "((sighand_exec==1))"
+       line 355, "pan.___", state 1625, "else"
+       line 361, "pan.___", state 1628, "sighand_exec = 1"
+       line 398, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 1643, "(1)"
+       line 398, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 1644, "else"
+       line 398, "pan.___", state 1647, "(1)"
+       line 402, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 1657, "(1)"
+       line 402, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 1658, "else"
+       line 402, "pan.___", state 1661, "(1)"
+       line 402, "pan.___", state 1662, "(1)"
+       line 402, "pan.___", state 1662, "(1)"
+       line 400, "pan.___", state 1667, "((i<1))"
+       line 400, "pan.___", state 1667, "((i>=1))"
+       line 407, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 1686, "(1)"
+       line 408, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 1687, "else"
+       line 408, "pan.___", state 1690, "(1)"
+       line 408, "pan.___", state 1691, "(1)"
+       line 408, "pan.___", state 1691, "(1)"
+       line 412, "pan.___", state 1699, "(1)"
+       line 412, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 1700, "else"
+       line 412, "pan.___", state 1703, "(1)"
+       line 412, "pan.___", state 1704, "(1)"
+       line 412, "pan.___", state 1704, "(1)"
+       line 410, "pan.___", state 1709, "((i<1))"
+       line 410, "pan.___", state 1709, "((i>=1))"
+       line 417, "pan.___", state 1716, "(1)"
+       line 417, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1717, "else"
+       line 417, "pan.___", state 1720, "(1)"
+       line 417, "pan.___", state 1721, "(1)"
+       line 417, "pan.___", state 1721, "(1)"
+       line 419, "pan.___", state 1724, "(1)"
+       line 419, "pan.___", state 1724, "(1)"
+       line 361, "pan.___", state 1733, "sighand_exec = 1"
+       line 178, "pan.___", state 1758, "(1)"
+       line 182, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1779, "(1)"
+       line 163, "pan.___", state 1787, "(1)"
+       line 167, "pan.___", state 1799, "(1)"
+       line 174, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1832, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1842, "(1)"
+       line 163, "pan.___", state 1850, "(1)"
+       line 167, "pan.___", state 1862, "(1)"
+       line 174, "pan.___", state 1877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1886, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1899, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1909, "(1)"
+       line 163, "pan.___", state 1917, "(1)"
+       line 167, "pan.___", state 1929, "(1)"
+       line 701, "pan.___", state 1968, "-end-"
+       (215 of 1968 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 0.85 seconds
+pan: rate 104585.88 states/second
+pan: avg transition delay 7.827e-07 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input
new file mode 100644 (file)
index 0000000..5b64404
--- /dev/null
@@ -0,0 +1,722 @@
+#define READER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_progress_reader.spin.input.trail
new file mode 100644 (file)
index 0000000..7c42af1
--- /dev/null
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+1064:3:4315
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+1112:0:4401
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+-1:-1:-1
+1240:0:4405
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+1255:3:4347
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diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.define b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.define
new file mode 100644 (file)
index 0000000..1e4417f
--- /dev/null
@@ -0,0 +1 @@
+#define WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.log b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.log
new file mode 100644 (file)
index 0000000..02c53cf
--- /dev/null
@@ -0,0 +1,348 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+depth 12: Claim reached state 9 (line 747)
+depth 28: Claim reached state 9 (line 746)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10679, errors: 0
+    38555 states, stored (92500 visited)
+  1044204 states, matched
+  1136704 transitions (= visited+matched)
+  3867169 atomic steps
+hash conflicts:      8572 (resolved)
+
+Stats on memory usage (in Megabytes):
+    3.089      equivalent memory usage for states (stored*(State-vector + overhead))
+    2.930      actual memory usage for states (compression: 94.87%)
+               state-vector as stored = 52 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  468.596      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 402, "pan.___", state 330, "(1)"
+       line 613, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 160, "(1)"
+       line 651, "pan.___", state 213, "(1)"
+       line 174, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 233, "(1)"
+       line 159, "pan.___", state 254, "(1)"
+       line 163, "pan.___", state 262, "(1)"
+       line 167, "pan.___", state 274, "(1)"
+       line 174, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 317, "(1)"
+       line 163, "pan.___", state 325, "(1)"
+       line 167, "pan.___", state 337, "(1)"
+       line 174, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 384, "(1)"
+       line 163, "pan.___", state 392, "(1)"
+       line 167, "pan.___", state 404, "(1)"
+       line 398, "pan.___", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 441, "(1)"
+       line 407, "pan.___", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 470, "(1)"
+       line 417, "pan.___", state 500, "(1)"
+       line 398, "pan.___", state 526, "(1)"
+       line 402, "pan.___", state 540, "(1)"
+       line 407, "pan.___", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 599, "(1)"
+       line 402, "pan.___", state 640, "(1)"
+       line 407, "pan.___", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 699, "(1)"
+       line 174, "pan.___", state 720, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 722, "(1)"
+       line 178, "pan.___", state 729, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 731, "(1)"
+       line 178, "pan.___", state 732, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 732, "else"
+       line 176, "pan.___", state 737, "((j<1))"
+       line 176, "pan.___", state 737, "((j>=1))"
+       line 182, "pan.___", state 742, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 752, "(1)"
+       line 163, "pan.___", state 760, "(1)"
+       line 163, "pan.___", state 761, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 761, "else"
+       line 161, "pan.___", state 766, "((j<1))"
+       line 161, "pan.___", state 766, "((j>=1))"
+       line 167, "pan.___", state 772, "(1)"
+       line 167, "pan.___", state 773, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 773, "else"
+       line 169, "pan.___", state 776, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 776, "else"
+       line 174, "pan.___", state 783, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 785, "(1)"
+       line 178, "pan.___", state 792, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 794, "(1)"
+       line 178, "pan.___", state 795, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 795, "else"
+       line 176, "pan.___", state 800, "((j<1))"
+       line 176, "pan.___", state 800, "((j>=1))"
+       line 182, "pan.___", state 805, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 815, "(1)"
+       line 163, "pan.___", state 823, "(1)"
+       line 163, "pan.___", state 824, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 824, "else"
+       line 161, "pan.___", state 829, "((j<1))"
+       line 161, "pan.___", state 829, "((j>=1))"
+       line 167, "pan.___", state 835, "(1)"
+       line 167, "pan.___", state 836, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 836, "else"
+       line 169, "pan.___", state 839, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 839, "else"
+       line 201, "pan.___", state 841, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 201, "pan.___", state 841, "else"
+       line 213, "pan.___", state 845, "((i<1))"
+       line 213, "pan.___", state 845, "((i>=1))"
+       line 174, "pan.___", state 850, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 852, "(1)"
+       line 178, "pan.___", state 859, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 861, "(1)"
+       line 178, "pan.___", state 862, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 862, "else"
+       line 176, "pan.___", state 867, "((j<1))"
+       line 176, "pan.___", state 867, "((j>=1))"
+       line 182, "pan.___", state 872, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 882, "(1)"
+       line 163, "pan.___", state 890, "(1)"
+       line 163, "pan.___", state 891, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 891, "else"
+       line 161, "pan.___", state 896, "((j<1))"
+       line 161, "pan.___", state 896, "((j>=1))"
+       line 167, "pan.___", state 902, "(1)"
+       line 167, "pan.___", state 903, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 903, "else"
+       line 169, "pan.___", state 906, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 906, "else"
+       line 201, "pan.___", state 908, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 201, "pan.___", state 908, "else"
+       line 220, "pan.___", state 909, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 909, "else"
+       line 355, "pan.___", state 915, "((sighand_exec==1))"
+       line 355, "pan.___", state 915, "else"
+       line 361, "pan.___", state 918, "sighand_exec = 1"
+       line 398, "pan.___", state 931, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 933, "(1)"
+       line 398, "pan.___", state 934, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 934, "else"
+       line 398, "pan.___", state 937, "(1)"
+       line 402, "pan.___", state 945, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 947, "(1)"
+       line 402, "pan.___", state 948, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 948, "else"
+       line 402, "pan.___", state 951, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 402, "pan.___", state 952, "(1)"
+       line 400, "pan.___", state 957, "((i<1))"
+       line 400, "pan.___", state 957, "((i>=1))"
+       line 407, "pan.___", state 963, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 976, "(1)"
+       line 408, "pan.___", state 977, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 977, "else"
+       line 408, "pan.___", state 980, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 408, "pan.___", state 981, "(1)"
+       line 412, "pan.___", state 989, "(1)"
+       line 412, "pan.___", state 990, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 990, "else"
+       line 412, "pan.___", state 993, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 412, "pan.___", state 994, "(1)"
+       line 410, "pan.___", state 999, "((i<1))"
+       line 410, "pan.___", state 999, "((i>=1))"
+       line 417, "pan.___", state 1006, "(1)"
+       line 417, "pan.___", state 1007, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1007, "else"
+       line 417, "pan.___", state 1010, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 417, "pan.___", state 1011, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 419, "pan.___", state 1014, "(1)"
+       line 361, "pan.___", state 1023, "sighand_exec = 1"
+       line 402, "pan.___", state 1054, "(1)"
+       line 407, "pan.___", state 1070, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1113, "(1)"
+       line 402, "pan.___", state 1151, "(1)"
+       line 407, "pan.___", state 1167, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1210, "(1)"
+       line 398, "pan.___", state 1236, "(1)"
+       line 402, "pan.___", state 1250, "(1)"
+       line 407, "pan.___", state 1266, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1309, "(1)"
+       line 402, "pan.___", state 1350, "(1)"
+       line 407, "pan.___", state 1366, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 417, "pan.___", state 1409, "(1)"
+       line 174, "pan.___", state 1430, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1432, "(1)"
+       line 178, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1441, "(1)"
+       line 178, "pan.___", state 1442, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1442, "else"
+       line 176, "pan.___", state 1447, "((j<1))"
+       line 176, "pan.___", state 1447, "((j>=1))"
+       line 182, "pan.___", state 1452, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1462, "(1)"
+       line 163, "pan.___", state 1470, "(1)"
+       line 163, "pan.___", state 1471, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1471, "else"
+       line 161, "pan.___", state 1476, "((j<1))"
+       line 161, "pan.___", state 1476, "((j>=1))"
+       line 167, "pan.___", state 1482, "(1)"
+       line 167, "pan.___", state 1483, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1483, "else"
+       line 169, "pan.___", state 1486, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 1486, "else"
+       line 174, "pan.___", state 1493, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 174, "pan.___", state 1495, "(1)"
+       line 178, "pan.___", state 1502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1504, "(1)"
+       line 178, "pan.___", state 1505, "((cache_dirty_urcu_active_readers.bitfield&(1<<i)))"
+       line 178, "pan.___", state 1505, "else"
+       line 176, "pan.___", state 1510, "((j<1))"
+       line 176, "pan.___", state 1510, "((j>=1))"
+       line 182, "pan.___", state 1515, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1525, "(1)"
+       line 163, "pan.___", state 1533, "(1)"
+       line 163, "pan.___", state 1534, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 163, "pan.___", state 1534, "else"
+       line 161, "pan.___", state 1539, "((j<1))"
+       line 161, "pan.___", state 1539, "((j>=1))"
+       line 167, "pan.___", state 1545, "(1)"
+       line 167, "pan.___", state 1546, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 167, "pan.___", state 1546, "else"
+       line 169, "pan.___", state 1549, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 1549, "else"
+       line 201, "pan.___", state 1551, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<i)))"
+       line 201, "pan.___", state 1551, "else"
+       line 213, "pan.___", state 1555, "((i<1))"
+       line 213, "pan.___", state 1555, "((i>=1))"
+       line 174, "pan.___", state 1560, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 174, "pan.___", state 1562, "(1)"
+       line 178, "pan.___", state 1569, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1571, "(1)"
+       line 178, "pan.___", state 1572, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 178, "pan.___", state 1572, "else"
+       line 176, "pan.___", state 1577, "((j<1))"
+       line 176, "pan.___", state 1577, "((j>=1))"
+       line 182, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1592, "(1)"
+       line 163, "pan.___", state 1600, "(1)"
+       line 163, "pan.___", state 1601, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 163, "pan.___", state 1601, "else"
+       line 161, "pan.___", state 1606, "((j<1))"
+       line 161, "pan.___", state 1606, "((j>=1))"
+       line 167, "pan.___", state 1612, "(1)"
+       line 167, "pan.___", state 1613, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 167, "pan.___", state 1613, "else"
+       line 169, "pan.___", state 1616, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 169, "pan.___", state 1616, "else"
+       line 201, "pan.___", state 1618, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 201, "pan.___", state 1618, "else"
+       line 220, "pan.___", state 1619, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 220, "pan.___", state 1619, "else"
+       line 355, "pan.___", state 1625, "((sighand_exec==1))"
+       line 355, "pan.___", state 1625, "else"
+       line 361, "pan.___", state 1628, "sighand_exec = 1"
+       line 398, "pan.___", state 1641, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 398, "pan.___", state 1643, "(1)"
+       line 398, "pan.___", state 1644, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 398, "pan.___", state 1644, "else"
+       line 398, "pan.___", state 1647, "(1)"
+       line 402, "pan.___", state 1655, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 402, "pan.___", state 1657, "(1)"
+       line 402, "pan.___", state 1658, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 402, "pan.___", state 1658, "else"
+       line 402, "pan.___", state 1661, "(1)"
+       line 402, "pan.___", state 1662, "(1)"
+       line 402, "pan.___", state 1662, "(1)"
+       line 400, "pan.___", state 1667, "((i<1))"
+       line 400, "pan.___", state 1667, "((i>=1))"
+       line 407, "pan.___", state 1673, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 1686, "(1)"
+       line 408, "pan.___", state 1687, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 408, "pan.___", state 1687, "else"
+       line 408, "pan.___", state 1690, "(1)"
+       line 408, "pan.___", state 1691, "(1)"
+       line 408, "pan.___", state 1691, "(1)"
+       line 412, "pan.___", state 1699, "(1)"
+       line 412, "pan.___", state 1700, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 412, "pan.___", state 1700, "else"
+       line 412, "pan.___", state 1703, "(1)"
+       line 412, "pan.___", state 1704, "(1)"
+       line 412, "pan.___", state 1704, "(1)"
+       line 410, "pan.___", state 1709, "((i<1))"
+       line 410, "pan.___", state 1709, "((i>=1))"
+       line 417, "pan.___", state 1716, "(1)"
+       line 417, "pan.___", state 1717, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 417, "pan.___", state 1717, "else"
+       line 417, "pan.___", state 1720, "(1)"
+       line 417, "pan.___", state 1721, "(1)"
+       line 417, "pan.___", state 1721, "(1)"
+       line 419, "pan.___", state 1724, "(1)"
+       line 419, "pan.___", state 1724, "(1)"
+       line 361, "pan.___", state 1733, "sighand_exec = 1"
+       line 178, "pan.___", state 1758, "(1)"
+       line 182, "pan.___", state 1769, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1779, "(1)"
+       line 163, "pan.___", state 1787, "(1)"
+       line 167, "pan.___", state 1799, "(1)"
+       line 174, "pan.___", state 1810, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 1819, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1832, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1842, "(1)"
+       line 163, "pan.___", state 1850, "(1)"
+       line 167, "pan.___", state 1862, "(1)"
+       line 174, "pan.___", state 1877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 178, "pan.___", state 1886, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 182, "pan.___", state 1899, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 159, "pan.___", state 1909, "(1)"
+       line 163, "pan.___", state 1917, "(1)"
+       line 167, "pan.___", state 1929, "(1)"
+       line 701, "pan.___", state 1968, "-end-"
+       (215 of 1968 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 0.89 seconds
+pan: rate 103932.58 states/second
+pan: avg transition delay 7.8297e-07 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input
new file mode 100644 (file)
index 0000000..6ba27b1
--- /dev/null
@@ -0,0 +1,722 @@
+#define WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.define b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.define
new file mode 100644 (file)
index 0000000..8d304f5
--- /dev/null
@@ -0,0 +1,2 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.log b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.log
new file mode 100644 (file)
index 0000000..cd4e32b
--- /dev/null
@@ -0,0 +1,286 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 743)
+depth 12: Claim reached state 9 (line 748)
+depth 28: Claim reached state 9 (line 747)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 10679, errors: 0
+    38555 states, stored (92500 visited)
+  1044204 states, matched
+  1136704 transitions (= visited+matched)
+  3867169 atomic steps
+hash conflicts:      6390 (resolved)
+
+Stats on memory usage (in Megabytes):
+    3.089      equivalent memory usage for states (stored*(State-vector + overhead))
+    2.767      actual memory usage for states (compression: 89.58%)
+               state-vector as stored = 47 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  468.498      total actual memory usage
+
+unreached in proctype urcu_reader_sig
+       line 403, "pan.___", state 330, "(1)"
+       line 614, "pan.___", state 411, "-end-"
+       (2 of 411 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 115, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 160, "(1)"
+       line 652, "pan.___", state 213, "(1)"
+       line 175, "pan.___", state 222, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 179, "pan.___", state 233, "(1)"
+       line 160, "pan.___", state 254, "(1)"
+       line 164, "pan.___", state 262, "(1)"
+       line 168, "pan.___", state 274, "(1)"
+       line 175, "pan.___", state 285, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 179, "pan.___", state 294, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 307, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 317, "(1)"
+       line 164, "pan.___", state 325, "(1)"
+       line 168, "pan.___", state 337, "(1)"
+       line 175, "pan.___", state 352, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 179, "pan.___", state 361, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 183, "pan.___", state 374, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 160, "pan.___", state 384, "(1)"
+       line 164, "pan.___", state 392, "(1)"
+       line 168, "pan.___", state 404, "(1)"
+       line 399, "pan.___", state 425, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 441, "(1)"
+       line 408, "pan.___", state 457, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 470, "(1)"
+       line 418, "pan.___", state 500, "(1)"
+       line 399, "pan.___", state 526, "(1)"
+       line 403, "pan.___", state 540, "(1)"
+       line 408, "pan.___", state 556, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 599, "(1)"
+       line 403, "pan.___", state 640, "(1)"
+       line 408, "pan.___", state 656, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 699, "(1)"
+       line 399, "pan.___", state 721, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 723, "(1)"
+       line 399, "pan.___", state 724, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 724, "else"
+       line 399, "pan.___", state 727, "(1)"
+       line 403, "pan.___", state 735, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 737, "(1)"
+       line 403, "pan.___", state 738, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 738, "else"
+       line 403, "pan.___", state 741, "(1)"
+       line 403, "pan.___", state 742, "(1)"
+       line 403, "pan.___", state 742, "(1)"
+       line 401, "pan.___", state 747, "((i<1))"
+       line 401, "pan.___", state 747, "((i>=1))"
+       line 408, "pan.___", state 753, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 766, "(1)"
+       line 409, "pan.___", state 767, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 767, "else"
+       line 409, "pan.___", state 770, "(1)"
+       line 409, "pan.___", state 771, "(1)"
+       line 409, "pan.___", state 771, "(1)"
+       line 413, "pan.___", state 779, "(1)"
+       line 413, "pan.___", state 780, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 780, "else"
+       line 413, "pan.___", state 783, "(1)"
+       line 413, "pan.___", state 784, "(1)"
+       line 413, "pan.___", state 784, "(1)"
+       line 411, "pan.___", state 789, "((i<1))"
+       line 411, "pan.___", state 789, "((i>=1))"
+       line 418, "pan.___", state 796, "(1)"
+       line 418, "pan.___", state 797, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 797, "else"
+       line 418, "pan.___", state 800, "(1)"
+       line 418, "pan.___", state 801, "(1)"
+       line 418, "pan.___", state 801, "(1)"
+       line 420, "pan.___", state 804, "(1)"
+       line 420, "pan.___", state 804, "(1)"
+       line 356, "pan.___", state 810, "((sighand_exec==1))"
+       line 356, "pan.___", state 810, "else"
+       line 362, "pan.___", state 813, "sighand_exec = 1"
+       line 399, "pan.___", state 826, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 828, "(1)"
+       line 399, "pan.___", state 829, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 829, "else"
+       line 399, "pan.___", state 832, "(1)"
+       line 403, "pan.___", state 840, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 842, "(1)"
+       line 403, "pan.___", state 843, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 843, "else"
+       line 403, "pan.___", state 846, "(1)"
+       line 403, "pan.___", state 847, "(1)"
+       line 403, "pan.___", state 847, "(1)"
+       line 401, "pan.___", state 852, "((i<1))"
+       line 401, "pan.___", state 852, "((i>=1))"
+       line 408, "pan.___", state 858, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 871, "(1)"
+       line 409, "pan.___", state 872, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 872, "else"
+       line 409, "pan.___", state 875, "(1)"
+       line 409, "pan.___", state 876, "(1)"
+       line 409, "pan.___", state 876, "(1)"
+       line 413, "pan.___", state 884, "(1)"
+       line 413, "pan.___", state 885, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 885, "else"
+       line 413, "pan.___", state 888, "(1)"
+       line 413, "pan.___", state 889, "(1)"
+       line 413, "pan.___", state 889, "(1)"
+       line 411, "pan.___", state 894, "((i<1))"
+       line 411, "pan.___", state 894, "((i>=1))"
+       line 418, "pan.___", state 901, "(1)"
+       line 418, "pan.___", state 902, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 902, "else"
+       line 418, "pan.___", state 905, "(1)"
+       line 418, "pan.___", state 906, "(1)"
+       line 418, "pan.___", state 906, "(1)"
+       line 420, "pan.___", state 909, "(1)"
+       line 420, "pan.___", state 909, "(1)"
+       line 362, "pan.___", state 918, "sighand_exec = 1"
+       line 403, "pan.___", state 949, "(1)"
+       line 408, "pan.___", state 965, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 1008, "(1)"
+       line 403, "pan.___", state 1046, "(1)"
+       line 408, "pan.___", state 1062, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 1105, "(1)"
+       line 399, "pan.___", state 1131, "(1)"
+       line 403, "pan.___", state 1145, "(1)"
+       line 408, "pan.___", state 1161, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 1204, "(1)"
+       line 403, "pan.___", state 1245, "(1)"
+       line 408, "pan.___", state 1261, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 418, "pan.___", state 1304, "(1)"
+       line 399, "pan.___", state 1326, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1328, "(1)"
+       line 399, "pan.___", state 1329, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1329, "else"
+       line 399, "pan.___", state 1332, "(1)"
+       line 403, "pan.___", state 1340, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1342, "(1)"
+       line 403, "pan.___", state 1343, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1343, "else"
+       line 403, "pan.___", state 1346, "(1)"
+       line 403, "pan.___", state 1347, "(1)"
+       line 403, "pan.___", state 1347, "(1)"
+       line 401, "pan.___", state 1352, "((i<1))"
+       line 401, "pan.___", state 1352, "((i>=1))"
+       line 408, "pan.___", state 1358, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1371, "(1)"
+       line 409, "pan.___", state 1372, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1372, "else"
+       line 409, "pan.___", state 1375, "(1)"
+       line 409, "pan.___", state 1376, "(1)"
+       line 409, "pan.___", state 1376, "(1)"
+       line 413, "pan.___", state 1384, "(1)"
+       line 413, "pan.___", state 1385, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1385, "else"
+       line 413, "pan.___", state 1388, "(1)"
+       line 413, "pan.___", state 1389, "(1)"
+       line 413, "pan.___", state 1389, "(1)"
+       line 411, "pan.___", state 1394, "((i<1))"
+       line 411, "pan.___", state 1394, "((i>=1))"
+       line 418, "pan.___", state 1401, "(1)"
+       line 418, "pan.___", state 1402, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1402, "else"
+       line 418, "pan.___", state 1405, "(1)"
+       line 418, "pan.___", state 1406, "(1)"
+       line 418, "pan.___", state 1406, "(1)"
+       line 420, "pan.___", state 1409, "(1)"
+       line 420, "pan.___", state 1409, "(1)"
+       line 356, "pan.___", state 1415, "((sighand_exec==1))"
+       line 356, "pan.___", state 1415, "else"
+       line 362, "pan.___", state 1418, "sighand_exec = 1"
+       line 399, "pan.___", state 1431, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 399, "pan.___", state 1433, "(1)"
+       line 399, "pan.___", state 1434, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<0)))"
+       line 399, "pan.___", state 1434, "else"
+       line 399, "pan.___", state 1437, "(1)"
+       line 403, "pan.___", state 1445, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 403, "pan.___", state 1447, "(1)"
+       line 403, "pan.___", state 1448, "((cache_dirty_urcu_active_readers.bitfield&(1<<0)))"
+       line 403, "pan.___", state 1448, "else"
+       line 403, "pan.___", state 1451, "(1)"
+       line 403, "pan.___", state 1452, "(1)"
+       line 403, "pan.___", state 1452, "(1)"
+       line 401, "pan.___", state 1457, "((i<1))"
+       line 401, "pan.___", state 1457, "((i>=1))"
+       line 408, "pan.___", state 1463, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 409, "pan.___", state 1476, "(1)"
+       line 409, "pan.___", state 1477, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<0))))"
+       line 409, "pan.___", state 1477, "else"
+       line 409, "pan.___", state 1480, "(1)"
+       line 409, "pan.___", state 1481, "(1)"
+       line 409, "pan.___", state 1481, "(1)"
+       line 413, "pan.___", state 1489, "(1)"
+       line 413, "pan.___", state 1490, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<0))))"
+       line 413, "pan.___", state 1490, "else"
+       line 413, "pan.___", state 1493, "(1)"
+       line 413, "pan.___", state 1494, "(1)"
+       line 413, "pan.___", state 1494, "(1)"
+       line 411, "pan.___", state 1499, "((i<1))"
+       line 411, "pan.___", state 1499, "((i>=1))"
+       line 418, "pan.___", state 1506, "(1)"
+       line 418, "pan.___", state 1507, "(!((cache_dirty_generation_ptr.bitfield&(1<<0))))"
+       line 418, "pan.___", state 1507, "else"
+       line 418, "pan.___", state 1510, "(1)"
+       line 418, "pan.___", state 1511, "(1)"
+       line 418, "pan.___", state 1511, "(1)"
+       line 420, "pan.___", state 1514, "(1)"
+       line 420, "pan.___", state 1514, "(1)"
+       line 362, "pan.___", state 1523, "sighand_exec = 1"
+       line 179, "pan.___", state 1548, "(1)"
+       line 183, "pan.___", state 1559, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 160, "pan.___", state 1569, "(1)"
+       line 164, "pan.___", state 1577, "(1)"
+       line 168, "pan.___", state 1589, "(1)"
+       line 175, "pan.___", state 1600, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 179, "pan.___", state 1609, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1622, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1632, "(1)"
+       line 164, "pan.___", state 1640, "(1)"
+       line 168, "pan.___", state 1652, "(1)"
+       line 175, "pan.___", state 1667, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<0)))"
+       line 179, "pan.___", state 1676, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<0)))"
+       line 183, "pan.___", state 1689, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<0)))"
+       line 160, "pan.___", state 1699, "(1)"
+       line 164, "pan.___", state 1707, "(1)"
+       line 168, "pan.___", state 1719, "(1)"
+       line 702, "pan.___", state 1758, "-end-"
+       (173 of 1758 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 750, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 0.89 seconds
+pan: rate 103932.58 states/second
+pan: avg transition delay 7.8297e-07 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input
new file mode 100644 (file)
index 0000000..e998d85
--- /dev/null
@@ -0,0 +1,723 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu/result-signal-over-writer/urcu_progress_writer_error.spin.input.trail
new file mode 100644 (file)
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+4214:2:2416
+4215:2:2423
+4216:2:2424
+4217:2:2435
+4218:2:2443
+4219:2:2444
+4220:2:2448
+4221:2:2453
+4222:2:2454
+4223:0:2969
+4224:2:2466
+4225:0:2969
+4226:2:2467
+4227:0:2969
+4228:1:13
diff --git a/formal-model/urcu/result-standard-execution-nest/DEFINES b/formal-model/urcu/result-standard-execution-nest/DEFINES
new file mode 100644 (file)
index 0000000..150a83c
--- /dev/null
@@ -0,0 +1,17 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-standard-execution-nest/Makefile b/formal-model/urcu/result-standard-execution-nest/Makefile
new file mode 100644 (file)
index 0000000..8af320d
--- /dev/null
@@ -0,0 +1,172 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       #nested useless with signal test.
+       #make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-standard-execution-nest/asserts.log b/formal-model/urcu/result-standard-execution-nest/asserts.log
new file mode 100644 (file)
index 0000000..51f1ac0
--- /dev/null
@@ -0,0 +1,250 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+Depth=    3212 States=    1e+06 Transitions= 1.17e+07 Memory=   519.572        t=   7.66 R=   1e+05
+Depth=    3212 States=    2e+06 Transitions= 2.38e+07 Memory=   572.990        t=     16 R=   1e+05
+Depth=    3212 States=    3e+06 Transitions= 3.62e+07 Memory=   626.408        t=   24.9 R=   1e+05
+pan: resizing hashtable to -w22..  done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             - (none specified)
+       assertion violations    +
+       cycle checks            - (disabled by -DSAFETY)
+       invalid end states      +
+
+State-vector 48 byte, depth reached 3212, errors: 0
+  3539988 states, stored
+ 39085459 states, matched
+ 42625447 transitions (= stored+matched)
+1.5602888e+08 atomic steps
+hash conflicts:  28971442 (resolved)
+
+Stats on memory usage (in Megabytes):
+  256.576      equivalent memory usage for states (stored*(State-vector + overhead))
+  196.718      actual memory usage for states (compression: 76.67%)
+               state-vector as stored = 30 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  686.338      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, ".input.spin", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 61, "(1)"
+       line 417, ".input.spin", state 91, "(1)"
+       line 398, ".input.spin", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 151, "(1)"
+       line 417, ".input.spin", state 181, "(1)"
+       line 398, ".input.spin", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 242, "(1)"
+       line 417, ".input.spin", state 272, "(1)"
+       line 398, ".input.spin", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 360, "(1)"
+       line 417, ".input.spin", state 390, "(1)"
+       line 539, ".input.spin", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 398, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 59, "(1)"
+       line 412, ".input.spin", state 72, "(1)"
+       line 417, ".input.spin", state 89, "(1)"
+       line 398, ".input.spin", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 153, "(1)"
+       line 412, ".input.spin", state 166, "(1)"
+       line 651, ".input.spin", state 199, "(1)"
+       line 174, ".input.spin", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 240, "(1)"
+       line 163, ".input.spin", state 248, "(1)"
+       line 167, ".input.spin", state 260, "(1)"
+       line 174, ".input.spin", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 303, "(1)"
+       line 163, ".input.spin", state 311, "(1)"
+       line 167, ".input.spin", state 323, "(1)"
+       line 174, ".input.spin", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 370, "(1)"
+       line 163, ".input.spin", state 378, "(1)"
+       line 167, ".input.spin", state 390, "(1)"
+       line 398, ".input.spin", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 449, "(1)"
+       line 412, ".input.spin", state 462, "(1)"
+       line 417, ".input.spin", state 479, "(1)"
+       line 398, ".input.spin", state 498, "(1)"
+       line 402, ".input.spin", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 554, "(1)"
+       line 417, ".input.spin", state 571, "(1)"
+       line 402, ".input.spin", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 647, "(1)"
+       line 417, ".input.spin", state 664, "(1)"
+       line 178, ".input.spin", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 710, "(1)"
+       line 163, ".input.spin", state 718, "(1)"
+       line 167, ".input.spin", state 730, "(1)"
+       line 174, ".input.spin", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 773, "(1)"
+       line 163, ".input.spin", state 781, "(1)"
+       line 167, ".input.spin", state 793, "(1)"
+       line 174, ".input.spin", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 840, "(1)"
+       line 163, ".input.spin", state 848, "(1)"
+       line 167, ".input.spin", state 860, "(1)"
+       line 398, ".input.spin", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, ".input.spin", state 884, "(1)"
+       line 398, ".input.spin", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, ".input.spin", state 885, "else"
+       line 398, ".input.spin", state 888, "(1)"
+       line 402, ".input.spin", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 898, "(1)"
+       line 402, ".input.spin", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, ".input.spin", state 899, "else"
+       line 402, ".input.spin", state 902, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 400, ".input.spin", state 908, "((i<1))"
+       line 400, ".input.spin", state 908, "((i>=1))"
+       line 407, ".input.spin", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 927, "(1)"
+       line 408, ".input.spin", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, ".input.spin", state 928, "else"
+       line 408, ".input.spin", state 931, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 412, ".input.spin", state 940, "(1)"
+       line 412, ".input.spin", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, ".input.spin", state 941, "else"
+       line 412, ".input.spin", state 944, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 410, ".input.spin", state 950, "((i<1))"
+       line 410, ".input.spin", state 950, "((i>=1))"
+       line 417, ".input.spin", state 957, "(1)"
+       line 417, ".input.spin", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, ".input.spin", state 958, "else"
+       line 417, ".input.spin", state 961, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 402, ".input.spin", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1040, "(1)"
+       line 417, ".input.spin", state 1057, "(1)"
+       line 402, ".input.spin", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1130, "(1)"
+       line 417, ".input.spin", state 1147, "(1)"
+       line 398, ".input.spin", state 1166, "(1)"
+       line 402, ".input.spin", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1222, "(1)"
+       line 417, ".input.spin", state 1239, "(1)"
+       line 402, ".input.spin", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1315, "(1)"
+       line 417, ".input.spin", state 1332, "(1)"
+       line 178, ".input.spin", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1378, "(1)"
+       line 163, ".input.spin", state 1386, "(1)"
+       line 167, ".input.spin", state 1398, "(1)"
+       line 174, ".input.spin", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1441, "(1)"
+       line 163, ".input.spin", state 1449, "(1)"
+       line 167, ".input.spin", state 1461, "(1)"
+       line 174, ".input.spin", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1508, "(1)"
+       line 163, ".input.spin", state 1516, "(1)"
+       line 167, ".input.spin", state 1528, "(1)"
+       line 398, ".input.spin", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, ".input.spin", state 1552, "(1)"
+       line 398, ".input.spin", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, ".input.spin", state 1553, "else"
+       line 398, ".input.spin", state 1556, "(1)"
+       line 402, ".input.spin", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 1566, "(1)"
+       line 402, ".input.spin", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, ".input.spin", state 1567, "else"
+       line 402, ".input.spin", state 1570, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 400, ".input.spin", state 1576, "((i<1))"
+       line 400, ".input.spin", state 1576, "((i>=1))"
+       line 407, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 1595, "(1)"
+       line 408, ".input.spin", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, ".input.spin", state 1596, "else"
+       line 408, ".input.spin", state 1599, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 412, ".input.spin", state 1608, "(1)"
+       line 412, ".input.spin", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, ".input.spin", state 1609, "else"
+       line 412, ".input.spin", state 1612, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 410, ".input.spin", state 1618, "((i<1))"
+       line 410, ".input.spin", state 1618, "((i>=1))"
+       line 417, ".input.spin", state 1625, "(1)"
+       line 417, ".input.spin", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, ".input.spin", state 1626, "else"
+       line 417, ".input.spin", state 1629, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 178, ".input.spin", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1681, "(1)"
+       line 163, ".input.spin", state 1689, "(1)"
+       line 167, ".input.spin", state 1701, "(1)"
+       line 174, ".input.spin", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1744, "(1)"
+       line 163, ".input.spin", state 1752, "(1)"
+       line 167, ".input.spin", state 1764, "(1)"
+       line 174, ".input.spin", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1811, "(1)"
+       line 163, ".input.spin", state 1819, "(1)"
+       line 167, ".input.spin", state 1831, "(1)"
+       line 701, ".input.spin", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+
+pan: elapsed time 29.8 seconds
+pan: rate 118871.32 states/second
+pan: avg transition delay 6.9864e-07 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/asserts.spin.input b/formal-model/urcu/result-standard-execution-nest/asserts.spin.input
new file mode 100644 (file)
index 0000000..f2f00e4
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/asserts.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu.sh b/formal-model/urcu/result-standard-execution-nest/urcu.sh
new file mode 100644 (file)
index 0000000..65ff517
--- /dev/null
@@ -0,0 +1,29 @@
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+#               Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+#          Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu.spin b/formal-model/urcu/result-standard-execution-nest/urcu.spin
new file mode 100644 (file)
index 0000000..2cfcb70
--- /dev/null
@@ -0,0 +1,705 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free.log b/formal-model/urcu/result-standard-execution-nest/urcu_free.log
new file mode 100644 (file)
index 0000000..884b15e
--- /dev/null
@@ -0,0 +1,262 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 743)
+Depth=    3880 States=    1e+06 Transitions= 1.18e+07 Memory=   527.190        t=   9.53 R=   1e+05
+Depth=    3880 States=    2e+06 Transitions= 2.39e+07 Memory=   588.225        t=   19.8 R=   1e+05
+Depth=    3880 States=    3e+06 Transitions= 3.61e+07 Memory=   649.260        t=   30.5 R=   1e+05
+pan: resizing hashtable to -w22..  done
+Depth=    3880 States=    4e+06 Transitions= 4.84e+07 Memory=   741.318        t=   41.1 R=   1e+05
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3880, errors: 0
+  4015564 states, stored
+ 44539121 states, matched
+ 48554685 transitions (= stored+matched)
+1.7777933e+08 atomic steps
+hash conflicts:  33629695 (resolved)
+
+Stats on memory usage (in Megabytes):
+  321.681      equivalent memory usage for states (stored*(State-vector + overhead))
+  252.629      actual memory usage for states (compression: 78.53%)
+               state-vector as stored = 38 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  742.295      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 61, "(1)"
+       line 417, "pan.___", state 91, "(1)"
+       line 398, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 151, "(1)"
+       line 417, "pan.___", state 181, "(1)"
+       line 398, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 242, "(1)"
+       line 417, "pan.___", state 272, "(1)"
+       line 398, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 360, "(1)"
+       line 417, "pan.___", state 390, "(1)"
+       line 539, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 412, "pan.___", state 72, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 153, "(1)"
+       line 412, "pan.___", state 166, "(1)"
+       line 651, "pan.___", state 199, "(1)"
+       line 174, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 240, "(1)"
+       line 163, "pan.___", state 248, "(1)"
+       line 167, "pan.___", state 260, "(1)"
+       line 174, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 303, "(1)"
+       line 163, "pan.___", state 311, "(1)"
+       line 167, "pan.___", state 323, "(1)"
+       line 174, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 370, "(1)"
+       line 163, "pan.___", state 378, "(1)"
+       line 167, "pan.___", state 390, "(1)"
+       line 398, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 449, "(1)"
+       line 412, "pan.___", state 462, "(1)"
+       line 417, "pan.___", state 479, "(1)"
+       line 398, "pan.___", state 498, "(1)"
+       line 402, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 554, "(1)"
+       line 417, "pan.___", state 571, "(1)"
+       line 402, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 647, "(1)"
+       line 417, "pan.___", state 664, "(1)"
+       line 178, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 710, "(1)"
+       line 163, "pan.___", state 718, "(1)"
+       line 167, "pan.___", state 730, "(1)"
+       line 174, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 773, "(1)"
+       line 163, "pan.___", state 781, "(1)"
+       line 167, "pan.___", state 793, "(1)"
+       line 174, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 840, "(1)"
+       line 163, "pan.___", state 848, "(1)"
+       line 167, "pan.___", state 860, "(1)"
+       line 398, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, "pan.___", state 884, "(1)"
+       line 398, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, "pan.___", state 885, "else"
+       line 398, "pan.___", state 888, "(1)"
+       line 402, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, "pan.___", state 899, "else"
+       line 402, "pan.___", state 902, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 400, "pan.___", state 908, "((i<1))"
+       line 400, "pan.___", state 908, "((i>=1))"
+       line 407, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 927, "(1)"
+       line 408, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, "pan.___", state 928, "else"
+       line 408, "pan.___", state 931, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 412, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, "pan.___", state 941, "else"
+       line 412, "pan.___", state 944, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 410, "pan.___", state 950, "((i<1))"
+       line 410, "pan.___", state 950, "((i>=1))"
+       line 417, "pan.___", state 957, "(1)"
+       line 417, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, "pan.___", state 958, "else"
+       line 417, "pan.___", state 961, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 402, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1040, "(1)"
+       line 417, "pan.___", state 1057, "(1)"
+       line 402, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1130, "(1)"
+       line 417, "pan.___", state 1147, "(1)"
+       line 398, "pan.___", state 1166, "(1)"
+       line 402, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1222, "(1)"
+       line 417, "pan.___", state 1239, "(1)"
+       line 402, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1315, "(1)"
+       line 417, "pan.___", state 1332, "(1)"
+       line 178, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1378, "(1)"
+       line 163, "pan.___", state 1386, "(1)"
+       line 167, "pan.___", state 1398, "(1)"
+       line 174, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1441, "(1)"
+       line 163, "pan.___", state 1449, "(1)"
+       line 167, "pan.___", state 1461, "(1)"
+       line 174, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1508, "(1)"
+       line 163, "pan.___", state 1516, "(1)"
+       line 167, "pan.___", state 1528, "(1)"
+       line 398, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, "pan.___", state 1552, "(1)"
+       line 398, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, "pan.___", state 1553, "else"
+       line 398, "pan.___", state 1556, "(1)"
+       line 402, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 1566, "(1)"
+       line 402, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, "pan.___", state 1567, "else"
+       line 402, "pan.___", state 1570, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 400, "pan.___", state 1576, "((i<1))"
+       line 400, "pan.___", state 1576, "((i>=1))"
+       line 407, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1595, "(1)"
+       line 408, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, "pan.___", state 1596, "else"
+       line 408, "pan.___", state 1599, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 412, "pan.___", state 1608, "(1)"
+       line 412, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, "pan.___", state 1609, "else"
+       line 412, "pan.___", state 1612, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 410, "pan.___", state 1618, "((i<1))"
+       line 410, "pan.___", state 1618, "((i>=1))"
+       line 417, "pan.___", state 1625, "(1)"
+       line 417, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, "pan.___", state 1626, "else"
+       line 417, "pan.___", state 1629, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 178, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1681, "(1)"
+       line 163, "pan.___", state 1689, "(1)"
+       line 167, "pan.___", state 1701, "(1)"
+       line 174, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1744, "(1)"
+       line 163, "pan.___", state 1752, "(1)"
+       line 167, "pan.___", state 1764, "(1)"
+       line 174, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1811, "(1)"
+       line 163, "pan.___", state 1819, "(1)"
+       line 167, "pan.___", state 1831, "(1)"
+       line 701, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 748, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 41.3 seconds
+pan: rate 97205.616 states/second
+pan: avg transition delay 8.5079e-07 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free.ltl b/formal-model/urcu/result-standard-execution-nest/urcu_free.ltl
new file mode 100644 (file)
index 0000000..1954414
--- /dev/null
@@ -0,0 +1 @@
+[] (read_free -> !read_free_race)
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input
new file mode 100644 (file)
index 0000000..f2f00e4
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_free.spin.input.trail
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index 0000000..837f3d9
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.define b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.define
new file mode 100644 (file)
index 0000000..136ef67
--- /dev/null
@@ -0,0 +1,2 @@
+#define NO_RMB
+#define NO_WMB
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.log b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.log
new file mode 100644 (file)
index 0000000..27a963a
--- /dev/null
@@ -0,0 +1,267 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+Depth=   11386 States=    1e+06 Transitions= 1.56e+07 Memory=   527.287        t=   12.8 R=   8e+04
+pan: claim violated! (at depth 2146)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 72 byte, depth reached 11386, errors: 1
+  1223588 states, stored
+ 17987399 states, matched
+ 19210987 transitions (= stored+matched)
+ 70012127 atomic steps
+hash conflicts:   4173157 (resolved)
+
+Stats on memory usage (in Megabytes):
+  116.690      equivalent memory usage for states (stored*(State-vector + overhead))
+   75.177      actual memory usage for states (compression: 64.42%)
+               state-vector as stored = 36 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  540.861      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 151, "(1)"
+       line 419, "pan.___", state 181, "(1)"
+       line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 242, "(1)"
+       line 419, "pan.___", state 272, "(1)"
+       line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 331, "(1)"
+       line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 360, "(1)"
+       line 419, "pan.___", state 390, "(1)"
+       line 541, "pan.___", state 414, "-end-"
+       (18 of 414 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 410, "pan.___", state 153, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 400, "pan.___", state 209, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 223, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 254, "(1)"
+       line 414, "pan.___", state 267, "(1)"
+       line 400, "pan.___", state 300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 314, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 345, "(1)"
+       line 414, "pan.___", state 358, "(1)"
+       line 400, "pan.___", state 395, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 409, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 440, "(1)"
+       line 414, "pan.___", state 453, "(1)"
+       line 400, "pan.___", state 488, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 533, "(1)"
+       line 414, "pan.___", state 546, "(1)"
+       line 400, "pan.___", state 582, "(1)"
+       line 404, "pan.___", state 594, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 638, "(1)"
+       line 404, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 731, "(1)"
+       line 404, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 821, "(1)"
+       line 419, "pan.___", state 838, "(1)"
+       line 404, "pan.___", state 868, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 886, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 912, "(1)"
+       line 419, "pan.___", state 929, "(1)"
+       line 404, "pan.___", state 963, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 981, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1007, "(1)"
+       line 419, "pan.___", state 1024, "(1)"
+       line 400, "pan.___", state 1050, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1053, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1053, "else"
+       line 400, "pan.___", state 1056, "(1)"
+       line 404, "pan.___", state 1064, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1066, "(1)"
+       line 404, "pan.___", state 1067, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1067, "else"
+       line 404, "pan.___", state 1070, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 402, "pan.___", state 1076, "((i<1))"
+       line 402, "pan.___", state 1076, "((i>=1))"
+       line 409, "pan.___", state 1082, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1095, "(1)"
+       line 410, "pan.___", state 1096, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1096, "else"
+       line 410, "pan.___", state 1099, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 414, "pan.___", state 1108, "(1)"
+       line 414, "pan.___", state 1109, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1109, "else"
+       line 414, "pan.___", state 1112, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 412, "pan.___", state 1118, "((i<1))"
+       line 412, "pan.___", state 1118, "((i>=1))"
+       line 419, "pan.___", state 1125, "(1)"
+       line 419, "pan.___", state 1126, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1126, "else"
+       line 419, "pan.___", state 1129, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 404, "pan.___", state 1164, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1208, "(1)"
+       line 404, "pan.___", state 1254, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1298, "(1)"
+       line 400, "pan.___", state 1334, "(1)"
+       line 404, "pan.___", state 1346, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1390, "(1)"
+       line 404, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1483, "(1)"
+       line 404, "pan.___", state 1529, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1547, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1573, "(1)"
+       line 419, "pan.___", state 1590, "(1)"
+       line 404, "pan.___", state 1620, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1638, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1664, "(1)"
+       line 419, "pan.___", state 1681, "(1)"
+       line 404, "pan.___", state 1715, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1733, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1759, "(1)"
+       line 419, "pan.___", state 1776, "(1)"
+       line 400, "pan.___", state 1802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1804, "(1)"
+       line 400, "pan.___", state 1805, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1805, "else"
+       line 400, "pan.___", state 1808, "(1)"
+       line 404, "pan.___", state 1816, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1818, "(1)"
+       line 404, "pan.___", state 1819, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1819, "else"
+       line 404, "pan.___", state 1822, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 402, "pan.___", state 1828, "((i<1))"
+       line 402, "pan.___", state 1828, "((i>=1))"
+       line 409, "pan.___", state 1834, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1847, "(1)"
+       line 410, "pan.___", state 1848, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1848, "else"
+       line 410, "pan.___", state 1851, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 414, "pan.___", state 1860, "(1)"
+       line 414, "pan.___", state 1861, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1861, "else"
+       line 414, "pan.___", state 1864, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 412, "pan.___", state 1870, "((i<1))"
+       line 412, "pan.___", state 1870, "((i>=1))"
+       line 419, "pan.___", state 1877, "(1)"
+       line 419, "pan.___", state 1878, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1878, "else"
+       line 419, "pan.___", state 1881, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 404, "pan.___", state 1916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1960, "(1)"
+       line 404, "pan.___", state 2007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 2051, "(1)"
+       line 404, "pan.___", state 2102, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 2146, "(1)"
+       line 703, "pan.___", state 2192, "-end-"
+       (144 of 2192 states)
+unreached in proctype :init:
+       line 710, "pan.___", state 9, "((j<2))"
+       line 710, "pan.___", state 9, "((j>=2))"
+       line 711, "pan.___", state 20, "((j<2))"
+       line 711, "pan.___", state 20, "((j>=2))"
+       line 716, "pan.___", state 33, "((j<2))"
+       line 716, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 750, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 15.9 seconds
+pan: rate 77100.693 states/second
+pan: avg transition delay 8.2609e-07 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input
new file mode 100644 (file)
index 0000000..927df3f
--- /dev/null
@@ -0,0 +1,724 @@
+#define NO_RMB
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_mb.spin.input.trail
new file mode 100644 (file)
index 0000000..04e7425
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.define b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.define
new file mode 100644 (file)
index 0000000..73e61a4
--- /dev/null
@@ -0,0 +1 @@
+#define NO_RMB
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.log b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.log
new file mode 100644 (file)
index 0000000..b7f3b80
--- /dev/null
@@ -0,0 +1,266 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+Depth=    5439 States=    1e+06 Transitions= 1.03e+07 Memory=   527.190        t=   8.16 R=   1e+05
+pan: claim violated! (at depth 1801)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 5439, errors: 1
+  1006552 states, stored
+  9396280 states, matched
+ 10402832 transitions (= stored+matched)
+ 36844262 atomic steps
+hash conflicts:   1832712 (resolved)
+
+Stats on memory usage (in Megabytes):
+   80.634      equivalent memory usage for states (stored*(State-vector + overhead))
+   61.871      actual memory usage for states (compression: 76.73%)
+               state-vector as stored = 36 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  527.580      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 243, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 265, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 291, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 304, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 320, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 334, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 352, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 365, "(1)"
+       line 413, "pan.___", state 378, "(1)"
+       line 418, "pan.___", state 395, "(1)"
+       line 399, "pan.___", state 414, "(1)"
+       line 403, "pan.___", state 426, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 444, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 470, "(1)"
+       line 418, "pan.___", state 487, "(1)"
+       line 403, "pan.___", state 519, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 537, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 563, "(1)"
+       line 418, "pan.___", state 580, "(1)"
+       line 179, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 629, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 651, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 677, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 690, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 714, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 716, "(1)"
+       line 399, "pan.___", state 717, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 717, "else"
+       line 399, "pan.___", state 720, "(1)"
+       line 403, "pan.___", state 728, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 730, "(1)"
+       line 403, "pan.___", state 731, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 731, "else"
+       line 403, "pan.___", state 734, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 401, "pan.___", state 740, "((i<1))"
+       line 401, "pan.___", state 740, "((i>=1))"
+       line 408, "pan.___", state 746, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 759, "(1)"
+       line 409, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 760, "else"
+       line 409, "pan.___", state 763, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 413, "pan.___", state 772, "(1)"
+       line 413, "pan.___", state 773, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 773, "else"
+       line 413, "pan.___", state 776, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 411, "pan.___", state 782, "((i<1))"
+       line 411, "pan.___", state 782, "((i>=1))"
+       line 418, "pan.___", state 789, "(1)"
+       line 418, "pan.___", state 790, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 790, "else"
+       line 418, "pan.___", state 793, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 403, "pan.___", state 828, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 846, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 872, "(1)"
+       line 418, "pan.___", state 889, "(1)"
+       line 403, "pan.___", state 918, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 936, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 979, "(1)"
+       line 399, "pan.___", state 998, "(1)"
+       line 403, "pan.___", state 1010, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1028, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1054, "(1)"
+       line 418, "pan.___", state 1071, "(1)"
+       line 403, "pan.___", state 1103, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1121, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1147, "(1)"
+       line 418, "pan.___", state 1164, "(1)"
+       line 179, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1200, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 1213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1235, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1252, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1261, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1300, "(1)"
+       line 399, "pan.___", state 1301, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1301, "else"
+       line 399, "pan.___", state 1304, "(1)"
+       line 403, "pan.___", state 1312, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1314, "(1)"
+       line 403, "pan.___", state 1315, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1315, "else"
+       line 403, "pan.___", state 1318, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 401, "pan.___", state 1324, "((i<1))"
+       line 401, "pan.___", state 1324, "((i>=1))"
+       line 408, "pan.___", state 1330, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1343, "(1)"
+       line 409, "pan.___", state 1344, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1344, "else"
+       line 409, "pan.___", state 1347, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 413, "pan.___", state 1356, "(1)"
+       line 413, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1357, "else"
+       line 413, "pan.___", state 1360, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 411, "pan.___", state 1366, "((i<1))"
+       line 411, "pan.___", state 1366, "((i>=1))"
+       line 418, "pan.___", state 1373, "(1)"
+       line 418, "pan.___", state 1374, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1374, "else"
+       line 418, "pan.___", state 1377, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 179, "pan.___", state 1406, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1419, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1454, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1471, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1480, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1493, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 702, "pan.___", state 1520, "-end-"
+       (144 of 1520 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 8.24 seconds
+pan: rate 122154.37 states/second
+pan: avg transition delay 7.9209e-07 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input
new file mode 100644 (file)
index 0000000..6dea6e1
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_RMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_rmb.spin.input.trail
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.define b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.define
new file mode 100644 (file)
index 0000000..710f29d
--- /dev/null
@@ -0,0 +1 @@
+#define NO_WMB
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.log b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.log
new file mode 100644 (file)
index 0000000..4dd3892
--- /dev/null
@@ -0,0 +1,294 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+pan: claim violated! (at depth 1882)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 4174, errors: 1
+   367189 states, stored
+  3431533 states, matched
+  3798722 transitions (= stored+matched)
+ 13407384 atomic steps
+hash conflicts:    253700 (resolved)
+
+Stats on memory usage (in Megabytes):
+   29.415      equivalent memory usage for states (stored*(State-vector + overhead))
+   22.811      actual memory usage for states (compression: 77.55%)
+               state-vector as stored = 37 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  488.518      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 331, "(1)"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (18 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 401, "pan.___", state 134, "((i<1))"
+       line 401, "pan.___", state 134, "((i>=1))"
+       line 409, "pan.___", state 153, "(1)"
+       line 409, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 154, "else"
+       line 409, "pan.___", state 157, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 413, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 167, "else"
+       line 413, "pan.___", state 170, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 411, "pan.___", state 176, "((i<1))"
+       line 411, "pan.___", state 176, "((i>=1))"
+       line 418, "pan.___", state 183, "(1)"
+       line 418, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 184, "else"
+       line 418, "pan.___", state 187, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 369, "pan.___", state 193, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 646, "pan.___", state 202, "((write_lock==0))"
+       line 646, "pan.___", state 202, "else"
+       line 644, "pan.___", state 203, "(1)"
+       line 160, "pan.___", state 209, "(1)"
+       line 164, "pan.___", state 217, "(1)"
+       line 164, "pan.___", state 218, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 164, "pan.___", state 218, "else"
+       line 162, "pan.___", state 223, "((j<1))"
+       line 162, "pan.___", state 223, "((j>=1))"
+       line 168, "pan.___", state 229, "(1)"
+       line 168, "pan.___", state 230, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 168, "pan.___", state 230, "else"
+       line 160, "pan.___", state 241, "(1)"
+       line 168, "pan.___", state 261, "(1)"
+       line 160, "pan.___", state 277, "(1)"
+       line 164, "pan.___", state 285, "(1)"
+       line 168, "pan.___", state 297, "(1)"
+       line 399, "pan.___", state 311, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 325, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 343, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 356, "(1)"
+       line 413, "pan.___", state 369, "(1)"
+       line 418, "pan.___", state 386, "(1)"
+       line 399, "pan.___", state 405, "(1)"
+       line 403, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 461, "(1)"
+       line 418, "pan.___", state 478, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 164, "pan.___", state 594, "(1)"
+       line 168, "pan.___", state 606, "(1)"
+       line 160, "pan.___", state 618, "(1)"
+       line 168, "pan.___", state 638, "(1)"
+       line 164, "pan.___", state 662, "(1)"
+       line 168, "pan.___", state 674, "(1)"
+       line 399, "pan.___", state 696, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 698, "(1)"
+       line 399, "pan.___", state 699, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 699, "else"
+       line 399, "pan.___", state 702, "(1)"
+       line 403, "pan.___", state 710, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 712, "(1)"
+       line 403, "pan.___", state 713, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 713, "else"
+       line 403, "pan.___", state 716, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 401, "pan.___", state 722, "((i<1))"
+       line 401, "pan.___", state 722, "((i>=1))"
+       line 408, "pan.___", state 728, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 741, "(1)"
+       line 409, "pan.___", state 742, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 742, "else"
+       line 409, "pan.___", state 745, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 413, "pan.___", state 754, "(1)"
+       line 413, "pan.___", state 755, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 755, "else"
+       line 413, "pan.___", state 758, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 411, "pan.___", state 764, "((i<1))"
+       line 411, "pan.___", state 764, "((i>=1))"
+       line 418, "pan.___", state 771, "(1)"
+       line 418, "pan.___", state 772, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 772, "else"
+       line 418, "pan.___", state 775, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 403, "pan.___", state 810, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 828, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 854, "(1)"
+       line 418, "pan.___", state 871, "(1)"
+       line 403, "pan.___", state 900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 918, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 944, "(1)"
+       line 418, "pan.___", state 961, "(1)"
+       line 399, "pan.___", state 980, "(1)"
+       line 403, "pan.___", state 992, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1010, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1036, "(1)"
+       line 418, "pan.___", state 1053, "(1)"
+       line 403, "pan.___", state 1085, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1103, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1129, "(1)"
+       line 418, "pan.___", state 1146, "(1)"
+       line 164, "pan.___", state 1169, "(1)"
+       line 168, "pan.___", state 1181, "(1)"
+       line 160, "pan.___", state 1193, "(1)"
+       line 168, "pan.___", state 1213, "(1)"
+       line 164, "pan.___", state 1237, "(1)"
+       line 168, "pan.___", state 1249, "(1)"
+       line 399, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1273, "(1)"
+       line 399, "pan.___", state 1274, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1274, "else"
+       line 399, "pan.___", state 1277, "(1)"
+       line 403, "pan.___", state 1285, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1287, "(1)"
+       line 403, "pan.___", state 1288, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1288, "else"
+       line 403, "pan.___", state 1291, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 401, "pan.___", state 1297, "((i<1))"
+       line 401, "pan.___", state 1297, "((i>=1))"
+       line 408, "pan.___", state 1303, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1316, "(1)"
+       line 409, "pan.___", state 1317, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1317, "else"
+       line 409, "pan.___", state 1320, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 413, "pan.___", state 1329, "(1)"
+       line 413, "pan.___", state 1330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1330, "else"
+       line 413, "pan.___", state 1333, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 411, "pan.___", state 1339, "((i<1))"
+       line 411, "pan.___", state 1339, "((i>=1))"
+       line 418, "pan.___", state 1346, "(1)"
+       line 418, "pan.___", state 1347, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1347, "else"
+       line 418, "pan.___", state 1350, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 164, "pan.___", state 1379, "(1)"
+       line 168, "pan.___", state 1391, "(1)"
+       line 160, "pan.___", state 1403, "(1)"
+       line 168, "pan.___", state 1423, "(1)"
+       line 164, "pan.___", state 1447, "(1)"
+       line 168, "pan.___", state 1459, "(1)"
+       line 702, "pan.___", state 1484, "-end-"
+       (160 of 1484 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 2.96 seconds
+pan: rate 124050.34 states/second
+pan: avg transition delay 7.7921e-07 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input
new file mode 100644 (file)
index 0000000..f4d8acb
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_free_no_wmb.spin.input.trail
new file mode 100644 (file)
index 0000000..f73a838
--- /dev/null
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.define b/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.define
new file mode 100644 (file)
index 0000000..5e642ef
--- /dev/null
@@ -0,0 +1 @@
+#define SINGLE_FLIP
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.log b/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.log
new file mode 100644 (file)
index 0000000..2a80112
--- /dev/null
@@ -0,0 +1,197 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+pan: claim violated! (at depth 1371)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3387, errors: 1
+   206295 states, stored
+  1902753 states, matched
+  2109048 transitions (= stored+matched)
+  7663223 atomic steps
+hash conflicts:    101109 (resolved)
+
+Stats on memory usage (in Megabytes):
+   16.526      equivalent memory usage for states (stored*(State-vector + overhead))
+   13.080      actual memory usage for states (compression: 79.15%)
+               state-vector as stored = 38 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  478.752      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 179, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1003, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1013, "(1)"
+       line 164, "pan.___", state 1021, "(1)"
+       line 168, "pan.___", state 1033, "(1)"
+       line 175, "pan.___", state 1044, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1066, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1076, "(1)"
+       line 164, "pan.___", state 1084, "(1)"
+       line 168, "pan.___", state 1096, "(1)"
+       line 175, "pan.___", state 1111, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1133, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1143, "(1)"
+       line 164, "pan.___", state 1151, "(1)"
+       line 168, "pan.___", state 1163, "(1)"
+       line 702, "pan.___", state 1188, "-end-"
+       (100 of 1188 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 1.66 seconds
+pan: rate  124274.1 states/second
+pan: avg transition delay 7.8708e-07 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input
new file mode 100644 (file)
index 0000000..93aae44
--- /dev/null
@@ -0,0 +1,723 @@
+#define SINGLE_FLIP
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_free_single_flip.spin.input.trail
new file mode 100644 (file)
index 0000000..73c1400
--- /dev/null
@@ -0,0 +1,1374 @@
+-2:3:-2
+-4:-4:-4
+1:0:1650
+2:3:1602
+3:3:1605
+4:3:1605
+5:3:1608
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+26:2:428
+27:2:429
+28:2:437
+29:2:438
+30:2:442
+31:2:443
+32:2:451
+33:2:456
+34:2:460
+35:2:461
+36:2:468
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+41:2:493
+42:2:498
+43:2:499
+44:0:1650
+45:2:511
+46:0:1650
+47:2:513
+48:2:514
+49:0:1650
+50:2:518
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress.ltl b/formal-model/urcu/result-standard-execution-nest/urcu_progress.ltl
new file mode 100644 (file)
index 0000000..8718641
--- /dev/null
@@ -0,0 +1 @@
+([] <> !np_)
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.define b/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.define
new file mode 100644 (file)
index 0000000..ff3f783
--- /dev/null
@@ -0,0 +1 @@
+#define READER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.log b/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.log
new file mode 100644 (file)
index 0000000..9e98b9f
--- /dev/null
@@ -0,0 +1,275 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 1767: Claim reached state 9 (line 748)
+Depth=    3880 States=    1e+06 Transitions= 1.71e+07 Memory=   499.651        t=   14.5 R=   7e+04
+Depth=    3880 States=    2e+06 Transitions= 3.79e+07 Memory=   532.365        t=   32.3 R=   6e+04
+Depth=    3880 States=    3e+06 Transitions= 5.83e+07 Memory=   564.983        t=   50.2 R=   6e+04
+pan: resizing hashtable to -w22..  done
+Depth=    3880 States=    4e+06 Transitions= 7.76e+07 Memory=   629.307        t=     67 R=   6e+04
+Depth=    3880 States=    5e+06 Transitions= 9.78e+07 Memory=   662.315        t=   84.2 R=   6e+04
+Depth=    3880 States=    6e+06 Transitions= 1.19e+08 Memory=   694.736        t=    102 R=   6e+04
+Depth=    3880 States=    7e+06 Transitions= 1.38e+08 Memory=   727.842        t=    119 R=   6e+04
+Depth=    3880 States=    8e+06 Transitions= 1.59e+08 Memory=   760.752        t=    137 R=   6e+04
+Depth=    3880 States=    9e+06 Transitions= 1.79e+08 Memory=   793.174        t=    155 R=   6e+04
+pan: resizing hashtable to -w24..  done
+Depth=    3880 States=    1e+07 Transitions= 1.98e+08 Memory=   950.568        t=    172 R=   6e+04
+Depth=    3880 States=  1.1e+07 Transitions= 2.19e+08 Memory=   983.479        t=    189 R=   6e+04
+Depth=    3880 States=  1.2e+07 Transitions=  2.4e+08 Memory=  1015.901        t=    207 R=   6e+04
+Depth=    3880 States=  1.3e+07 Transitions= 2.58e+08 Memory=  1049.397        t=    223 R=   6e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3880, errors: 0
+  7197860 states, stored (1.33457e+07 visited)
+2.5266654e+08 states, matched
+2.6601223e+08 transitions (= visited+matched)
+9.9067284e+08 atomic steps
+hash conflicts:  87783920 (resolved)
+
+Stats on memory usage (in Megabytes):
+  576.611      equivalent memory usage for states (stored*(State-vector + overhead))
+  474.839      actual memory usage for states (compression: 82.35%)
+               state-vector as stored = 41 byte + 28 byte overhead
+  128.000      memory used for hash table (-w24)
+  457.764      memory used for DFS stack (-m10000000)
+ 1060.529      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 230 seconds
+pan: rate  58151.15 states/second
+pan: avg transition delay 8.6274e-07 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input
new file mode 100644 (file)
index 0000000..4b3d02e
--- /dev/null
@@ -0,0 +1,723 @@
+#define READER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_progress_reader.spin.input.trail
new file mode 100644 (file)
index 0000000..7c42af1
--- /dev/null
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+-1:-1:-1
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diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.define b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.define
new file mode 100644 (file)
index 0000000..1e4417f
--- /dev/null
@@ -0,0 +1 @@
+#define WRITER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.log b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.log
new file mode 100644 (file)
index 0000000..434151a
--- /dev/null
@@ -0,0 +1,275 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 291: Claim reached state 9 (line 748)
+Depth=    2677 States=    1e+06 Transitions= 1.57e+07 Memory=   487.932        t=   13.4 R=   7e+04
+Depth=    3023 States=    2e+06 Transitions= 3.19e+07 Memory=   509.709        t=   27.3 R=   7e+04
+Depth=    3610 States=    3e+06 Transitions= 4.84e+07 Memory=   531.486        t=   41.6 R=   7e+04
+pan: resizing hashtable to -w22..  done
+Depth=    3956 States=    4e+06 Transitions= 6.63e+07 Memory=   595.029        t=     57 R=   7e+04
+Depth=    3956 States=    5e+06 Transitions= 8.67e+07 Memory=   617.783        t=   74.5 R=   7e+04
+Depth=    3956 States=    6e+06 Transitions= 1.08e+08 Memory=   660.850        t=     93 R=   6e+04
+Depth=    3956 States=    7e+06 Transitions= 1.28e+08 Memory=   690.928        t=    110 R=   6e+04
+Depth=    3956 States=    8e+06 Transitions= 1.51e+08 Memory=   729.600        t=    129 R=   6e+04
+Depth=    3956 States=    9e+06 Transitions=  1.7e+08 Memory=   765.830        t=    146 R=   6e+04
+pan: resizing hashtable to -w24..  done
+Depth=    3956 States=    1e+07 Transitions= 1.92e+08 Memory=   919.611        t=    166 R=   6e+04
+Depth=    3956 States=  1.1e+07 Transitions= 2.13e+08 Memory=   958.576        t=    183 R=   6e+04
+Depth=    3956 States=  1.2e+07 Transitions= 2.33e+08 Memory=   985.627        t=    201 R=   6e+04
+Depth=    3956 States=  1.3e+07 Transitions= 2.55e+08 Memory=  1027.033        t=    220 R=   6e+04
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3956, errors: 0
+  7045896 states, stored (1.35792e+07 visited)
+2.5326206e+08 states, matched
+2.668413e+08 transitions (= visited+matched)
+9.9425626e+08 atomic steps
+hash conflicts:  65494104 (resolved)
+
+Stats on memory usage (in Megabytes):
+  564.437      equivalent memory usage for states (stored*(State-vector + overhead))
+  465.758      actual memory usage for states (compression: 82.52%)
+               state-vector as stored = 41 byte + 28 byte overhead
+  128.000      memory used for hash table (-w24)
+  457.764      memory used for DFS stack (-m10000000)
+ 1051.350      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 230 seconds
+pan: rate 59137.889 states/second
+pan: avg transition delay 8.6051e-07 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input
new file mode 100644 (file)
index 0000000..575305f
--- /dev/null
@@ -0,0 +1,723 @@
+#define WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.define b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.define
new file mode 100644 (file)
index 0000000..8d304f5
--- /dev/null
@@ -0,0 +1,2 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.log b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.log
new file mode 100644 (file)
index 0000000..7fafb9e
--- /dev/null
@@ -0,0 +1,514 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+depth 15: Claim reached state 9 (line 750)
+depth 291: Claim reached state 9 (line 749)
+pan: acceptance cycle (at depth 4308)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 4820, errors: 1
+    62091 states, stored (169917 visited)
+  2179326 states, matched
+  2349243 transitions (= visited+matched)
+  8805349 atomic steps
+hash conflicts:     50953 (resolved)
+
+Stats on memory usage (in Megabytes):
+    4.974      equivalent memory usage for states (stored*(State-vector + overhead))
+    4.145      actual memory usage for states (compression: 83.33%)
+               state-vector as stored = 42 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  469.865      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 151, "(1)"
+       line 419, "pan.___", state 181, "(1)"
+       line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 242, "(1)"
+       line 419, "pan.___", state 272, "(1)"
+       line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 360, "(1)"
+       line 419, "pan.___", state 390, "(1)"
+       line 541, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 402, "pan.___", state 134, "((i<1))"
+       line 402, "pan.___", state 134, "((i>=1))"
+       line 410, "pan.___", state 153, "(1)"
+       line 410, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 154, "else"
+       line 410, "pan.___", state 157, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 414, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 167, "else"
+       line 414, "pan.___", state 170, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 412, "pan.___", state 176, "((i<1))"
+       line 412, "pan.___", state 176, "((i>=1))"
+       line 419, "pan.___", state 183, "(1)"
+       line 419, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 184, "else"
+       line 419, "pan.___", state 187, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 370, "pan.___", state 193, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 647, "pan.___", state 202, "((write_lock==0))"
+       line 647, "pan.___", state 202, "else"
+       line 645, "pan.___", state 203, "(1)"
+       line 176, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 225, "((j<1))"
+       line 178, "pan.___", state 225, "((j>=1))"
+       line 184, "pan.___", state 230, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 240, "(1)"
+       line 165, "pan.___", state 248, "(1)"
+       line 165, "pan.___", state 249, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 165, "pan.___", state 249, "else"
+       line 163, "pan.___", state 254, "((j<1))"
+       line 163, "pan.___", state 254, "((j>=1))"
+       line 169, "pan.___", state 260, "(1)"
+       line 169, "pan.___", state 261, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 169, "pan.___", state 261, "else"
+       line 171, "pan.___", state 264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 171, "pan.___", state 264, "else"
+       line 176, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 180, "pan.___", state 280, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 288, "((j<1))"
+       line 178, "pan.___", state 288, "((j>=1))"
+       line 184, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 303, "(1)"
+       line 165, "pan.___", state 311, "(1)"
+       line 165, "pan.___", state 312, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 165, "pan.___", state 312, "else"
+       line 163, "pan.___", state 317, "((j<1))"
+       line 163, "pan.___", state 317, "((j>=1))"
+       line 169, "pan.___", state 323, "(1)"
+       line 169, "pan.___", state 324, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 324, "else"
+       line 171, "pan.___", state 327, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 171, "pan.___", state 327, "else"
+       line 215, "pan.___", state 333, "((i<1))"
+       line 215, "pan.___", state 333, "((i>=1))"
+       line 176, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 355, "((j<1))"
+       line 178, "pan.___", state 355, "((j>=1))"
+       line 184, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 370, "(1)"
+       line 165, "pan.___", state 378, "(1)"
+       line 165, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 165, "pan.___", state 379, "else"
+       line 163, "pan.___", state 384, "((j<1))"
+       line 163, "pan.___", state 384, "((j>=1))"
+       line 169, "pan.___", state 390, "(1)"
+       line 169, "pan.___", state 391, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 169, "pan.___", state 391, "else"
+       line 171, "pan.___", state 394, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 171, "pan.___", state 394, "else"
+       line 400, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 410, "(1)"
+       line 404, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 424, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 402, "pan.___", state 430, "((i<1))"
+       line 402, "pan.___", state 430, "((i>=1))"
+       line 409, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 449, "(1)"
+       line 410, "pan.___", state 450, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 450, "else"
+       line 410, "pan.___", state 453, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 414, "pan.___", state 462, "(1)"
+       line 414, "pan.___", state 463, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 463, "else"
+       line 414, "pan.___", state 466, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 412, "pan.___", state 472, "((i<1))"
+       line 412, "pan.___", state 472, "((i>=1))"
+       line 419, "pan.___", state 479, "(1)"
+       line 419, "pan.___", state 480, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 480, "else"
+       line 419, "pan.___", state 483, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 370, "pan.___", state 489, "(1)"
+       line 662, "pan.___", state 492, "cached_urcu_gp_ctr.val[_pid] = (tmp^(1<<7))"
+       line 400, "pan.___", state 498, "(1)"
+       line 400, "pan.___", state 499, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 499, "else"
+       line 400, "pan.___", state 502, "(1)"
+       line 404, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 516, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 402, "pan.___", state 522, "((i<1))"
+       line 402, "pan.___", state 522, "((i>=1))"
+       line 409, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 541, "(1)"
+       line 410, "pan.___", state 542, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 542, "else"
+       line 410, "pan.___", state 545, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 414, "pan.___", state 554, "(1)"
+       line 414, "pan.___", state 555, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 555, "else"
+       line 414, "pan.___", state 558, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 412, "pan.___", state 564, "((i<1))"
+       line 412, "pan.___", state 564, "((i>=1))"
+       line 419, "pan.___", state 571, "(1)"
+       line 419, "pan.___", state 572, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 572, "else"
+       line 419, "pan.___", state 575, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 370, "pan.___", state 581, "(1)"
+       line 400, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 595, "(1)"
+       line 404, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 609, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 402, "pan.___", state 615, "((i<1))"
+       line 402, "pan.___", state 615, "((i>=1))"
+       line 409, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 634, "(1)"
+       line 410, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 635, "else"
+       line 410, "pan.___", state 638, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 414, "pan.___", state 647, "(1)"
+       line 414, "pan.___", state 648, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 648, "else"
+       line 414, "pan.___", state 651, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 412, "pan.___", state 657, "((i<1))"
+       line 412, "pan.___", state 657, "((i>=1))"
+       line 419, "pan.___", state 664, "(1)"
+       line 419, "pan.___", state 665, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 665, "else"
+       line 419, "pan.___", state 668, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 370, "pan.___", state 674, "(1)"
+       line 400, "pan.___", state 679, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 681, "(1)"
+       line 400, "pan.___", state 682, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 682, "else"
+       line 400, "pan.___", state 685, "(1)"
+       line 404, "pan.___", state 693, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 695, "(1)"
+       line 404, "pan.___", state 696, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 696, "else"
+       line 404, "pan.___", state 699, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 402, "pan.___", state 705, "((i<1))"
+       line 402, "pan.___", state 705, "((i>=1))"
+       line 409, "pan.___", state 711, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 724, "(1)"
+       line 410, "pan.___", state 725, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 725, "else"
+       line 410, "pan.___", state 728, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 414, "pan.___", state 737, "(1)"
+       line 414, "pan.___", state 738, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 738, "else"
+       line 414, "pan.___", state 741, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 412, "pan.___", state 747, "((i<1))"
+       line 412, "pan.___", state 747, "((i>=1))"
+       line 419, "pan.___", state 754, "(1)"
+       line 419, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 755, "else"
+       line 419, "pan.___", state 758, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 370, "pan.___", state 764, "(1)"
+       line 430, "pan.___", state 767, "(((tmp2&((1<<7)-1))&&((tmp2^cached_urcu_gp_ctr.val[_pid])&(1<<7))))"
+       line 430, "pan.___", state 767, "else"
+       line 400, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 779, "(1)"
+       line 400, "pan.___", state 780, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 780, "else"
+       line 400, "pan.___", state 783, "(1)"
+       line 404, "pan.___", state 791, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 793, "(1)"
+       line 404, "pan.___", state 794, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 794, "else"
+       line 404, "pan.___", state 797, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 402, "pan.___", state 803, "((i<1))"
+       line 402, "pan.___", state 803, "((i>=1))"
+       line 409, "pan.___", state 809, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 822, "(1)"
+       line 410, "pan.___", state 823, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 823, "else"
+       line 410, "pan.___", state 826, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 414, "pan.___", state 835, "(1)"
+       line 414, "pan.___", state 836, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 836, "else"
+       line 414, "pan.___", state 839, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 412, "pan.___", state 845, "((i<1))"
+       line 412, "pan.___", state 845, "((i>=1))"
+       line 419, "pan.___", state 852, "(1)"
+       line 419, "pan.___", state 853, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 853, "else"
+       line 419, "pan.___", state 856, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 370, "pan.___", state 862, "(1)"
+       line 449, "pan.___", state 870, "((tmp<1))"
+       line 449, "pan.___", state 870, "((tmp>=1))"
+       line 462, "pan.___", state 873, "tmp = 0"
+       line 400, "pan.___", state 877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 883, "(1)"
+       line 404, "pan.___", state 891, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 897, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 903, "((i<1))"
+       line 402, "pan.___", state 903, "((i>=1))"
+       line 409, "pan.___", state 909, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 922, "(1)"
+       line 410, "pan.___", state 923, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 923, "else"
+       line 410, "pan.___", state 926, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 414, "pan.___", state 935, "(1)"
+       line 414, "pan.___", state 936, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 936, "else"
+       line 414, "pan.___", state 939, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 945, "((i<1))"
+       line 412, "pan.___", state 945, "((i>=1))"
+       line 419, "pan.___", state 952, "(1)"
+       line 419, "pan.___", state 953, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 953, "else"
+       line 419, "pan.___", state 956, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 370, "pan.___", state 962, "(1)"
+       line 671, "pan.___", state 963, "tmp = cached_urcu_gp_ctr.val[_pid]"
+       line 400, "pan.___", state 967, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 973, "(1)"
+       line 404, "pan.___", state 981, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 987, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 402, "pan.___", state 993, "((i<1))"
+       line 402, "pan.___", state 993, "((i>=1))"
+       line 409, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1012, "(1)"
+       line 410, "pan.___", state 1013, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1013, "else"
+       line 410, "pan.___", state 1016, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 414, "pan.___", state 1025, "(1)"
+       line 414, "pan.___", state 1026, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1026, "else"
+       line 414, "pan.___", state 1029, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 412, "pan.___", state 1035, "((i<1))"
+       line 412, "pan.___", state 1035, "((i>=1))"
+       line 419, "pan.___", state 1042, "(1)"
+       line 419, "pan.___", state 1043, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1043, "else"
+       line 419, "pan.___", state 1046, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 370, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1061, "(1)"
+       line 404, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1117, "(1)"
+       line 419, "pan.___", state 1134, "(1)"
+       line 404, "pan.___", state 1166, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1184, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1210, "(1)"
+       line 419, "pan.___", state 1227, "(1)"
+       line 400, "pan.___", state 1242, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1256, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1287, "(1)"
+       line 414, "pan.___", state 1300, "(1)"
+       line 419, "pan.___", state 1317, "(1)"
+       line 400, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1342, "(1)"
+       line 400, "pan.___", state 1343, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1343, "else"
+       line 400, "pan.___", state 1346, "(1)"
+       line 404, "pan.___", state 1354, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1356, "(1)"
+       line 404, "pan.___", state 1357, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1357, "else"
+       line 404, "pan.___", state 1360, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 402, "pan.___", state 1366, "((i<1))"
+       line 402, "pan.___", state 1366, "((i>=1))"
+       line 409, "pan.___", state 1372, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1385, "(1)"
+       line 410, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1386, "else"
+       line 410, "pan.___", state 1389, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 414, "pan.___", state 1398, "(1)"
+       line 414, "pan.___", state 1399, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1399, "else"
+       line 414, "pan.___", state 1402, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 412, "pan.___", state 1408, "((i<1))"
+       line 412, "pan.___", state 1408, "((i>=1))"
+       line 419, "pan.___", state 1415, "(1)"
+       line 419, "pan.___", state 1416, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1416, "else"
+       line 419, "pan.___", state 1419, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 180, "pan.___", state 1448, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 184, "pan.___", state 1461, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 1471, "(1)"
+       line 165, "pan.___", state 1479, "(1)"
+       line 169, "pan.___", state 1491, "(1)"
+       line 176, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 184, "pan.___", state 1524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 1534, "(1)"
+       line 165, "pan.___", state 1542, "(1)"
+       line 169, "pan.___", state 1554, "(1)"
+       line 176, "pan.___", state 1569, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 184, "pan.___", state 1591, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 1601, "(1)"
+       line 165, "pan.___", state 1609, "(1)"
+       line 169, "pan.___", state 1621, "(1)"
+       line 370, "pan.___", state 1642, "(1)"
+       line 696, "pan.___", state 1643, "(1)"
+       line 703, "pan.___", state 1646, "-end-"
+       (308 of 1646 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 752, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 2.02 seconds
+pan: rate 84117.327 states/second
+pan: avg transition delay 8.5985e-07 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input
new file mode 100644 (file)
index 0000000..2aac6eb
--- /dev/null
@@ -0,0 +1,724 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+//#define READER_NEST_LEVEL 1
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu/result-standard-execution-nest/urcu_progress_writer_error.spin.input.trail
new file mode 100644 (file)
index 0000000..5bb8316
--- /dev/null
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diff --git a/formal-model/urcu/result-standard-execution-nonest/DEFINES b/formal-model/urcu/result-standard-execution-nonest/DEFINES
new file mode 100644 (file)
index 0000000..5d5147e
--- /dev/null
@@ -0,0 +1,17 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
diff --git a/formal-model/urcu/result-standard-execution-nonest/Makefile b/formal-model/urcu/result-standard-execution-nonest/Makefile
new file mode 100644 (file)
index 0000000..8af320d
--- /dev/null
@@ -0,0 +1,172 @@
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) Mathieu Desnoyers, 2009
+#
+# Authors: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+#CFLAGS=-DSAFETY
+#for multi-core verif, 15.5GB shared mem, use files if full
+#CFLAGS=-DHASH64 -DMEMLIM=15500 -DNCORE=2
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88 -DMEMLIM=15500 -DNCORE=8
+
+#liveness
+#CFLAGS=-DHASH64 -DCOLLAPSE -DMA=88
+CFLAGS=-DHASH64
+
+SPINFILE=urcu.spin
+
+default:
+       make urcu_free | tee urcu_free.log
+       #nested useless with signal test.
+       #make urcu_free_nested | tee urcu_free_nested.log
+       make urcu_free_no_rmb | tee urcu_free_no_rmb.log
+       make urcu_free_no_wmb | tee urcu_free_no_wmb.log
+       make urcu_free_no_mb | tee urcu_free_no_mb.log
+       make urcu_free_single_flip | tee urcu_free_single_flip.log
+       make urcu_progress_writer | tee urcu_progress_writer.log
+       make urcu_progress_reader | tee urcu_progress_reader.log
+       make urcu_progress_writer_error | tee urcu_progress_writer_error.log
+       make asserts | tee asserts.log
+       make summary
+
+#show trail : spin -v -t -N pan.ltl input.spin
+# after each individual make.
+
+summary:
+       @echo
+       @echo "Verification summary"
+       @grep errors: *.log
+
+asserts: clean
+       cat DEFINES > .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X .input.spin
+       gcc -O2 -w ${CFLAGS} -DSAFETY -o pan pan.c
+       ./pan -v -c1 -X -m10000000 -w20
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free: clean urcu_free_ltl run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested: clean urcu_free_ltl urcu_free_nested_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_nested_define:
+       cp urcu_free_nested.define .input.define
+
+urcu_free_no_rmb: clean urcu_free_ltl urcu_free_no_rmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_rmb_define:
+       cp urcu_free_no_rmb.define .input.define
+
+urcu_free_no_wmb: clean urcu_free_ltl urcu_free_no_wmb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_wmb_define:
+       cp urcu_free_no_wmb.define .input.define
+
+urcu_free_no_mb: clean urcu_free_ltl urcu_free_no_mb_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_no_mb_define:
+       cp urcu_free_no_mb.define .input.define
+
+urcu_free_single_flip: clean urcu_free_ltl urcu_free_single_flip_define run
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_free_single_flip_define:
+       cp urcu_free_single_flip.define .input.define
+
+urcu_free_ltl:
+       touch .input.define
+       cat .input.define >> pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+
+# Progress checks
+
+urcu_progress_writer: clean urcu_progress_writer_ltl \
+               urcu_progress_writer_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_define:
+       cp urcu_progress_writer.define .input.define
+
+urcu_progress_writer_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_reader: clean urcu_progress_reader_ltl \
+               urcu_progress_reader_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_reader_define:
+       cp urcu_progress_reader.define .input.define
+
+urcu_progress_reader_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+urcu_progress_writer_error: clean urcu_progress_writer_error_ltl \
+               urcu_progress_writer_error_define run_weak_fair
+       cp .input.spin $@.spin.input
+       -cp .input.spin.trail $@.spin.input.trail
+
+urcu_progress_writer_error_define:
+       cp urcu_progress_writer_error.define .input.define
+
+urcu_progress_writer_error_ltl:
+       touch .input.define
+       cat .input.define > pan.ltl
+       cat DEFINES >> pan.ltl
+       spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+
+
+run_weak_fair: pan
+       ./pan -a -f -v -c1 -X -m10000000 -w20
+
+run: pan
+       ./pan -a -v -c1 -X -m10000000 -w20
+
+pan: pan.c
+       gcc -O2 -w ${CFLAGS} -o pan pan.c
+
+pan.c: pan.ltl ${SPINFILE}
+       cat .input.define > .input.spin
+       cat DEFINES >> .input.spin
+       cat ${SPINFILE} >> .input.spin
+       rm -f .input.spin.trail
+       spin -a -X -N pan.ltl .input.spin
+
+.PHONY: clean default distclean summary
+clean:
+       rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+distclean:
+       rm -f *.trail *.input *.log
diff --git a/formal-model/urcu/result-standard-execution-nonest/asserts.log b/formal-model/urcu/result-standard-execution-nonest/asserts.log
new file mode 100644 (file)
index 0000000..1071a7a
--- /dev/null
@@ -0,0 +1,246 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+cat DEFINES > .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w20
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             - (none specified)
+       assertion violations    +
+       cycle checks            - (disabled by -DSAFETY)
+       invalid end states      +
+
+State-vector 48 byte, depth reached 2084, errors: 0
+   847558 states, stored
+  9221089 states, matched
+ 10068647 transitions (= stored+matched)
+ 36786866 atomic steps
+hash conflicts:   2126850 (resolved)
+
+Stats on memory usage (in Megabytes):
+   61.430      equivalent memory usage for states (stored*(State-vector + overhead))
+   45.632      actual memory usage for states (compression: 74.28%)
+               state-vector as stored = 28 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  511.369      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, ".input.spin", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 61, "(1)"
+       line 417, ".input.spin", state 91, "(1)"
+       line 398, ".input.spin", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 151, "(1)"
+       line 417, ".input.spin", state 181, "(1)"
+       line 398, ".input.spin", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 242, "(1)"
+       line 417, ".input.spin", state 272, "(1)"
+       line 398, ".input.spin", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 360, "(1)"
+       line 417, ".input.spin", state 390, "(1)"
+       line 539, ".input.spin", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 398, ".input.spin", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 59, "(1)"
+       line 412, ".input.spin", state 72, "(1)"
+       line 417, ".input.spin", state 89, "(1)"
+       line 398, ".input.spin", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 153, "(1)"
+       line 412, ".input.spin", state 166, "(1)"
+       line 651, ".input.spin", state 199, "(1)"
+       line 174, ".input.spin", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 240, "(1)"
+       line 163, ".input.spin", state 248, "(1)"
+       line 167, ".input.spin", state 260, "(1)"
+       line 174, ".input.spin", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 303, "(1)"
+       line 163, ".input.spin", state 311, "(1)"
+       line 167, ".input.spin", state 323, "(1)"
+       line 174, ".input.spin", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 370, "(1)"
+       line 163, ".input.spin", state 378, "(1)"
+       line 167, ".input.spin", state 390, "(1)"
+       line 398, ".input.spin", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 449, "(1)"
+       line 412, ".input.spin", state 462, "(1)"
+       line 417, ".input.spin", state 479, "(1)"
+       line 398, ".input.spin", state 498, "(1)"
+       line 402, ".input.spin", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 554, "(1)"
+       line 417, ".input.spin", state 571, "(1)"
+       line 402, ".input.spin", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 647, "(1)"
+       line 417, ".input.spin", state 664, "(1)"
+       line 178, ".input.spin", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 710, "(1)"
+       line 163, ".input.spin", state 718, "(1)"
+       line 167, ".input.spin", state 730, "(1)"
+       line 174, ".input.spin", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 773, "(1)"
+       line 163, ".input.spin", state 781, "(1)"
+       line 167, ".input.spin", state 793, "(1)"
+       line 174, ".input.spin", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 840, "(1)"
+       line 163, ".input.spin", state 848, "(1)"
+       line 167, ".input.spin", state 860, "(1)"
+       line 398, ".input.spin", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, ".input.spin", state 884, "(1)"
+       line 398, ".input.spin", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, ".input.spin", state 885, "else"
+       line 398, ".input.spin", state 888, "(1)"
+       line 402, ".input.spin", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 898, "(1)"
+       line 402, ".input.spin", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, ".input.spin", state 899, "else"
+       line 402, ".input.spin", state 902, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 402, ".input.spin", state 903, "(1)"
+       line 400, ".input.spin", state 908, "((i<1))"
+       line 400, ".input.spin", state 908, "((i>=1))"
+       line 407, ".input.spin", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 927, "(1)"
+       line 408, ".input.spin", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, ".input.spin", state 928, "else"
+       line 408, ".input.spin", state 931, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 408, ".input.spin", state 932, "(1)"
+       line 412, ".input.spin", state 940, "(1)"
+       line 412, ".input.spin", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, ".input.spin", state 941, "else"
+       line 412, ".input.spin", state 944, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 412, ".input.spin", state 945, "(1)"
+       line 410, ".input.spin", state 950, "((i<1))"
+       line 410, ".input.spin", state 950, "((i>=1))"
+       line 417, ".input.spin", state 957, "(1)"
+       line 417, ".input.spin", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, ".input.spin", state 958, "else"
+       line 417, ".input.spin", state 961, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 417, ".input.spin", state 962, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 419, ".input.spin", state 965, "(1)"
+       line 402, ".input.spin", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1040, "(1)"
+       line 417, ".input.spin", state 1057, "(1)"
+       line 402, ".input.spin", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1130, "(1)"
+       line 417, ".input.spin", state 1147, "(1)"
+       line 398, ".input.spin", state 1166, "(1)"
+       line 402, ".input.spin", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1222, "(1)"
+       line 417, ".input.spin", state 1239, "(1)"
+       line 402, ".input.spin", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, ".input.spin", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, ".input.spin", state 1315, "(1)"
+       line 417, ".input.spin", state 1332, "(1)"
+       line 178, ".input.spin", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1378, "(1)"
+       line 163, ".input.spin", state 1386, "(1)"
+       line 167, ".input.spin", state 1398, "(1)"
+       line 174, ".input.spin", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1441, "(1)"
+       line 163, ".input.spin", state 1449, "(1)"
+       line 167, ".input.spin", state 1461, "(1)"
+       line 174, ".input.spin", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1508, "(1)"
+       line 163, ".input.spin", state 1516, "(1)"
+       line 167, ".input.spin", state 1528, "(1)"
+       line 398, ".input.spin", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, ".input.spin", state 1552, "(1)"
+       line 398, ".input.spin", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, ".input.spin", state 1553, "else"
+       line 398, ".input.spin", state 1556, "(1)"
+       line 402, ".input.spin", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, ".input.spin", state 1566, "(1)"
+       line 402, ".input.spin", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, ".input.spin", state 1567, "else"
+       line 402, ".input.spin", state 1570, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 402, ".input.spin", state 1571, "(1)"
+       line 400, ".input.spin", state 1576, "((i<1))"
+       line 400, ".input.spin", state 1576, "((i>=1))"
+       line 407, ".input.spin", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, ".input.spin", state 1595, "(1)"
+       line 408, ".input.spin", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, ".input.spin", state 1596, "else"
+       line 408, ".input.spin", state 1599, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 408, ".input.spin", state 1600, "(1)"
+       line 412, ".input.spin", state 1608, "(1)"
+       line 412, ".input.spin", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, ".input.spin", state 1609, "else"
+       line 412, ".input.spin", state 1612, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 412, ".input.spin", state 1613, "(1)"
+       line 410, ".input.spin", state 1618, "((i<1))"
+       line 410, ".input.spin", state 1618, "((i>=1))"
+       line 417, ".input.spin", state 1625, "(1)"
+       line 417, ".input.spin", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, ".input.spin", state 1626, "else"
+       line 417, ".input.spin", state 1629, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 417, ".input.spin", state 1630, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 419, ".input.spin", state 1633, "(1)"
+       line 178, ".input.spin", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1681, "(1)"
+       line 163, ".input.spin", state 1689, "(1)"
+       line 167, ".input.spin", state 1701, "(1)"
+       line 174, ".input.spin", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, ".input.spin", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, ".input.spin", state 1744, "(1)"
+       line 163, ".input.spin", state 1752, "(1)"
+       line 167, ".input.spin", state 1764, "(1)"
+       line 174, ".input.spin", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, ".input.spin", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, ".input.spin", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, ".input.spin", state 1811, "(1)"
+       line 163, ".input.spin", state 1819, "(1)"
+       line 167, ".input.spin", state 1831, "(1)"
+       line 701, ".input.spin", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+
+pan: elapsed time 6.68 seconds
+pan: rate 126879.94 states/second
+pan: avg transition delay 6.6345e-07 usec
+cp .input.spin asserts.spin.input
+cp .input.spin.trail asserts.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/asserts.spin.input b/formal-model/urcu/result-standard-execution-nonest/asserts.spin.input
new file mode 100644 (file)
index 0000000..e17e80e
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/asserts.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/asserts.spin.input.trail
new file mode 100644 (file)
index 0000000..287e52a
--- /dev/null
@@ -0,0 +1,6 @@
+-4:-4:-4
+1:0:2673
+2:0:2674
+3:0:2675
+4:0:2676
+5:4:1129
diff --git a/formal-model/urcu/result-standard-execution-nonest/references.txt b/formal-model/urcu/result-standard-execution-nonest/references.txt
new file mode 100644 (file)
index 0000000..72c67a2
--- /dev/null
@@ -0,0 +1,13 @@
+http://spinroot.com/spin/Man/ltl.html
+http://en.wikipedia.org/wiki/Linear_temporal_logic
+http://www.dcs.gla.ac.uk/~muffy/MRS4-2002/lect11.ppt
+
+http://www.lsv.ens-cachan.fr/~gastin/ltl2ba/index.php
+http://spinroot.com/spin/Man/index.html
+http://spinroot.com/spin/Man/promela.html
+
+LTL vs CTL :
+
+http://spinroot.com/spin/Doc/course/lecture12.pdf p. 9, p. 15, p. 18
+http://www-i2.informatik.rwth-aachen.de/i2/fileadmin/user_upload/documents/Introduction_to_Model_Checking/mc_lec18.pdf
+  (downloaded)
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu.sh b/formal-model/urcu/result-standard-execution-nonest/urcu.sh
new file mode 100644 (file)
index 0000000..65ff517
--- /dev/null
@@ -0,0 +1,29 @@
+#!/bin/sh
+#
+# Compiles and runs the urcu.spin Promela model.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# Copyright (C) IBM Corporation, 2009
+#               Mathieu Desnoyers, 2009
+#
+# Authors: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
+#          Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+
+# Basic execution, without LTL clauses. See Makefile.
+
+spin -a urcu.spin
+cc -DSAFETY -o pan pan.c
+./pan -v -c1 -X -m10000000 -w21
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu.spin b/formal-model/urcu/result-standard-execution-nonest/urcu.spin
new file mode 100644 (file)
index 0000000..2cfcb70
--- /dev/null
@@ -0,0 +1,705 @@
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free.log
new file mode 100644 (file)
index 0000000..00b1f6c
--- /dev/null
@@ -0,0 +1,257 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 743)
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 2560, errors: 0
+   954166 states, stored
+ 10460008 states, matched
+ 11414174 transitions (= stored+matched)
+ 41707752 atomic steps
+hash conflicts:   2907736 (resolved)
+
+Stats on memory usage (in Megabytes):
+   76.437      equivalent memory usage for states (stored*(State-vector + overhead))
+   58.605      actual memory usage for states (compression: 76.67%)
+               state-vector as stored = 36 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  524.358      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 398, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 61, "(1)"
+       line 417, "pan.___", state 91, "(1)"
+       line 398, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 151, "(1)"
+       line 417, "pan.___", state 181, "(1)"
+       line 398, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 242, "(1)"
+       line 417, "pan.___", state 272, "(1)"
+       line 398, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 360, "(1)"
+       line 417, "pan.___", state 390, "(1)"
+       line 539, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 398, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 59, "(1)"
+       line 412, "pan.___", state 72, "(1)"
+       line 417, "pan.___", state 89, "(1)"
+       line 398, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 153, "(1)"
+       line 412, "pan.___", state 166, "(1)"
+       line 651, "pan.___", state 199, "(1)"
+       line 174, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 240, "(1)"
+       line 163, "pan.___", state 248, "(1)"
+       line 167, "pan.___", state 260, "(1)"
+       line 174, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 303, "(1)"
+       line 163, "pan.___", state 311, "(1)"
+       line 167, "pan.___", state 323, "(1)"
+       line 174, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 370, "(1)"
+       line 163, "pan.___", state 378, "(1)"
+       line 167, "pan.___", state 390, "(1)"
+       line 398, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 449, "(1)"
+       line 412, "pan.___", state 462, "(1)"
+       line 417, "pan.___", state 479, "(1)"
+       line 398, "pan.___", state 498, "(1)"
+       line 402, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 554, "(1)"
+       line 417, "pan.___", state 571, "(1)"
+       line 402, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 647, "(1)"
+       line 417, "pan.___", state 664, "(1)"
+       line 178, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 710, "(1)"
+       line 163, "pan.___", state 718, "(1)"
+       line 167, "pan.___", state 730, "(1)"
+       line 174, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 773, "(1)"
+       line 163, "pan.___", state 781, "(1)"
+       line 167, "pan.___", state 793, "(1)"
+       line 174, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 840, "(1)"
+       line 163, "pan.___", state 848, "(1)"
+       line 167, "pan.___", state 860, "(1)"
+       line 398, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, "pan.___", state 884, "(1)"
+       line 398, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, "pan.___", state 885, "else"
+       line 398, "pan.___", state 888, "(1)"
+       line 402, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, "pan.___", state 899, "else"
+       line 402, "pan.___", state 902, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 402, "pan.___", state 903, "(1)"
+       line 400, "pan.___", state 908, "((i<1))"
+       line 400, "pan.___", state 908, "((i>=1))"
+       line 407, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 927, "(1)"
+       line 408, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, "pan.___", state 928, "else"
+       line 408, "pan.___", state 931, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 408, "pan.___", state 932, "(1)"
+       line 412, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, "pan.___", state 941, "else"
+       line 412, "pan.___", state 944, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 412, "pan.___", state 945, "(1)"
+       line 410, "pan.___", state 950, "((i<1))"
+       line 410, "pan.___", state 950, "((i>=1))"
+       line 417, "pan.___", state 957, "(1)"
+       line 417, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, "pan.___", state 958, "else"
+       line 417, "pan.___", state 961, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 417, "pan.___", state 962, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 419, "pan.___", state 965, "(1)"
+       line 402, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1040, "(1)"
+       line 417, "pan.___", state 1057, "(1)"
+       line 402, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1130, "(1)"
+       line 417, "pan.___", state 1147, "(1)"
+       line 398, "pan.___", state 1166, "(1)"
+       line 402, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1222, "(1)"
+       line 417, "pan.___", state 1239, "(1)"
+       line 402, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 407, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 412, "pan.___", state 1315, "(1)"
+       line 417, "pan.___", state 1332, "(1)"
+       line 178, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1378, "(1)"
+       line 163, "pan.___", state 1386, "(1)"
+       line 167, "pan.___", state 1398, "(1)"
+       line 174, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1441, "(1)"
+       line 163, "pan.___", state 1449, "(1)"
+       line 167, "pan.___", state 1461, "(1)"
+       line 174, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1508, "(1)"
+       line 163, "pan.___", state 1516, "(1)"
+       line 167, "pan.___", state 1528, "(1)"
+       line 398, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 398, "pan.___", state 1552, "(1)"
+       line 398, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 398, "pan.___", state 1553, "else"
+       line 398, "pan.___", state 1556, "(1)"
+       line 402, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 402, "pan.___", state 1566, "(1)"
+       line 402, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 402, "pan.___", state 1567, "else"
+       line 402, "pan.___", state 1570, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 402, "pan.___", state 1571, "(1)"
+       line 400, "pan.___", state 1576, "((i<1))"
+       line 400, "pan.___", state 1576, "((i>=1))"
+       line 407, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1595, "(1)"
+       line 408, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 408, "pan.___", state 1596, "else"
+       line 408, "pan.___", state 1599, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 408, "pan.___", state 1600, "(1)"
+       line 412, "pan.___", state 1608, "(1)"
+       line 412, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 412, "pan.___", state 1609, "else"
+       line 412, "pan.___", state 1612, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 412, "pan.___", state 1613, "(1)"
+       line 410, "pan.___", state 1618, "((i<1))"
+       line 410, "pan.___", state 1618, "((i>=1))"
+       line 417, "pan.___", state 1625, "(1)"
+       line 417, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 417, "pan.___", state 1626, "else"
+       line 417, "pan.___", state 1629, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 417, "pan.___", state 1630, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 419, "pan.___", state 1633, "(1)"
+       line 178, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1681, "(1)"
+       line 163, "pan.___", state 1689, "(1)"
+       line 167, "pan.___", state 1701, "(1)"
+       line 174, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 182, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 159, "pan.___", state 1744, "(1)"
+       line 163, "pan.___", state 1752, "(1)"
+       line 167, "pan.___", state 1764, "(1)"
+       line 174, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 182, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 159, "pan.___", state 1811, "(1)"
+       line 163, "pan.___", state 1819, "(1)"
+       line 167, "pan.___", state 1831, "(1)"
+       line 701, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 748, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 9.16 seconds
+pan: rate 104166.59 states/second
+pan: avg transition delay 8.0251e-07 usec
+cp .input.spin urcu_free.spin.input
+cp .input.spin.trail urcu_free.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free.ltl b/formal-model/urcu/result-standard-execution-nonest/urcu_free.ltl
new file mode 100644 (file)
index 0000000..1954414
--- /dev/null
@@ -0,0 +1 @@
+[] (read_free -> !read_free_race)
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input
new file mode 100644 (file)
index 0000000..e17e80e
--- /dev/null
@@ -0,0 +1,722 @@
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free.spin.input.trail
new file mode 100644 (file)
index 0000000..837f3d9
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+15020:2:1791
+15021:2:1792
+15022:2:1799
+15023:2:1800
+15024:2:1811
+15025:2:1812
+15026:2:1813
+15027:2:1811
+15028:2:1812
+15029:2:1813
+15030:2:1824
+15031:2:1829
+15032:2:1830
+15033:0:4365
+15034:2:1842
+15035:0:4365
+15036:3:2427
+15037:0:4365
+15038:2:1844
+15039:0:4363
+15040:3:2428
+15041:0:4369
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.define b/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.define
new file mode 100644 (file)
index 0000000..0fb59bd
--- /dev/null
@@ -0,0 +1 @@
+#define READER_NEST_LEVEL 2
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.log
new file mode 100644 (file)
index 0000000..d503334
--- /dev/null
@@ -0,0 +1,20 @@
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_nested.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 742)
+Depth=    3880 States=    1e+06 Transitions= 1.18e+07 Memory=   527.190        t=   9.48 R=   1e+05
+Depth=    3880 States=    2e+06 Transitions= 2.39e+07 Memory=   588.225        t=   19.6 R=   1e+05
+Depth=    3880 States=    3e+06 Transitions= 3.61e+07 Memory=   649.260        t=   30.3 R=   1e+05
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input
new file mode 100644 (file)
index 0000000..c94928c
--- /dev/null
@@ -0,0 +1,696 @@
+#define READER_NEST_LEVEL 1
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+#define TEST_SIGNAL
+#define TEST_SIGNAL_ON_READ
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+#define get_pid()      ((_pid < 1) -> 0 : 1)
+#elif defined(TEST_SIGNAL_ON_READ)
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+#else
+#define get_pid()      (_pid)
+#endif
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb(i, j)
+{
+       if
+       :: get_pid() >= NR_READERS ->
+               smp_mb_pid(get_pid(), j);
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       smp_mb_pid(i, j);
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               smp_mb_pid(get_pid(), j);
+       :: else -> skip;
+       fi;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+#define get_readerid() (get_pid())
+#define get_writerid() (get_readerid() + NR_READERS)
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       dispatch_sighand_read_exec();
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       dispatch_sighand_read_exec();
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       dispatch_sighand_read_exec();
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               if
+               :: get_readerid() == 0 ->
+progress_reader:
+                       skip;
+               fi;
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       ooo_mem(i);
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       ooo_mem(i);
+       data_access[get_readerid()] = 1;
+       ooo_mem(i);
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+               /* Only test progress of one random reader. They are all the
+                * same. */
+               if
+               :: get_readerid() == 0 ->
+progress_reader:
+                       skip;
+               fi;
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free_nested.spin.input.trail
new file mode 100644 (file)
index 0000000..6f29ad2
--- /dev/null
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.define b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.define
new file mode 100644 (file)
index 0000000..136ef67
--- /dev/null
@@ -0,0 +1,2 @@
+#define NO_RMB
+#define NO_WMB
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.log
new file mode 100644 (file)
index 0000000..c420e43
--- /dev/null
@@ -0,0 +1,266 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_mb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+pan: claim violated! (at depth 2071)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 72 byte, depth reached 5140, errors: 1
+   264561 states, stored
+  3902374 states, matched
+  4166935 transitions (= stored+matched)
+ 15172302 atomic steps
+hash conflicts:    196282 (resolved)
+
+Stats on memory usage (in Megabytes):
+   25.231      equivalent memory usage for states (stored*(State-vector + overhead))
+   16.681      actual memory usage for states (compression: 66.12%)
+               state-vector as stored = 38 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  482.365      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 151, "(1)"
+       line 419, "pan.___", state 181, "(1)"
+       line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 242, "(1)"
+       line 419, "pan.___", state 272, "(1)"
+       line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 331, "(1)"
+       line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 360, "(1)"
+       line 419, "pan.___", state 390, "(1)"
+       line 541, "pan.___", state 414, "-end-"
+       (18 of 414 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 421, "pan.___", state 97, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 410, "pan.___", state 153, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 400, "pan.___", state 209, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 223, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 254, "(1)"
+       line 414, "pan.___", state 267, "(1)"
+       line 400, "pan.___", state 300, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 314, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 345, "(1)"
+       line 414, "pan.___", state 358, "(1)"
+       line 400, "pan.___", state 395, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 409, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 440, "(1)"
+       line 414, "pan.___", state 453, "(1)"
+       line 400, "pan.___", state 488, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 502, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 533, "(1)"
+       line 414, "pan.___", state 546, "(1)"
+       line 400, "pan.___", state 582, "(1)"
+       line 404, "pan.___", state 594, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 638, "(1)"
+       line 404, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 731, "(1)"
+       line 404, "pan.___", state 777, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 795, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 821, "(1)"
+       line 419, "pan.___", state 838, "(1)"
+       line 404, "pan.___", state 868, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 886, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 912, "(1)"
+       line 419, "pan.___", state 929, "(1)"
+       line 404, "pan.___", state 963, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 981, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1007, "(1)"
+       line 419, "pan.___", state 1024, "(1)"
+       line 400, "pan.___", state 1050, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1053, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1053, "else"
+       line 400, "pan.___", state 1056, "(1)"
+       line 404, "pan.___", state 1064, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1066, "(1)"
+       line 404, "pan.___", state 1067, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1067, "else"
+       line 404, "pan.___", state 1070, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 404, "pan.___", state 1071, "(1)"
+       line 402, "pan.___", state 1076, "((i<1))"
+       line 402, "pan.___", state 1076, "((i>=1))"
+       line 409, "pan.___", state 1082, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1095, "(1)"
+       line 410, "pan.___", state 1096, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1096, "else"
+       line 410, "pan.___", state 1099, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 410, "pan.___", state 1100, "(1)"
+       line 414, "pan.___", state 1108, "(1)"
+       line 414, "pan.___", state 1109, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1109, "else"
+       line 414, "pan.___", state 1112, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 414, "pan.___", state 1113, "(1)"
+       line 412, "pan.___", state 1118, "((i<1))"
+       line 412, "pan.___", state 1118, "((i>=1))"
+       line 419, "pan.___", state 1125, "(1)"
+       line 419, "pan.___", state 1126, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1126, "else"
+       line 419, "pan.___", state 1129, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 419, "pan.___", state 1130, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 421, "pan.___", state 1133, "(1)"
+       line 404, "pan.___", state 1164, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1208, "(1)"
+       line 404, "pan.___", state 1254, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1298, "(1)"
+       line 400, "pan.___", state 1334, "(1)"
+       line 404, "pan.___", state 1346, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1390, "(1)"
+       line 404, "pan.___", state 1439, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1483, "(1)"
+       line 404, "pan.___", state 1529, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1547, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1573, "(1)"
+       line 419, "pan.___", state 1590, "(1)"
+       line 404, "pan.___", state 1620, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1638, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1664, "(1)"
+       line 419, "pan.___", state 1681, "(1)"
+       line 404, "pan.___", state 1715, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1733, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1759, "(1)"
+       line 419, "pan.___", state 1776, "(1)"
+       line 400, "pan.___", state 1802, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1804, "(1)"
+       line 400, "pan.___", state 1805, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1805, "else"
+       line 400, "pan.___", state 1808, "(1)"
+       line 404, "pan.___", state 1816, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1818, "(1)"
+       line 404, "pan.___", state 1819, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1819, "else"
+       line 404, "pan.___", state 1822, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 404, "pan.___", state 1823, "(1)"
+       line 402, "pan.___", state 1828, "((i<1))"
+       line 402, "pan.___", state 1828, "((i>=1))"
+       line 409, "pan.___", state 1834, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1847, "(1)"
+       line 410, "pan.___", state 1848, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1848, "else"
+       line 410, "pan.___", state 1851, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 410, "pan.___", state 1852, "(1)"
+       line 414, "pan.___", state 1860, "(1)"
+       line 414, "pan.___", state 1861, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1861, "else"
+       line 414, "pan.___", state 1864, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 414, "pan.___", state 1865, "(1)"
+       line 412, "pan.___", state 1870, "((i<1))"
+       line 412, "pan.___", state 1870, "((i>=1))"
+       line 419, "pan.___", state 1877, "(1)"
+       line 419, "pan.___", state 1878, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1878, "else"
+       line 419, "pan.___", state 1881, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 419, "pan.___", state 1882, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 421, "pan.___", state 1885, "(1)"
+       line 404, "pan.___", state 1916, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1960, "(1)"
+       line 404, "pan.___", state 2007, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 2051, "(1)"
+       line 404, "pan.___", state 2102, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 2146, "(1)"
+       line 703, "pan.___", state 2192, "-end-"
+       (144 of 2192 states)
+unreached in proctype :init:
+       line 710, "pan.___", state 9, "((j<2))"
+       line 710, "pan.___", state 9, "((j>=2))"
+       line 711, "pan.___", state 20, "((j<2))"
+       line 711, "pan.___", state 20, "((j>=2))"
+       line 716, "pan.___", state 33, "((j<2))"
+       line 716, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 750, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 3.37 seconds
+pan: rate 78504.748 states/second
+pan: avg transition delay 8.0875e-07 usec
+cp .input.spin urcu_free_no_mb.spin.input
+cp .input.spin.trail urcu_free_no_mb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input
new file mode 100644 (file)
index 0000000..3831d86
--- /dev/null
@@ -0,0 +1,724 @@
+#define NO_RMB
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_mb.spin.input.trail
new file mode 100644 (file)
index 0000000..7b2040a
--- /dev/null
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.define b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.define
new file mode 100644 (file)
index 0000000..73e61a4
--- /dev/null
@@ -0,0 +1 @@
+#define NO_RMB
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.log
new file mode 100644 (file)
index 0000000..439c78e
--- /dev/null
@@ -0,0 +1,265 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_rmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+pan: claim violated! (at depth 1726)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3264, errors: 1
+   229629 states, stored
+  2119227 states, matched
+  2348856 transitions (= stored+matched)
+  8294746 atomic steps
+hash conflicts:     96242 (resolved)
+
+Stats on memory usage (in Megabytes):
+   18.395      equivalent memory usage for states (stored*(State-vector + overhead))
+   14.410      actual memory usage for states (compression: 78.34%)
+               state-vector as stored = 38 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  480.119      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 243, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 265, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 282, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 291, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 304, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 320, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 334, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 352, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 365, "(1)"
+       line 413, "pan.___", state 378, "(1)"
+       line 418, "pan.___", state 395, "(1)"
+       line 399, "pan.___", state 414, "(1)"
+       line 403, "pan.___", state 426, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 444, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 470, "(1)"
+       line 418, "pan.___", state 487, "(1)"
+       line 403, "pan.___", state 519, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 537, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 563, "(1)"
+       line 418, "pan.___", state 580, "(1)"
+       line 179, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 616, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 629, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 651, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 668, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 677, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 690, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 714, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 716, "(1)"
+       line 399, "pan.___", state 717, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 717, "else"
+       line 399, "pan.___", state 720, "(1)"
+       line 403, "pan.___", state 728, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 730, "(1)"
+       line 403, "pan.___", state 731, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 731, "else"
+       line 403, "pan.___", state 734, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 403, "pan.___", state 735, "(1)"
+       line 401, "pan.___", state 740, "((i<1))"
+       line 401, "pan.___", state 740, "((i>=1))"
+       line 408, "pan.___", state 746, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 759, "(1)"
+       line 409, "pan.___", state 760, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 760, "else"
+       line 409, "pan.___", state 763, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 409, "pan.___", state 764, "(1)"
+       line 413, "pan.___", state 772, "(1)"
+       line 413, "pan.___", state 773, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 773, "else"
+       line 413, "pan.___", state 776, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 413, "pan.___", state 777, "(1)"
+       line 411, "pan.___", state 782, "((i<1))"
+       line 411, "pan.___", state 782, "((i>=1))"
+       line 418, "pan.___", state 789, "(1)"
+       line 418, "pan.___", state 790, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 790, "else"
+       line 418, "pan.___", state 793, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 418, "pan.___", state 794, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 420, "pan.___", state 797, "(1)"
+       line 403, "pan.___", state 828, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 846, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 872, "(1)"
+       line 418, "pan.___", state 889, "(1)"
+       line 403, "pan.___", state 918, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 936, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 979, "(1)"
+       line 399, "pan.___", state 998, "(1)"
+       line 403, "pan.___", state 1010, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1028, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1054, "(1)"
+       line 418, "pan.___", state 1071, "(1)"
+       line 403, "pan.___", state 1103, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1121, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1147, "(1)"
+       line 418, "pan.___", state 1164, "(1)"
+       line 179, "pan.___", state 1187, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1200, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 1213, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1235, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1252, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1261, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1298, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1300, "(1)"
+       line 399, "pan.___", state 1301, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1301, "else"
+       line 399, "pan.___", state 1304, "(1)"
+       line 403, "pan.___", state 1312, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1314, "(1)"
+       line 403, "pan.___", state 1315, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1315, "else"
+       line 403, "pan.___", state 1318, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 403, "pan.___", state 1319, "(1)"
+       line 401, "pan.___", state 1324, "((i<1))"
+       line 401, "pan.___", state 1324, "((i>=1))"
+       line 408, "pan.___", state 1330, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1343, "(1)"
+       line 409, "pan.___", state 1344, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1344, "else"
+       line 409, "pan.___", state 1347, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 409, "pan.___", state 1348, "(1)"
+       line 413, "pan.___", state 1356, "(1)"
+       line 413, "pan.___", state 1357, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1357, "else"
+       line 413, "pan.___", state 1360, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 413, "pan.___", state 1361, "(1)"
+       line 411, "pan.___", state 1366, "((i<1))"
+       line 411, "pan.___", state 1366, "((i>=1))"
+       line 418, "pan.___", state 1373, "(1)"
+       line 418, "pan.___", state 1374, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1374, "else"
+       line 418, "pan.___", state 1377, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 418, "pan.___", state 1378, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 420, "pan.___", state 1381, "(1)"
+       line 179, "pan.___", state 1406, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1419, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 175, "pan.___", state 1432, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1454, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 175, "pan.___", state 1471, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1480, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1493, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 702, "pan.___", state 1520, "-end-"
+       (144 of 1520 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 1.88 seconds
+pan: rate 122143.09 states/second
+pan: avg transition delay 8.0039e-07 usec
+cp .input.spin urcu_free_no_rmb.spin.input
+cp .input.spin.trail urcu_free_no_rmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input
new file mode 100644 (file)
index 0000000..6ccb255
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_RMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_rmb.spin.input.trail
new file mode 100644 (file)
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.define b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.define
new file mode 100644 (file)
index 0000000..710f29d
--- /dev/null
@@ -0,0 +1 @@
+#define NO_WMB
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.log
new file mode 100644 (file)
index 0000000..abf7b83
--- /dev/null
@@ -0,0 +1,294 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_no_wmb.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+pan: claim violated! (at depth 1614)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 2823, errors: 1
+    81228 states, stored
+   752552 states, matched
+   833780 transitions (= stored+matched)
+  2934533 atomic steps
+hash conflicts:     10835 (resolved)
+
+Stats on memory usage (in Megabytes):
+    6.507      equivalent memory usage for states (stored*(State-vector + overhead))
+    5.330      actual memory usage for states (compression: 81.92%)
+               state-vector as stored = 41 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  471.037      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 331, "(1)"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (18 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 20, "(1)"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 34, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 403, "pan.___", state 35, "(1)"
+       line 401, "pan.___", state 40, "((i<1))"
+       line 401, "pan.___", state 40, "((i>=1))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 409, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 60, "else"
+       line 409, "pan.___", state 63, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 409, "pan.___", state 64, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 413, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 73, "else"
+       line 413, "pan.___", state 76, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 413, "pan.___", state 77, "(1)"
+       line 411, "pan.___", state 82, "((i<1))"
+       line 411, "pan.___", state 82, "((i>=1))"
+       line 418, "pan.___", state 89, "(1)"
+       line 418, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 90, "else"
+       line 418, "pan.___", state 93, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 418, "pan.___", state 94, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 420, "pan.___", state 97, "(1)"
+       line 369, "pan.___", state 99, "(1)"
+       line 639, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 637, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 114, "(1)"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 128, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 403, "pan.___", state 129, "(1)"
+       line 401, "pan.___", state 134, "((i<1))"
+       line 401, "pan.___", state 134, "((i>=1))"
+       line 409, "pan.___", state 153, "(1)"
+       line 409, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 154, "else"
+       line 409, "pan.___", state 157, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 409, "pan.___", state 158, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 413, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 167, "else"
+       line 413, "pan.___", state 170, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 413, "pan.___", state 171, "(1)"
+       line 411, "pan.___", state 176, "((i<1))"
+       line 411, "pan.___", state 176, "((i>=1))"
+       line 418, "pan.___", state 183, "(1)"
+       line 418, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 184, "else"
+       line 418, "pan.___", state 187, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 418, "pan.___", state 188, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 420, "pan.___", state 191, "(1)"
+       line 369, "pan.___", state 193, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 646, "pan.___", state 202, "((write_lock==0))"
+       line 646, "pan.___", state 202, "else"
+       line 644, "pan.___", state 203, "(1)"
+       line 160, "pan.___", state 209, "(1)"
+       line 164, "pan.___", state 217, "(1)"
+       line 164, "pan.___", state 218, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 164, "pan.___", state 218, "else"
+       line 162, "pan.___", state 223, "((j<1))"
+       line 162, "pan.___", state 223, "((j>=1))"
+       line 168, "pan.___", state 229, "(1)"
+       line 168, "pan.___", state 230, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 168, "pan.___", state 230, "else"
+       line 160, "pan.___", state 241, "(1)"
+       line 168, "pan.___", state 261, "(1)"
+       line 160, "pan.___", state 277, "(1)"
+       line 164, "pan.___", state 285, "(1)"
+       line 168, "pan.___", state 297, "(1)"
+       line 399, "pan.___", state 311, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 325, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 343, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 356, "(1)"
+       line 413, "pan.___", state 369, "(1)"
+       line 418, "pan.___", state 386, "(1)"
+       line 399, "pan.___", state 405, "(1)"
+       line 403, "pan.___", state 417, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 435, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 461, "(1)"
+       line 418, "pan.___", state 478, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 164, "pan.___", state 594, "(1)"
+       line 168, "pan.___", state 606, "(1)"
+       line 160, "pan.___", state 618, "(1)"
+       line 168, "pan.___", state 638, "(1)"
+       line 164, "pan.___", state 662, "(1)"
+       line 168, "pan.___", state 674, "(1)"
+       line 399, "pan.___", state 696, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 698, "(1)"
+       line 399, "pan.___", state 699, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 699, "else"
+       line 399, "pan.___", state 702, "(1)"
+       line 403, "pan.___", state 710, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 712, "(1)"
+       line 403, "pan.___", state 713, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 713, "else"
+       line 403, "pan.___", state 716, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 403, "pan.___", state 717, "(1)"
+       line 401, "pan.___", state 722, "((i<1))"
+       line 401, "pan.___", state 722, "((i>=1))"
+       line 408, "pan.___", state 728, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 741, "(1)"
+       line 409, "pan.___", state 742, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 742, "else"
+       line 409, "pan.___", state 745, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 409, "pan.___", state 746, "(1)"
+       line 413, "pan.___", state 754, "(1)"
+       line 413, "pan.___", state 755, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 755, "else"
+       line 413, "pan.___", state 758, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 413, "pan.___", state 759, "(1)"
+       line 411, "pan.___", state 764, "((i<1))"
+       line 411, "pan.___", state 764, "((i>=1))"
+       line 418, "pan.___", state 771, "(1)"
+       line 418, "pan.___", state 772, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 772, "else"
+       line 418, "pan.___", state 775, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 418, "pan.___", state 776, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 420, "pan.___", state 779, "(1)"
+       line 403, "pan.___", state 810, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 828, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 854, "(1)"
+       line 418, "pan.___", state 871, "(1)"
+       line 403, "pan.___", state 900, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 918, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 944, "(1)"
+       line 418, "pan.___", state 961, "(1)"
+       line 399, "pan.___", state 980, "(1)"
+       line 403, "pan.___", state 992, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1010, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1036, "(1)"
+       line 418, "pan.___", state 1053, "(1)"
+       line 403, "pan.___", state 1085, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1103, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1129, "(1)"
+       line 418, "pan.___", state 1146, "(1)"
+       line 164, "pan.___", state 1169, "(1)"
+       line 168, "pan.___", state 1181, "(1)"
+       line 160, "pan.___", state 1193, "(1)"
+       line 168, "pan.___", state 1213, "(1)"
+       line 164, "pan.___", state 1237, "(1)"
+       line 168, "pan.___", state 1249, "(1)"
+       line 399, "pan.___", state 1271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1273, "(1)"
+       line 399, "pan.___", state 1274, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1274, "else"
+       line 399, "pan.___", state 1277, "(1)"
+       line 403, "pan.___", state 1285, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1287, "(1)"
+       line 403, "pan.___", state 1288, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1288, "else"
+       line 403, "pan.___", state 1291, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 403, "pan.___", state 1292, "(1)"
+       line 401, "pan.___", state 1297, "((i<1))"
+       line 401, "pan.___", state 1297, "((i>=1))"
+       line 408, "pan.___", state 1303, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1316, "(1)"
+       line 409, "pan.___", state 1317, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1317, "else"
+       line 409, "pan.___", state 1320, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 409, "pan.___", state 1321, "(1)"
+       line 413, "pan.___", state 1329, "(1)"
+       line 413, "pan.___", state 1330, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1330, "else"
+       line 413, "pan.___", state 1333, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 413, "pan.___", state 1334, "(1)"
+       line 411, "pan.___", state 1339, "((i<1))"
+       line 411, "pan.___", state 1339, "((i>=1))"
+       line 418, "pan.___", state 1346, "(1)"
+       line 418, "pan.___", state 1347, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1347, "else"
+       line 418, "pan.___", state 1350, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 418, "pan.___", state 1351, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 420, "pan.___", state 1354, "(1)"
+       line 164, "pan.___", state 1379, "(1)"
+       line 168, "pan.___", state 1391, "(1)"
+       line 160, "pan.___", state 1403, "(1)"
+       line 168, "pan.___", state 1423, "(1)"
+       line 164, "pan.___", state 1447, "(1)"
+       line 168, "pan.___", state 1459, "(1)"
+       line 702, "pan.___", state 1484, "-end-"
+       (160 of 1484 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 0.66 seconds
+pan: rate 123072.73 states/second
+pan: avg transition delay 7.9158e-07 usec
+cp .input.spin urcu_free_no_wmb.spin.input
+cp .input.spin.trail urcu_free_no_wmb.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input
new file mode 100644 (file)
index 0000000..df3cc4b
--- /dev/null
@@ -0,0 +1,723 @@
+#define NO_WMB
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free_no_wmb.spin.input.trail
new file mode 100644 (file)
index 0000000..fe987f0
--- /dev/null
@@ -0,0 +1,1617 @@
+-2:3:-2
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.define b/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.define
new file mode 100644 (file)
index 0000000..5e642ef
--- /dev/null
@@ -0,0 +1 @@
+#define SINGLE_FLIP
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.log b/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.log
new file mode 100644 (file)
index 0000000..16843a5
--- /dev/null
@@ -0,0 +1,197 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define >> pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_free.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_free_single_flip.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+pan: claim violated! (at depth 1316)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness disabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 2045, errors: 1
+    52434 states, stored
+   479392 states, matched
+   531826 transitions (= stored+matched)
+  1926196 atomic steps
+hash conflicts:      6594 (resolved)
+
+Stats on memory usage (in Megabytes):
+    4.200      equivalent memory usage for states (stored*(State-vector + overhead))
+    3.608      actual memory usage for states (compression: 85.89%)
+               state-vector as stored = 44 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  469.279      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 179, "pan.___", state 990, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1003, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1013, "(1)"
+       line 164, "pan.___", state 1021, "(1)"
+       line 168, "pan.___", state 1033, "(1)"
+       line 175, "pan.___", state 1044, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1066, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1076, "(1)"
+       line 164, "pan.___", state 1084, "(1)"
+       line 168, "pan.___", state 1096, "(1)"
+       line 175, "pan.___", state 1111, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1120, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1133, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1143, "(1)"
+       line 164, "pan.___", state 1151, "(1)"
+       line 168, "pan.___", state 1163, "(1)"
+       line 702, "pan.___", state 1188, "-end-"
+       (100 of 1188 states)
+unreached in proctype :init:
+       line 709, "pan.___", state 9, "((j<2))"
+       line 709, "pan.___", state 9, "((j>=2))"
+       line 710, "pan.___", state 20, "((j<2))"
+       line 710, "pan.___", state 20, "((j>=2))"
+       line 715, "pan.___", state 33, "((j<2))"
+       line 715, "pan.___", state 33, "((j>=2))"
+       (3 of 46 states)
+unreached in proctype :never:
+       line 749, "pan.___", state 8, "-end-"
+       (1 of 8 states)
+
+pan: elapsed time 0.43 seconds
+pan: rate 121939.53 states/second
+pan: avg transition delay 8.0854e-07 usec
+cp .input.spin urcu_free_single_flip.spin.input
+cp .input.spin.trail urcu_free_single_flip.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input
new file mode 100644 (file)
index 0000000..bb95a2d
--- /dev/null
@@ -0,0 +1,723 @@
+#define SINGLE_FLIP
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_free_single_flip.spin.input.trail
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress.ltl b/formal-model/urcu/result-standard-execution-nonest/urcu_progress.ltl
new file mode 100644 (file)
index 0000000..8718641
--- /dev/null
@@ -0,0 +1 @@
+([] <> !np_)
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.define b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.define
new file mode 100644 (file)
index 0000000..ff3f783
--- /dev/null
@@ -0,0 +1 @@
+#define READER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.log b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.log
new file mode 100644 (file)
index 0000000..8835ef4
--- /dev/null
@@ -0,0 +1,264 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_reader.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 1767: Claim reached state 9 (line 748)
+Depth=    2582 States=    1e+06 Transitions= 1.91e+07 Memory=   498.674        t=   16.1 R=   6e+04
+Depth=    2582 States=    2e+06 Transitions= 3.89e+07 Memory=   531.096        t=     33 R=   6e+04
+Depth=    2582 States=    3e+06 Transitions= 5.89e+07 Memory=   563.518        t=   50.5 R=   6e+04
+pan: resizing hashtable to -w22..  done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 2582, errors: 0
+  1743405 states, stored (3.27749e+06 visited)
+ 60942540 states, matched
+ 64220033 transitions (= visited+matched)
+2.3877948e+08 atomic steps
+hash conflicts:  25318829 (resolved)
+
+Stats on memory usage (in Megabytes):
+  139.662      equivalent memory usage for states (stored*(State-vector + overhead))
+  113.924      actual memory usage for states (compression: 81.57%)
+               state-vector as stored = 41 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  603.623      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 55.3 seconds
+pan: rate 59256.789 states/second
+pan: avg transition delay 8.6126e-07 usec
+cp .input.spin urcu_progress_reader.spin.input
+cp .input.spin.trail urcu_progress_reader.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input
new file mode 100644 (file)
index 0000000..7e6b28a
--- /dev/null
@@ -0,0 +1,723 @@
+#define READER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_reader.spin.input.trail
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diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.define b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.define
new file mode 100644 (file)
index 0000000..1e4417f
--- /dev/null
@@ -0,0 +1 @@
+#define WRITER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.log b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.log
new file mode 100644 (file)
index 0000000..be944b5
--- /dev/null
@@ -0,0 +1,264 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 744)
+depth 15: Claim reached state 9 (line 749)
+depth 205: Claim reached state 9 (line 748)
+Depth=    2535 States=    1e+06 Transitions=  1.7e+07 Memory=   489.885        t=   14.4 R=   7e+04
+Depth=    2535 States=    2e+06 Transitions= 3.76e+07 Memory=   523.186        t=     32 R=   6e+04
+Depth=    2535 States=    3e+06 Transitions= 5.78e+07 Memory=   555.901        t=   49.6 R=   6e+04
+pan: resizing hashtable to -w22..  done
+
+(Spin Version 5.1.7 -- 23 December 2008)
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 2535, errors: 0
+  1687360 states, stored (3.30264e+06 visited)
+ 60975458 states, matched
+ 64278093 transitions (= visited+matched)
+2.3918285e+08 atomic steps
+hash conflicts:  20728375 (resolved)
+
+Stats on memory usage (in Megabytes):
+  135.172      equivalent memory usage for states (stored*(State-vector + overhead))
+  110.532      actual memory usage for states (compression: 81.77%)
+               state-vector as stored = 41 byte + 28 byte overhead
+   32.000      memory used for hash table (-w22)
+  457.764      memory used for DFS stack (-m10000000)
+  600.205      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 399, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 61, "(1)"
+       line 418, "pan.___", state 91, "(1)"
+       line 399, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 151, "(1)"
+       line 418, "pan.___", state 181, "(1)"
+       line 399, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 242, "(1)"
+       line 418, "pan.___", state 272, "(1)"
+       line 399, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 360, "(1)"
+       line 418, "pan.___", state 390, "(1)"
+       line 540, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 399, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 59, "(1)"
+       line 413, "pan.___", state 72, "(1)"
+       line 418, "pan.___", state 89, "(1)"
+       line 399, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 153, "(1)"
+       line 413, "pan.___", state 166, "(1)"
+       line 652, "pan.___", state 199, "(1)"
+       line 175, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 240, "(1)"
+       line 164, "pan.___", state 248, "(1)"
+       line 168, "pan.___", state 260, "(1)"
+       line 175, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 303, "(1)"
+       line 164, "pan.___", state 311, "(1)"
+       line 168, "pan.___", state 323, "(1)"
+       line 175, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 370, "(1)"
+       line 164, "pan.___", state 378, "(1)"
+       line 168, "pan.___", state 390, "(1)"
+       line 399, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 449, "(1)"
+       line 413, "pan.___", state 462, "(1)"
+       line 418, "pan.___", state 479, "(1)"
+       line 399, "pan.___", state 498, "(1)"
+       line 403, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 554, "(1)"
+       line 418, "pan.___", state 571, "(1)"
+       line 403, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 647, "(1)"
+       line 418, "pan.___", state 664, "(1)"
+       line 179, "pan.___", state 687, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 700, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 710, "(1)"
+       line 164, "pan.___", state 718, "(1)"
+       line 168, "pan.___", state 730, "(1)"
+       line 175, "pan.___", state 741, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 763, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 773, "(1)"
+       line 164, "pan.___", state 781, "(1)"
+       line 168, "pan.___", state 793, "(1)"
+       line 175, "pan.___", state 808, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 817, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 830, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 840, "(1)"
+       line 164, "pan.___", state 848, "(1)"
+       line 168, "pan.___", state 860, "(1)"
+       line 399, "pan.___", state 882, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 884, "(1)"
+       line 399, "pan.___", state 885, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 885, "else"
+       line 399, "pan.___", state 888, "(1)"
+       line 403, "pan.___", state 896, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 898, "(1)"
+       line 403, "pan.___", state 899, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 899, "else"
+       line 403, "pan.___", state 902, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 403, "pan.___", state 903, "(1)"
+       line 401, "pan.___", state 908, "((i<1))"
+       line 401, "pan.___", state 908, "((i>=1))"
+       line 408, "pan.___", state 914, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 927, "(1)"
+       line 409, "pan.___", state 928, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 928, "else"
+       line 409, "pan.___", state 931, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 409, "pan.___", state 932, "(1)"
+       line 413, "pan.___", state 940, "(1)"
+       line 413, "pan.___", state 941, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 941, "else"
+       line 413, "pan.___", state 944, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 413, "pan.___", state 945, "(1)"
+       line 411, "pan.___", state 950, "((i<1))"
+       line 411, "pan.___", state 950, "((i>=1))"
+       line 418, "pan.___", state 957, "(1)"
+       line 418, "pan.___", state 958, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 958, "else"
+       line 418, "pan.___", state 961, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 418, "pan.___", state 962, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 420, "pan.___", state 965, "(1)"
+       line 403, "pan.___", state 996, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1014, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1040, "(1)"
+       line 418, "pan.___", state 1057, "(1)"
+       line 403, "pan.___", state 1086, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1104, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1130, "(1)"
+       line 418, "pan.___", state 1147, "(1)"
+       line 399, "pan.___", state 1166, "(1)"
+       line 403, "pan.___", state 1178, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1196, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1222, "(1)"
+       line 418, "pan.___", state 1239, "(1)"
+       line 403, "pan.___", state 1271, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 408, "pan.___", state 1289, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 413, "pan.___", state 1315, "(1)"
+       line 418, "pan.___", state 1332, "(1)"
+       line 179, "pan.___", state 1355, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1368, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1378, "(1)"
+       line 164, "pan.___", state 1386, "(1)"
+       line 168, "pan.___", state 1398, "(1)"
+       line 175, "pan.___", state 1409, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1431, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1441, "(1)"
+       line 164, "pan.___", state 1449, "(1)"
+       line 168, "pan.___", state 1461, "(1)"
+       line 175, "pan.___", state 1476, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1485, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1498, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1508, "(1)"
+       line 164, "pan.___", state 1516, "(1)"
+       line 168, "pan.___", state 1528, "(1)"
+       line 399, "pan.___", state 1550, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 399, "pan.___", state 1552, "(1)"
+       line 399, "pan.___", state 1553, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 399, "pan.___", state 1553, "else"
+       line 399, "pan.___", state 1556, "(1)"
+       line 403, "pan.___", state 1564, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 403, "pan.___", state 1566, "(1)"
+       line 403, "pan.___", state 1567, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 403, "pan.___", state 1567, "else"
+       line 403, "pan.___", state 1570, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 403, "pan.___", state 1571, "(1)"
+       line 401, "pan.___", state 1576, "((i<1))"
+       line 401, "pan.___", state 1576, "((i>=1))"
+       line 408, "pan.___", state 1582, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1595, "(1)"
+       line 409, "pan.___", state 1596, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 409, "pan.___", state 1596, "else"
+       line 409, "pan.___", state 1599, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 409, "pan.___", state 1600, "(1)"
+       line 413, "pan.___", state 1608, "(1)"
+       line 413, "pan.___", state 1609, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 413, "pan.___", state 1609, "else"
+       line 413, "pan.___", state 1612, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 413, "pan.___", state 1613, "(1)"
+       line 411, "pan.___", state 1618, "((i<1))"
+       line 411, "pan.___", state 1618, "((i>=1))"
+       line 418, "pan.___", state 1625, "(1)"
+       line 418, "pan.___", state 1626, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 418, "pan.___", state 1626, "else"
+       line 418, "pan.___", state 1629, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 418, "pan.___", state 1630, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 420, "pan.___", state 1633, "(1)"
+       line 179, "pan.___", state 1658, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1671, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1681, "(1)"
+       line 164, "pan.___", state 1689, "(1)"
+       line 168, "pan.___", state 1701, "(1)"
+       line 175, "pan.___", state 1712, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 183, "pan.___", state 1734, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 160, "pan.___", state 1744, "(1)"
+       line 164, "pan.___", state 1752, "(1)"
+       line 168, "pan.___", state 1764, "(1)"
+       line 175, "pan.___", state 1779, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 179, "pan.___", state 1788, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 183, "pan.___", state 1801, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 160, "pan.___", state 1811, "(1)"
+       line 164, "pan.___", state 1819, "(1)"
+       line 168, "pan.___", state 1831, "(1)"
+       line 702, "pan.___", state 1856, "-end-"
+       (158 of 1856 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 751, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 55.4 seconds
+pan: rate 59582.086 states/second
+pan: avg transition delay 8.6235e-07 usec
+cp .input.spin urcu_progress_writer.spin.input
+cp .input.spin.trail urcu_progress_writer.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input
new file mode 100644 (file)
index 0000000..84739c0
--- /dev/null
@@ -0,0 +1,723 @@
+#define WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer.spin.input.trail
new file mode 100644 (file)
index 0000000..e65d663
--- /dev/null
@@ -0,0 +1,9 @@
+-2:3:-2
+-4:-4:-4
+1:0:2679
+2:1:2673
+3:1:2674
+4:1:2675
+5:1:2676
+6:0:2685
+7:5:1129
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.define b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.define
new file mode 100644 (file)
index 0000000..8d304f5
--- /dev/null
@@ -0,0 +1,2 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.log b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.log
new file mode 100644 (file)
index 0000000..80c9c6d
--- /dev/null
@@ -0,0 +1,514 @@
+make[1]: Entering directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
+rm -f pan* trail.out .input.spin* *.spin.trail .input.define
+touch .input.define
+cat .input.define > pan.ltl
+cat DEFINES >> pan.ltl
+spin -f "!(`cat urcu_progress.ltl | grep -v ^//`)" >> pan.ltl
+cp urcu_progress_writer_error.define .input.define
+cat .input.define > .input.spin
+cat DEFINES >> .input.spin
+cat urcu.spin >> .input.spin
+rm -f .input.spin.trail
+spin -a -X -N pan.ltl .input.spin
+Exit-Status 0
+gcc -O2 -w -DHASH64 -o pan pan.c
+./pan -a -f -v -c1 -X -m10000000 -w20
+warning: for p.o. reduction to be valid the never claim must be stutter-invariant
+(never claims generated from LTL formulae are stutter-invariant)
+depth 0: Claim reached state 5 (line 745)
+depth 15: Claim reached state 9 (line 750)
+depth 205: Claim reached state 9 (line 749)
+pan: acceptance cycle (at depth 1651)
+pan: wrote .input.spin.trail
+
+(Spin Version 5.1.7 -- 23 December 2008)
+Warning: Search not completed
+       + Partial Order Reduction
+
+Full statespace search for:
+       never claim             +
+       assertion violations    + (if within scope of claim)
+       acceptance   cycles     + (fairness enabled)
+       invalid end states      - (disabled by never claim)
+
+State-vector 56 byte, depth reached 3006, errors: 1
+    19244 states, stored (53713 visited)
+   704248 states, matched
+   757961 transitions (= visited+matched)
+  2831420 atomic steps
+hash conflicts:      5063 (resolved)
+
+Stats on memory usage (in Megabytes):
+    1.542      equivalent memory usage for states (stored*(State-vector + overhead))
+    1.605      actual memory usage for states (unsuccessful compression: 104.14%)
+               state-vector as stored = 59 byte + 28 byte overhead
+    8.000      memory used for hash table (-w20)
+  457.764      memory used for DFS stack (-m10000000)
+  467.326      total actual memory usage
+
+unreached in proctype urcu_reader
+       line 400, "pan.___", state 16, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 48, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 61, "(1)"
+       line 419, "pan.___", state 91, "(1)"
+       line 400, "pan.___", state 106, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 138, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 151, "(1)"
+       line 419, "pan.___", state 181, "(1)"
+       line 400, "pan.___", state 197, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 229, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 242, "(1)"
+       line 419, "pan.___", state 272, "(1)"
+       line 400, "pan.___", state 315, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 347, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 360, "(1)"
+       line 419, "pan.___", state 390, "(1)"
+       line 541, "pan.___", state 414, "-end-"
+       (17 of 414 states)
+unreached in proctype urcu_writer
+       line 400, "pan.___", state 14, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 20, "(1)"
+       line 404, "pan.___", state 28, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 34, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 404, "pan.___", state 35, "(1)"
+       line 402, "pan.___", state 40, "((i<1))"
+       line 402, "pan.___", state 40, "((i>=1))"
+       line 409, "pan.___", state 46, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 59, "(1)"
+       line 410, "pan.___", state 60, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 60, "else"
+       line 410, "pan.___", state 63, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 410, "pan.___", state 64, "(1)"
+       line 414, "pan.___", state 72, "(1)"
+       line 414, "pan.___", state 73, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 73, "else"
+       line 414, "pan.___", state 76, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 414, "pan.___", state 77, "(1)"
+       line 412, "pan.___", state 82, "((i<1))"
+       line 412, "pan.___", state 82, "((i>=1))"
+       line 419, "pan.___", state 89, "(1)"
+       line 419, "pan.___", state 90, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 90, "else"
+       line 419, "pan.___", state 93, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 419, "pan.___", state 94, "(1)"
+       line 370, "pan.___", state 99, "(1)"
+       line 640, "pan.___", state 103, "cached_generation_ptr.val[_pid] = (old_gen+1)"
+       line 638, "pan.___", state 104, "old_gen = cached_generation_ptr.val[_pid]"
+       line 400, "pan.___", state 108, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 114, "(1)"
+       line 404, "pan.___", state 122, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 128, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 404, "pan.___", state 129, "(1)"
+       line 402, "pan.___", state 134, "((i<1))"
+       line 402, "pan.___", state 134, "((i>=1))"
+       line 410, "pan.___", state 153, "(1)"
+       line 410, "pan.___", state 154, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 154, "else"
+       line 410, "pan.___", state 157, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 410, "pan.___", state 158, "(1)"
+       line 414, "pan.___", state 166, "(1)"
+       line 414, "pan.___", state 167, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 167, "else"
+       line 414, "pan.___", state 170, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 414, "pan.___", state 171, "(1)"
+       line 412, "pan.___", state 176, "((i<1))"
+       line 412, "pan.___", state 176, "((i>=1))"
+       line 419, "pan.___", state 183, "(1)"
+       line 419, "pan.___", state 184, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 184, "else"
+       line 419, "pan.___", state 187, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 419, "pan.___", state 188, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 421, "pan.___", state 191, "(1)"
+       line 370, "pan.___", state 193, "(1)"
+       line 653, "pan.___", state 199, "(1)"
+       line 647, "pan.___", state 202, "((write_lock==0))"
+       line 647, "pan.___", state 202, "else"
+       line 645, "pan.___", state 203, "(1)"
+       line 176, "pan.___", state 208, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 217, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 225, "((j<1))"
+       line 178, "pan.___", state 225, "((j>=1))"
+       line 184, "pan.___", state 230, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 240, "(1)"
+       line 165, "pan.___", state 248, "(1)"
+       line 165, "pan.___", state 249, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 165, "pan.___", state 249, "else"
+       line 163, "pan.___", state 254, "((j<1))"
+       line 163, "pan.___", state 254, "((j>=1))"
+       line 169, "pan.___", state 260, "(1)"
+       line 169, "pan.___", state 261, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 169, "pan.___", state 261, "else"
+       line 171, "pan.___", state 264, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 171, "pan.___", state 264, "else"
+       line 176, "pan.___", state 271, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 180, "pan.___", state 280, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<i)))"
+       line 178, "pan.___", state 288, "((j<1))"
+       line 178, "pan.___", state 288, "((j>=1))"
+       line 184, "pan.___", state 293, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 303, "(1)"
+       line 165, "pan.___", state 311, "(1)"
+       line 165, "pan.___", state 312, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<i))))"
+       line 165, "pan.___", state 312, "else"
+       line 163, "pan.___", state 317, "((j<1))"
+       line 163, "pan.___", state 317, "((j>=1))"
+       line 169, "pan.___", state 323, "(1)"
+       line 169, "pan.___", state 324, "(!((cache_dirty_generation_ptr.bitfield&(1<<i))))"
+       line 169, "pan.___", state 324, "else"
+       line 171, "pan.___", state 327, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<i))))"
+       line 171, "pan.___", state 327, "else"
+       line 215, "pan.___", state 333, "((i<1))"
+       line 215, "pan.___", state 333, "((i>=1))"
+       line 176, "pan.___", state 338, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 347, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 178, "pan.___", state 355, "((j<1))"
+       line 178, "pan.___", state 355, "((j>=1))"
+       line 184, "pan.___", state 360, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 370, "(1)"
+       line 165, "pan.___", state 378, "(1)"
+       line 165, "pan.___", state 379, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 165, "pan.___", state 379, "else"
+       line 163, "pan.___", state 384, "((j<1))"
+       line 163, "pan.___", state 384, "((j>=1))"
+       line 169, "pan.___", state 390, "(1)"
+       line 169, "pan.___", state 391, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 169, "pan.___", state 391, "else"
+       line 171, "pan.___", state 394, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 171, "pan.___", state 394, "else"
+       line 400, "pan.___", state 404, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 410, "(1)"
+       line 404, "pan.___", state 418, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 424, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 404, "pan.___", state 425, "(1)"
+       line 402, "pan.___", state 430, "((i<1))"
+       line 402, "pan.___", state 430, "((i>=1))"
+       line 409, "pan.___", state 436, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 449, "(1)"
+       line 410, "pan.___", state 450, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 450, "else"
+       line 410, "pan.___", state 453, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 410, "pan.___", state 454, "(1)"
+       line 414, "pan.___", state 462, "(1)"
+       line 414, "pan.___", state 463, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 463, "else"
+       line 414, "pan.___", state 466, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 414, "pan.___", state 467, "(1)"
+       line 412, "pan.___", state 472, "((i<1))"
+       line 412, "pan.___", state 472, "((i>=1))"
+       line 419, "pan.___", state 479, "(1)"
+       line 419, "pan.___", state 480, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 480, "else"
+       line 419, "pan.___", state 483, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 419, "pan.___", state 484, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 421, "pan.___", state 487, "(1)"
+       line 370, "pan.___", state 489, "(1)"
+       line 662, "pan.___", state 492, "cached_urcu_gp_ctr.val[_pid] = (tmp^(1<<7))"
+       line 400, "pan.___", state 498, "(1)"
+       line 400, "pan.___", state 499, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 499, "else"
+       line 400, "pan.___", state 502, "(1)"
+       line 404, "pan.___", state 510, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 516, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 404, "pan.___", state 517, "(1)"
+       line 402, "pan.___", state 522, "((i<1))"
+       line 402, "pan.___", state 522, "((i>=1))"
+       line 409, "pan.___", state 528, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 541, "(1)"
+       line 410, "pan.___", state 542, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 542, "else"
+       line 410, "pan.___", state 545, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 410, "pan.___", state 546, "(1)"
+       line 414, "pan.___", state 554, "(1)"
+       line 414, "pan.___", state 555, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 555, "else"
+       line 414, "pan.___", state 558, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 414, "pan.___", state 559, "(1)"
+       line 412, "pan.___", state 564, "((i<1))"
+       line 412, "pan.___", state 564, "((i>=1))"
+       line 419, "pan.___", state 571, "(1)"
+       line 419, "pan.___", state 572, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 572, "else"
+       line 419, "pan.___", state 575, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 419, "pan.___", state 576, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 421, "pan.___", state 579, "(1)"
+       line 370, "pan.___", state 581, "(1)"
+       line 400, "pan.___", state 589, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 595, "(1)"
+       line 404, "pan.___", state 603, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 609, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 404, "pan.___", state 610, "(1)"
+       line 402, "pan.___", state 615, "((i<1))"
+       line 402, "pan.___", state 615, "((i>=1))"
+       line 409, "pan.___", state 621, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 634, "(1)"
+       line 410, "pan.___", state 635, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 635, "else"
+       line 410, "pan.___", state 638, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 410, "pan.___", state 639, "(1)"
+       line 414, "pan.___", state 647, "(1)"
+       line 414, "pan.___", state 648, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 648, "else"
+       line 414, "pan.___", state 651, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 414, "pan.___", state 652, "(1)"
+       line 412, "pan.___", state 657, "((i<1))"
+       line 412, "pan.___", state 657, "((i>=1))"
+       line 419, "pan.___", state 664, "(1)"
+       line 419, "pan.___", state 665, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 665, "else"
+       line 419, "pan.___", state 668, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 419, "pan.___", state 669, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 421, "pan.___", state 672, "(1)"
+       line 370, "pan.___", state 674, "(1)"
+       line 400, "pan.___", state 679, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 681, "(1)"
+       line 400, "pan.___", state 682, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 682, "else"
+       line 400, "pan.___", state 685, "(1)"
+       line 404, "pan.___", state 693, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 695, "(1)"
+       line 404, "pan.___", state 696, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 696, "else"
+       line 404, "pan.___", state 699, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 404, "pan.___", state 700, "(1)"
+       line 402, "pan.___", state 705, "((i<1))"
+       line 402, "pan.___", state 705, "((i>=1))"
+       line 409, "pan.___", state 711, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 724, "(1)"
+       line 410, "pan.___", state 725, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 725, "else"
+       line 410, "pan.___", state 728, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 410, "pan.___", state 729, "(1)"
+       line 414, "pan.___", state 737, "(1)"
+       line 414, "pan.___", state 738, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 738, "else"
+       line 414, "pan.___", state 741, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 414, "pan.___", state 742, "(1)"
+       line 412, "pan.___", state 747, "((i<1))"
+       line 412, "pan.___", state 747, "((i>=1))"
+       line 419, "pan.___", state 754, "(1)"
+       line 419, "pan.___", state 755, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 755, "else"
+       line 419, "pan.___", state 758, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 419, "pan.___", state 759, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 421, "pan.___", state 762, "(1)"
+       line 370, "pan.___", state 764, "(1)"
+       line 430, "pan.___", state 767, "(((tmp2&((1<<7)-1))&&((tmp2^cached_urcu_gp_ctr.val[_pid])&(1<<7))))"
+       line 430, "pan.___", state 767, "else"
+       line 400, "pan.___", state 777, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 779, "(1)"
+       line 400, "pan.___", state 780, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 780, "else"
+       line 400, "pan.___", state 783, "(1)"
+       line 404, "pan.___", state 791, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 793, "(1)"
+       line 404, "pan.___", state 794, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 794, "else"
+       line 404, "pan.___", state 797, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 404, "pan.___", state 798, "(1)"
+       line 402, "pan.___", state 803, "((i<1))"
+       line 402, "pan.___", state 803, "((i>=1))"
+       line 409, "pan.___", state 809, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 822, "(1)"
+       line 410, "pan.___", state 823, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 823, "else"
+       line 410, "pan.___", state 826, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 410, "pan.___", state 827, "(1)"
+       line 414, "pan.___", state 835, "(1)"
+       line 414, "pan.___", state 836, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 836, "else"
+       line 414, "pan.___", state 839, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 414, "pan.___", state 840, "(1)"
+       line 412, "pan.___", state 845, "((i<1))"
+       line 412, "pan.___", state 845, "((i>=1))"
+       line 419, "pan.___", state 852, "(1)"
+       line 419, "pan.___", state 853, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 853, "else"
+       line 419, "pan.___", state 856, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 419, "pan.___", state 857, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 421, "pan.___", state 860, "(1)"
+       line 370, "pan.___", state 862, "(1)"
+       line 449, "pan.___", state 870, "((tmp<1))"
+       line 449, "pan.___", state 870, "((tmp>=1))"
+       line 462, "pan.___", state 873, "tmp = 0"
+       line 400, "pan.___", state 877, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 883, "(1)"
+       line 404, "pan.___", state 891, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 897, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 404, "pan.___", state 898, "(1)"
+       line 402, "pan.___", state 903, "((i<1))"
+       line 402, "pan.___", state 903, "((i>=1))"
+       line 409, "pan.___", state 909, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 922, "(1)"
+       line 410, "pan.___", state 923, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 923, "else"
+       line 410, "pan.___", state 926, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 410, "pan.___", state 927, "(1)"
+       line 414, "pan.___", state 935, "(1)"
+       line 414, "pan.___", state 936, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 936, "else"
+       line 414, "pan.___", state 939, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 414, "pan.___", state 940, "(1)"
+       line 412, "pan.___", state 945, "((i<1))"
+       line 412, "pan.___", state 945, "((i>=1))"
+       line 419, "pan.___", state 952, "(1)"
+       line 419, "pan.___", state 953, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 953, "else"
+       line 419, "pan.___", state 956, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 419, "pan.___", state 957, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 421, "pan.___", state 960, "(1)"
+       line 370, "pan.___", state 962, "(1)"
+       line 671, "pan.___", state 963, "tmp = cached_urcu_gp_ctr.val[_pid]"
+       line 400, "pan.___", state 967, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 973, "(1)"
+       line 404, "pan.___", state 981, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 987, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 404, "pan.___", state 988, "(1)"
+       line 402, "pan.___", state 993, "((i<1))"
+       line 402, "pan.___", state 993, "((i>=1))"
+       line 409, "pan.___", state 999, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1012, "(1)"
+       line 410, "pan.___", state 1013, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1013, "else"
+       line 410, "pan.___", state 1016, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 410, "pan.___", state 1017, "(1)"
+       line 414, "pan.___", state 1025, "(1)"
+       line 414, "pan.___", state 1026, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1026, "else"
+       line 414, "pan.___", state 1029, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 414, "pan.___", state 1030, "(1)"
+       line 412, "pan.___", state 1035, "((i<1))"
+       line 412, "pan.___", state 1035, "((i>=1))"
+       line 419, "pan.___", state 1042, "(1)"
+       line 419, "pan.___", state 1043, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1043, "else"
+       line 419, "pan.___", state 1046, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 419, "pan.___", state 1047, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 421, "pan.___", state 1050, "(1)"
+       line 370, "pan.___", state 1052, "(1)"
+       line 400, "pan.___", state 1061, "(1)"
+       line 404, "pan.___", state 1073, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1091, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1117, "(1)"
+       line 419, "pan.___", state 1134, "(1)"
+       line 404, "pan.___", state 1166, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1184, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 414, "pan.___", state 1210, "(1)"
+       line 419, "pan.___", state 1227, "(1)"
+       line 400, "pan.___", state 1242, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1256, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 409, "pan.___", state 1274, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1287, "(1)"
+       line 414, "pan.___", state 1300, "(1)"
+       line 419, "pan.___", state 1317, "(1)"
+       line 400, "pan.___", state 1340, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 400, "pan.___", state 1342, "(1)"
+       line 400, "pan.___", state 1343, "((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid)))"
+       line 400, "pan.___", state 1343, "else"
+       line 400, "pan.___", state 1346, "(1)"
+       line 404, "pan.___", state 1354, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 404, "pan.___", state 1356, "(1)"
+       line 404, "pan.___", state 1357, "((cache_dirty_urcu_active_readers.bitfield&(1<<_pid)))"
+       line 404, "pan.___", state 1357, "else"
+       line 404, "pan.___", state 1360, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 404, "pan.___", state 1361, "(1)"
+       line 402, "pan.___", state 1366, "((i<1))"
+       line 402, "pan.___", state 1366, "((i>=1))"
+       line 409, "pan.___", state 1372, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 410, "pan.___", state 1385, "(1)"
+       line 410, "pan.___", state 1386, "(!((cache_dirty_urcu_gp_ctr.bitfield&(1<<_pid))))"
+       line 410, "pan.___", state 1386, "else"
+       line 410, "pan.___", state 1389, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 410, "pan.___", state 1390, "(1)"
+       line 414, "pan.___", state 1398, "(1)"
+       line 414, "pan.___", state 1399, "(!((cache_dirty_urcu_active_readers.bitfield&(1<<_pid))))"
+       line 414, "pan.___", state 1399, "else"
+       line 414, "pan.___", state 1402, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 414, "pan.___", state 1403, "(1)"
+       line 412, "pan.___", state 1408, "((i<1))"
+       line 412, "pan.___", state 1408, "((i>=1))"
+       line 419, "pan.___", state 1415, "(1)"
+       line 419, "pan.___", state 1416, "(!((cache_dirty_generation_ptr.bitfield&(1<<_pid))))"
+       line 419, "pan.___", state 1416, "else"
+       line 419, "pan.___", state 1419, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 419, "pan.___", state 1420, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 421, "pan.___", state 1423, "(1)"
+       line 180, "pan.___", state 1448, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 184, "pan.___", state 1461, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 1471, "(1)"
+       line 165, "pan.___", state 1479, "(1)"
+       line 169, "pan.___", state 1491, "(1)"
+       line 176, "pan.___", state 1502, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<i)))"
+       line 184, "pan.___", state 1524, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<i)))"
+       line 161, "pan.___", state 1534, "(1)"
+       line 165, "pan.___", state 1542, "(1)"
+       line 169, "pan.___", state 1554, "(1)"
+       line 176, "pan.___", state 1569, "cache_dirty_urcu_gp_ctr.bitfield = (cache_dirty_urcu_gp_ctr.bitfield&~((1<<_pid)))"
+       line 180, "pan.___", state 1578, "cache_dirty_urcu_active_readers.bitfield = (cache_dirty_urcu_active_readers.bitfield&~((1<<_pid)))"
+       line 184, "pan.___", state 1591, "cache_dirty_generation_ptr.bitfield = (cache_dirty_generation_ptr.bitfield&~((1<<_pid)))"
+       line 161, "pan.___", state 1601, "(1)"
+       line 165, "pan.___", state 1609, "(1)"
+       line 169, "pan.___", state 1621, "(1)"
+       line 370, "pan.___", state 1642, "(1)"
+       line 696, "pan.___", state 1643, "(1)"
+       line 703, "pan.___", state 1646, "-end-"
+       (308 of 1646 states)
+unreached in proctype :init:
+       (0 of 46 states)
+unreached in proctype :never:
+       line 752, "pan.___", state 11, "-end-"
+       (1 of 11 states)
+
+pan: elapsed time 0.65 seconds
+pan: rate 82635.385 states/second
+pan: avg transition delay 8.5756e-07 usec
+cp .input.spin urcu_progress_writer_error.spin.input
+cp .input.spin.trail urcu_progress_writer_error.spin.input.trail
+make[1]: Leaving directory `/home/compudj/doc/userspace-rcu/formal-model/urcu'
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input
new file mode 100644 (file)
index 0000000..90957bb
--- /dev/null
@@ -0,0 +1,724 @@
+#define WRITER_PROGRESS
+#define GEN_ERROR_WRITER_PROGRESS
+
+#define read_free_race (read_generation[0] == last_free_gen)
+#define read_free      (free_done && data_access[0])
+
+//#define TEST_SIGNAL
+//#define TEST_SIGNAL_ON_READ
+//#define TEST_SIGNAL_ON_WRITE
+
+#define RCU_GP_CTR_BIT (1 << 7)
+#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
+
+#ifndef READER_NEST_LEVEL
+#define READER_NEST_LEVEL 1
+//#define READER_NEST_LEVEL 2
+#endif
+
+#define REMOTE_BARRIERS
+/*
+ * mem.spin: Promela code to validate memory barriers with OOO memory.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (c) 2009 Mathieu Desnoyers
+ */
+
+/* Promela validation variables. */
+
+/* specific defines "included" here */
+/* DEFINES file "included" here */
+
+/* All signal readers have same PID and uses same reader variable */
+#ifdef TEST_SIGNAL_ON_WRITE
+
+#define NR_READERS 1   /* the writer is also a signal reader */
+#define NR_WRITERS 1
+
+#define NR_PROCS 1
+
+#define get_pid()      (0)
+
+#elif defined(TEST_SIGNAL_ON_READ)
+
+#define get_pid()      ((_pid < 2) -> 0 : 1)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#else
+
+#define get_pid()      (_pid)
+
+#define NR_READERS 1
+#define NR_WRITERS 1
+
+#define NR_PROCS 2
+
+#endif
+
+#define get_readerid() (get_pid())
+
+/*
+ * Each process have its own data in cache. Caches are randomly updated.
+ * smp_wmb and smp_rmb forces cache updates (write and read), smp_mb forces
+ * both.
+ */
+
+typedef per_proc_byte {
+       byte val[NR_PROCS];
+};
+
+/* Bitfield has a maximum of 8 procs */
+typedef per_proc_bit {
+       byte bitfield;
+};
+
+#define DECLARE_CACHED_VAR(type, x)    \
+       type mem_##x;                   \
+       per_proc_##type cached_##x;     \
+       per_proc_bit cache_dirty_##x;
+
+#define INIT_CACHED_VAR(x, v, j)       \
+       mem_##x = v;                    \
+       cache_dirty_##x.bitfield = 0;   \
+       j = 0;                          \
+       do                              \
+       :: j < NR_PROCS ->              \
+               cached_##x.val[j] = v;  \
+               j++                     \
+       :: j >= NR_PROCS -> break       \
+       od;
+
+#define IS_CACHE_DIRTY(x, id)  (cache_dirty_##x.bitfield & (1 << id))
+
+#define READ_CACHED_VAR(x)     (cached_##x.val[get_pid()])
+
+#define WRITE_CACHED_VAR(x, v)                         \
+       atomic {                                        \
+               cached_##x.val[get_pid()] = v;          \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield | (1 << get_pid());    \
+       }
+
+#define CACHE_WRITE_TO_MEM(x, id)                      \
+       if                                              \
+       :: IS_CACHE_DIRTY(x, id) ->                     \
+               mem_##x = cached_##x.val[id];           \
+               cache_dirty_##x.bitfield =              \
+                       cache_dirty_##x.bitfield & (~(1 << id));        \
+       :: else ->                                      \
+               skip                                    \
+       fi;
+
+#define CACHE_READ_FROM_MEM(x, id)     \
+       if                              \
+       :: !IS_CACHE_DIRTY(x, id) ->    \
+               cached_##x.val[id] = mem_##x;\
+       :: else ->                      \
+               skip                    \
+       fi;
+
+/*
+ * May update other caches if cache is dirty, or not.
+ */
+#define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_WRITE_TO_MEM(x, id);      \
+       :: 1 -> skip                    \
+       fi;
+
+#define RANDOM_CACHE_READ_FROM_MEM(x, id)\
+       if                              \
+       :: 1 -> CACHE_READ_FROM_MEM(x, id);     \
+       :: 1 -> skip                    \
+       fi;
+
+/*
+ * Remote barriers tests the scheme where a signal (or IPI) is sent to all
+ * reader threads to promote their compiler barrier to a smp_mb().
+ */
+#ifdef REMOTE_BARRIERS
+
+inline smp_rmb_pid(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_wmb_pid(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
+               j = 0;
+               do
+               :: j < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[j], i);
+                       j++
+               :: j >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, i);
+       }
+}
+
+inline smp_mb_pid(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb_pid(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb_pid(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(j);
+#endif
+#endif
+       }
+}
+
+/*
+ * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
+ * signal or IPI to have all readers execute a smp_mb.
+ * We are not modeling the whole rendez-vous between readers and writers here,
+ * we just let the writer update each reader's caches remotely.
+ */
+inline smp_mb_writer(i, j)
+{
+       smp_mb_pid(get_pid(), j);
+       i = 0;
+       do
+       :: i < NR_READERS ->
+               smp_mb_pid(i, j);
+               i++;
+       :: i >= NR_READERS -> break
+       od;
+       smp_mb_pid(get_pid(), j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       skip;
+}
+
+#else
+
+inline smp_rmb(i, j)
+{
+       atomic {
+               CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_READ_FROM_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_wmb(i, j)
+{
+       atomic {
+               CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       CACHE_WRITE_TO_MEM(urcu_active_readers[i], get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline smp_mb(i, j)
+{
+       atomic {
+#ifndef NO_WMB
+               smp_wmb(i, j);
+#endif
+#ifndef NO_RMB
+               smp_rmb(i, j);
+#endif
+#ifdef NO_WMB
+#ifdef NO_RMB
+               ooo_mem(i);
+#endif
+#endif
+       }
+}
+
+inline smp_mb_writer(i, j)
+{
+       smp_mb(i, j);
+}
+
+inline smp_mb_reader(i, j)
+{
+       smp_mb(i, j);
+}
+
+#endif
+
+/* Keep in sync manually with smp_rmb, wmp_wmb, ooo_mem and init() */
+DECLARE_CACHED_VAR(byte, urcu_gp_ctr);
+/* Note ! currently only two readers */
+DECLARE_CACHED_VAR(byte, urcu_active_readers[NR_READERS]);
+/* pointer generation */
+DECLARE_CACHED_VAR(byte, generation_ptr);
+
+byte last_free_gen = 0;
+bit free_done = 0;
+byte read_generation[NR_READERS];
+bit data_access[NR_READERS];
+
+bit write_lock = 0;
+
+bit init_done = 0;
+
+bit sighand_exec = 0;
+
+inline wait_init_done()
+{
+       do
+       :: init_done == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TEST_SIGNAL
+
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else -> break;
+       od;
+}
+
+#ifdef TOO_BIG_STATE_SPACE
+inline wait_for_sighand_exec()
+{
+       sighand_exec = 0;
+       do
+       :: sighand_exec == 0 -> skip;
+       :: else ->
+               if
+               :: 1 -> break;
+               :: 1 -> sighand_exec = 0;
+                       skip;
+               fi;
+       od;
+}
+#endif
+
+#else
+
+inline wait_for_sighand_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_WRITE
+/* Block on signal handler execution */
+inline dispatch_sighand_write_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_write_exec()
+{
+       skip;
+}
+
+#endif
+
+#ifdef TEST_SIGNAL_ON_READ
+/* Block on signal handler execution */
+inline dispatch_sighand_read_exec()
+{
+       sighand_exec = 1;
+       do
+       :: sighand_exec == 1 ->
+               skip;
+       :: else ->
+               break;
+       od;
+}
+
+#else
+
+inline dispatch_sighand_read_exec()
+{
+       skip;
+}
+
+#endif
+
+
+inline ooo_mem(i)
+{
+       atomic {
+               RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
+               RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers[i],
+                               get_pid());
+                       i++
+               :: i >= NR_READERS -> break
+               od;
+               RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
+       }
+}
+
+inline wait_for_reader(tmp, tmp2, i, j)
+{
+       do
+       :: 1 ->
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[tmp]);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               if
+               :: (tmp2 & RCU_GP_CTR_NEST_MASK)
+                       && ((tmp2 ^ READ_CACHED_VAR(urcu_gp_ctr))
+                               & RCU_GP_CTR_BIT) ->
+#ifndef GEN_ERROR_WRITER_PROGRESS
+                       smp_mb_writer(i, j);
+#else
+                       ooo_mem(i);
+#endif
+                       dispatch_sighand_write_exec();
+               :: else ->
+                       break;
+               fi;
+       od;
+}
+
+inline wait_for_quiescent_state(tmp, tmp2, i, j)
+{
+       tmp = 0;
+       do
+       :: tmp < NR_READERS ->
+               wait_for_reader(tmp, tmp2, i, j);
+               if
+               :: (NR_READERS > 1) && (tmp < NR_READERS - 1)
+                       -> ooo_mem(i);
+                          dispatch_sighand_write_exec();
+               :: else
+                       -> skip;
+               fi;
+               tmp++
+       :: tmp >= NR_READERS -> break
+       od;
+}
+
+/* Model the RCU read-side critical section. */
+
+#ifndef TEST_SIGNAL_ON_WRITE
+
+inline urcu_one_read(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       dispatch_sighand_read_exec();
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               dispatch_sighand_read_exec();
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               dispatch_sighand_read_exec();
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //dispatch_sighand_read_exec();
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif //!TEST_SIGNAL_ON_WRITE
+
+#ifdef TEST_SIGNAL
+/* signal handler reader */
+
+inline urcu_one_read_sig(i, j, nest_i, tmp, tmp2)
+{
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               ooo_mem(i);
+               tmp = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               if
+               :: (!(tmp & RCU_GP_CTR_NEST_MASK))
+                       ->
+                       tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
+                       ooo_mem(i);
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp2);
+               :: else ->
+                       WRITE_CACHED_VAR(urcu_active_readers[get_readerid()],
+                                        tmp + 1);
+               fi;
+               smp_mb_reader(i, j);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+
+       read_generation[get_readerid()] = READ_CACHED_VAR(generation_ptr);
+       data_access[get_readerid()] = 1;
+       data_access[get_readerid()] = 0;
+
+       nest_i = 0;
+       do
+       :: nest_i < READER_NEST_LEVEL ->
+               smp_mb_reader(i, j);
+               tmp2 = READ_CACHED_VAR(urcu_active_readers[get_readerid()]);
+               ooo_mem(i);
+               WRITE_CACHED_VAR(urcu_active_readers[get_readerid()], tmp2 - 1);
+               nest_i++;
+       :: nest_i >= READER_NEST_LEVEL -> break;
+       od;
+       //ooo_mem(i);
+       //smp_mc(i);    /* added */
+}
+
+active proctype urcu_reader_sig()
+{
+       byte i, j, nest_i;
+       byte tmp, tmp2;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+end_reader:
+       do
+       :: 1 ->
+               wait_for_sighand_exec();
+               /*
+                * We do not test reader's progress here, because we are mainly
+                * interested in writer's progress. The reader never blocks
+                * anyway. We have to test for reader/writer's progress
+                * separately, otherwise we could think the writer is doing
+                * progress when it's blocked by an always progressing reader.
+                */
+#ifdef READER_PROGRESS
+progress_reader:
+#endif
+               urcu_one_read_sig(i, j, nest_i, tmp, tmp2);
+       od;
+}
+
+#endif
+
+/* Model the RCU update process. */
+
+active proctype urcu_writer()
+{
+       byte i, j;
+       byte tmp, tmp2;
+       byte old_gen;
+
+       wait_init_done();
+
+       assert(get_pid() < NR_PROCS);
+
+       do
+       :: (READ_CACHED_VAR(generation_ptr) < 5) ->
+#ifdef WRITER_PROGRESS
+progress_writer1:
+#endif
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               atomic {
+                       old_gen = READ_CACHED_VAR(generation_ptr);
+                       WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
+               }
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+
+               do
+               :: 1 ->
+                       atomic {
+                               if
+                               :: write_lock == 0 ->
+                                       write_lock = 1;
+                                       break;
+                               :: else ->
+                                       skip;
+                               fi;
+                       }
+               od;
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               //smp_mc(i);
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+               //smp_mc(i);
+#ifndef SINGLE_FLIP
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               tmp = READ_CACHED_VAR(urcu_gp_ctr);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
+               //smp_mc(i);
+               ooo_mem(i);
+               dispatch_sighand_write_exec();
+               wait_for_quiescent_state(tmp, tmp2, i, j);
+#endif
+               smp_mb_writer(i, j);
+               dispatch_sighand_write_exec();
+               write_lock = 0;
+               /* free-up step, e.g., kfree(). */
+               atomic {
+                       last_free_gen = old_gen;
+                       free_done = 1;
+               }
+       :: else -> break;
+       od;
+       /*
+        * Given the reader loops infinitely, let the writer also busy-loop
+        * with progress here so, with weak fairness, we can test the
+        * writer's progress.
+        */
+end_writer:
+       do
+       :: 1 ->
+#ifdef WRITER_PROGRESS
+progress_writer2:
+#endif
+               dispatch_sighand_write_exec();
+       od;
+}
+
+/* Leave after the readers and writers so the pid count is ok. */
+init {
+       byte i, j;
+
+       atomic {
+               INIT_CACHED_VAR(urcu_gp_ctr, 1, j);
+               INIT_CACHED_VAR(generation_ptr, 0, j);
+
+               i = 0;
+               do
+               :: i < NR_READERS ->
+                       INIT_CACHED_VAR(urcu_active_readers[i], 0, j);
+                       read_generation[i] = 1;
+                       data_access[i] = 0;
+                       i++;
+               :: i >= NR_READERS -> break
+               od;
+               init_done = 1;
+       }
+}
diff --git a/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input.trail b/formal-model/urcu/result-standard-execution-nonest/urcu_progress_writer_error.spin.input.trail
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