Add support for the RISC-V architecture
authorMichael Jeanson <mjeanson@efficios.com>
Wed, 21 Mar 2018 21:38:41 +0000 (17:38 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Fri, 23 Mar 2018 21:51:28 +0000 (17:51 -0400)
commitfdfad81006c2c964781b616f0a75578507be809c
treef5e890941fa42e3f67994b631148069b0fd6480f
parent4b2d70a71f5d7ac75c9eb2589c3df26a2ed0684a
Add support for the RISC-V architecture

Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go
through the benchmarks reliably.

Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
configure.ac
include/Makefile.am
include/urcu/arch/riscv.h [new file with mode: 0644]
include/urcu/uatomic/riscv.h [new file with mode: 0644]
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