urcu: Add extra "engineering safety factor" memory barrier in update_counter_and_wait()
authorMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Sun, 14 Mar 2010 19:33:51 +0000 (15:33 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Sun, 14 Mar 2010 19:33:51 +0000 (15:33 -0400)
commit935b11ff4cf9053954d21b9d63c4ee367b12a652
tree621c26bc0582f8d156525beb68a392620e5d19cf
parent7a5a38f52b8814d0188b74a91cb635bc205df96c
urcu: Add extra "engineering safety factor" memory barrier in update_counter_and_wait()

Even though the memory barriers within update_counter_and_wait() are proven not
to be needed in urcu-mb/signal/qsbr implementations, we leave them in place as
an engineering safety factor. Basically, we've proven they are not required
(formally for urcu-mb and urcu-signal by model checking, less formally for
urcu-qsbr by looking at the execution order of concurrent synchronize_rcu() and
RCU read-sides with out-of-order load/stores). However, given that on the
overall performance impact of synchronize_rcu(), these memory barriers do not
add a significant overhead, let's leave them in place with a comment stating
that they are not required.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
urcu-qsbr.c
urcu.c
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