urcu: Add extra "engineering safety factor" memory barrier in update_counter_and_wait()

urcu: Add extra "engineering safety factor" memory barrier in update_counter_and_wait()

Even though the memory barriers within update_counter_and_wait() are proven not
to be needed in urcu-mb/signal/qsbr implementations, we leave them in place as
an engineering safety factor. Basically, we've proven they are not required
(formally for urcu-mb and urcu-signal by model checking, less formally for
urcu-qsbr by looking at the execution order of concurrent synchronize_rcu() and
RCU read-sides with out-of-order load/stores). However, given that on the
overall performance impact of synchronize_rcu(), these memory barriers do not
add a significant overhead, let's leave them in place with a comment stating
that they are not required.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>