X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_x86.h;h=d0a58e80caa5abfc980a58ad51407f82b0ceeee6;hp=c4674de0d35adfbe3eaa19560ba3a4750583fecb;hb=5481ddb381061bda64aebc039900d21cac6a6caf;hpb=e4d1eb09301904b56cdf22e1d6042df4492d57cb

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index c4674de..d0a58e8 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -5,13 +5,13 @@
  * arch_x86.h: trivial definitions for the x86 architecture.
  *
  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
  * License as published by the Free Software Foundation; either
  * version 2.1 of the License, or (at your option) any later version.
-*
+ *
  * This library is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
@@ -32,31 +32,21 @@ extern "C" {
 #define CACHE_LINE_SIZE	128
 
 #ifdef CONFIG_RCU_HAVE_FENCE
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence"::: "memory")
+#define cmm_mb()    asm volatile("mfence":::"memory")
+#define cmm_rmb()   asm volatile("lfence":::"memory")
+#define cmm_wmb()   asm volatile("sfence"::: "memory")
 #else
 /*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
+ * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
  * nop for these.
  */
-#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
-#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
 #define cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- * Cannot use cpuid on PIC because it clobbers the ebx register;
- * error: PIC register 'ebx' clobbered in 'asm'
- */
-#ifndef __PIC__
-#define sync_core()							  \
-	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-#endif
-
 #define rdtscll(val)							  \
 	do {						  		  \
 	     unsigned int __a, __d;					  \