X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_sparc64.h;h=283a8f482f018b755b5fd739472c9d4efceb6c0a;hp=a260e3a39abb29b94124cf838dd137a9be234849;hb=af7c2dbeac32c663b64ad05e4eca70e18784463b;hpb=58de5a4bc81e0b64f4fbd46973b5c8b0cd06cda6

diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
index a260e3a..283a8f4 100644
--- a/urcu/arch_sparc64.h
+++ b/urcu/arch_sparc64.h
@@ -5,13 +5,13 @@
  * arch_sparc64.h: trivial definitions for the Sparc64 architecture.
  *
  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
  * License as published by the Free Software Foundation; either
  * version 2.1 of the License, or (at your option) any later version.
-*
+ *
  * This library is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
@@ -25,13 +25,11 @@
 #include <urcu/compiler.h>
 #include <urcu/config.h>
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
-#define CACHE_LINE_SIZE	256
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
+#define CAA_CACHE_LINE_SIZE	256
 
 /*
  * Inspired from the Linux kernel. Workaround Spitfire bug #51.
@@ -42,62 +40,21 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"	\
 		     "1:\n"			\
 		     : : : "memory")
 
-#define mb()    membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
-#define rmb()    membar_safe("#LoadLoad")
-#define wmb()    membar_safe("#StoreStore")
+#define cmm_mb()	membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
+#define cmm_rmb()	membar_safe("#LoadLoad")
+#define cmm_wmb()	membar_safe("#StoreStore")
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
+typedef unsigned long long cycles_t;
 
-static inline void cpu_relax(void)
+static inline cycles_t caa_get_cycles (void)
 {
-	barrier();
+	return 0;	/* unimplemented */
 }
 
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-	mb();
+#ifdef __cplusplus 
 }
+#endif
 
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles (void)
-{
-	return 0;	/* unimplemented */
-}
+#include <urcu/arch_generic.h>
 
 #endif /* _URCU_ARCH_SPARC64_H */