X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_ppc.h;h=e1a827044aa424ead1d48510eb6b90a7e598b1a6;hp=c1762ae2d8dd3385b793f2df95a248695f7593c7;hb=06f22bdbb0c4c4d5db42a2e2dc35818aa61415be;hpb=02be55611d3b1c7bf4fdfcb3a9c98f621882d417 diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h index c1762ae..e1a8270 100644 --- a/urcu/arch_ppc.h +++ b/urcu/arch_ppc.h @@ -5,13 +5,13 @@ * arch_ppc.h: trivial definitions for the powerpc architecture. * * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. - * Copyright (c) 2009 Mathieu Desnoyers + * Copyright (c) 2009 Mathieu Desnoyers * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. -* + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU @@ -29,65 +29,10 @@ extern "C" { #endif -#define CONFIG_HAVE_MEM_COHERENCY - /* Include size of POWER5+ L3 cache lines: 256 bytes */ -#define CACHE_LINE_SIZE 256 - -#ifndef BITS_PER_LONG -#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) -#endif - -#define mb() asm volatile("sync":::"memory") -#define rmb() asm volatile("sync":::"memory") -#define wmb() asm volatile("sync"::: "memory") +#define CAA_CACHE_LINE_SIZE 256 -/* - * Architectures without cache coherency need something like the following: - * - * #define mb() mc() - * #define rmb() rmc() - * #define wmb() wmc() - * #define mc() arch_cache_flush() - * #define rmc() arch_cache_flush_read() - * #define wmc() arch_cache_flush_write() - */ - -#define mc() barrier() -#define rmc() barrier() -#define wmc() barrier() - -#ifdef CONFIG_RCU_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_mc() mc() -#define smp_rmc() rmc() -#define smp_wmc() wmc() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_mc() barrier() -#define smp_rmc() barrier() -#define smp_wmc() barrier() -#endif - -/* Nop everywhere except on alpha. */ -#define smp_read_barrier_depends() - -static inline void cpu_relax(void) -{ - barrier(); -} - -/* - * Serialize core instruction execution. Also acts as a compiler barrier. - */ -static inline void sync_core() -{ - asm volatile("isync" : : : "memory"); -} +#define cmm_mb() asm volatile("sync":::"memory") #define mftbl() \ ({ \ @@ -111,9 +56,9 @@ static inline cycles_t get_cycles (void) for (;;) { h = mftbu(); - barrier(); + cmm_barrier(); l = mftbl(); - barrier(); + cmm_barrier(); if (mftbu() == h) return (((cycles_t) h) << 32) + l; } @@ -123,4 +68,6 @@ static inline cycles_t get_cycles (void) } #endif +#include + #endif /* _URCU_ARCH_PPC_H */