X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch%2Fppc.h;h=7e2b6218f82ddc4808a775010c8bfd0c6e25ea5c;hp=d7317bb327c72afa48f087f50251cbe311a2ff62;hb=3fa182868e25068413fdaa1bef290365e99ab246;hpb=1b9119f8d4c3f40a61d4ee5403f0e7e5967c33d8

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index d7317bb..7e2b621 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -24,35 +24,78 @@
 
 #include <urcu/compiler.h>
 #include <urcu/config.h>
+#include <urcu/syscall-compat.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
-#endif 
+#endif
 
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CAA_CACHE_LINE_SIZE	256
 
-#define cmm_mb()    asm volatile("sync":::"memory")
+#ifdef __NO_LWSYNC__
+#define LWSYNC_OPCODE	"sync\n"
+#else
+#define LWSYNC_OPCODE	"lwsync\n"
+#endif
+
+/*
+ * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
+ * preserve ordering of cacheable vs. non-cacheable accesses, so it
+ * should not be used to order with respect to MMIO operations.  An
+ * eieio+lwsync pair is also not enough for cmm_rmb, because it will
+ * order cacheable and non-cacheable memory operations separately---i.e.
+ * not the latter against the former.
+ */
+#define cmm_mb()         __asm__ __volatile__ ("sync":::"memory")
+
+/*
+ * lwsync orders loads in cacheable memory with respect to other loads,
+ * and stores in cacheable memory with respect to other stores.
+ * Therefore, use it for barriers ordering accesses to cacheable memory
+ * only.
+ */
+#define cmm_smp_rmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
+#define cmm_smp_wmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
 
 #define mftbl()						\
+	__extension__					\
 	({ 						\
 		unsigned long rval;			\
-		asm volatile("mftbl %0" : "=r" (rval));	\
+		__asm__ __volatile__ ("mftbl %0" : "=r" (rval));	\
 		rval;					\
 	})
 
 #define mftbu()						\
+	__extension__					\
 	({						\
 		unsigned long rval;			\
-		asm volatile("mftbu %0" : "=r" (rval));	\
+		__asm__ __volatile__ ("mftbu %0" : "=r" (rval));	\
 		rval;					\
 	})
 
-typedef unsigned long long cycles_t;
+#define mftb()						\
+	__extension__					\
+	({						\
+		unsigned long long rval;		\
+		__asm__ __volatile__ ("mftb %0" : "=r" (rval));		\
+		rval;					\
+	})
 
-static inline cycles_t caa_get_cycles (void)
+#define HAS_CAA_GET_CYCLES
+
+typedef uint64_t caa_cycles_t;
+
+#ifdef __powerpc64__
+static inline caa_cycles_t caa_get_cycles(void)
 {
-	long h, l;
+	return (caa_cycles_t) mftb();
+}
+#else
+static inline caa_cycles_t caa_get_cycles(void)
+{
+	unsigned long h, l;
 
 	for (;;) {
 		h = mftbu();
@@ -60,11 +103,20 @@ static inline cycles_t caa_get_cycles (void)
 		l = mftbl();
 		cmm_barrier();
 		if (mftbu() == h)
-			return (((cycles_t) h) << 32) + l;
+			return (((caa_cycles_t) h) << 32) + l;
 	}
 }
+#endif
 
-#ifdef __cplusplus 
+/*
+ * Define the membarrier system call number if not yet available in the
+ * system headers.
+ */
+#ifndef __NR_membarrier
+#define __NR_membarrier		365
+#endif
+
+#ifdef __cplusplus
 }
 #endif