X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=test_qsbr_timing.c;h=e46a435d8d53ee68dce0032c78dbb2cb8cadeb29;hp=e296ced657d8d28a3d3fa74fd62669046e1e6e74;hb=ec817b748bf0004a2948937b7d04cd26c106598a;hpb=2c9689fe0485146fc5ff5e5023c941629eee124d

diff --git a/test_qsbr_timing.c b/test_qsbr_timing.c
index e296ced..e46a435 100644
--- a/test_qsbr_timing.c
+++ b/test_qsbr_timing.c
@@ -32,6 +32,9 @@
 #include <sys/syscall.h>
 #include <arch.h>
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
@@ -93,8 +96,8 @@ static int num_write;
 #define NR_READ num_read
 #define NR_WRITE num_write
 
-static cycles_t __attribute__((aligned(128))) *reader_time;
-static cycles_t __attribute__((aligned(128))) *writer_time;
+static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time;
+static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time;
 
 void *thr_reader(void *arg)
 {