X-Git-Url: http://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=arch_x86.h;h=e7d945e3859393edece5eb4b2aee4c99538083e2;hp=99ccd298dce87faada641ddc11e017c97c8eeced;hb=ebb22fff4a06b0661b55726ad332c4c53f6603fe;hpb=6d0ce021ac1529a40ca7029133e09ad14c064df4

diff --git a/arch_x86.h b/arch_x86.h
index 99ccd29..e7d945e 100644
--- a/arch_x86.h
+++ b/arch_x86.h
@@ -1,27 +1,38 @@
+#ifndef _ARCH_X86_H
+#define _ARCH_X86_H
+
 /*
- * arch_x86.h: Definitions for the x86 architecture, derived from Linux.
+ * arch_x86.h: trivial definitions for the x86 architecture.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; but only version 2 of the License given
- * that this comes from the Linux kernel.
+ * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
  *
- * This program is distributed in the hope that it will be useful,
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+*
+ * This library is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
  *
- * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <compiler.h>
+#include <arch_atomic.h>
+
 /* Assume P4 or newer */
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+#ifndef BITS_PER_LONG
+#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
+#endif
+
 #ifdef CONFIG_HAVE_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
@@ -51,10 +62,31 @@
 #define rmc()	barrier()
 #define wmc()	barrier()
 
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
+/* Assume SMP machine, given we don't have this information */
+#define CONFIG_SMP 1
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#define smp_mc()	mc()
+#define smp_rmc()	rmc()
+#define smp_wmc()	wmc()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#define smp_mc()	barrier()
+#define smp_rmc()	barrier()
+#define smp_wmc()	barrier()
+#endif
+
+/* Nop everywhere except on alpha. */
+#define smp_read_barrier_depends()
+
 static inline void rep_nop(void)
 {
-	asm volatile("rep; nop" ::: "memory");
+	asm volatile("rep; nop" : : : "memory");
 }
 
 static inline void cpu_relax(void)
@@ -62,76 +94,30 @@ static inline void cpu_relax(void)
 	rep_nop();
 }
 
-#ifndef _INCLUDE_API_H
-
-static inline void atomic_inc(int *v)
-{
-	asm volatile("lock; incl %0"
-		     : "+m" (*v));
-}
-
-#endif /* #ifndef _INCLUDE_API_H */
-
-#define xchg(ptr, v)							\
-	((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
-
-struct __xchg_dummy {
-	unsigned long a[100];
-};
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
 /*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *	  but generally the primitive is invalid, *ptr is output argument. --ANK
- * x is considered local, ptr is considered remote.
+ * Serialize core instruction execution. Also acts as a compiler barrier.
  */
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-				   int size)
+static inline void sync_core(void)
 {
-	switch (size) {
-	case 1:
-		asm volatile("xchgb %b0,%1"
-			     : "=q" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 2:
-		asm volatile("xchgw %w0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 4:
-		asm volatile("xchgl %k0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 8:
-		asm volatile("xchgq %0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	}
-	smp_wmc();
-	return x;
+	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
 }
 
-
-#define rdtscll(val) do { \
-     unsigned int __a,__d; \
-     asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
-     (val) = ((unsigned long long)__a) | (((unsigned long long)__d)<<32); \
-} while(0)
+#define rdtscll(val)							  \
+	do {						  		  \
+	     unsigned int __a, __d;					  \
+	     asm volatile("rdtsc" : "=a" (__a), "=d" (__d));		  \
+	     (val) = ((unsigned long long)__a)				  \
+			| (((unsigned long long)__d) << 32);		  \
+	} while(0)
 
 typedef unsigned long long cycles_t;
 
-static inline cycles_t get_cycles (void)
+static inline cycles_t get_cycles(void)
 {
-        unsigned long long ret = 0;
+        cycles_t ret = 0;
 
         rdtscll(ret);
         return ret;
 }
+
+#endif /* _ARCH_X86_H */