Add support for x86 older than P4, with CONFIG_HAS_FENCE option

[urcu.git] / urcu.h

diff --git a/urcu.h b/urcu.h
index c4a7992b4b7b166d527411d4ae5108cac174fc95..3e1ad78324cda478711e1c3f521bd62359bd2212 100644 (file)
--- a/urcu.h
+++ b/urcu.h
@@ -26,10 +26,36 @@
 #define likely(x)       __builtin_expect(!!(x), 1)
 #define unlikely(x)     __builtin_expect(!!(x), 0)
 
+/* Assume P4 or newer */
+#define CONFIG_HAS_FENCE 1
+
 /* x86 32/64 specific */
+#ifdef CONFIG_HAS_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence" ::: "memory")
+#define wmb()   asm volatile("sfence"::: "memory")
+#else
+/*
+ * Some non-Intel clones support out of order store. wmb() ceases to be a
+ * nop for these.
+ */
+#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
+#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
+#endif
+
+/* Assume SMP machine, given we don't have this information */
+#define CONFIG_SMP 1
+
+#ifdef CONFIG_SMP
+#define smp_mb()       mb()
+#define smp_rmb()      rmb()
+#define smp_wmb()      wmb()
+#else
+#define smp_mb()       barrier()
+#define smp_rmb()      barrier()
+#define smp_wmb()      barrier()
+#endif
 
 static inline void atomic_inc(int *v)
 {
@@ -117,6 +143,13 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
 
 #define SIGURCU SIGUSR1
 
+/*
+ * If a reader is really non-cooperative and refuses to commit its
+ * urcu_active_readers count to memory (there is no barrier in the reader
+ * per-se), kick it after a few loops waiting for it.
+ */
+#define KICK_READER_LOOPS 10000
+
 #ifdef DEBUG_YIELD
 #include <sched.h>
 #include <time.h>
@@ -173,7 +206,7 @@ static inline void debug_yield_init(void)
 #ifdef DEBUG_FULL_MB
 static inline void read_barrier()
 {
-       mb();
+       smp_mb();
 }
 #else
 static inline void read_barrier()
@@ -206,13 +239,11 @@ static inline int rcu_old_gp_ongoing(long *value)
 
        if (value == NULL)
                return 0;
-       debug_yield_write();
        /*
         * Make sure both tests below are done on the same version of *value
         * to insure consistency.
         */
        v = ACCESS_ONCE(*value);
-       debug_yield_write();
        return (v & RCU_GP_CTR_NEST_MASK) &&
                 ((v ^ urcu_gp_ctr) & RCU_GP_CTR_BIT);
 }
@@ -221,34 +252,29 @@ static inline void rcu_read_lock(void)
 {
        long tmp;
 
-       debug_yield_read();
        tmp = urcu_active_readers;
-       debug_yield_read();
        /* urcu_gp_ctr = RCU_GP_COUNT | (~RCU_GP_CTR_BIT or RCU_GP_CTR_BIT) */
+       /* The data dependency "read urcu_gp_ctr, write urcu_active_readers",
+        * serializes those two memory operations. */
        if (likely(!(tmp & RCU_GP_CTR_NEST_MASK)))
-               urcu_active_readers = urcu_gp_ctr;
+               urcu_active_readers = ACCESS_ONCE(urcu_gp_ctr);
        else
                urcu_active_readers = tmp + RCU_GP_COUNT;
-       debug_yield_read();
        /*
         * Increment active readers count before accessing the pointer.
         * See force_mb_all_threads().
         */
        read_barrier();
-       debug_yield_read();
 }
 
 static inline void rcu_read_unlock(void)
 {
-       debug_yield_read();
        read_barrier();
-       debug_yield_read();
        /*
         * Finish using rcu before decrementing the pointer.
         * See force_mb_all_threads().
         */
        urcu_active_readers -= RCU_GP_COUNT;
-       debug_yield_read();
 }
 
 /**
@@ -289,7 +315,6 @@ extern void synchronize_rcu(void);
 #define urcu_publish_content(p, v) \
        ({ \
                void *oldptr; \
-               debug_yield_write(); \
                oldptr = rcu_xchg_pointer(p, v); \
                synchronize_rcu(); \
                oldptr; \