define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_urcu_defer.c

diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c
index e56dffe2e308374dad1554b32013e3718309f4f1..08e3e60b404927ae9c76b275f8bf12e5f498dc9a 100644 (file)
--- a/tests/test_urcu_defer.c
+++ b/tests/test_urcu_defer.c
@@ -33,10 +33,7 @@
 #include <sys/syscall.h>
 #include <sched.h>
 
-#include "../arch.h"
-
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
+#include <urcu/arch.h>
 
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
@@ -61,8 +58,8 @@ static inline pid_t gettid(void)
 #else
 #define debug_yield_read()
 #endif
-#include "../urcu.h"
-#include "../urcu-defer.h"
+#include <urcu.h>
+#include <urcu-defer.h>
 
 struct test_array {
        int a;
@@ -209,6 +206,14 @@ void *thr_reader(void *_count)
 
 }
 
+static void test_cb2(void *data)
+{
+}
+
+static void test_cb1(void *data)
+{
+}
+
 void *thr_writer(void *data)
 {
        unsigned long wtidx = (unsigned long)data;
@@ -230,7 +235,14 @@ void *thr_writer(void *data)
                new = malloc(sizeof(*new));
                new->a = 8;
                old = rcu_xchg_pointer(&test_rcu_pointer, new);
-               rcu_defer_queue(old);
+               call_rcu(free, old);
+               call_rcu(test_cb1, old);
+               call_rcu(test_cb1, (void *)-2L);
+               call_rcu(test_cb1, (void *)-2L);
+               call_rcu(test_cb1, old);
+               call_rcu(test_cb2, (void *)-2L);
+               call_rcu(test_cb2, (void *)-4L);
+               call_rcu(test_cb2, (void *)-2L);
                nr_writes++;
                if (unlikely(!test_duration_write()))
                        break;