define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_urcu_defer.c

diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c
index 0961b8d2de85335efea234f63769e1bce98f00eb..08e3e60b404927ae9c76b275f8bf12e5f498dc9a 100644 (file)
--- a/tests/test_urcu_defer.c
+++ b/tests/test_urcu_defer.c
@@ -33,10 +33,7 @@
 #include <sys/syscall.h>
 #include <sched.h>
 
-#include "../arch.h"
-
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
+#include <urcu/arch.h>
 
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
@@ -61,8 +58,8 @@ static inline pid_t gettid(void)
 #else
 #define debug_yield_read()
 #endif
-#include "../urcu.h"
-#include "../urcu-defer.h"
+#include <urcu.h>
+#include <urcu-defer.h>
 
 struct test_array {
        int a;