Deal with POWER5+ 256B L3 cachefalse sharing for per thread lock

[urcu.git] / test_urcu.c

diff --git a/test_urcu.c b/test_urcu.c
index 696c09e39e3b254da74f4ce82766468f0bd03a21..fc9e8b539a9b3a9f21eb05702230602dd760b6d0 100644 (file)
--- a/test_urcu.c
+++ b/test_urcu.c
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)