update license

[urcu.git] / test_rwlock_timing.c

diff --git a/test_rwlock_timing.c b/test_rwlock_timing.c
index cd2087650437b9d8be01896fcc920112c100513a..4884e4dc2a4840ad7db45311684d87f673a32e02 100644 (file)
--- a/test_rwlock_timing.c
+++ b/test_rwlock_timing.c
@@ -33,6 +33,9 @@
 #include <pthread.h>
 #include <arch.h>
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
@@ -72,8 +75,8 @@ static int num_write;
 #define NR_READ num_read
 #define NR_WRITE num_write
 
-static cycles_t __attribute__((aligned(128))) *reader_time;
-static cycles_t __attribute__((aligned(128))) *writer_time;
+static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time;
+static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time;
 
 void *thr_reader(void *arg)
 {