Deal with POWER5+ 256B L3 cachefalse sharing for per thread lock

[urcu.git] / test_qsbr.c

diff --git a/test_qsbr.c b/test_qsbr.c
index dc871dc118ee9c82d5fd1676533eef1751552844..2e1a0ecff23f183ed43a920b495b8c1c61bf7dff 100644 (file)
--- a/test_qsbr.c
+++ b/test_qsbr.c
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)