Deal with POWER5+ 256B L3 cachefalse sharing for per thread lock

[urcu.git] / test_mutex.c

diff --git a/test_mutex.c b/test_mutex.c
index d48181082af7ab3a5c5aefd86ff716c96b5337d8..8b480403fcabdd4adccfe0774c51a9d8a45cb42d 100644 (file)
--- a/test_mutex.c
+++ b/test_mutex.c
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
@@ -104,8 +107,10 @@ static int test_duration_read(void)
 static unsigned long long __thread nr_writes;
 static unsigned long long __thread nr_reads;
 
-static unsigned long long __attribute__((aligned(128))) *tot_nr_writes;
-static unsigned long long __attribute__((aligned(128))) *tot_nr_reads;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_writes;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_reads;
 
 static unsigned int nr_readers;
 static unsigned int nr_writers;