Public headers: use SPDX identifiers

[urcu.git] / include / urcu / arch / x86.h

diff --git a/include/urcu/arch/x86.h b/include/urcu/arch/x86.h
index aac8ca1384b63f4ce321680cffbcaca661a0f16c..dcff3a8d16c19b56a1ee62657dfddfd579dd3c7f 100644 (file)
--- a/include/urcu/arch/x86.h
+++ b/include/urcu/arch/x86.h
@@ -1,25 +1,13 @@
+// SPDX-FileCopyrightText: 2009 Paul E. McKenney, IBM Corporation.
+// SPDX-FileCopyrightText: 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
+//
+// SPDX-License-Identifier: LGPL-2.1-or-later
+
 #ifndef _URCU_ARCH_X86_H
 #define _URCU_ARCH_X86_H
 
 /*
  * arch_x86.h: trivial definitions for the x86 architecture.
- *
- * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include <urcu/compiler.h>
@@ -33,7 +21,19 @@ extern "C" {
 
 #define CAA_CACHE_LINE_SIZE    128
 
-#ifdef CONFIG_RCU_HAVE_FENCE
+/*
+ * For now, using lock; addl compatibility mode even for i686, because the
+ * Pentium III is seen as a i686, but lacks mfence instruction.  Only using
+ * fence for x86_64.
+ *
+ * k1om (__MIC__) is the name for the Intel MIC family (Xeon Phi). It is an
+ * x86_64 variant but lacks fence instructions.
+ */
+#if (defined(URCU_ARCH_AMD64) && !defined(URCU_ARCH_K1OM))
+
+/* For backwards compat */
+#define CONFIG_RCU_HAVE_FENCE 1
+
 #define cmm_mb()    __asm__ __volatile__ ("mfence":::"memory")
 
 /*
@@ -45,7 +45,9 @@ extern "C" {
 #define cmm_wmb()     __asm__ __volatile__ ("sfence"::: "memory")
 #define cmm_smp_rmb() cmm_barrier()
 #define cmm_smp_wmb() cmm_barrier()
+
 #else
+
 /*
  * We leave smp_rmb/smp_wmb as full barriers for processors that do not have
  * fence instructions.