Add missing rcu_cmpxchg_pointer define

[urcu.git] / arch_x86.h

diff --git a/arch_x86.h b/arch_x86.h
index 01b5d50bde8e174cd255a4270172b48bca55e784..8a5732536c9d3106af919b5467dab1f58c5f9313 100644 (file)
--- a/arch_x86.h
+++ b/arch_x86.h
@@ -23,13 +23,14 @@
  */
 
 #include <compiler.h>
+#include <arch_atomic.h>
 
 /* Assume P4 or newer */
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
 #ifndef BITS_PER_LONG
-#define BITS_PER_LONG  (sizeof(unsigned long) * 8)
+#define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
 #endif
 
 #ifdef CONFIG_HAVE_FENCE
@@ -83,10 +84,9 @@
 /* Nop everywhere except on alpha. */
 #define smp_read_barrier_depends()
 
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 static inline void rep_nop(void)
 {
-       asm volatile("rep; nop" ::: "memory");
+       asm volatile("rep; nop" : : : "memory");
 }
 
 static inline void cpu_relax(void)
@@ -94,55 +94,25 @@ static inline void cpu_relax(void)
        rep_nop();
 }
 
-#define xchg(ptr, v)   \
-       ((__typeof__(*(ptr)))__xchg((ptr), (unsigned long)(v), sizeof(*(ptr))))
-
-struct __xchg_ptr_as_array {
-       unsigned long a[100];
-};
-
-#define __xchg_ptr_as_array(x) ((struct __xchg_ptr_as_array *)(x))
-
 /*
- * xchg always implies a "lock" prefix, even on UP. See Intel documentation.
- * volatile attribute is neccessary due to xchg side effect.
- * *ptr is an output argument.
- * x is considered local, ptr is considered remote.
+ * Serialize core instruction execution. Also acts as a compiler barrier.
+ */
+#ifdef __PIC__
+/*
+ * Cannot use cpuid because it clobbers the ebx register and clashes
+ * with -fPIC :
+ * error: PIC register 'ebx' clobbered in 'asm'
  */
-static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
-                                  int size)
+static inline void sync_core(void)
 {
-       switch (size) {
-       case 1:
-               asm volatile("xchgb %b0,%1"
-                            : "=q" (x)
-                            : "m" (*__xchg_ptr_as_array(ptr)), "0" (x)
-                            : "memory");
-               break;
-       case 2:
-               asm volatile("xchgw %w0,%1"
-                            : "=r" (x)
-                            : "m" (*__xchg_ptr_as_array(ptr)), "0" (x)
-                            : "memory");
-               break;
-       case 4:
-               asm volatile("xchgl %k0,%1"
-                            : "=r" (x)
-                            : "m" (*__xchg_ptr_as_array(ptr)), "0" (x)
-                            : "memory");
-               break;
-#if (BITS_PER_LONG == 64)
-       case 8:
-               asm volatile("xchgq %0,%1"
-                            : "=r" (x)
-                            : "m" (*__xchg_ptr_as_array(ptr)), "0" (x)
-                            : "memory");
-               break;
-#endif
-       }
-       smp_wmc();
-       return x;
+       mb();
 }
+#else
+static inline void sync_core(void)
+{
+       asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
+}
+#endif
 
 #define rdtscll(val)                                                     \
        do {                                                              \