urcu/uatomic_arch_ppc.h

   1 #ifndef _URCU_ARCH_UATOMIC_PPC_H
   2 #define _URCU_ARCH_UATOMIC_PPC_H
   3
   4 /*
   5  * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
   6  * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
   7  * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
   8  * Copyright (c) 2009      Mathieu Desnoyers
   9  *
  10  * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
  11  * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
  12  *
  13  * Permission is hereby granted to use or copy this program
  14  * for any purpose,  provided the above notices are retained on all copies.
  15  * Permission to modify the code and to distribute modified code is granted,
  16  * provided the above notices are retained, and a notice that the code was
  17  * modified is included with the above copyright notice.
  18  *
  19  * Code inspired from libuatomic_ops-1.2, inherited in part from the
  20  * Boehm-Demers-Weiser conservative garbage collector.
  21  */
  22
  23 #include <urcu/compiler.h>
  24 #include <urcu/system.h>
  25
  26 #ifdef __cplusplus
  27 extern "C" {
  28 #endif
  29
  30 #ifndef __SIZEOF_LONG__
  31 #ifdef __powerpc64__
  32 #define __SIZEOF_LONG__ 8
  33 #else
  34 #define __SIZEOF_LONG__ 4
  35 #endif
  36 #endif
  37
  38 #ifndef BITS_PER_LONG
  39 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  40 #endif
  41
  42 #define ILLEGAL_INSTR   ".long  0xd00d00"
  43
  44 #define uatomic_set(addr, v)    STORE_SHARED(*(addr), (v))
  45 #define uatomic_read(addr)      LOAD_SHARED(*(addr))
  46
  47 /*
  48  * Using a isync as second barrier for exchange to provide acquire semantic.
  49  * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
  50  * explicit that this also has acquire semantics."
  51  * Derived from AO_compare_and_swap(), but removed the comparison.
  52  */
  53
  54 /* xchg */
  55
  56 static inline __attribute__((always_inline))
  57 unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
  58 {
  59         switch (len) {
  60         case 4:
  61         {
  62                 unsigned int result;
  63
  64                 __asm__ __volatile__(
  65                         "lwsync\n"
  66                 "1:\t"  "lwarx %0,0,%1\n"       /* load and reserve */
  67                         "stwcx. %2,0,%1\n"      /* else store conditional */
  68                         "bne- 1b\n"             /* retry if lost reservation */
  69                         "isync\n"
  70                                 : "=&r"(result)
  71                                 : "r"(addr), "r"(val)
  72                                 : "memory", "cc");
  73
  74                 return result;
  75         }
  76 #if (BITS_PER_LONG == 64)
  77         case 8:
  78         {
  79                 unsigned long result;
  80
  81                 __asm__ __volatile__(
  82                         "lwsync\n"
  83                 "1:\t"  "ldarx %0,0,%1\n"       /* load and reserve */
  84                         "stdcx. %2,0,%1\n"      /* else store conditional */
  85                         "bne- 1b\n"             /* retry if lost reservation */
  86                         "isync\n"
  87                                 : "=&r"(result)
  88                                 : "r"(addr), "r"(val)
  89                                 : "memory", "cc");
  90
  91                 return result;
  92         }
  93 #endif
  94         }
  95         /* generate an illegal instruction. Cannot catch this with linker tricks
  96          * when optimizations are disabled. */
  97         __asm__ __volatile__(ILLEGAL_INSTR);
  98         return 0;
  99 }
 100
 101 #define uatomic_xchg(addr, v)                                               \
 102         ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
 103                                                 sizeof(*(addr))))
 104 /* cmpxchg */
 105
 106 static inline __attribute__((always_inline))
 107 unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
 108                               unsigned long _new, int len)
 109 {
 110         switch (len) {
 111         case 4:
 112         {
 113                 unsigned int old_val;
 114
 115                 __asm__ __volatile__(
 116                         "lwsync\n"
 117                 "1:\t"  "lwarx %0,0,%1\n"       /* load and reserve */
 118                         "cmpd %0,%3\n"          /* if load is not equal to */
 119                         "bne 2f\n"              /* old, fail */
 120                         "stwcx. %2,0,%1\n"      /* else store conditional */
 121                         "bne- 1b\n"             /* retry if lost reservation */
 122                         "isync\n"
 123                 "2:\n"
 124                                 : "=&r"(old_val)
 125                                 : "r"(addr), "r"((unsigned int)_new),
 126                                   "r"((unsigned int)old)
 127                                 : "memory", "cc");
 128
 129                 return old_val;
 130         }
 131 #if (BITS_PER_LONG == 64)
 132         case 8:
 133         {
 134                 unsigned long old_val;
 135
 136                 __asm__ __volatile__(
 137                         "lwsync\n"
 138                 "1:\t"  "ldarx %0,0,%1\n"       /* load and reserve */
 139                         "cmpd %0,%3\n"          /* if load is not equal to */
 140                         "bne 2f\n"              /* old, fail */
 141                         "stdcx. %2,0,%1\n"      /* else store conditional */
 142                         "bne- 1b\n"             /* retry if lost reservation */
 143                         "isync\n"
 144                 "2:\n"
 145                                 : "=&r"(old_val),
 146                                 : "r"(addr), "r"((unsigned long)_new),
 147                                   "r"((unsigned long)old)
 148                                 : "memory", "cc");
 149
 150                 return old_val;
 151         }
 152 #endif
 153         }
 154         /* generate an illegal instruction. Cannot catch this with linker tricks
 155          * when optimizations are disabled. */
 156         __asm__ __volatile__(ILLEGAL_INSTR);
 157         return 0;
 158 }
 159
 160
 161 #define uatomic_cmpxchg(addr, old, _new)                                    \
 162         ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
 163                                                 (unsigned long)(_new),      \
 164                                                 sizeof(*(addr))))
 165
 166 /* uatomic_add_return */
 167
 168 static inline __attribute__((always_inline))
 169 unsigned long _uatomic_add_return(void *addr, unsigned long val,
 170                                  int len)
 171 {
 172         switch (len) {
 173         case 4:
 174         {
 175                 unsigned int result;
 176
 177                 __asm__ __volatile__(
 178                         "lwsync\n"
 179                 "1:\t"  "lwarx %0,0,%1\n"       /* load and reserve */
 180                         "add %0,%2,%0\n"        /* add val to value loaded */
 181                         "stwcx. %0,0,%1\n"      /* store conditional */
 182                         "bne- 1b\n"             /* retry if lost reservation */
 183                         "isync\n"
 184                                 : "=&r"(result)
 185                                 : "r"(addr), "r"(val)
 186                                 : "memory", "cc");
 187
 188                 return result;
 189         }
 190 #if (BITS_PER_LONG == 64)
 191         case 8:
 192         {
 193                 unsigned long result;
 194
 195                 __asm__ __volatile__(
 196                         "lwsync\n"
 197                 "1:\t"  "ldarx %0,0,%1\n"       /* load and reserve */
 198                         "add %0,%2,%0\n"        /* add val to value loaded */
 199                         "stdcx. %0,0,%1\n"      /* store conditional */
 200                         "bne- 1b\n"             /* retry if lost reservation */
 201                         "isync\n"
 202                                 : "=&r"(result)
 203                                 : "r"(addr), "r"(val)
 204                                 : "memory", "cc");
 205
 206                 return result;
 207         }
 208 #endif
 209         }
 210         /* generate an illegal instruction. Cannot catch this with linker tricks
 211          * when optimizations are disabled. */
 212         __asm__ __volatile__(ILLEGAL_INSTR);
 213         return 0;
 214 }
 215
 216
 217 #define uatomic_add_return(addr, v)                                     \
 218         ((__typeof__(*(addr))) _uatomic_add_return((addr),              \
 219                                                   (unsigned long)(v),   \
 220                                                   sizeof(*(addr))))
 221
 222 /* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
 223
 224 #define uatomic_sub_return(addr, v)     uatomic_add_return((addr), -(v))
 225
 226 #define uatomic_add(addr, v)            (void)uatomic_add_return((addr), (v))
 227 #define uatomic_sub(addr, v)            (void)uatomic_sub_return((addr), (v))
 228
 229 #define uatomic_inc(addr)               uatomic_add((addr), 1)
 230 #define uatomic_dec(addr)               uatomic_add((addr), -1)
 231
 232 #define compat_uatomic_cmpxchg(ptr, old, _new)  uatomic_cmpxchg(ptr, old, _new)
 233
 234 #ifdef __cplusplus
 235 }
 236 #endif
 237
 238 #endif /* _URCU_ARCH_UATOMIC_PPC_H */