[urcu.git] / urcu / arch_x86.h

#ifndef _URCU_ARCH_X86_H
#define _URCU_ARCH_X86_H

/*
 * arch_x86.h: trivial definitions for the x86 architecture.
 *
 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
*
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

#include <urcu/compiler.h>
#include <urcu/arch_uatomic.h>

/* Assume P4 or newer */
#define CONFIG_HAVE_FENCE 1
#define CONFIG_HAVE_MEM_COHERENCY

#define CACHE_LINE_SIZE	128

#ifndef BITS_PER_LONG
#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
#endif

#ifdef CONFIG_HAVE_FENCE
#define mb()    asm volatile("mfence":::"memory")
#define rmb()   asm volatile("lfence":::"memory")
#define wmb()   asm volatile("sfence"::: "memory")
#else
/*
 * Some non-Intel clones support out of order store. wmb() ceases to be a
 * nop for these.
 */
#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
#endif

/*
 * Architectures without cache coherency need something like the following:
 *
 * #define mb()		mc()
 * #define rmb()	rmc()
 * #define wmb()	wmc()
 * #define mc()		arch_cache_flush()
 * #define rmc()	arch_cache_flush_read()
 * #define wmc()	arch_cache_flush_write()
 */

#define mc()	barrier()
#define rmc()	barrier()
#define wmc()	barrier()

/* Assume SMP machine, given we don't have this information */
#define CONFIG_SMP 1

#ifdef CONFIG_SMP
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	wmb()
#define smp_mc()	mc()
#define smp_rmc()	rmc()
#define smp_wmc()	wmc()
#else
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#define smp_mc()	barrier()
#define smp_rmc()	barrier()
#define smp_wmc()	barrier()
#endif

/* Nop everywhere except on alpha. */
#define smp_read_barrier_depends()

static inline void rep_nop(void)
{
	asm volatile("rep; nop" : : : "memory");
}

static inline void cpu_relax(void)
{
	rep_nop();
}

/*
 * Serialize core instruction execution. Also acts as a compiler barrier.
 */
#ifdef __PIC__
/*
 * Cannot use cpuid because it clobbers the ebx register and clashes
 * with -fPIC :
 * error: PIC register 'ebx' clobbered in 'asm'
 */
static inline void sync_core(void)
{
	mb();
}
#else
static inline void sync_core(void)
{
	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
}
#endif

#define rdtscll(val)							  \
	do {						  		  \
	     unsigned int __a, __d;					  \
	     asm volatile("rdtsc" : "=a" (__a), "=d" (__d));		  \
	     (val) = ((unsigned long long)__a)				  \
			| (((unsigned long long)__d) << 32);		  \
	} while(0)

typedef unsigned long long cycles_t;

static inline cycles_t get_cycles(void)
{
        cycles_t ret = 0;

        rdtscll(ret);
        return ret;
}

#endif /* _URCU_ARCH_X86_H */
Commit	Line	Data
	1	#ifndef _URCU_ARCH_X86_H
	2	#define _URCU_ARCH_X86_H
	3
	4	/*
	5	* arch_x86.h: trivial definitions for the x86 architecture.
	6	*
	7	* Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
	8	* Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2.1 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
	23	*/
	24
	25	#include <urcu/compiler.h>
	26	#include <urcu/arch_uatomic.h>
	27
	28	/* Assume P4 or newer */
	29	#define CONFIG_HAVE_FENCE 1
	30	#define CONFIG_HAVE_MEM_COHERENCY
	31
	32	#define CACHE_LINE_SIZE 128
	33
	34	#ifndef BITS_PER_LONG
	35	#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
	36	#endif
	37
	38	#ifdef CONFIG_HAVE_FENCE
	39	#define mb() asm volatile("mfence":::"memory")
	40	#define rmb() asm volatile("lfence":::"memory")
	41	#define wmb() asm volatile("sfence"::: "memory")
	42	#else
	43	/*
	44	* Some non-Intel clones support out of order store. wmb() ceases to be a
	45	* nop for these.
	46	*/
	47	#define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	48	#define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	49	#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
	50	#endif
	51
	52	/*
	53	* Architectures without cache coherency need something like the following:
	54	*
	55	* #define mb() mc()
	56	* #define rmb() rmc()
	57	* #define wmb() wmc()
	58	* #define mc() arch_cache_flush()
	59	* #define rmc() arch_cache_flush_read()
	60	* #define wmc() arch_cache_flush_write()
	61	*/
	62
	63	#define mc() barrier()
	64	#define rmc() barrier()
	65	#define wmc() barrier()
	66
	67	/* Assume SMP machine, given we don't have this information */
	68	#define CONFIG_SMP 1
	69
	70	#ifdef CONFIG_SMP
	71	#define smp_mb() mb()
	72	#define smp_rmb() rmb()
	73	#define smp_wmb() wmb()
	74	#define smp_mc() mc()
	75	#define smp_rmc() rmc()
	76	#define smp_wmc() wmc()
	77	#else
	78	#define smp_mb() barrier()
	79	#define smp_rmb() barrier()
	80	#define smp_wmb() barrier()
	81	#define smp_mc() barrier()
	82	#define smp_rmc() barrier()
	83	#define smp_wmc() barrier()
	84	#endif
	85
	86	/* Nop everywhere except on alpha. */
	87	#define smp_read_barrier_depends()
	88
	89	static inline void rep_nop(void)
	90	{
	91	asm volatile("rep; nop" : : : "memory");
	92	}
	93
	94	static inline void cpu_relax(void)
	95	{
	96	rep_nop();
	97	}
	98
	99	/*
	100	* Serialize core instruction execution. Also acts as a compiler barrier.
	101	*/
	102	#ifdef __PIC__
	103	/*
	104	* Cannot use cpuid because it clobbers the ebx register and clashes
	105	* with -fPIC :
	106	* error: PIC register 'ebx' clobbered in 'asm'
	107	*/
	108	static inline void sync_core(void)
	109	{
	110	mb();
	111	}
	112	#else
	113	static inline void sync_core(void)
	114	{
	115	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
	116	}
	117	#endif
	118
	119	#define rdtscll(val) \
	120	do { \
	121	unsigned int __a, __d; \
	122	asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
	123	(val) = ((unsigned long long)__a) \
	124	\| (((unsigned long long)__d) << 32); \
	125	} while(0)
	126
	127	typedef unsigned long long cycles_t;
	128
	129	static inline cycles_t get_cycles(void)
	130	{
	131	cycles_t ret = 0;
	132
	133	rdtscll(ret);
	134	return ret;
	135	}
	136
	137	#endif /* _URCU_ARCH_X86_H */