| | 1 | #ifndef _ARCH_PPC_H |
| | 2 | #define _ARCH_PPC_H |
| | 3 | |
| | 4 | /* |
| | 5 | * arch_ppc.h: trivial definitions for the powerpc architecture. |
| | 6 | * |
| | 7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
| | 8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> |
| | 9 | * |
| | 10 | * This library is free software; you can redistribute it and/or |
| | 11 | * modify it under the terms of the GNU Lesser General Public |
| | 12 | * License as published by the Free Software Foundation; either |
| | 13 | * version 2.1 of the License, or (at your option) any later version. |
| | 14 | * |
| | 15 | * This library is distributed in the hope that it will be useful, |
| | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| | 18 | * Lesser General Public License for more details. |
| | 19 | * |
| | 20 | * You should have received a copy of the GNU Lesser General Public |
| | 21 | * License along with this library; if not, write to the Free Software |
| | 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
| | 23 | */ |
| | 24 | |
| | 25 | #include <compiler.h> |
| | 26 | #include <arch_atomic.h> |
| | 27 | |
| | 28 | #define CONFIG_HAVE_FENCE 1 |
| | 29 | #define CONFIG_HAVE_MEM_COHERENCY |
| | 30 | |
| | 31 | #ifndef BITS_PER_LONG |
| | 32 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) |
| | 33 | #endif |
| | 34 | |
| | 35 | #define mb() asm volatile("sync":::"memory") |
| | 36 | #define rmb() asm volatile("sync":::"memory") |
| | 37 | #define wmb() asm volatile("sync"::: "memory") |
| | 38 | |
| | 39 | /* |
| | 40 | * Architectures without cache coherency need something like the following: |
| | 41 | * |
| | 42 | * #define mb() mc() |
| | 43 | * #define rmb() rmc() |
| | 44 | * #define wmb() wmc() |
| | 45 | * #define mc() arch_cache_flush() |
| | 46 | * #define rmc() arch_cache_flush_read() |
| | 47 | * #define wmc() arch_cache_flush_write() |
| | 48 | */ |
| | 49 | |
| | 50 | #define mc() barrier() |
| | 51 | #define rmc() barrier() |
| | 52 | #define wmc() barrier() |
| | 53 | |
| | 54 | /* Assume SMP machine, given we don't have this information */ |
| | 55 | #define CONFIG_SMP 1 |
| | 56 | |
| | 57 | #ifdef CONFIG_SMP |
| | 58 | #define smp_mb() mb() |
| | 59 | #define smp_rmb() rmb() |
| | 60 | #define smp_wmb() wmb() |
| | 61 | #define smp_mc() mc() |
| | 62 | #define smp_rmc() rmc() |
| | 63 | #define smp_wmc() wmc() |
| | 64 | #else |
| | 65 | #define smp_mb() barrier() |
| | 66 | #define smp_rmb() barrier() |
| | 67 | #define smp_wmb() barrier() |
| | 68 | #define smp_mc() barrier() |
| | 69 | #define smp_rmc() barrier() |
| | 70 | #define smp_wmc() barrier() |
| | 71 | #endif |
| | 72 | |
| | 73 | /* Nop everywhere except on alpha. */ |
| | 74 | #define smp_read_barrier_depends() |
| | 75 | |
| | 76 | static inline void cpu_relax(void) |
| | 77 | { |
| | 78 | barrier(); |
| | 79 | } |
| | 80 | |
| | 81 | #define mftbl() \ |
| | 82 | ({ \ |
| | 83 | unsigned long rval; \ |
| | 84 | asm volatile("mftbl %0" : "=r" (rval)); \ |
| | 85 | rval; \ |
| | 86 | }) |
| | 87 | |
| | 88 | #define mftbu() \ |
| | 89 | ({ \ |
| | 90 | unsigned long rval; \ |
| | 91 | asm volatile("mftbu %0" : "=r" (rval)); \ |
| | 92 | rval; \ |
| | 93 | }) |
| | 94 | |
| | 95 | typedef unsigned long long cycles_t; |
| | 96 | |
| | 97 | static inline cycles_t get_cycles (void) |
| | 98 | { |
| | 99 | long h, l; |
| | 100 | |
| | 101 | for (;;) { |
| | 102 | h = mftbu(); |
| | 103 | barrier(); |
| | 104 | l = mftbl(); |
| | 105 | barrier(); |
| | 106 | if (mftbu() == h) |
| | 107 | return (((cycles_t) h) << 32) + l; |
| | 108 | } |
| | 109 | } |
| | 110 | |
| | 111 | #endif /* _ARCH_PPC_H */ |
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