[urcu.git] / urcu / uatomic_arch_ppc.h

#ifndef _URCU_ARCH_UATOMIC_PPC_H
#define _URCU_ARCH_UATOMIC_PPC_H

/* 
 * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
 * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
 * Copyright (c) 2009      Mathieu Desnoyers
 *
 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
 * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
 *
 * Permission is hereby granted to use or copy this program
 * for any purpose,  provided the above notices are retained on all copies.
 * Permission to modify the code and to distribute modified code is granted,
 * provided the above notices are retained, and a notice that the code was
 * modified is included with the above copyright notice.
 *
 * Code inspired from libuatomic_ops-1.2, inherited in part from the
 * Boehm-Demers-Weiser conservative garbage collector.
 */

#include <urcu/compiler.h>
#include <urcu/system.h>

#ifdef __cplusplus
extern "C" {
#endif 

#ifndef __SIZEOF_LONG__
#ifdef __powerpc64__
#define __SIZEOF_LONG__ 8
#else
#define __SIZEOF_LONG__ 4
#endif
#endif

#ifndef BITS_PER_LONG
#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
#endif

#define ILLEGAL_INSTR	".long	0xd00d00"

#define uatomic_set(addr, v)	STORE_SHARED(*(addr), (v))
#define uatomic_read(addr)	LOAD_SHARED(*(addr))

/*
 * Using a isync as second barrier for exchange to provide acquire semantic.
 * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
 * explicit that this also has acquire semantics."
 * Derived from AO_compare_and_swap(), but removed the comparison.
 */

/* xchg */

static inline __attribute__((always_inline))
unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
{
	switch (len) {
	case 4:
	{
		unsigned int result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"stwcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"stdcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}

#define uatomic_xchg(addr, v)						    \
	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
						sizeof(*(addr))))
/* cmpxchg */

static inline __attribute__((always_inline))
unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
			      unsigned long _new, int len)
{
	switch (len) {
	case 4:
	{
		unsigned int old_val;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"cmpd %0,%3\n"		/* if load is not equal to */
			"bne 2f\n"		/* old, fail */
			"stwcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
		"2:\n"
				: "=&r"(old_val)
				: "r"(addr), "r"((unsigned int)_new),
				  "r"((unsigned int)old)
				: "memory", "cc");

		return old_val;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long old_val;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"cmpd %0,%3\n"		/* if load is not equal to */
			"bne 2f\n"		/* old, fail */
			"stdcx. %2,0,%1\n"	/* else store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
		"2:\n"
				: "=&r"(old_val),
				: "r"(addr), "r"((unsigned long)_new),
				  "r"((unsigned long)old)
				: "memory", "cc");

		return old_val;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}


#define uatomic_cmpxchg(addr, old, _new)				    \
	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
						(unsigned long)(_new), 	    \
						sizeof(*(addr))))

/* uatomic_add_return */

static inline __attribute__((always_inline))
unsigned long _uatomic_add_return(void *addr, unsigned long val,
				 int len)
{
	switch (len) {
	case 4:
	{
		unsigned int result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"lwarx %0,0,%1\n"	/* load and reserve */
			"add %0,%2,%0\n"	/* add val to value loaded */
			"stwcx. %0,0,%1\n"	/* store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#if (BITS_PER_LONG == 64)
	case 8:
	{
		unsigned long result;

		__asm__ __volatile__(
			"lwsync\n"
		"1:\t"	"ldarx %0,0,%1\n"	/* load and reserve */
			"add %0,%2,%0\n"	/* add val to value loaded */
			"stdcx. %0,0,%1\n"	/* store conditional */
			"bne- 1b\n"	 	/* retry if lost reservation */
			"isync\n"
				: "=&r"(result)
				: "r"(addr), "r"(val)
				: "memory", "cc");

		return result;
	}
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__(ILLEGAL_INSTR);
	return 0;
}


#define uatomic_add_return(addr, v)					\
	((__typeof__(*(addr))) _uatomic_add_return((addr),		\
						  (unsigned long)(v),	\
						  sizeof(*(addr))))

/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */

#define uatomic_sub_return(addr, v)	uatomic_add_return((addr), -(v))

#define uatomic_add(addr, v)		(void)uatomic_add_return((addr), (v))
#define uatomic_sub(addr, v)		(void)uatomic_sub_return((addr), (v))

#define uatomic_inc(addr)		uatomic_add((addr), 1)
#define uatomic_dec(addr)		uatomic_add((addr), -1)

#define compat_uatomic_cmpxchg(ptr, old, _new)	uatomic_cmpxchg(ptr, old, _new)

#ifdef __cplusplus 
}
#endif

#endif /* _URCU_ARCH_UATOMIC_PPC_H */
Commit	Line	Data
ec4e58a3 MD	1	#ifndef _URCU_ARCH_UATOMIC_PPC_H
ec4e58a3 MD	2	#define _URCU_ARCH_UATOMIC_PPC_H
0114ba7f MD	3
	4	/*
	5	* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
	6	* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
	7	* Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
	8	* Copyright (c) 2009 Mathieu Desnoyers
	9	*
	10	* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
	11	* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
	12	*
	13	* Permission is hereby granted to use or copy this program
	14	* for any purpose, provided the above notices are retained on all copies.
	15	* Permission to modify the code and to distribute modified code is granted,
	16	* provided the above notices are retained, and a notice that the code was
	17	* modified is included with the above copyright notice.
	18	*
ec4e58a3	19	* Code inspired from libuatomic_ops-1.2, inherited in part from the
0114ba7f MD	20	* Boehm-Demers-Weiser conservative garbage collector.
	21	*/
	22
ec4e58a3	23	#include <urcu/compiler.h>
b46b23cb	24	#include <urcu/system.h>
1315d277	25
36bc70a8 MD	26	#ifdef __cplusplus
	27	extern "C" {
	28	#endif
	29
bcf80111 SM	30	#ifndef __SIZEOF_LONG__
	31	#ifdef __powerpc64__
	32	#define __SIZEOF_LONG__ 8
	33	#else
	34	#define __SIZEOF_LONG__ 4
	35	#endif
	36	#endif
	37
0114ba7f MD	38	#ifndef BITS_PER_LONG
	39	#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
	40	#endif
	41
e7061ad2	42	#define ILLEGAL_INSTR ".long 0xd00d00"
0114ba7f	43
b46b23cb MD	44	#define uatomic_set(addr, v) STORE_SHARED(*(addr), (v))
b46b23cb MD	45	#define uatomic_read(addr) LOAD_SHARED(*(addr))
5f8052b4	46
0114ba7f MD	47	/*
0114ba7f MD	48	* Using a isync as second barrier for exchange to provide acquire semantic.
ec4e58a3	49	* According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
0114ba7f MD	50	* explicit that this also has acquire semantics."
	51	* Derived from AO_compare_and_swap(), but removed the comparison.
	52	*/
	53
f689dcbc MD	54	/* xchg */
f689dcbc MD	55
da1c1635	56	static inline __attribute__((always_inline))
ec4e58a3	57	unsigned long _uatomic_exchange(void *addr, unsigned long val, int len)
0114ba7f	58	{
f689dcbc MD	59	switch (len) {
	60	case 4:
	61	{
	62	unsigned int result;
	63
	64	__asm__ __volatile__(
	65	"lwsync\n"
	66	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	67	"stwcx. %2,0,%1\n" /* else store conditional */
	68	"bne- 1b\n" /* retry if lost reservation */
	69	"isync\n"
	70	: "=&r"(result)
	71	: "r"(addr), "r"(val)
	72	: "memory", "cc");
	73
	74	return result;
	75	}
	76	#if (BITS_PER_LONG == 64)
	77	case 8:
	78	{
	79	unsigned long result;
	80
	81	__asm__ __volatile__(
	82	"lwsync\n"
	83	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	84	"stdcx. %2,0,%1\n" /* else store conditional */
	85	"bne- 1b\n" /* retry if lost reservation */
	86	"isync\n"
	87	: "=&r"(result)
	88	: "r"(addr), "r"(val)
	89	: "memory", "cc");
	90
	91	return result;
	92	}
	93	#endif
	94	}
	95	/* generate an illegal instruction. Cannot catch this with linker tricks
	96	* when optimizations are disabled. */
	97	__asm__ __volatile__(ILLEGAL_INSTR);
	98	return 0;
0114ba7f MD	99	}
0114ba7f MD	100
ec4e58a3 MD	101	#define uatomic_xchg(addr, v) \
ec4e58a3 MD	102	((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
da1c1635	103	sizeof(*(addr))))
f689dcbc	104	/* cmpxchg */
0114ba7f	105
da1c1635	106	static inline __attribute__((always_inline))
ec4e58a3	107	unsigned long _uatomic_cmpxchg(void *addr, unsigned long old,
f689dcbc	108	unsigned long _new, int len)
0114ba7f	109	{
f689dcbc MD	110	switch (len) {
	111	case 4:
	112	{
	113	unsigned int old_val;
	114
	115	__asm__ __volatile__(
	116	"lwsync\n"
	117	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	118	"cmpd %0,%3\n" /* if load is not equal to */
	119	"bne 2f\n" /* old, fail */
	120	"stwcx. %2,0,%1\n" /* else store conditional */
	121	"bne- 1b\n" /* retry if lost reservation */
	122	"isync\n"
	123	"2:\n"
e72f4937	124	: "=&r"(old_val)
f689dcbc MD	125	: "r"(addr), "r"((unsigned int)_new),
	126	"r"((unsigned int)old)
	127	: "memory", "cc");
	128
	129	return old_val;
	130	}
	131	#if (BITS_PER_LONG == 64)
	132	case 8:
	133	{
	134	unsigned long old_val;
	135
	136	__asm__ __volatile__(
	137	"lwsync\n"
	138	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	139	"cmpd %0,%3\n" /* if load is not equal to */
	140	"bne 2f\n" /* old, fail */
	141	"stdcx. %2,0,%1\n" /* else store conditional */
	142	"bne- 1b\n" /* retry if lost reservation */
	143	"isync\n"
	144	"2:\n"
	145	: "=&r"(old_val),
	146	: "r"(addr), "r"((unsigned long)_new),
	147	"r"((unsigned long)old)
	148	: "memory", "cc");
	149
	150	return old_val;
	151	}
	152	#endif
	153	}
	154	/* generate an illegal instruction. Cannot catch this with linker tricks
	155	* when optimizations are disabled. */
	156	__asm__ __volatile__(ILLEGAL_INSTR);
	157	return 0;
0114ba7f MD	158	}
0114ba7f MD	159
da1c1635	160
ec4e58a3 MD	161	#define uatomic_cmpxchg(addr, old, _new) \
ec4e58a3 MD	162	((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
da1c1635 MD	163	(unsigned long)(_new), \
da1c1635 MD	164	sizeof(*(addr))))
f689dcbc	165
ec4e58a3	166	/* uatomic_add_return */
0114ba7f	167
da1c1635	168	static inline __attribute__((always_inline))
ec4e58a3	169	unsigned long _uatomic_add_return(void *addr, unsigned long val,
f689dcbc	170	int len)
0114ba7f MD	171	{
0114ba7f MD	172	switch (len) {
f689dcbc MD	173	case 4:
	174	{
	175	unsigned int result;
	176
	177	__asm__ __volatile__(
	178	"lwsync\n"
	179	"1:\t" "lwarx %0,0,%1\n" /* load and reserve */
	180	"add %0,%2,%0\n" /* add val to value loaded */
	181	"stwcx. %0,0,%1\n" /* store conditional */
	182	"bne- 1b\n" /* retry if lost reservation */
	183	"isync\n"
	184	: "=&r"(result)
	185	: "r"(addr), "r"(val)
	186	: "memory", "cc");
	187
	188	return result;
	189	}
0114ba7f	190	#if (BITS_PER_LONG == 64)
f689dcbc MD	191	case 8:
	192	{
	193	unsigned long result;
	194
	195	__asm__ __volatile__(
	196	"lwsync\n"
	197	"1:\t" "ldarx %0,0,%1\n" /* load and reserve */
	198	"add %0,%2,%0\n" /* add val to value loaded */
	199	"stdcx. %0,0,%1\n" /* store conditional */
	200	"bne- 1b\n" /* retry if lost reservation */
	201	"isync\n"
	202	: "=&r"(result)
	203	: "r"(addr), "r"(val)
	204	: "memory", "cc");
	205
	206	return result;
	207	}
0114ba7f MD	208	#endif
	209	}
	210	/* generate an illegal instruction. Cannot catch this with linker tricks
	211	* when optimizations are disabled. */
	212	__asm__ __volatile__(ILLEGAL_INSTR);
	213	return 0;
	214	}
	215
da1c1635	216
ec4e58a3 MD	217	#define uatomic_add_return(addr, v) \
ec4e58a3 MD	218	((__typeof__(*(addr))) _uatomic_add_return((addr), \
da1c1635 MD	219	(unsigned long)(v), \
da1c1635 MD	220	sizeof(*(addr))))
f689dcbc	221
ec4e58a3	222	/* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
f689dcbc	223
ec4e58a3	224	#define uatomic_sub_return(addr, v) uatomic_add_return((addr), -(v))
f689dcbc	225
ec4e58a3 MD	226	#define uatomic_add(addr, v) (void)uatomic_add_return((addr), (v))
ec4e58a3 MD	227	#define uatomic_sub(addr, v) (void)uatomic_sub_return((addr), (v))
f689dcbc	228
ec4e58a3 MD	229	#define uatomic_inc(addr) uatomic_add((addr), 1)
ec4e58a3 MD	230	#define uatomic_dec(addr) uatomic_add((addr), -1)
0114ba7f	231
7d413817 MD	232	#define compat_uatomic_cmpxchg(ptr, old, _new) uatomic_cmpxchg(ptr, old, _new)
7d413817 MD	233
36bc70a8 MD	234	#ifdef __cplusplus
	235	}
	236	#endif
	237
ec4e58a3	238	#endif /* _URCU_ARCH_UATOMIC_PPC_H */