Add missing rcu_cmpxchg_pointer define
[urcu.git] / arch_ppc.h
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1#ifndef _ARCH_PPC_H
2#define _ARCH_PPC_H
3
6d0ce021 4/*
af02d47e 5 * arch_ppc.h: trivial definitions for the powerpc architecture.
6d0ce021 6 *
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7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
6d0ce021 9 *
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10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14*
15 * This library is distributed in the hope that it will be useful,
6d0ce021 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
6d0ce021 19 *
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20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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23 */
24
121a5d44 25#include <compiler.h>
0114ba7f 26#include <arch_atomic.h>
121a5d44 27
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28#define CONFIG_HAVE_FENCE 1
29#define CONFIG_HAVE_MEM_COHERENCY
30
af02d47e 31#ifndef BITS_PER_LONG
41e6b690 32#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
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33#endif
34
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35#define mb() asm volatile("sync":::"memory")
36#define rmb() asm volatile("sync":::"memory")
37#define wmb() asm volatile("sync"::: "memory")
38
39/*
40 * Architectures without cache coherency need something like the following:
41 *
42 * #define mb() mc()
43 * #define rmb() rmc()
44 * #define wmb() wmc()
45 * #define mc() arch_cache_flush()
46 * #define rmc() arch_cache_flush_read()
47 * #define wmc() arch_cache_flush_write()
48 */
49
50#define mc() barrier()
51#define rmc() barrier()
52#define wmc() barrier()
53
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54/* Assume SMP machine, given we don't have this information */
55#define CONFIG_SMP 1
56
57#ifdef CONFIG_SMP
58#define smp_mb() mb()
59#define smp_rmb() rmb()
60#define smp_wmb() wmb()
61#define smp_mc() mc()
62#define smp_rmc() rmc()
63#define smp_wmc() wmc()
64#else
65#define smp_mb() barrier()
66#define smp_rmb() barrier()
67#define smp_wmb() barrier()
68#define smp_mc() barrier()
69#define smp_rmc() barrier()
70#define smp_wmc() barrier()
71#endif
72
73/* Nop everywhere except on alpha. */
74#define smp_read_barrier_depends()
75
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76static inline void cpu_relax(void)
77{
78 barrier();
79}
80
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81/*
82 * Serialize core instruction execution. Also acts as a compiler barrier.
83 */
84static inline void sync_core()
85{
86 asm volatile("isync" : : : "memory");
87}
88
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89#define mftbl() \
90 ({ \
91 unsigned long rval; \
92 asm volatile("mftbl %0" : "=r" (rval)); \
93 rval; \
94 })
95
96#define mftbu() \
97 ({ \
98 unsigned long rval; \
99 asm volatile("mftbu %0" : "=r" (rval)); \
100 rval; \
101 })
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102
103typedef unsigned long long cycles_t;
104
105static inline cycles_t get_cycles (void)
106{
af02d47e 107 long h, l;
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108
109 for (;;) {
110 h = mftbu();
af02d47e 111 barrier();
6d0ce021 112 l = mftbl();
af02d47e 113 barrier();
6d0ce021 114 if (mftbu() == h)
af02d47e 115 return (((cycles_t) h) << 32) + l;
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116 }
117}
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118
119#endif /* _ARCH_PPC_H */
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