X-Git-Url: http://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch_ppc.h;h=eeeb753936d6c0f036305905829513aecc11843b;hb=1b27a7725e853b9f0673a0ed2639b8dc1065f21b;hp=aaf61d30f03e7749823f0aff154987a07398e071;hpb=b4e52e3e9e563d38607a8e0ab0aa72e7ab2b47b4;p=urcu.git

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index aaf61d3..eeeb753 100644
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -23,71 +23,21 @@
  */
 
 #include <urcu/compiler.h>
-#include <urcu/arch_uatomic.h>
+#include <urcu/config.h>
 
-#define CONFIG_HAVE_FENCE 1
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CACHE_LINE_SIZE	256
 
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
-
 #define mb()    asm volatile("sync":::"memory")
-#define rmb()   asm volatile("sync":::"memory")
-#define wmb()   asm volatile("sync"::: "memory")
-
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-/* Assume SMP machine, given we don't have this information */
-#define CONFIG_SMP 1
-
-#ifdef CONFIG_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
  */
-static inline void sync_core()
-{
-	asm volatile("isync" : : : "memory");
-}
+#define sync_core()	asm volatile("isync" : : : "memory")
 
 #define mftbl()						\
 	({ 						\
@@ -119,4 +69,10 @@ static inline cycles_t get_cycles (void)
 	}
 }
 
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_PPC_H */