X-Git-Url: http://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch%2Fppc.h;h=2fcbf5660958a12d2ad6dd957838ed73da4f2bec;hb=14b2b8b8b23d8bf89411ed532cbf9011041981c6;hp=a03d688837344f0bb2d438c7161d43dcb208a5ef;hpb=9a9d403acee72d36d17988ae5a6ce9ede8051f11;p=urcu.git

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index a03d688..2fcbf56 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -32,7 +32,30 @@ extern "C" {
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CAA_CACHE_LINE_SIZE	256
 
-#define cmm_mb()    asm volatile("sync":::"memory")
+#ifdef __NO_LWSYNC__
+#define LWSYNC_OPCODE	"sync\n"
+#else
+#define LWSYNC_OPCODE	"lwsync\n"
+#endif
+
+/*
+ * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
+ * preserve ordering of cacheable vs. non-cacheable accesses, so it
+ * should not be used to order with respect to MMIO operations.  An
+ * eieio+lwsync pair is also not enough for cmm_rmb, because it will
+ * order cacheable and non-cacheable memory operations separately---i.e.
+ * not the latter against the former.
+ */
+#define cmm_mb()         asm volatile("sync":::"memory")
+
+/*
+ * lwsync orders loads in cacheable memory with respect to other loads,
+ * and stores in cacheable memory with respect to other stores.
+ * Therefore, use it for barriers ordering accesses to cacheable memory
+ * only.
+ */
+#define cmm_smp_rmb()    asm volatile(LWSYNC_OPCODE:::"memory")
+#define cmm_smp_wmb()    asm volatile(LWSYNC_OPCODE:::"memory")
 
 #define mftbl()						\
 	({ 						\